ths7303.c 10 KB

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  1. /*
  2. * ths7303/53- THS7303/53 Video Amplifier driver
  3. *
  4. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  5. * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
  6. *
  7. * Author: Chaithrika U S <chaithrika@ti.com>
  8. *
  9. * Contributors:
  10. * Hans Verkuil <hans.verkuil@cisco.com>
  11. * Lad, Prabhakar <prabhakar.lad@ti.com>
  12. * Martin Bugge <marbugge@cisco.com>
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation version 2.
  17. *
  18. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  19. * kind, whether express or implied; without even the implied warranty
  20. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. */
  23. #include <linux/i2c.h>
  24. #include <linux/module.h>
  25. #include <linux/slab.h>
  26. #include <media/ths7303.h>
  27. #include <media/v4l2-chip-ident.h>
  28. #include <media/v4l2-device.h>
  29. #define THS7303_CHANNEL_1 1
  30. #define THS7303_CHANNEL_2 2
  31. #define THS7303_CHANNEL_3 3
  32. struct ths7303_state {
  33. struct v4l2_subdev sd;
  34. struct ths7303_platform_data pdata;
  35. struct v4l2_bt_timings bt;
  36. int std_id;
  37. int stream_on;
  38. int driver_data;
  39. };
  40. enum ths7303_filter_mode {
  41. THS7303_FILTER_MODE_480I_576I,
  42. THS7303_FILTER_MODE_480P_576P,
  43. THS7303_FILTER_MODE_720P_1080I,
  44. THS7303_FILTER_MODE_1080P,
  45. THS7303_FILTER_MODE_DISABLE
  46. };
  47. MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
  48. MODULE_AUTHOR("Chaithrika U S");
  49. MODULE_LICENSE("GPL");
  50. static int debug;
  51. module_param(debug, int, 0644);
  52. MODULE_PARM_DESC(debug, "Debug level 0-1");
  53. static inline struct ths7303_state *to_state(struct v4l2_subdev *sd)
  54. {
  55. return container_of(sd, struct ths7303_state, sd);
  56. }
  57. static int ths7303_read(struct v4l2_subdev *sd, u8 reg)
  58. {
  59. struct i2c_client *client = v4l2_get_subdevdata(sd);
  60. return i2c_smbus_read_byte_data(client, reg);
  61. }
  62. static int ths7303_write(struct v4l2_subdev *sd, u8 reg, u8 val)
  63. {
  64. struct i2c_client *client = v4l2_get_subdevdata(sd);
  65. int ret;
  66. int i;
  67. for (i = 0; i < 3; i++) {
  68. ret = i2c_smbus_write_byte_data(client, reg, val);
  69. if (ret == 0)
  70. return 0;
  71. }
  72. return ret;
  73. }
  74. /* following function is used to set ths7303 */
  75. int ths7303_setval(struct v4l2_subdev *sd, enum ths7303_filter_mode mode)
  76. {
  77. struct i2c_client *client = v4l2_get_subdevdata(sd);
  78. struct ths7303_state *state = to_state(sd);
  79. struct ths7303_platform_data *pdata = &state->pdata;
  80. u8 val, sel = 0;
  81. int err, disable = 0;
  82. if (!client)
  83. return -EINVAL;
  84. switch (mode) {
  85. case THS7303_FILTER_MODE_1080P:
  86. sel = 0x3; /*1080p and SXGA/UXGA */
  87. break;
  88. case THS7303_FILTER_MODE_720P_1080I:
  89. sel = 0x2; /*720p, 1080i and SVGA/XGA */
  90. break;
  91. case THS7303_FILTER_MODE_480P_576P:
  92. sel = 0x1; /* EDTV 480p/576p and VGA */
  93. break;
  94. case THS7303_FILTER_MODE_480I_576I:
  95. sel = 0x0; /* SDTV, S-Video, 480i/576i */
  96. break;
  97. default:
  98. /* disable all channels */
  99. disable = 1;
  100. }
  101. val = (sel << 6) | (sel << 3);
  102. if (!disable)
  103. val |= (pdata->ch_1 & 0x27);
  104. err = ths7303_write(sd, THS7303_CHANNEL_1, val);
  105. if (err)
  106. goto out;
  107. val = (sel << 6) | (sel << 3);
  108. if (!disable)
  109. val |= (pdata->ch_2 & 0x27);
  110. err = ths7303_write(sd, THS7303_CHANNEL_2, val);
  111. if (err)
  112. goto out;
  113. val = (sel << 6) | (sel << 3);
  114. if (!disable)
  115. val |= (pdata->ch_3 & 0x27);
  116. err = ths7303_write(sd, THS7303_CHANNEL_3, val);
  117. if (err)
  118. goto out;
  119. return 0;
  120. out:
  121. pr_info("write byte data failed\n");
  122. return err;
  123. }
  124. static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
  125. {
  126. struct ths7303_state *state = to_state(sd);
  127. if (norm & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
  128. state->std_id = 1;
  129. state->bt.pixelclock = 0;
  130. return ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
  131. }
  132. return ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
  133. }
  134. static int ths7303_config(struct v4l2_subdev *sd)
  135. {
  136. struct ths7303_state *state = to_state(sd);
  137. int res;
  138. if (!state->stream_on) {
  139. ths7303_write(sd, THS7303_CHANNEL_1,
  140. (ths7303_read(sd, THS7303_CHANNEL_1) & 0xf8) |
  141. 0x00);
  142. ths7303_write(sd, THS7303_CHANNEL_2,
  143. (ths7303_read(sd, THS7303_CHANNEL_2) & 0xf8) |
  144. 0x00);
  145. ths7303_write(sd, THS7303_CHANNEL_3,
  146. (ths7303_read(sd, THS7303_CHANNEL_3) & 0xf8) |
  147. 0x00);
  148. return 0;
  149. }
  150. if (state->bt.pixelclock > 120000000)
  151. res = ths7303_setval(sd, THS7303_FILTER_MODE_1080P);
  152. else if (state->bt.pixelclock > 70000000)
  153. res = ths7303_setval(sd, THS7303_FILTER_MODE_720P_1080I);
  154. else if (state->bt.pixelclock > 20000000)
  155. res = ths7303_setval(sd, THS7303_FILTER_MODE_480P_576P);
  156. else if (state->std_id)
  157. res = ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
  158. else
  159. /* disable all channels */
  160. res = ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
  161. return res;
  162. }
  163. static int ths7303_s_stream(struct v4l2_subdev *sd, int enable)
  164. {
  165. struct ths7303_state *state = to_state(sd);
  166. state->stream_on = enable;
  167. return ths7303_config(sd);
  168. }
  169. /* for setting filter for HD output */
  170. static int ths7303_s_dv_timings(struct v4l2_subdev *sd,
  171. struct v4l2_dv_timings *dv_timings)
  172. {
  173. struct ths7303_state *state = to_state(sd);
  174. if (!dv_timings || dv_timings->type != V4L2_DV_BT_656_1120)
  175. return -EINVAL;
  176. state->bt = dv_timings->bt;
  177. state->std_id = 0;
  178. return ths7303_config(sd);
  179. }
  180. static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
  181. struct v4l2_dbg_chip_ident *chip)
  182. {
  183. struct i2c_client *client = v4l2_get_subdevdata(sd);
  184. struct ths7303_state *state = to_state(sd);
  185. return v4l2_chip_ident_i2c_client(client, chip, state->driver_data, 0);
  186. }
  187. static const struct v4l2_subdev_video_ops ths7303_video_ops = {
  188. .s_stream = ths7303_s_stream,
  189. .s_std_output = ths7303_s_std_output,
  190. .s_dv_timings = ths7303_s_dv_timings,
  191. };
  192. #ifdef CONFIG_VIDEO_ADV_DEBUG
  193. static int ths7303_g_register(struct v4l2_subdev *sd,
  194. struct v4l2_dbg_register *reg)
  195. {
  196. struct i2c_client *client = v4l2_get_subdevdata(sd);
  197. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  198. return -EINVAL;
  199. reg->size = 1;
  200. reg->val = ths7303_read(sd, reg->reg);
  201. return 0;
  202. }
  203. static int ths7303_s_register(struct v4l2_subdev *sd,
  204. const struct v4l2_dbg_register *reg)
  205. {
  206. struct i2c_client *client = v4l2_get_subdevdata(sd);
  207. if (!v4l2_chip_match_i2c_client(client, &reg->match))
  208. return -EINVAL;
  209. ths7303_write(sd, reg->reg, reg->val);
  210. return 0;
  211. }
  212. #endif
  213. static const char * const stc_lpf_sel_txt[4] = {
  214. "500-kHz Filter",
  215. "2.5-MHz Filter",
  216. "5-MHz Filter",
  217. "5-MHz Filter",
  218. };
  219. static const char * const in_mux_sel_txt[2] = {
  220. "Input A Select",
  221. "Input B Select",
  222. };
  223. static const char * const lpf_freq_sel_txt[4] = {
  224. "9-MHz LPF",
  225. "16-MHz LPF",
  226. "35-MHz LPF",
  227. "Bypass LPF",
  228. };
  229. static const char * const in_bias_sel_dis_cont_txt[8] = {
  230. "Disable Channel",
  231. "Mute Function - No Output",
  232. "DC Bias Select",
  233. "DC Bias + 250 mV Offset Select",
  234. "AC Bias Select",
  235. "Sync Tip Clamp with low bias",
  236. "Sync Tip Clamp with mid bias",
  237. "Sync Tip Clamp with high bias",
  238. };
  239. static void ths7303_log_channel_status(struct v4l2_subdev *sd, u8 reg)
  240. {
  241. u8 val = ths7303_read(sd, reg);
  242. if ((val & 0x7) == 0) {
  243. v4l2_info(sd, "Channel %d Off\n", reg);
  244. return;
  245. }
  246. v4l2_info(sd, "Channel %d On\n", reg);
  247. v4l2_info(sd, " value 0x%x\n", val);
  248. v4l2_info(sd, " %s\n", stc_lpf_sel_txt[(val >> 6) & 0x3]);
  249. v4l2_info(sd, " %s\n", in_mux_sel_txt[(val >> 5) & 0x1]);
  250. v4l2_info(sd, " %s\n", lpf_freq_sel_txt[(val >> 3) & 0x3]);
  251. v4l2_info(sd, " %s\n", in_bias_sel_dis_cont_txt[(val >> 0) & 0x7]);
  252. }
  253. static int ths7303_log_status(struct v4l2_subdev *sd)
  254. {
  255. struct ths7303_state *state = to_state(sd);
  256. v4l2_info(sd, "stream %s\n", state->stream_on ? "On" : "Off");
  257. if (state->bt.pixelclock) {
  258. struct v4l2_bt_timings *bt = bt = &state->bt;
  259. u32 frame_width, frame_height;
  260. frame_width = bt->width + bt->hfrontporch +
  261. bt->hsync + bt->hbackporch;
  262. frame_height = bt->height + bt->vfrontporch +
  263. bt->vsync + bt->vbackporch;
  264. v4l2_info(sd,
  265. "timings: %dx%d%s%d (%dx%d). Pix freq. = %d Hz. Polarities = 0x%x\n",
  266. bt->width, bt->height, bt->interlaced ? "i" : "p",
  267. (frame_height * frame_width) > 0 ?
  268. (int)bt->pixelclock /
  269. (frame_height * frame_width) : 0,
  270. frame_width, frame_height,
  271. (int)bt->pixelclock, bt->polarities);
  272. } else {
  273. v4l2_info(sd, "no timings set\n");
  274. }
  275. ths7303_log_channel_status(sd, THS7303_CHANNEL_1);
  276. ths7303_log_channel_status(sd, THS7303_CHANNEL_2);
  277. ths7303_log_channel_status(sd, THS7303_CHANNEL_3);
  278. return 0;
  279. }
  280. static const struct v4l2_subdev_core_ops ths7303_core_ops = {
  281. .g_chip_ident = ths7303_g_chip_ident,
  282. .log_status = ths7303_log_status,
  283. #ifdef CONFIG_VIDEO_ADV_DEBUG
  284. .g_register = ths7303_g_register,
  285. .s_register = ths7303_s_register,
  286. #endif
  287. };
  288. static const struct v4l2_subdev_ops ths7303_ops = {
  289. .core = &ths7303_core_ops,
  290. .video = &ths7303_video_ops,
  291. };
  292. static int ths7303_probe(struct i2c_client *client,
  293. const struct i2c_device_id *id)
  294. {
  295. struct ths7303_platform_data *pdata = client->dev.platform_data;
  296. struct ths7303_state *state;
  297. struct v4l2_subdev *sd;
  298. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  299. return -ENODEV;
  300. v4l_info(client, "chip found @ 0x%x (%s)\n",
  301. client->addr << 1, client->adapter->name);
  302. state = devm_kzalloc(&client->dev, sizeof(struct ths7303_state),
  303. GFP_KERNEL);
  304. if (!state)
  305. return -ENOMEM;
  306. if (!pdata)
  307. v4l_warn(client, "No platform data, using default data!\n");
  308. else
  309. state->pdata = *pdata;
  310. sd = &state->sd;
  311. v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
  312. /* store the driver data to differntiate the chip */
  313. state->driver_data = (int)id->driver_data;
  314. /* set to default 480I_576I filter mode */
  315. if (ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I) < 0) {
  316. v4l_err(client, "Setting to 480I_576I filter mode failed!\n");
  317. return -EINVAL;
  318. }
  319. return 0;
  320. }
  321. static int ths7303_remove(struct i2c_client *client)
  322. {
  323. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  324. v4l2_device_unregister_subdev(sd);
  325. return 0;
  326. }
  327. static const struct i2c_device_id ths7303_id[] = {
  328. {"ths7303", V4L2_IDENT_THS7303},
  329. {"ths7353", V4L2_IDENT_THS7353},
  330. {},
  331. };
  332. MODULE_DEVICE_TABLE(i2c, ths7303_id);
  333. static struct i2c_driver ths7303_driver = {
  334. .driver = {
  335. .owner = THIS_MODULE,
  336. .name = "ths73x3",
  337. },
  338. .probe = ths7303_probe,
  339. .remove = ths7303_remove,
  340. .id_table = ths7303_id,
  341. };
  342. module_i2c_driver(ths7303_driver);