gdth.c 197 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.74 2006/04/10 13:44:47 achim
  34. * Community changes for 2.6.x
  35. * Kernel 2.2.x no longer supported
  36. * scsi_request interface removed, thanks to Christoph Hellwig
  37. *
  38. * Revision 1.73 2004/03/31 13:33:03 achim
  39. * Special command 0xfd implemented to detect 64-bit DMA support
  40. *
  41. * Revision 1.72 2004/03/17 08:56:04 achim
  42. * 64-bit DMA only enabled if FW >= x.43
  43. *
  44. * Revision 1.71 2004/03/05 15:51:29 achim
  45. * Screen service: separate message buffer, bugfixes
  46. *
  47. * Revision 1.70 2004/02/27 12:19:07 achim
  48. * Bugfix: Reset bit in config (0xfe) call removed
  49. *
  50. * Revision 1.69 2004/02/20 09:50:24 achim
  51. * Compatibility changes for kernels < 2.4.20
  52. * Bugfix screen service command size
  53. * pci_set_dma_mask() error handling added
  54. *
  55. * Revision 1.68 2004/02/19 15:46:54 achim
  56. * 64-bit DMA bugfixes
  57. * Drive size bugfix for drives > 1TB
  58. *
  59. * Revision 1.67 2004/01/14 13:11:57 achim
  60. * Tool access over /proc no longer supported
  61. * Bugfixes IOCTLs
  62. *
  63. * Revision 1.66 2003/12/19 15:04:06 achim
  64. * Bugfixes support for drives > 2TB
  65. *
  66. * Revision 1.65 2003/12/15 11:21:56 achim
  67. * 64-bit DMA support added
  68. * Support for drives > 2 TB implemented
  69. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  70. *
  71. * Revision 1.64 2003/09/17 08:30:26 achim
  72. * EISA/ISA controller scan disabled
  73. * Command line switch probe_eisa_isa added
  74. *
  75. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  76. * Minor cleanups in gdth_ioctl.
  77. *
  78. * Revision 1.62 2003/02/27 15:01:59 achim
  79. * Dynamic DMA mapping implemented
  80. * New (character device) IOCTL interface added
  81. * Other controller related changes made
  82. *
  83. * Revision 1.61 2002/11/08 13:09:52 boji
  84. * Added support for XSCALE based RAID Controllers
  85. * Fixed SCREENSERVICE initialization in SMP cases
  86. * Added checks for gdth_polling before GDTH_HA_LOCK
  87. *
  88. * Revision 1.60 2002/02/05 09:35:22 achim
  89. * MODULE_LICENSE only if kernel >= 2.4.11
  90. *
  91. * Revision 1.59 2002/01/30 09:46:33 achim
  92. * Small changes
  93. *
  94. * Revision 1.58 2002/01/29 15:30:02 achim
  95. * Set default value of shared_access to Y
  96. * New status S_CACHE_RESERV for clustering added
  97. *
  98. * Revision 1.57 2001/08/21 11:16:35 achim
  99. * Bugfix free_irq()
  100. *
  101. * Revision 1.56 2001/08/09 11:19:39 achim
  102. * Scsi_Host_Template changes
  103. *
  104. * Revision 1.55 2001/08/09 10:11:28 achim
  105. * Command HOST_UNFREEZE_IO before cache service init.
  106. *
  107. * Revision 1.54 2001/07/20 13:48:12 achim
  108. * Expand: gdth_analyse_hdrive() removed
  109. *
  110. * Revision 1.53 2001/07/17 09:52:49 achim
  111. * Small OEM related change
  112. *
  113. * Revision 1.52 2001/06/19 15:06:20 achim
  114. * New host command GDT_UNFREEZE_IO added
  115. *
  116. * Revision 1.51 2001/05/22 06:42:37 achim
  117. * PCI: Subdevice ID added
  118. *
  119. * Revision 1.50 2001/05/17 13:42:16 achim
  120. * Support for Intel Storage RAID Controllers added
  121. *
  122. * Revision 1.50 2001/05/17 12:12:34 achim
  123. * Support for Intel Storage RAID Controllers added
  124. *
  125. * Revision 1.49 2001/03/15 15:07:17 achim
  126. * New __setup interface for boot command line options added
  127. *
  128. * Revision 1.48 2001/02/06 12:36:28 achim
  129. * Bugfix Cluster protocol
  130. *
  131. * Revision 1.47 2001/01/10 14:42:06 achim
  132. * New switch shared_access added
  133. *
  134. * Revision 1.46 2001/01/09 08:11:35 achim
  135. * gdth_command() removed
  136. * meaning of Scsi_Pointer members changed
  137. *
  138. * Revision 1.45 2000/11/16 12:02:24 achim
  139. * Changes for kernel 2.4
  140. *
  141. * Revision 1.44 2000/10/11 08:44:10 achim
  142. * Clustering changes: New flag media_changed added
  143. *
  144. * Revision 1.43 2000/09/20 12:59:01 achim
  145. * DPMEM remap functions for all PCI controller types implemented
  146. * Small changes for ia64 platform
  147. *
  148. * Revision 1.42 2000/07/20 09:04:50 achim
  149. * Small changes for kernel 2.4
  150. *
  151. * Revision 1.41 2000/07/04 14:11:11 achim
  152. * gdth_analyse_hdrive() added to rescan drives after online expansion
  153. *
  154. * Revision 1.40 2000/06/27 11:24:16 achim
  155. * Changes Clustering, Screenservice
  156. *
  157. * Revision 1.39 2000/06/15 13:09:04 achim
  158. * Changes for gdth_do_cmd()
  159. *
  160. * Revision 1.38 2000/06/15 12:08:43 achim
  161. * Bugfix gdth_sync_event(), service SCREENSERVICE
  162. * Data direction for command 0xc2 changed to DOU
  163. *
  164. * Revision 1.37 2000/05/25 13:50:10 achim
  165. * New driver parameter virt_ctr added
  166. *
  167. * Revision 1.36 2000/05/04 08:50:46 achim
  168. * Event buffer now in gdth_ha_str
  169. *
  170. * Revision 1.35 2000/03/03 10:44:08 achim
  171. * New event_string only valid for the RP controller family
  172. *
  173. * Revision 1.34 2000/03/02 14:55:29 achim
  174. * New mechanism for async. event handling implemented
  175. *
  176. * Revision 1.33 2000/02/21 15:37:37 achim
  177. * Bugfix Alpha platform + DPMEM above 4GB
  178. *
  179. * Revision 1.32 2000/02/14 16:17:37 achim
  180. * Bugfix sense_buffer[] + raw devices
  181. *
  182. * Revision 1.31 2000/02/10 10:29:00 achim
  183. * Delete sense_buffer[0], if command OK
  184. *
  185. * Revision 1.30 1999/11/02 13:42:39 achim
  186. * ARRAY_DRV_LIST2 implemented
  187. * Now 255 log. and 100 host drives supported
  188. *
  189. * Revision 1.29 1999/10/05 13:28:47 achim
  190. * GDT_CLUST_RESET added
  191. *
  192. * Revision 1.28 1999/08/12 13:44:54 achim
  193. * MOUNTALL removed
  194. * Cluster drives -> removeable drives
  195. *
  196. * Revision 1.27 1999/06/22 07:22:38 achim
  197. * Small changes
  198. *
  199. * Revision 1.26 1999/06/10 16:09:12 achim
  200. * Cluster Host Drive support: Bugfixes
  201. *
  202. * Revision 1.25 1999/06/01 16:03:56 achim
  203. * gdth_init_pci(): Manipulate config. space to start RP controller
  204. *
  205. * Revision 1.24 1999/05/26 11:53:06 achim
  206. * Cluster Host Drive support added
  207. *
  208. * Revision 1.23 1999/03/26 09:12:31 achim
  209. * Default value for hdr_channel set to 0
  210. *
  211. * Revision 1.22 1999/03/22 16:27:16 achim
  212. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  213. *
  214. * Revision 1.21 1999/03/16 13:40:34 achim
  215. * Problems with reserved drives solved
  216. * gdth_eh_bus_reset() implemented
  217. *
  218. * Revision 1.20 1999/03/10 09:08:13 achim
  219. * Bugfix: Corrections in gdth_direction_tab[] made
  220. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  221. *
  222. * Revision 1.19 1999/03/05 14:38:16 achim
  223. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  224. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  225. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  226. * with BIOS disabled and memory test set to Intensive
  227. * Enhanced /proc support
  228. *
  229. * Revision 1.18 1999/02/24 09:54:33 achim
  230. * Command line parameter hdr_channel implemented
  231. * Bugfix for EISA controllers + Linux 2.2.x
  232. *
  233. * Revision 1.17 1998/12/17 15:58:11 achim
  234. * Command line parameters implemented
  235. * Changes for Alpha platforms
  236. * PCI controller scan changed
  237. * SMP support improved (spin_lock_irqsave(),...)
  238. * New async. events, new scan/reserve commands included
  239. *
  240. * Revision 1.16 1998/09/28 16:08:46 achim
  241. * GDT_PCIMPR: DPMEM remapping, if required
  242. * mdelay() added
  243. *
  244. * Revision 1.15 1998/06/03 14:54:06 achim
  245. * gdth_delay(), gdth_flush() implemented
  246. * Bugfix: gdth_release() changed
  247. *
  248. * Revision 1.14 1998/05/22 10:01:17 achim
  249. * mj: pcibios_strerror() removed
  250. * Improved SMP support (if version >= 2.1.95)
  251. * gdth_halt(): halt_called flag added (if version < 2.1)
  252. *
  253. * Revision 1.13 1998/04/16 09:14:57 achim
  254. * Reserve drives (for raw service) implemented
  255. * New error handling code enabled
  256. * Get controller name from board_info() IOCTL
  257. * Final round of PCI device driver patches by Martin Mares
  258. *
  259. * Revision 1.12 1998/03/03 09:32:37 achim
  260. * Fibre channel controller support added
  261. *
  262. * Revision 1.11 1998/01/27 16:19:14 achim
  263. * SA_SHIRQ added
  264. * add_timer()/del_timer() instead of GDTH_TIMER
  265. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  266. * New error handling included
  267. *
  268. * Revision 1.10 1997/10/31 12:29:57 achim
  269. * Read heads/sectors from host drive
  270. *
  271. * Revision 1.9 1997/09/04 10:07:25 achim
  272. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  273. * register_reboot_notifier() to get a notify on shutown used
  274. *
  275. * Revision 1.8 1997/04/02 12:14:30 achim
  276. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  277. *
  278. * Revision 1.7 1997/03/12 13:33:37 achim
  279. * gdth_reset() changed, new async. events
  280. *
  281. * Revision 1.6 1997/03/04 14:01:11 achim
  282. * Shutdown routine gdth_halt() implemented
  283. *
  284. * Revision 1.5 1997/02/21 09:08:36 achim
  285. * New controller included (RP, RP1, RP2 series)
  286. * IOCTL interface implemented
  287. *
  288. * Revision 1.4 1996/07/05 12:48:55 achim
  289. * Function gdth_bios_param() implemented
  290. * New constant GDTH_MAXC_P_L inserted
  291. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  292. * Function gdth_reset() changed
  293. *
  294. * Revision 1.3 1996/05/10 09:04:41 achim
  295. * Small changes for Linux 1.2.13
  296. *
  297. * Revision 1.2 1996/05/09 12:45:27 achim
  298. * Loadable module support implemented
  299. * /proc support corrections made
  300. *
  301. * Revision 1.1 1996/04/11 07:35:57 achim
  302. * Initial revision
  303. *
  304. ************************************************************************/
  305. /* All GDT Disk Array Controllers are fully supported by this driver.
  306. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  307. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  308. * list of all controller types.
  309. *
  310. * If you have one or more GDT3000/3020 EISA controllers with
  311. * controller BIOS disabled, you have to set the IRQ values with the
  312. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  313. * the IRQ values for the EISA controllers.
  314. *
  315. * After the optional list of IRQ values, other possible
  316. * command line options are:
  317. * disable:Y disable driver
  318. * disable:N enable driver
  319. * reserve_mode:0 reserve no drives for the raw service
  320. * reserve_mode:1 reserve all not init., removable drives
  321. * reserve_mode:2 reserve all not init. drives
  322. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  323. * h- controller no., b- channel no.,
  324. * t- target ID, l- LUN
  325. * reverse_scan:Y reverse scan order for PCI controllers
  326. * reverse_scan:N scan PCI controllers like BIOS
  327. * max_ids:x x - target ID count per channel (1..MAXID)
  328. * rescan:Y rescan all channels/IDs
  329. * rescan:N use all devices found until now
  330. * virt_ctr:Y map every channel to a virtual controller
  331. * virt_ctr:N use multi channel support
  332. * hdr_channel:x x - number of virtual bus for host drives
  333. * shared_access:Y disable driver reserve/release protocol to
  334. * access a shared resource from several nodes,
  335. * appropriate controller firmware required
  336. * shared_access:N enable driver reserve/release protocol
  337. * probe_eisa_isa:Y scan for EISA/ISA controllers
  338. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  339. * force_dma32:Y use only 32 bit DMA mode
  340. * force_dma32:N use 64 bit DMA mode, if supported
  341. *
  342. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  343. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  344. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  345. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  346. *
  347. * When loading the gdth driver as a module, the same options are available.
  348. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  349. * options changes slightly. You must replace all ',' between options
  350. * with ' ' and all ':' with '=' and you must use
  351. * '1' in place of 'Y' and '0' in place of 'N'.
  352. *
  353. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  354. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  355. * probe_eisa_isa=0 force_dma32=0"
  356. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  357. */
  358. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  359. * ptr: Chaining
  360. * this_residual: Command priority
  361. * buffer: phys. DMA sense buffer
  362. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  363. * buffers_residual: Timeout value
  364. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  365. * Message: Additional info (gdth_do_cmd()), DMA direction
  366. * have_data_in: Flag for gdth_wait_completion()
  367. * sent_command: Opcode special command
  368. * phase: Service/parameter/return code special command
  369. */
  370. /* interrupt coalescing */
  371. /* #define INT_COAL */
  372. /* statistics */
  373. #define GDTH_STATISTICS
  374. #include <linux/module.h>
  375. #include <linux/version.h>
  376. #include <linux/kernel.h>
  377. #include <linux/types.h>
  378. #include <linux/pci.h>
  379. #include <linux/string.h>
  380. #include <linux/ctype.h>
  381. #include <linux/ioport.h>
  382. #include <linux/delay.h>
  383. #include <linux/interrupt.h>
  384. #include <linux/in.h>
  385. #include <linux/proc_fs.h>
  386. #include <linux/time.h>
  387. #include <linux/timer.h>
  388. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
  389. #include <linux/dma-mapping.h>
  390. #else
  391. #define DMA_32BIT_MASK 0x00000000ffffffffULL
  392. #define DMA_64BIT_MASK 0xffffffffffffffffULL
  393. #endif
  394. #ifdef GDTH_RTC
  395. #include <linux/mc146818rtc.h>
  396. #endif
  397. #include <linux/reboot.h>
  398. #include <asm/dma.h>
  399. #include <asm/system.h>
  400. #include <asm/io.h>
  401. #include <asm/uaccess.h>
  402. #include <linux/spinlock.h>
  403. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  404. #include <linux/blkdev.h>
  405. #else
  406. #include <linux/blk.h>
  407. #include "sd.h"
  408. #endif
  409. #include "scsi.h"
  410. #include <scsi/scsi_host.h>
  411. #include "gdth_kcompat.h"
  412. #include "gdth.h"
  413. static void gdth_delay(int milliseconds);
  414. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  415. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  416. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  417. static int gdth_async_event(int hanum);
  418. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  419. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  420. static void gdth_next(int hanum);
  421. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  422. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  423. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  424. ushort idx, gdth_evt_data *evt);
  425. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  426. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  427. gdth_evt_str *estr);
  428. static void gdth_clear_events(void);
  429. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  430. char *buffer,ushort count);
  431. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  432. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  433. static void gdth_enable_int(int hanum);
  434. static int gdth_get_status(unchar *pIStatus,int irq);
  435. static int gdth_test_busy(int hanum);
  436. static int gdth_get_cmd_index(int hanum);
  437. static void gdth_release_event(int hanum);
  438. static int gdth_wait(int hanum,int index,ulong32 time);
  439. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  440. ulong64 p2,ulong64 p3);
  441. static int gdth_search_drives(int hanum);
  442. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  443. static const char *gdth_ctr_name(int hanum);
  444. static int gdth_open(struct inode *inode, struct file *filep);
  445. static int gdth_close(struct inode *inode, struct file *filep);
  446. static int gdth_ioctl(struct inode *inode, struct file *filep,
  447. unsigned int cmd, unsigned long arg);
  448. static void gdth_flush(int hanum);
  449. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  450. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  451. static void gdth_scsi_done(struct scsi_cmnd *scp);
  452. #ifdef CONFIG_ISA
  453. static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
  454. #endif
  455. #ifdef CONFIG_EISA
  456. static int gdth_eisa_probe_one(struct scsi_host_template *, ushort);
  457. #endif
  458. #ifdef CONFIG_PCI
  459. static int gdth_pci_probe_one(struct scsi_host_template *, gdth_pci_str *, int);
  460. #endif
  461. #ifdef DEBUG_GDTH
  462. static unchar DebugState = DEBUG_GDTH;
  463. #ifdef __SERIAL__
  464. #define MAX_SERBUF 160
  465. static void ser_init(void);
  466. static void ser_puts(char *str);
  467. static void ser_putc(char c);
  468. static int ser_printk(const char *fmt, ...);
  469. static char strbuf[MAX_SERBUF+1];
  470. #ifdef __COM2__
  471. #define COM_BASE 0x2f8
  472. #else
  473. #define COM_BASE 0x3f8
  474. #endif
  475. static void ser_init()
  476. {
  477. unsigned port=COM_BASE;
  478. outb(0x80,port+3);
  479. outb(0,port+1);
  480. /* 19200 Baud, if 9600: outb(12,port) */
  481. outb(6, port);
  482. outb(3,port+3);
  483. outb(0,port+1);
  484. /*
  485. ser_putc('I');
  486. ser_putc(' ');
  487. */
  488. }
  489. static void ser_puts(char *str)
  490. {
  491. char *ptr;
  492. ser_init();
  493. for (ptr=str;*ptr;++ptr)
  494. ser_putc(*ptr);
  495. }
  496. static void ser_putc(char c)
  497. {
  498. unsigned port=COM_BASE;
  499. while ((inb(port+5) & 0x20)==0);
  500. outb(c,port);
  501. if (c==0x0a)
  502. {
  503. while ((inb(port+5) & 0x20)==0);
  504. outb(0x0d,port);
  505. }
  506. }
  507. static int ser_printk(const char *fmt, ...)
  508. {
  509. va_list args;
  510. int i;
  511. va_start(args,fmt);
  512. i = vsprintf(strbuf,fmt,args);
  513. ser_puts(strbuf);
  514. va_end(args);
  515. return i;
  516. }
  517. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  518. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  519. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  520. #else /* !__SERIAL__ */
  521. #define TRACE(a) {if (DebugState==1) {printk a;}}
  522. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  523. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  524. #endif
  525. #else /* !DEBUG */
  526. #define TRACE(a)
  527. #define TRACE2(a)
  528. #define TRACE3(a)
  529. #endif
  530. #ifdef GDTH_STATISTICS
  531. static ulong32 max_rq=0, max_index=0, max_sg=0;
  532. #ifdef INT_COAL
  533. static ulong32 max_int_coal=0;
  534. #endif
  535. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  536. static struct timer_list gdth_timer;
  537. #endif
  538. #define PTR2USHORT(a) (ushort)(ulong)(a)
  539. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  540. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  541. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  542. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  543. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  544. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  545. #define gdth_readb(addr) readb(addr)
  546. #define gdth_readw(addr) readw(addr)
  547. #define gdth_readl(addr) readl(addr)
  548. #define gdth_writeb(b,addr) writeb((b),(addr))
  549. #define gdth_writew(b,addr) writew((b),(addr))
  550. #define gdth_writel(b,addr) writel((b),(addr))
  551. #ifdef CONFIG_ISA
  552. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  553. #endif
  554. #ifdef CONFIG_EISA
  555. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  556. #endif
  557. static unchar gdth_polling; /* polling if TRUE */
  558. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  559. static int wait_index,wait_hanum; /* gdth_wait() */
  560. static int gdth_ctr_count = 0; /* controller count */
  561. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  562. static int gdth_ctr_released = 0; /* gdth_release() */
  563. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  564. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  565. static unchar gdth_write_through = FALSE; /* write through */
  566. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  567. static int elastidx;
  568. static int eoldidx;
  569. static int major;
  570. #define DIN 1 /* IN data direction */
  571. #define DOU 2 /* OUT data direction */
  572. #define DNO DIN /* no data transfer */
  573. #define DUN DIN /* unknown data direction */
  574. static unchar gdth_direction_tab[0x100] = {
  575. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  576. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  577. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  578. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  579. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  580. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  581. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  582. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  583. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  584. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  585. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  586. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  587. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  588. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  589. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  590. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  591. };
  592. /* LILO and modprobe/insmod parameters */
  593. /* IRQ list for GDT3000/3020 EISA controllers */
  594. static int irq[MAXHA] __initdata =
  595. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  596. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  597. /* disable driver flag */
  598. static int disable __initdata = 0;
  599. /* reserve flag */
  600. static int reserve_mode = 1;
  601. /* reserve list */
  602. static int reserve_list[MAX_RES_ARGS] =
  603. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  604. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  605. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  606. /* scan order for PCI controllers */
  607. static int reverse_scan = 0;
  608. /* virtual channel for the host drives */
  609. static int hdr_channel = 0;
  610. /* max. IDs per channel */
  611. static int max_ids = MAXID;
  612. /* rescan all IDs */
  613. static int rescan = 0;
  614. /* map channels to virtual controllers */
  615. static int virt_ctr = 0;
  616. /* shared access */
  617. static int shared_access = 1;
  618. /* enable support for EISA and ISA controllers */
  619. static int probe_eisa_isa = 0;
  620. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  621. static int force_dma32 = 0;
  622. /* parameters for modprobe/insmod */
  623. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
  624. module_param_array(irq, int, NULL, 0);
  625. module_param(disable, int, 0);
  626. module_param(reserve_mode, int, 0);
  627. module_param_array(reserve_list, int, NULL, 0);
  628. module_param(reverse_scan, int, 0);
  629. module_param(hdr_channel, int, 0);
  630. module_param(max_ids, int, 0);
  631. module_param(rescan, int, 0);
  632. module_param(virt_ctr, int, 0);
  633. module_param(shared_access, int, 0);
  634. module_param(probe_eisa_isa, int, 0);
  635. module_param(force_dma32, int, 0);
  636. #else
  637. MODULE_PARM(irq, "i");
  638. MODULE_PARM(disable, "i");
  639. MODULE_PARM(reserve_mode, "i");
  640. MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
  641. MODULE_PARM(reverse_scan, "i");
  642. MODULE_PARM(hdr_channel, "i");
  643. MODULE_PARM(max_ids, "i");
  644. MODULE_PARM(rescan, "i");
  645. MODULE_PARM(virt_ctr, "i");
  646. MODULE_PARM(shared_access, "i");
  647. MODULE_PARM(probe_eisa_isa, "i");
  648. MODULE_PARM(force_dma32, "i");
  649. #endif
  650. MODULE_AUTHOR("Achim Leubner");
  651. MODULE_LICENSE("GPL");
  652. /* ioctl interface */
  653. static const struct file_operations gdth_fops = {
  654. .ioctl = gdth_ioctl,
  655. .open = gdth_open,
  656. .release = gdth_close,
  657. };
  658. #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
  659. #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
  660. #include "gdth_proc.h"
  661. #include "gdth_proc.c"
  662. /* notifier block to get a notify on system shutdown/halt/reboot */
  663. static struct notifier_block gdth_notifier = {
  664. gdth_halt, NULL, 0
  665. };
  666. static int notifier_disabled = 0;
  667. static void gdth_delay(int milliseconds)
  668. {
  669. if (milliseconds == 0) {
  670. udelay(1);
  671. } else {
  672. mdelay(milliseconds);
  673. }
  674. }
  675. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  676. static void gdth_scsi_done(struct scsi_cmnd *scp)
  677. {
  678. TRACE2(("gdth_scsi_done()\n"));
  679. if (IS_GDTH_INTERNAL_CMD(scp))
  680. complete((struct completion *)scp->request);
  681. else
  682. scp->scsi_done(scp);
  683. }
  684. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  685. int timeout, u32 *info)
  686. {
  687. Scsi_Cmnd *scp;
  688. DECLARE_COMPLETION_ONSTACK(wait);
  689. int rval;
  690. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  691. if (!scp)
  692. return -ENOMEM;
  693. scp->device = sdev;
  694. /* use request field to save the ptr. to completion struct. */
  695. scp->request = (struct request *)&wait;
  696. scp->timeout_per_command = timeout*HZ;
  697. scp->request_buffer = gdtcmd;
  698. scp->cmd_len = 12;
  699. memcpy(scp->cmnd, cmnd, 12);
  700. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  701. scp->underflow = GDTH_MAGIC;
  702. gdth_queuecommand(scp, NULL);
  703. wait_for_completion(&wait);
  704. rval = scp->SCp.Status;
  705. if (info)
  706. *info = scp->SCp.Message;
  707. kfree(scp);
  708. return rval;
  709. }
  710. #else
  711. static void gdth_scsi_done(Scsi_Cmnd *scp)
  712. {
  713. TRACE2(("gdth_scsi_done()\n"));
  714. scp->request.rq_status = RQ_SCSI_DONE;
  715. if (scp->request.waiting)
  716. complete(scp->request.waiting);
  717. }
  718. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  719. int timeout, u32 *info)
  720. {
  721. Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
  722. unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
  723. DECLARE_COMPLETION_ONSTACK(wait);
  724. int rval;
  725. if (!scp)
  726. return -ENOMEM;
  727. scp->cmd_len = 12;
  728. scp->use_sg = 0;
  729. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  730. scp->request.rq_status = RQ_SCSI_BUSY;
  731. scp->request.waiting = &wait;
  732. scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
  733. wait_for_completion(&wait);
  734. rval = scp->SCp.Status;
  735. if (info)
  736. *info = scp->SCp.Message;
  737. scsi_release_command(scp);
  738. return rval;
  739. }
  740. #endif
  741. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  742. int timeout, u32 *info)
  743. {
  744. struct scsi_device *sdev = scsi_get_host_dev(shost);
  745. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  746. scsi_free_host_dev(sdev);
  747. return rval;
  748. }
  749. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  750. {
  751. *cyls = size /HEADS/SECS;
  752. if (*cyls <= MAXCYLS) {
  753. *heads = HEADS;
  754. *secs = SECS;
  755. } else { /* too high for 64*32 */
  756. *cyls = size /MEDHEADS/MEDSECS;
  757. if (*cyls <= MAXCYLS) {
  758. *heads = MEDHEADS;
  759. *secs = MEDSECS;
  760. } else { /* too high for 127*63 */
  761. *cyls = size /BIGHEADS/BIGSECS;
  762. *heads = BIGHEADS;
  763. *secs = BIGSECS;
  764. }
  765. }
  766. }
  767. /* controller search and initialization functions */
  768. #ifdef CONFIG_EISA
  769. static int __init gdth_search_eisa(ushort eisa_adr)
  770. {
  771. ulong32 id;
  772. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  773. id = inl(eisa_adr+ID0REG);
  774. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  775. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  776. return 0; /* not EISA configured */
  777. return 1;
  778. }
  779. if (id == GDT3_ID) /* GDT3000 */
  780. return 1;
  781. return 0;
  782. }
  783. #endif /* CONFIG_EISA */
  784. #ifdef CONFIG_ISA
  785. static int __init gdth_search_isa(ulong32 bios_adr)
  786. {
  787. void __iomem *addr;
  788. ulong32 id;
  789. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  790. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  791. id = gdth_readl(addr);
  792. iounmap(addr);
  793. if (id == GDT2_ID) /* GDT2000 */
  794. return 1;
  795. }
  796. return 0;
  797. }
  798. #endif /* CONFIG_ISA */
  799. #ifdef CONFIG_PCI
  800. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  801. ushort vendor, ushort dev);
  802. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  803. {
  804. ushort device, cnt;
  805. TRACE(("gdth_search_pci()\n"));
  806. cnt = 0;
  807. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  808. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  809. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  810. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  811. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  812. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  813. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  814. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  815. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  816. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  817. PCI_DEVICE_ID_INTEL_SRC);
  818. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  819. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  820. return cnt;
  821. }
  822. /* Vortex only makes RAID controllers.
  823. * We do not really want to specify all 550 ids here, so wildcard match.
  824. */
  825. static struct pci_device_id gdthtable[] __maybe_unused = {
  826. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  827. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  828. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  829. {0}
  830. };
  831. MODULE_DEVICE_TABLE(pci,gdthtable);
  832. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  833. ushort vendor, ushort device)
  834. {
  835. ulong base0, base1, base2;
  836. struct pci_dev *pdev;
  837. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  838. *cnt, vendor, device));
  839. pdev = NULL;
  840. while ((pdev = pci_find_device(vendor, device, pdev))
  841. != NULL) {
  842. if (pci_enable_device(pdev))
  843. continue;
  844. if (*cnt >= MAXHA)
  845. return;
  846. /* GDT PCI controller found, resources are already in pdev */
  847. pcistr[*cnt].pdev = pdev;
  848. pcistr[*cnt].irq = pdev->irq;
  849. base0 = pci_resource_flags(pdev, 0);
  850. base1 = pci_resource_flags(pdev, 1);
  851. base2 = pci_resource_flags(pdev, 2);
  852. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  853. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  854. if (!(base0 & IORESOURCE_MEM))
  855. continue;
  856. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  857. } else { /* GDT6110, GDT6120, .. */
  858. if (!(base0 & IORESOURCE_MEM) ||
  859. !(base2 & IORESOURCE_MEM) ||
  860. !(base1 & IORESOURCE_IO))
  861. continue;
  862. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  863. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  864. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  865. }
  866. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  867. pcistr[*cnt].pdev->bus->number,
  868. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  869. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  870. (*cnt)++;
  871. }
  872. }
  873. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  874. {
  875. gdth_pci_str temp;
  876. int i, changed;
  877. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  878. if (cnt == 0)
  879. return;
  880. do {
  881. changed = FALSE;
  882. for (i = 0; i < cnt-1; ++i) {
  883. if (!reverse_scan) {
  884. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  885. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  886. PCI_SLOT(pcistr[i].pdev->devfn) >
  887. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  888. temp = pcistr[i];
  889. pcistr[i] = pcistr[i+1];
  890. pcistr[i+1] = temp;
  891. changed = TRUE;
  892. }
  893. } else {
  894. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  895. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  896. PCI_SLOT(pcistr[i].pdev->devfn) <
  897. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  898. temp = pcistr[i];
  899. pcistr[i] = pcistr[i+1];
  900. pcistr[i+1] = temp;
  901. changed = TRUE;
  902. }
  903. }
  904. }
  905. } while (changed);
  906. }
  907. #endif /* CONFIG_PCI */
  908. #ifdef CONFIG_EISA
  909. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  910. {
  911. ulong32 retries,id;
  912. unchar prot_ver,eisacf,i,irq_found;
  913. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  914. /* disable board interrupts, deinitialize services */
  915. outb(0xff,eisa_adr+EDOORREG);
  916. outb(0x00,eisa_adr+EDENABREG);
  917. outb(0x00,eisa_adr+EINTENABREG);
  918. outb(0xff,eisa_adr+LDOORREG);
  919. retries = INIT_RETRIES;
  920. gdth_delay(20);
  921. while (inb(eisa_adr+EDOORREG) != 0xff) {
  922. if (--retries == 0) {
  923. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  924. return 0;
  925. }
  926. gdth_delay(1);
  927. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  928. }
  929. prot_ver = inb(eisa_adr+MAILBOXREG);
  930. outb(0xff,eisa_adr+EDOORREG);
  931. if (prot_ver != PROTOCOL_VERSION) {
  932. printk("GDT-EISA: Illegal protocol version\n");
  933. return 0;
  934. }
  935. ha->bmic = eisa_adr;
  936. ha->brd_phys = (ulong32)eisa_adr >> 12;
  937. outl(0,eisa_adr+MAILBOXREG);
  938. outl(0,eisa_adr+MAILBOXREG+4);
  939. outl(0,eisa_adr+MAILBOXREG+8);
  940. outl(0,eisa_adr+MAILBOXREG+12);
  941. /* detect IRQ */
  942. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  943. ha->oem_id = OEM_ID_ICP;
  944. ha->type = GDT_EISA;
  945. ha->stype = id;
  946. outl(1,eisa_adr+MAILBOXREG+8);
  947. outb(0xfe,eisa_adr+LDOORREG);
  948. retries = INIT_RETRIES;
  949. gdth_delay(20);
  950. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  951. if (--retries == 0) {
  952. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  953. return 0;
  954. }
  955. gdth_delay(1);
  956. }
  957. ha->irq = inb(eisa_adr+MAILBOXREG);
  958. outb(0xff,eisa_adr+EDOORREG);
  959. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  960. /* check the result */
  961. if (ha->irq == 0) {
  962. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  963. for (i = 0, irq_found = FALSE;
  964. i < MAXHA && irq[i] != 0xff; ++i) {
  965. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  966. irq_found = TRUE;
  967. break;
  968. }
  969. }
  970. if (irq_found) {
  971. ha->irq = irq[i];
  972. irq[i] = 0;
  973. printk("GDT-EISA: Can not detect controller IRQ,\n");
  974. printk("Use IRQ setting from command line (IRQ = %d)\n",
  975. ha->irq);
  976. } else {
  977. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  978. printk("the controller BIOS or use command line parameters\n");
  979. return 0;
  980. }
  981. }
  982. } else {
  983. eisacf = inb(eisa_adr+EISAREG) & 7;
  984. if (eisacf > 4) /* level triggered */
  985. eisacf -= 4;
  986. ha->irq = gdth_irq_tab[eisacf];
  987. ha->oem_id = OEM_ID_ICP;
  988. ha->type = GDT_EISA;
  989. ha->stype = id;
  990. }
  991. ha->dma64_support = 0;
  992. return 1;
  993. }
  994. #endif /* CONFIG_EISA */
  995. #ifdef CONFIG_ISA
  996. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  997. {
  998. register gdt2_dpram_str __iomem *dp2_ptr;
  999. int i;
  1000. unchar irq_drq,prot_ver;
  1001. ulong32 retries;
  1002. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  1003. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  1004. if (ha->brd == NULL) {
  1005. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  1006. return 0;
  1007. }
  1008. dp2_ptr = ha->brd;
  1009. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  1010. /* reset interface area */
  1011. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  1012. if (gdth_readl(&dp2_ptr->u) != 0) {
  1013. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  1014. iounmap(ha->brd);
  1015. return 0;
  1016. }
  1017. /* disable board interrupts, read DRQ and IRQ */
  1018. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1019. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  1020. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  1021. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  1022. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  1023. for (i=0; i<3; ++i) {
  1024. if ((irq_drq & 1)==0)
  1025. break;
  1026. irq_drq >>= 1;
  1027. }
  1028. ha->drq = gdth_drq_tab[i];
  1029. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  1030. for (i=1; i<5; ++i) {
  1031. if ((irq_drq & 1)==0)
  1032. break;
  1033. irq_drq >>= 1;
  1034. }
  1035. ha->irq = gdth_irq_tab[i];
  1036. /* deinitialize services */
  1037. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  1038. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  1039. gdth_writeb(0, &dp2_ptr->io.event);
  1040. retries = INIT_RETRIES;
  1041. gdth_delay(20);
  1042. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  1043. if (--retries == 0) {
  1044. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  1045. iounmap(ha->brd);
  1046. return 0;
  1047. }
  1048. gdth_delay(1);
  1049. }
  1050. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  1051. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1052. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1053. if (prot_ver != PROTOCOL_VERSION) {
  1054. printk("GDT-ISA: Illegal protocol version\n");
  1055. iounmap(ha->brd);
  1056. return 0;
  1057. }
  1058. ha->oem_id = OEM_ID_ICP;
  1059. ha->type = GDT_ISA;
  1060. ha->ic_all_size = sizeof(dp2_ptr->u);
  1061. ha->stype= GDT2_ID;
  1062. ha->brd_phys = bios_adr >> 4;
  1063. /* special request to controller BIOS */
  1064. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  1065. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  1066. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  1067. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  1068. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  1069. gdth_writeb(0, &dp2_ptr->io.event);
  1070. retries = INIT_RETRIES;
  1071. gdth_delay(20);
  1072. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  1073. if (--retries == 0) {
  1074. printk("GDT-ISA: Initialization error\n");
  1075. iounmap(ha->brd);
  1076. return 0;
  1077. }
  1078. gdth_delay(1);
  1079. }
  1080. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1081. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1082. ha->dma64_support = 0;
  1083. return 1;
  1084. }
  1085. #endif /* CONFIG_ISA */
  1086. #ifdef CONFIG_PCI
  1087. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  1088. {
  1089. register gdt6_dpram_str __iomem *dp6_ptr;
  1090. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1091. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1092. ulong32 retries;
  1093. unchar prot_ver;
  1094. ushort command;
  1095. int i, found = FALSE;
  1096. TRACE(("gdth_init_pci()\n"));
  1097. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  1098. ha->oem_id = OEM_ID_INTEL;
  1099. else
  1100. ha->oem_id = OEM_ID_ICP;
  1101. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  1102. ha->stype = (ulong32)pcistr->pdev->device;
  1103. ha->irq = pcistr->irq;
  1104. ha->pdev = pcistr->pdev;
  1105. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  1106. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1107. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  1108. if (ha->brd == NULL) {
  1109. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1110. return 0;
  1111. }
  1112. /* check and reset interface area */
  1113. dp6_ptr = ha->brd;
  1114. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1115. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1116. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1117. pcistr->dpmem);
  1118. found = FALSE;
  1119. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1120. iounmap(ha->brd);
  1121. ha->brd = ioremap(i, sizeof(ushort));
  1122. if (ha->brd == NULL) {
  1123. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1124. return 0;
  1125. }
  1126. if (gdth_readw(ha->brd) != 0xffff) {
  1127. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1128. continue;
  1129. }
  1130. iounmap(ha->brd);
  1131. pci_write_config_dword(pcistr->pdev,
  1132. PCI_BASE_ADDRESS_0, i);
  1133. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1134. if (ha->brd == NULL) {
  1135. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1136. return 0;
  1137. }
  1138. dp6_ptr = ha->brd;
  1139. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1140. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1141. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1142. found = TRUE;
  1143. break;
  1144. }
  1145. }
  1146. if (!found) {
  1147. printk("GDT-PCI: No free address found!\n");
  1148. iounmap(ha->brd);
  1149. return 0;
  1150. }
  1151. }
  1152. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1153. if (gdth_readl(&dp6_ptr->u) != 0) {
  1154. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1155. iounmap(ha->brd);
  1156. return 0;
  1157. }
  1158. /* disable board interrupts, deinit services */
  1159. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1160. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1161. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1162. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1163. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1164. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1165. gdth_writeb(0, &dp6_ptr->io.event);
  1166. retries = INIT_RETRIES;
  1167. gdth_delay(20);
  1168. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1169. if (--retries == 0) {
  1170. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1171. iounmap(ha->brd);
  1172. return 0;
  1173. }
  1174. gdth_delay(1);
  1175. }
  1176. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1177. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1178. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1179. if (prot_ver != PROTOCOL_VERSION) {
  1180. printk("GDT-PCI: Illegal protocol version\n");
  1181. iounmap(ha->brd);
  1182. return 0;
  1183. }
  1184. ha->type = GDT_PCI;
  1185. ha->ic_all_size = sizeof(dp6_ptr->u);
  1186. /* special command to controller BIOS */
  1187. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1188. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1189. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1190. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1191. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1192. gdth_writeb(0, &dp6_ptr->io.event);
  1193. retries = INIT_RETRIES;
  1194. gdth_delay(20);
  1195. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1196. if (--retries == 0) {
  1197. printk("GDT-PCI: Initialization error\n");
  1198. iounmap(ha->brd);
  1199. return 0;
  1200. }
  1201. gdth_delay(1);
  1202. }
  1203. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1204. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1205. ha->dma64_support = 0;
  1206. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1207. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1208. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1209. pcistr->dpmem,ha->irq));
  1210. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1211. if (ha->brd == NULL) {
  1212. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1213. iounmap(ha->brd);
  1214. return 0;
  1215. }
  1216. /* check and reset interface area */
  1217. dp6c_ptr = ha->brd;
  1218. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1219. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1220. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1221. pcistr->dpmem);
  1222. found = FALSE;
  1223. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1224. iounmap(ha->brd);
  1225. ha->brd = ioremap(i, sizeof(ushort));
  1226. if (ha->brd == NULL) {
  1227. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1228. return 0;
  1229. }
  1230. if (gdth_readw(ha->brd) != 0xffff) {
  1231. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1232. continue;
  1233. }
  1234. iounmap(ha->brd);
  1235. pci_write_config_dword(pcistr->pdev,
  1236. PCI_BASE_ADDRESS_2, i);
  1237. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1238. if (ha->brd == NULL) {
  1239. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1240. return 0;
  1241. }
  1242. dp6c_ptr = ha->brd;
  1243. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1244. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1245. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1246. found = TRUE;
  1247. break;
  1248. }
  1249. }
  1250. if (!found) {
  1251. printk("GDT-PCI: No free address found!\n");
  1252. iounmap(ha->brd);
  1253. return 0;
  1254. }
  1255. }
  1256. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1257. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1258. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1259. iounmap(ha->brd);
  1260. return 0;
  1261. }
  1262. /* disable board interrupts, deinit services */
  1263. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1264. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1265. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1266. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1267. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1268. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1269. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1270. retries = INIT_RETRIES;
  1271. gdth_delay(20);
  1272. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1273. if (--retries == 0) {
  1274. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1275. iounmap(ha->brd);
  1276. return 0;
  1277. }
  1278. gdth_delay(1);
  1279. }
  1280. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1281. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1282. if (prot_ver != PROTOCOL_VERSION) {
  1283. printk("GDT-PCI: Illegal protocol version\n");
  1284. iounmap(ha->brd);
  1285. return 0;
  1286. }
  1287. ha->type = GDT_PCINEW;
  1288. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1289. /* special command to controller BIOS */
  1290. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1291. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1292. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1293. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1294. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1295. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1296. retries = INIT_RETRIES;
  1297. gdth_delay(20);
  1298. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1299. if (--retries == 0) {
  1300. printk("GDT-PCI: Initialization error\n");
  1301. iounmap(ha->brd);
  1302. return 0;
  1303. }
  1304. gdth_delay(1);
  1305. }
  1306. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1307. ha->dma64_support = 0;
  1308. } else { /* MPR */
  1309. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1310. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1311. if (ha->brd == NULL) {
  1312. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1313. return 0;
  1314. }
  1315. /* manipulate config. space to enable DPMEM, start RP controller */
  1316. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1317. command |= 6;
  1318. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1319. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1320. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1321. i = 0xFEFF0001UL;
  1322. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1323. gdth_delay(1);
  1324. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1325. pci_resource_start(pcistr->pdev, 8));
  1326. dp6m_ptr = ha->brd;
  1327. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1328. * Aditional check needed for Xscale based RAID controllers */
  1329. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1330. gdth_delay(1);
  1331. /* check and reset interface area */
  1332. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1333. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1334. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1335. pcistr->dpmem);
  1336. found = FALSE;
  1337. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1338. iounmap(ha->brd);
  1339. ha->brd = ioremap(i, sizeof(ushort));
  1340. if (ha->brd == NULL) {
  1341. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1342. return 0;
  1343. }
  1344. if (gdth_readw(ha->brd) != 0xffff) {
  1345. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1346. continue;
  1347. }
  1348. iounmap(ha->brd);
  1349. pci_write_config_dword(pcistr->pdev,
  1350. PCI_BASE_ADDRESS_0, i);
  1351. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1352. if (ha->brd == NULL) {
  1353. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1354. return 0;
  1355. }
  1356. dp6m_ptr = ha->brd;
  1357. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1358. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1359. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1360. found = TRUE;
  1361. break;
  1362. }
  1363. }
  1364. if (!found) {
  1365. printk("GDT-PCI: No free address found!\n");
  1366. iounmap(ha->brd);
  1367. return 0;
  1368. }
  1369. }
  1370. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1371. /* disable board interrupts, deinit services */
  1372. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1373. &dp6m_ptr->i960r.edoor_en_reg);
  1374. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1375. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1376. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1377. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1378. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1379. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1380. retries = INIT_RETRIES;
  1381. gdth_delay(20);
  1382. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1383. if (--retries == 0) {
  1384. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1385. iounmap(ha->brd);
  1386. return 0;
  1387. }
  1388. gdth_delay(1);
  1389. }
  1390. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1391. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1392. if (prot_ver != PROTOCOL_VERSION) {
  1393. printk("GDT-PCI: Illegal protocol version\n");
  1394. iounmap(ha->brd);
  1395. return 0;
  1396. }
  1397. ha->type = GDT_PCIMPR;
  1398. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1399. /* special command to controller BIOS */
  1400. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1401. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1402. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1403. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1404. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1405. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1406. retries = INIT_RETRIES;
  1407. gdth_delay(20);
  1408. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1409. if (--retries == 0) {
  1410. printk("GDT-PCI: Initialization error\n");
  1411. iounmap(ha->brd);
  1412. return 0;
  1413. }
  1414. gdth_delay(1);
  1415. }
  1416. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1417. /* read FW version to detect 64-bit DMA support */
  1418. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1419. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1420. retries = INIT_RETRIES;
  1421. gdth_delay(20);
  1422. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1423. if (--retries == 0) {
  1424. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1425. iounmap(ha->brd);
  1426. return 0;
  1427. }
  1428. gdth_delay(1);
  1429. }
  1430. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1431. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1432. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1433. ha->dma64_support = 0;
  1434. else
  1435. ha->dma64_support = 1;
  1436. }
  1437. return 1;
  1438. }
  1439. #endif /* CONFIG_PCI */
  1440. /* controller protocol functions */
  1441. static void __init gdth_enable_int(int hanum)
  1442. {
  1443. gdth_ha_str *ha;
  1444. ulong flags;
  1445. gdt2_dpram_str __iomem *dp2_ptr;
  1446. gdt6_dpram_str __iomem *dp6_ptr;
  1447. gdt6m_dpram_str __iomem *dp6m_ptr;
  1448. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1449. ha = HADATA(gdth_ctr_tab[hanum]);
  1450. spin_lock_irqsave(&ha->smp_lock, flags);
  1451. if (ha->type == GDT_EISA) {
  1452. outb(0xff, ha->bmic + EDOORREG);
  1453. outb(0xff, ha->bmic + EDENABREG);
  1454. outb(0x01, ha->bmic + EINTENABREG);
  1455. } else if (ha->type == GDT_ISA) {
  1456. dp2_ptr = ha->brd;
  1457. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1458. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1459. gdth_writeb(1, &dp2_ptr->io.irqen);
  1460. } else if (ha->type == GDT_PCI) {
  1461. dp6_ptr = ha->brd;
  1462. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1463. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1464. gdth_writeb(1, &dp6_ptr->io.irqen);
  1465. } else if (ha->type == GDT_PCINEW) {
  1466. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1467. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1468. } else if (ha->type == GDT_PCIMPR) {
  1469. dp6m_ptr = ha->brd;
  1470. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1471. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1472. &dp6m_ptr->i960r.edoor_en_reg);
  1473. }
  1474. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1475. }
  1476. static int gdth_get_status(unchar *pIStatus,int irq)
  1477. {
  1478. register gdth_ha_str *ha;
  1479. int i;
  1480. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1481. irq,gdth_ctr_count));
  1482. *pIStatus = 0;
  1483. for (i=0; i<gdth_ctr_count; ++i) {
  1484. ha = HADATA(gdth_ctr_tab[i]);
  1485. if (ha->irq != (unchar)irq) /* check IRQ */
  1486. continue;
  1487. if (ha->type == GDT_EISA)
  1488. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1489. else if (ha->type == GDT_ISA)
  1490. *pIStatus =
  1491. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1492. else if (ha->type == GDT_PCI)
  1493. *pIStatus =
  1494. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1495. else if (ha->type == GDT_PCINEW)
  1496. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1497. else if (ha->type == GDT_PCIMPR)
  1498. *pIStatus =
  1499. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1500. if (*pIStatus)
  1501. return i; /* board found */
  1502. }
  1503. return -1;
  1504. }
  1505. static int gdth_test_busy(int hanum)
  1506. {
  1507. register gdth_ha_str *ha;
  1508. register int gdtsema0 = 0;
  1509. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1510. ha = HADATA(gdth_ctr_tab[hanum]);
  1511. if (ha->type == GDT_EISA)
  1512. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1513. else if (ha->type == GDT_ISA)
  1514. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1515. else if (ha->type == GDT_PCI)
  1516. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1517. else if (ha->type == GDT_PCINEW)
  1518. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1519. else if (ha->type == GDT_PCIMPR)
  1520. gdtsema0 =
  1521. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1522. return (gdtsema0 & 1);
  1523. }
  1524. static int gdth_get_cmd_index(int hanum)
  1525. {
  1526. register gdth_ha_str *ha;
  1527. int i;
  1528. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1529. ha = HADATA(gdth_ctr_tab[hanum]);
  1530. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1531. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1532. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1533. ha->cmd_tab[i].service = ha->pccb->Service;
  1534. ha->pccb->CommandIndex = (ulong32)i+2;
  1535. return (i+2);
  1536. }
  1537. }
  1538. return 0;
  1539. }
  1540. static void gdth_set_sema0(int hanum)
  1541. {
  1542. register gdth_ha_str *ha;
  1543. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1544. ha = HADATA(gdth_ctr_tab[hanum]);
  1545. if (ha->type == GDT_EISA) {
  1546. outb(1, ha->bmic + SEMA0REG);
  1547. } else if (ha->type == GDT_ISA) {
  1548. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1549. } else if (ha->type == GDT_PCI) {
  1550. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1551. } else if (ha->type == GDT_PCINEW) {
  1552. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1553. } else if (ha->type == GDT_PCIMPR) {
  1554. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1555. }
  1556. }
  1557. static void gdth_copy_command(int hanum)
  1558. {
  1559. register gdth_ha_str *ha;
  1560. register gdth_cmd_str *cmd_ptr;
  1561. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1562. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1563. gdt6_dpram_str __iomem *dp6_ptr;
  1564. gdt2_dpram_str __iomem *dp2_ptr;
  1565. ushort cp_count,dp_offset,cmd_no;
  1566. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1567. ha = HADATA(gdth_ctr_tab[hanum]);
  1568. cp_count = ha->cmd_len;
  1569. dp_offset= ha->cmd_offs_dpmem;
  1570. cmd_no = ha->cmd_cnt;
  1571. cmd_ptr = ha->pccb;
  1572. ++ha->cmd_cnt;
  1573. if (ha->type == GDT_EISA)
  1574. return; /* no DPMEM, no copy */
  1575. /* set cpcount dword aligned */
  1576. if (cp_count & 3)
  1577. cp_count += (4 - (cp_count & 3));
  1578. ha->cmd_offs_dpmem += cp_count;
  1579. /* set offset and service, copy command to DPMEM */
  1580. if (ha->type == GDT_ISA) {
  1581. dp2_ptr = ha->brd;
  1582. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1583. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1584. gdth_writew((ushort)cmd_ptr->Service,
  1585. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1586. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1587. } else if (ha->type == GDT_PCI) {
  1588. dp6_ptr = ha->brd;
  1589. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1590. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1591. gdth_writew((ushort)cmd_ptr->Service,
  1592. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1593. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1594. } else if (ha->type == GDT_PCINEW) {
  1595. dp6c_ptr = ha->brd;
  1596. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1597. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1598. gdth_writew((ushort)cmd_ptr->Service,
  1599. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1600. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1601. } else if (ha->type == GDT_PCIMPR) {
  1602. dp6m_ptr = ha->brd;
  1603. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1604. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1605. gdth_writew((ushort)cmd_ptr->Service,
  1606. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1607. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1608. }
  1609. }
  1610. static void gdth_release_event(int hanum)
  1611. {
  1612. register gdth_ha_str *ha;
  1613. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1614. ha = HADATA(gdth_ctr_tab[hanum]);
  1615. #ifdef GDTH_STATISTICS
  1616. {
  1617. ulong32 i,j;
  1618. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1619. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1620. ++i;
  1621. }
  1622. if (max_index < i) {
  1623. max_index = i;
  1624. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1625. }
  1626. }
  1627. #endif
  1628. if (ha->pccb->OpCode == GDT_INIT)
  1629. ha->pccb->Service |= 0x80;
  1630. if (ha->type == GDT_EISA) {
  1631. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1632. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1633. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1634. } else if (ha->type == GDT_ISA) {
  1635. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1636. } else if (ha->type == GDT_PCI) {
  1637. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1638. } else if (ha->type == GDT_PCINEW) {
  1639. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1640. } else if (ha->type == GDT_PCIMPR) {
  1641. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1642. }
  1643. }
  1644. static int gdth_wait(int hanum,int index,ulong32 time)
  1645. {
  1646. gdth_ha_str *ha;
  1647. int answer_found = FALSE;
  1648. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1649. ha = HADATA(gdth_ctr_tab[hanum]);
  1650. if (index == 0)
  1651. return 1; /* no wait required */
  1652. gdth_from_wait = TRUE;
  1653. do {
  1654. gdth_interrupt((int)ha->irq,ha);
  1655. if (wait_hanum==hanum && wait_index==index) {
  1656. answer_found = TRUE;
  1657. break;
  1658. }
  1659. gdth_delay(1);
  1660. } while (--time);
  1661. gdth_from_wait = FALSE;
  1662. while (gdth_test_busy(hanum))
  1663. gdth_delay(0);
  1664. return (answer_found);
  1665. }
  1666. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1667. ulong64 p2,ulong64 p3)
  1668. {
  1669. register gdth_ha_str *ha;
  1670. register gdth_cmd_str *cmd_ptr;
  1671. int retries,index;
  1672. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1673. ha = HADATA(gdth_ctr_tab[hanum]);
  1674. cmd_ptr = ha->pccb;
  1675. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1676. /* make command */
  1677. for (retries = INIT_RETRIES;;) {
  1678. cmd_ptr->Service = service;
  1679. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1680. if (!(index=gdth_get_cmd_index(hanum))) {
  1681. TRACE(("GDT: No free command index found\n"));
  1682. return 0;
  1683. }
  1684. gdth_set_sema0(hanum);
  1685. cmd_ptr->OpCode = opcode;
  1686. cmd_ptr->BoardNode = LOCALBOARD;
  1687. if (service == CACHESERVICE) {
  1688. if (opcode == GDT_IOCTL) {
  1689. cmd_ptr->u.ioctl.subfunc = p1;
  1690. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1691. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1692. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1693. } else {
  1694. if (ha->cache_feat & GDT_64BIT) {
  1695. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1696. cmd_ptr->u.cache64.BlockNo = p2;
  1697. } else {
  1698. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1699. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1700. }
  1701. }
  1702. } else if (service == SCSIRAWSERVICE) {
  1703. if (ha->raw_feat & GDT_64BIT) {
  1704. cmd_ptr->u.raw64.direction = p1;
  1705. cmd_ptr->u.raw64.bus = (unchar)p2;
  1706. cmd_ptr->u.raw64.target = (unchar)p3;
  1707. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1708. } else {
  1709. cmd_ptr->u.raw.direction = p1;
  1710. cmd_ptr->u.raw.bus = (unchar)p2;
  1711. cmd_ptr->u.raw.target = (unchar)p3;
  1712. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1713. }
  1714. } else if (service == SCREENSERVICE) {
  1715. if (opcode == GDT_REALTIME) {
  1716. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1717. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1718. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1719. }
  1720. }
  1721. ha->cmd_len = sizeof(gdth_cmd_str);
  1722. ha->cmd_offs_dpmem = 0;
  1723. ha->cmd_cnt = 0;
  1724. gdth_copy_command(hanum);
  1725. gdth_release_event(hanum);
  1726. gdth_delay(20);
  1727. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1728. printk("GDT: Initialization error (timeout service %d)\n",service);
  1729. return 0;
  1730. }
  1731. if (ha->status != S_BSY || --retries == 0)
  1732. break;
  1733. gdth_delay(1);
  1734. }
  1735. return (ha->status != S_OK ? 0:1);
  1736. }
  1737. /* search for devices */
  1738. static int __init gdth_search_drives(int hanum)
  1739. {
  1740. register gdth_ha_str *ha;
  1741. ushort cdev_cnt, i;
  1742. int ok;
  1743. ulong32 bus_no, drv_cnt, drv_no, j;
  1744. gdth_getch_str *chn;
  1745. gdth_drlist_str *drl;
  1746. gdth_iochan_str *ioc;
  1747. gdth_raw_iochan_str *iocr;
  1748. gdth_arcdl_str *alst;
  1749. gdth_alist_str *alst2;
  1750. gdth_oem_str_ioctl *oemstr;
  1751. #ifdef INT_COAL
  1752. gdth_perf_modes *pmod;
  1753. #endif
  1754. #ifdef GDTH_RTC
  1755. unchar rtc[12];
  1756. ulong flags;
  1757. #endif
  1758. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1759. ha = HADATA(gdth_ctr_tab[hanum]);
  1760. ok = 0;
  1761. /* initialize controller services, at first: screen service */
  1762. ha->screen_feat = 0;
  1763. if (!force_dma32) {
  1764. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1765. if (ok)
  1766. ha->screen_feat = GDT_64BIT;
  1767. }
  1768. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1769. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1770. if (!ok) {
  1771. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1772. hanum, ha->status);
  1773. return 0;
  1774. }
  1775. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1776. #ifdef GDTH_RTC
  1777. /* read realtime clock info, send to controller */
  1778. /* 1. wait for the falling edge of update flag */
  1779. spin_lock_irqsave(&rtc_lock, flags);
  1780. for (j = 0; j < 1000000; ++j)
  1781. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1782. break;
  1783. for (j = 0; j < 1000000; ++j)
  1784. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1785. break;
  1786. /* 2. read info */
  1787. do {
  1788. for (j = 0; j < 12; ++j)
  1789. rtc[j] = CMOS_READ(j);
  1790. } while (rtc[0] != CMOS_READ(0));
  1791. spin_unlock_irqrestore(&rtc_lock, flags);
  1792. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1793. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1794. /* 3. send to controller firmware */
  1795. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1796. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1797. #endif
  1798. /* unfreeze all IOs */
  1799. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1800. /* initialize cache service */
  1801. ha->cache_feat = 0;
  1802. if (!force_dma32) {
  1803. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1804. if (ok)
  1805. ha->cache_feat = GDT_64BIT;
  1806. }
  1807. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1808. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1809. if (!ok) {
  1810. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1811. hanum, ha->status);
  1812. return 0;
  1813. }
  1814. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1815. cdev_cnt = (ushort)ha->info;
  1816. ha->fw_vers = ha->service;
  1817. #ifdef INT_COAL
  1818. if (ha->type == GDT_PCIMPR) {
  1819. /* set perf. modes */
  1820. pmod = (gdth_perf_modes *)ha->pscratch;
  1821. pmod->version = 1;
  1822. pmod->st_mode = 1; /* enable one status buffer */
  1823. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1824. pmod->st_buff_indx1 = COALINDEX;
  1825. pmod->st_buff_addr2 = 0;
  1826. pmod->st_buff_u_addr2 = 0;
  1827. pmod->st_buff_indx2 = 0;
  1828. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1829. pmod->cmd_mode = 0; // disable all cmd buffers
  1830. pmod->cmd_buff_addr1 = 0;
  1831. pmod->cmd_buff_u_addr1 = 0;
  1832. pmod->cmd_buff_indx1 = 0;
  1833. pmod->cmd_buff_addr2 = 0;
  1834. pmod->cmd_buff_u_addr2 = 0;
  1835. pmod->cmd_buff_indx2 = 0;
  1836. pmod->cmd_buff_size = 0;
  1837. pmod->reserved1 = 0;
  1838. pmod->reserved2 = 0;
  1839. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1840. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1841. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1842. }
  1843. }
  1844. #endif
  1845. /* detect number of buses - try new IOCTL */
  1846. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1847. iocr->hdr.version = 0xffffffff;
  1848. iocr->hdr.list_entries = MAXBUS;
  1849. iocr->hdr.first_chan = 0;
  1850. iocr->hdr.last_chan = MAXBUS-1;
  1851. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1852. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1853. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1854. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1855. ha->bus_cnt = iocr->hdr.chan_count;
  1856. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1857. if (iocr->list[bus_no].proc_id < MAXID)
  1858. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1859. else
  1860. ha->bus_id[bus_no] = 0xff;
  1861. }
  1862. } else {
  1863. /* old method */
  1864. chn = (gdth_getch_str *)ha->pscratch;
  1865. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1866. chn->channel_no = bus_no;
  1867. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1868. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1869. IO_CHANNEL | INVALID_CHANNEL,
  1870. sizeof(gdth_getch_str))) {
  1871. if (bus_no == 0) {
  1872. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1873. hanum, ha->status);
  1874. return 0;
  1875. }
  1876. break;
  1877. }
  1878. if (chn->siop_id < MAXID)
  1879. ha->bus_id[bus_no] = chn->siop_id;
  1880. else
  1881. ha->bus_id[bus_no] = 0xff;
  1882. }
  1883. ha->bus_cnt = (unchar)bus_no;
  1884. }
  1885. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1886. /* read cache configuration */
  1887. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1888. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1889. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1890. hanum, ha->status);
  1891. return 0;
  1892. }
  1893. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1894. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1895. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1896. ha->cpar.write_back,ha->cpar.block_size));
  1897. /* read board info and features */
  1898. ha->more_proc = FALSE;
  1899. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1900. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1901. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1902. sizeof(gdth_binfo_str));
  1903. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1904. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1905. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1906. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1907. ha->more_proc = TRUE;
  1908. }
  1909. } else {
  1910. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1911. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1912. }
  1913. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1914. /* read more informations */
  1915. if (ha->more_proc) {
  1916. /* physical drives, channel addresses */
  1917. ioc = (gdth_iochan_str *)ha->pscratch;
  1918. ioc->hdr.version = 0xffffffff;
  1919. ioc->hdr.list_entries = MAXBUS;
  1920. ioc->hdr.first_chan = 0;
  1921. ioc->hdr.last_chan = MAXBUS-1;
  1922. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1923. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1924. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1925. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1926. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1927. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1928. }
  1929. } else {
  1930. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1931. ha->raw[bus_no].address = IO_CHANNEL;
  1932. ha->raw[bus_no].local_no = bus_no;
  1933. }
  1934. }
  1935. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1936. chn = (gdth_getch_str *)ha->pscratch;
  1937. chn->channel_no = ha->raw[bus_no].local_no;
  1938. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1939. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1940. ha->raw[bus_no].address | INVALID_CHANNEL,
  1941. sizeof(gdth_getch_str))) {
  1942. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1943. TRACE2(("Channel %d: %d phys. drives\n",
  1944. bus_no,chn->drive_cnt));
  1945. }
  1946. if (ha->raw[bus_no].pdev_cnt > 0) {
  1947. drl = (gdth_drlist_str *)ha->pscratch;
  1948. drl->sc_no = ha->raw[bus_no].local_no;
  1949. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1950. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1951. SCSI_DR_LIST | L_CTRL_PATTERN,
  1952. ha->raw[bus_no].address | INVALID_CHANNEL,
  1953. sizeof(gdth_drlist_str))) {
  1954. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1955. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1956. } else {
  1957. ha->raw[bus_no].pdev_cnt = 0;
  1958. }
  1959. }
  1960. }
  1961. /* logical drives */
  1962. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1963. INVALID_CHANNEL,sizeof(ulong32))) {
  1964. drv_cnt = *(ulong32 *)ha->pscratch;
  1965. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1966. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1967. for (j = 0; j < drv_cnt; ++j) {
  1968. drv_no = ((ulong32 *)ha->pscratch)[j];
  1969. if (drv_no < MAX_LDRIVES) {
  1970. ha->hdr[drv_no].is_logdrv = TRUE;
  1971. TRACE2(("Drive %d is log. drive\n",drv_no));
  1972. }
  1973. }
  1974. }
  1975. alst = (gdth_arcdl_str *)ha->pscratch;
  1976. alst->entries_avail = MAX_LDRIVES;
  1977. alst->first_entry = 0;
  1978. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1979. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1980. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1981. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1982. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1983. for (j = 0; j < alst->entries_init; ++j) {
  1984. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1985. ha->hdr[j].is_master = alst->list[j].is_master;
  1986. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1987. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1988. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1989. }
  1990. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1991. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1992. 0, 35 * sizeof(gdth_alist_str))) {
  1993. for (j = 0; j < 35; ++j) {
  1994. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1995. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1996. ha->hdr[j].is_master = alst2->is_master;
  1997. ha->hdr[j].is_parity = alst2->is_parity;
  1998. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1999. ha->hdr[j].master_no = alst2->cd_handle;
  2000. }
  2001. }
  2002. }
  2003. }
  2004. /* initialize raw service */
  2005. ha->raw_feat = 0;
  2006. if (!force_dma32) {
  2007. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  2008. if (ok)
  2009. ha->raw_feat = GDT_64BIT;
  2010. }
  2011. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  2012. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  2013. if (!ok) {
  2014. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  2015. hanum, ha->status);
  2016. return 0;
  2017. }
  2018. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  2019. /* set/get features raw service (scatter/gather) */
  2020. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  2021. 0,0)) {
  2022. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  2023. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  2024. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  2025. ha->info));
  2026. ha->raw_feat |= (ushort)ha->info;
  2027. }
  2028. }
  2029. /* set/get features cache service (equal to raw service) */
  2030. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  2031. SCATTER_GATHER,0)) {
  2032. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  2033. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  2034. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  2035. ha->info));
  2036. ha->cache_feat |= (ushort)ha->info;
  2037. }
  2038. }
  2039. /* reserve drives for raw service */
  2040. if (reserve_mode != 0) {
  2041. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  2042. reserve_mode == 1 ? 1 : 3, 0, 0);
  2043. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  2044. ha->status));
  2045. }
  2046. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  2047. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  2048. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  2049. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  2050. reserve_list[i], reserve_list[i+1],
  2051. reserve_list[i+2], reserve_list[i+3]));
  2052. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  2053. reserve_list[i+1], reserve_list[i+2] |
  2054. (reserve_list[i+3] << 8))) {
  2055. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  2056. hanum, ha->status);
  2057. }
  2058. }
  2059. }
  2060. /* Determine OEM string using IOCTL */
  2061. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  2062. oemstr->params.ctl_version = 0x01;
  2063. oemstr->params.buffer_size = sizeof(oemstr->text);
  2064. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  2065. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  2066. sizeof(gdth_oem_str_ioctl))) {
  2067. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  2068. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  2069. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  2070. /* Save the Host Drive inquiry data */
  2071. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2072. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  2073. sizeof(ha->oem_name));
  2074. #else
  2075. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  2076. ha->oem_name[7] = '\0';
  2077. #endif
  2078. } else {
  2079. /* Old method, based on PCI ID */
  2080. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  2081. printk("GDT-HA %d: Name: %s\n",
  2082. hanum,ha->binfo.type_string);
  2083. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2084. if (ha->oem_id == OEM_ID_INTEL)
  2085. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  2086. else
  2087. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  2088. #else
  2089. if (ha->oem_id == OEM_ID_INTEL)
  2090. strcpy(ha->oem_name,"Intel ");
  2091. else
  2092. strcpy(ha->oem_name,"ICP ");
  2093. #endif
  2094. }
  2095. /* scanning for host drives */
  2096. for (i = 0; i < cdev_cnt; ++i)
  2097. gdth_analyse_hdrive(hanum,i);
  2098. TRACE(("gdth_search_drives() OK\n"));
  2099. return 1;
  2100. }
  2101. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  2102. {
  2103. register gdth_ha_str *ha;
  2104. ulong32 drv_cyls;
  2105. int drv_hds, drv_secs;
  2106. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  2107. if (hdrive >= MAX_HDRIVES)
  2108. return 0;
  2109. ha = HADATA(gdth_ctr_tab[hanum]);
  2110. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  2111. return 0;
  2112. ha->hdr[hdrive].present = TRUE;
  2113. ha->hdr[hdrive].size = ha->info;
  2114. /* evaluate mapping (sectors per head, heads per cylinder) */
  2115. ha->hdr[hdrive].size &= ~SECS32;
  2116. if (ha->info2 == 0) {
  2117. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2118. } else {
  2119. drv_hds = ha->info2 & 0xff;
  2120. drv_secs = (ha->info2 >> 8) & 0xff;
  2121. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2122. }
  2123. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2124. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2125. /* round size */
  2126. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2127. if (ha->cache_feat & GDT_64BIT) {
  2128. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2129. && ha->info2 != 0) {
  2130. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2131. }
  2132. }
  2133. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2134. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2135. /* get informations about device */
  2136. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2137. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2138. hdrive,ha->info));
  2139. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2140. }
  2141. /* cluster info */
  2142. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2143. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2144. hdrive,ha->info));
  2145. if (!shared_access)
  2146. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2147. }
  2148. /* R/W attributes */
  2149. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2150. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2151. hdrive,ha->info));
  2152. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2153. }
  2154. return 1;
  2155. }
  2156. /* command queueing/sending functions */
  2157. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2158. {
  2159. register gdth_ha_str *ha;
  2160. register Scsi_Cmnd *pscp;
  2161. register Scsi_Cmnd *nscp;
  2162. ulong flags;
  2163. unchar b, t;
  2164. TRACE(("gdth_putq() priority %d\n",priority));
  2165. ha = HADATA(gdth_ctr_tab[hanum]);
  2166. spin_lock_irqsave(&ha->smp_lock, flags);
  2167. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  2168. scp->SCp.this_residual = (int)priority;
  2169. b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
  2170. t = scp->device->id;
  2171. if (priority >= DEFAULT_PRI) {
  2172. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2173. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  2174. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  2175. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2176. }
  2177. }
  2178. }
  2179. if (ha->req_first==NULL) {
  2180. ha->req_first = scp; /* queue was empty */
  2181. scp->SCp.ptr = NULL;
  2182. } else { /* queue not empty */
  2183. pscp = ha->req_first;
  2184. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2185. /* priority: 0-highest,..,0xff-lowest */
  2186. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2187. pscp = nscp;
  2188. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2189. }
  2190. pscp->SCp.ptr = (char *)scp;
  2191. scp->SCp.ptr = (char *)nscp;
  2192. }
  2193. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2194. #ifdef GDTH_STATISTICS
  2195. flags = 0;
  2196. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2197. ++flags;
  2198. if (max_rq < flags) {
  2199. max_rq = flags;
  2200. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2201. }
  2202. #endif
  2203. }
  2204. static void gdth_next(int hanum)
  2205. {
  2206. register gdth_ha_str *ha;
  2207. register Scsi_Cmnd *pscp;
  2208. register Scsi_Cmnd *nscp;
  2209. unchar b, t, l, firsttime;
  2210. unchar this_cmd, next_cmd;
  2211. ulong flags = 0;
  2212. int cmd_index;
  2213. TRACE(("gdth_next() hanum %d\n",hanum));
  2214. ha = HADATA(gdth_ctr_tab[hanum]);
  2215. if (!gdth_polling)
  2216. spin_lock_irqsave(&ha->smp_lock, flags);
  2217. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2218. this_cmd = firsttime = TRUE;
  2219. next_cmd = gdth_polling ? FALSE:TRUE;
  2220. cmd_index = 0;
  2221. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2222. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2223. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2224. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  2225. b = virt_ctr ?
  2226. NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2227. t = nscp->device->id;
  2228. l = nscp->device->lun;
  2229. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2230. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2231. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2232. continue;
  2233. }
  2234. } else
  2235. b = t = l = 0;
  2236. if (firsttime) {
  2237. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2238. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2239. if (!gdth_polling) {
  2240. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2241. return;
  2242. }
  2243. while (gdth_test_busy(hanum))
  2244. gdth_delay(1);
  2245. }
  2246. firsttime = FALSE;
  2247. }
  2248. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  2249. if (nscp->SCp.phase == -1) {
  2250. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2251. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2252. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2253. b, t, l));
  2254. /* TEST_UNIT_READY -> set scan mode */
  2255. if ((ha->scan_mode & 0x0f) == 0) {
  2256. if (b == 0 && t == 0 && l == 0) {
  2257. ha->scan_mode |= 1;
  2258. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2259. }
  2260. } else if ((ha->scan_mode & 0x0f) == 1) {
  2261. if (b == 0 && ((t == 0 && l == 1) ||
  2262. (t == 1 && l == 0))) {
  2263. nscp->SCp.sent_command = GDT_SCAN_START;
  2264. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2265. | SCSIRAWSERVICE;
  2266. ha->scan_mode = 0x12;
  2267. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2268. ha->scan_mode));
  2269. } else {
  2270. ha->scan_mode &= 0x10;
  2271. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2272. }
  2273. } else if (ha->scan_mode == 0x12) {
  2274. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2275. nscp->SCp.phase = SCSIRAWSERVICE;
  2276. nscp->SCp.sent_command = GDT_SCAN_END;
  2277. ha->scan_mode &= 0x10;
  2278. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2279. ha->scan_mode));
  2280. }
  2281. }
  2282. }
  2283. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2284. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2285. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2286. /* always GDT_CLUST_INFO! */
  2287. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2288. }
  2289. }
  2290. }
  2291. if (nscp->SCp.sent_command != -1) {
  2292. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2293. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2294. this_cmd = FALSE;
  2295. next_cmd = FALSE;
  2296. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2297. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2298. this_cmd = FALSE;
  2299. next_cmd = FALSE;
  2300. } else {
  2301. memset((char*)nscp->sense_buffer,0,16);
  2302. nscp->sense_buffer[0] = 0x70;
  2303. nscp->sense_buffer[2] = NOT_READY;
  2304. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2305. if (!nscp->SCp.have_data_in)
  2306. nscp->SCp.have_data_in++;
  2307. else
  2308. gdth_scsi_done(nscp);
  2309. }
  2310. } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
  2311. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2312. this_cmd = FALSE;
  2313. next_cmd = FALSE;
  2314. } else if (b != ha->virt_bus) {
  2315. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2316. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2317. this_cmd = FALSE;
  2318. else
  2319. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2320. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2321. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2322. nscp->cmnd[0], b, t, l));
  2323. nscp->result = DID_BAD_TARGET << 16;
  2324. if (!nscp->SCp.have_data_in)
  2325. nscp->SCp.have_data_in++;
  2326. else
  2327. gdth_scsi_done(nscp);
  2328. } else {
  2329. switch (nscp->cmnd[0]) {
  2330. case TEST_UNIT_READY:
  2331. case INQUIRY:
  2332. case REQUEST_SENSE:
  2333. case READ_CAPACITY:
  2334. case VERIFY:
  2335. case START_STOP:
  2336. case MODE_SENSE:
  2337. case SERVICE_ACTION_IN:
  2338. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2339. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2340. nscp->cmnd[4],nscp->cmnd[5]));
  2341. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2342. /* return UNIT_ATTENTION */
  2343. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2344. nscp->cmnd[0], t));
  2345. ha->hdr[t].media_changed = FALSE;
  2346. memset((char*)nscp->sense_buffer,0,16);
  2347. nscp->sense_buffer[0] = 0x70;
  2348. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2349. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2350. if (!nscp->SCp.have_data_in)
  2351. nscp->SCp.have_data_in++;
  2352. else
  2353. gdth_scsi_done(nscp);
  2354. } else if (gdth_internal_cache_cmd(hanum, nscp))
  2355. gdth_scsi_done(nscp);
  2356. break;
  2357. case ALLOW_MEDIUM_REMOVAL:
  2358. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2359. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2360. nscp->cmnd[4],nscp->cmnd[5]));
  2361. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2362. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2363. nscp->result = DID_OK << 16;
  2364. nscp->sense_buffer[0] = 0;
  2365. if (!nscp->SCp.have_data_in)
  2366. nscp->SCp.have_data_in++;
  2367. else
  2368. gdth_scsi_done(nscp);
  2369. } else {
  2370. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2371. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2372. nscp->cmnd[4],nscp->cmnd[3]));
  2373. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2374. this_cmd = FALSE;
  2375. }
  2376. break;
  2377. case RESERVE:
  2378. case RELEASE:
  2379. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2380. "RESERVE" : "RELEASE"));
  2381. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2382. this_cmd = FALSE;
  2383. break;
  2384. case READ_6:
  2385. case WRITE_6:
  2386. case READ_10:
  2387. case WRITE_10:
  2388. case READ_16:
  2389. case WRITE_16:
  2390. if (ha->hdr[t].media_changed) {
  2391. /* return UNIT_ATTENTION */
  2392. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2393. nscp->cmnd[0], t));
  2394. ha->hdr[t].media_changed = FALSE;
  2395. memset((char*)nscp->sense_buffer,0,16);
  2396. nscp->sense_buffer[0] = 0x70;
  2397. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2398. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2399. if (!nscp->SCp.have_data_in)
  2400. nscp->SCp.have_data_in++;
  2401. else
  2402. gdth_scsi_done(nscp);
  2403. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
  2404. this_cmd = FALSE;
  2405. break;
  2406. default:
  2407. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2408. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2409. nscp->cmnd[4],nscp->cmnd[5]));
  2410. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2411. hanum, nscp->cmnd[0]);
  2412. nscp->result = DID_ABORT << 16;
  2413. if (!nscp->SCp.have_data_in)
  2414. nscp->SCp.have_data_in++;
  2415. else
  2416. gdth_scsi_done(nscp);
  2417. break;
  2418. }
  2419. }
  2420. if (!this_cmd)
  2421. break;
  2422. if (nscp == ha->req_first)
  2423. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2424. else
  2425. pscp->SCp.ptr = nscp->SCp.ptr;
  2426. if (!next_cmd)
  2427. break;
  2428. }
  2429. if (ha->cmd_cnt > 0) {
  2430. gdth_release_event(hanum);
  2431. }
  2432. if (!gdth_polling)
  2433. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2434. if (gdth_polling && ha->cmd_cnt > 0) {
  2435. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2436. printk("GDT-HA %d: Command %d timed out !\n",
  2437. hanum,cmd_index);
  2438. }
  2439. }
  2440. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2441. char *buffer,ushort count)
  2442. {
  2443. ushort cpcount,i;
  2444. ushort cpsum,cpnow;
  2445. struct scatterlist *sl;
  2446. gdth_ha_str *ha;
  2447. char *address;
  2448. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2449. ha = HADATA(gdth_ctr_tab[hanum]);
  2450. if (scp->use_sg) {
  2451. sl = (struct scatterlist *)scp->request_buffer;
  2452. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2453. unsigned long flags;
  2454. cpnow = (ushort)sl->length;
  2455. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2456. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2457. if (cpsum+cpnow > cpcount)
  2458. cpnow = cpcount - cpsum;
  2459. cpsum += cpnow;
  2460. if (!sl->page) {
  2461. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2462. hanum);
  2463. return;
  2464. }
  2465. local_irq_save(flags);
  2466. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2467. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2468. memcpy(address,buffer,cpnow);
  2469. flush_dcache_page(sl->page);
  2470. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2471. #else
  2472. address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
  2473. memcpy(address,buffer,cpnow);
  2474. flush_dcache_page(sl->page);
  2475. kunmap_atomic(address, KM_BH_IRQ);
  2476. #endif
  2477. local_irq_restore(flags);
  2478. if (cpsum == cpcount)
  2479. break;
  2480. buffer += cpnow;
  2481. }
  2482. } else {
  2483. TRACE(("copy_internal() count %d\n",cpcount));
  2484. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2485. }
  2486. }
  2487. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2488. {
  2489. register gdth_ha_str *ha;
  2490. unchar t;
  2491. gdth_inq_data inq;
  2492. gdth_rdcap_data rdc;
  2493. gdth_sense_data sd;
  2494. gdth_modep_data mpd;
  2495. ha = HADATA(gdth_ctr_tab[hanum]);
  2496. t = scp->device->id;
  2497. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2498. scp->cmnd[0],t));
  2499. scp->result = DID_OK << 16;
  2500. scp->sense_buffer[0] = 0;
  2501. switch (scp->cmnd[0]) {
  2502. case TEST_UNIT_READY:
  2503. case VERIFY:
  2504. case START_STOP:
  2505. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2506. break;
  2507. case INQUIRY:
  2508. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2509. t,ha->hdr[t].devtype));
  2510. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2511. /* you can here set all disks to removable, if you want to do
  2512. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2513. inq.modif_rmb = 0x00;
  2514. if ((ha->hdr[t].devtype & 1) ||
  2515. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2516. inq.modif_rmb = 0x80;
  2517. inq.version = 2;
  2518. inq.resp_aenc = 2;
  2519. inq.add_length= 32;
  2520. strcpy(inq.vendor,ha->oem_name);
  2521. sprintf(inq.product,"Host Drive #%02d",t);
  2522. strcpy(inq.revision," ");
  2523. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2524. break;
  2525. case REQUEST_SENSE:
  2526. TRACE2(("Request sense hdrive %d\n",t));
  2527. sd.errorcode = 0x70;
  2528. sd.segno = 0x00;
  2529. sd.key = NO_SENSE;
  2530. sd.info = 0;
  2531. sd.add_length= 0;
  2532. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2533. break;
  2534. case MODE_SENSE:
  2535. TRACE2(("Mode sense hdrive %d\n",t));
  2536. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2537. mpd.hd.data_length = sizeof(gdth_modep_data);
  2538. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2539. mpd.hd.bd_length = sizeof(mpd.bd);
  2540. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2541. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2542. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2543. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2544. break;
  2545. case READ_CAPACITY:
  2546. TRACE2(("Read capacity hdrive %d\n",t));
  2547. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2548. rdc.last_block_no = 0xffffffff;
  2549. else
  2550. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2551. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2552. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2553. break;
  2554. case SERVICE_ACTION_IN:
  2555. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2556. (ha->cache_feat & GDT_64BIT)) {
  2557. gdth_rdcap16_data rdc16;
  2558. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2559. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2560. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2561. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2562. } else {
  2563. scp->result = DID_ABORT << 16;
  2564. }
  2565. break;
  2566. default:
  2567. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2568. break;
  2569. }
  2570. if (!scp->SCp.have_data_in)
  2571. scp->SCp.have_data_in++;
  2572. else
  2573. return 1;
  2574. return 0;
  2575. }
  2576. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2577. {
  2578. register gdth_ha_str *ha;
  2579. register gdth_cmd_str *cmdp;
  2580. struct scatterlist *sl;
  2581. ulong32 cnt, blockcnt;
  2582. ulong64 no, blockno;
  2583. dma_addr_t phys_addr;
  2584. int i, cmd_index, read_write, sgcnt, mode64;
  2585. struct page *page;
  2586. ulong offset;
  2587. ha = HADATA(gdth_ctr_tab[hanum]);
  2588. cmdp = ha->pccb;
  2589. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2590. scp->cmnd[0],scp->cmd_len,hdrive));
  2591. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2592. return 0;
  2593. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2594. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2595. not required, should not occur due to error return on
  2596. READ_CAPACITY_16 */
  2597. cmdp->Service = CACHESERVICE;
  2598. cmdp->RequestBuffer = scp;
  2599. /* search free command index */
  2600. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2601. TRACE(("GDT: No free command index found\n"));
  2602. return 0;
  2603. }
  2604. /* if it's the first command, set command semaphore */
  2605. if (ha->cmd_cnt == 0)
  2606. gdth_set_sema0(hanum);
  2607. /* fill command */
  2608. read_write = 0;
  2609. if (scp->SCp.sent_command != -1)
  2610. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2611. else if (scp->cmnd[0] == RESERVE)
  2612. cmdp->OpCode = GDT_RESERVE_DRV;
  2613. else if (scp->cmnd[0] == RELEASE)
  2614. cmdp->OpCode = GDT_RELEASE_DRV;
  2615. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2616. if (scp->cmnd[4] & 1) /* prevent ? */
  2617. cmdp->OpCode = GDT_MOUNT;
  2618. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2619. cmdp->OpCode = GDT_UNMOUNT;
  2620. else
  2621. cmdp->OpCode = GDT_FLUSH;
  2622. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2623. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2624. ) {
  2625. read_write = 1;
  2626. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2627. (ha->cache_feat & GDT_WR_THROUGH)))
  2628. cmdp->OpCode = GDT_WRITE_THR;
  2629. else
  2630. cmdp->OpCode = GDT_WRITE;
  2631. } else {
  2632. read_write = 2;
  2633. cmdp->OpCode = GDT_READ;
  2634. }
  2635. cmdp->BoardNode = LOCALBOARD;
  2636. if (mode64) {
  2637. cmdp->u.cache64.DeviceNo = hdrive;
  2638. cmdp->u.cache64.BlockNo = 1;
  2639. cmdp->u.cache64.sg_canz = 0;
  2640. } else {
  2641. cmdp->u.cache.DeviceNo = hdrive;
  2642. cmdp->u.cache.BlockNo = 1;
  2643. cmdp->u.cache.sg_canz = 0;
  2644. }
  2645. if (read_write) {
  2646. if (scp->cmd_len == 16) {
  2647. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2648. blockno = be64_to_cpu(no);
  2649. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2650. blockcnt = be32_to_cpu(cnt);
  2651. } else if (scp->cmd_len == 10) {
  2652. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2653. blockno = be32_to_cpu(no);
  2654. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2655. blockcnt = be16_to_cpu(cnt);
  2656. } else {
  2657. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2658. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2659. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2660. }
  2661. if (mode64) {
  2662. cmdp->u.cache64.BlockNo = blockno;
  2663. cmdp->u.cache64.BlockCnt = blockcnt;
  2664. } else {
  2665. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2666. cmdp->u.cache.BlockCnt = blockcnt;
  2667. }
  2668. if (scp->use_sg) {
  2669. sl = (struct scatterlist *)scp->request_buffer;
  2670. sgcnt = scp->use_sg;
  2671. scp->SCp.Status = GDTH_MAP_SG;
  2672. scp->SCp.Message = (read_write == 1 ?
  2673. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2674. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2675. if (mode64) {
  2676. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2677. cmdp->u.cache64.sg_canz = sgcnt;
  2678. for (i=0; i<sgcnt; ++i,++sl) {
  2679. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2680. #ifdef GDTH_DMA_STATISTICS
  2681. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2682. ha->dma64_cnt++;
  2683. else
  2684. ha->dma32_cnt++;
  2685. #endif
  2686. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2687. }
  2688. } else {
  2689. cmdp->u.cache.DestAddr= 0xffffffff;
  2690. cmdp->u.cache.sg_canz = sgcnt;
  2691. for (i=0; i<sgcnt; ++i,++sl) {
  2692. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2693. #ifdef GDTH_DMA_STATISTICS
  2694. ha->dma32_cnt++;
  2695. #endif
  2696. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2697. }
  2698. }
  2699. #ifdef GDTH_STATISTICS
  2700. if (max_sg < (ulong32)sgcnt) {
  2701. max_sg = (ulong32)sgcnt;
  2702. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2703. }
  2704. #endif
  2705. } else if (scp->request_bufflen) {
  2706. scp->SCp.Status = GDTH_MAP_SINGLE;
  2707. scp->SCp.Message = (read_write == 1 ?
  2708. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2709. page = virt_to_page(scp->request_buffer);
  2710. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2711. phys_addr = pci_map_page(ha->pdev,page,offset,
  2712. scp->request_bufflen,scp->SCp.Message);
  2713. scp->SCp.dma_handle = phys_addr;
  2714. if (mode64) {
  2715. if (ha->cache_feat & SCATTER_GATHER) {
  2716. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2717. cmdp->u.cache64.sg_canz = 1;
  2718. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2719. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2720. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2721. } else {
  2722. cmdp->u.cache64.DestAddr = phys_addr;
  2723. cmdp->u.cache64.sg_canz= 0;
  2724. }
  2725. } else {
  2726. if (ha->cache_feat & SCATTER_GATHER) {
  2727. cmdp->u.cache.DestAddr = 0xffffffff;
  2728. cmdp->u.cache.sg_canz = 1;
  2729. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2730. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2731. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2732. } else {
  2733. cmdp->u.cache.DestAddr = phys_addr;
  2734. cmdp->u.cache.sg_canz= 0;
  2735. }
  2736. }
  2737. }
  2738. }
  2739. /* evaluate command size, check space */
  2740. if (mode64) {
  2741. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2742. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2743. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2744. cmdp->u.cache64.sg_lst[0].sg_len));
  2745. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2746. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2747. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2748. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2749. } else {
  2750. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2751. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2752. cmdp->u.cache.sg_lst[0].sg_ptr,
  2753. cmdp->u.cache.sg_lst[0].sg_len));
  2754. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2755. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2756. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2757. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2758. }
  2759. if (ha->cmd_len & 3)
  2760. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2761. if (ha->cmd_cnt > 0) {
  2762. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2763. ha->ic_all_size) {
  2764. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2765. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2766. return 0;
  2767. }
  2768. }
  2769. /* copy command */
  2770. gdth_copy_command(hanum);
  2771. return cmd_index;
  2772. }
  2773. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2774. {
  2775. register gdth_ha_str *ha;
  2776. register gdth_cmd_str *cmdp;
  2777. struct scatterlist *sl;
  2778. ushort i;
  2779. dma_addr_t phys_addr, sense_paddr;
  2780. int cmd_index, sgcnt, mode64;
  2781. unchar t,l;
  2782. struct page *page;
  2783. ulong offset;
  2784. ha = HADATA(gdth_ctr_tab[hanum]);
  2785. t = scp->device->id;
  2786. l = scp->device->lun;
  2787. cmdp = ha->pccb;
  2788. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2789. scp->cmnd[0],b,t,l));
  2790. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2791. return 0;
  2792. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2793. cmdp->Service = SCSIRAWSERVICE;
  2794. cmdp->RequestBuffer = scp;
  2795. /* search free command index */
  2796. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2797. TRACE(("GDT: No free command index found\n"));
  2798. return 0;
  2799. }
  2800. /* if it's the first command, set command semaphore */
  2801. if (ha->cmd_cnt == 0)
  2802. gdth_set_sema0(hanum);
  2803. /* fill command */
  2804. if (scp->SCp.sent_command != -1) {
  2805. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2806. cmdp->BoardNode = LOCALBOARD;
  2807. if (mode64) {
  2808. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2809. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2810. cmdp->OpCode, cmdp->u.raw64.direction));
  2811. /* evaluate command size */
  2812. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2813. } else {
  2814. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2815. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2816. cmdp->OpCode, cmdp->u.raw.direction));
  2817. /* evaluate command size */
  2818. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2819. }
  2820. } else {
  2821. page = virt_to_page(scp->sense_buffer);
  2822. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2823. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2824. 16,PCI_DMA_FROMDEVICE);
  2825. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2826. /* high part, if 64bit */
  2827. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2828. cmdp->OpCode = GDT_WRITE; /* always */
  2829. cmdp->BoardNode = LOCALBOARD;
  2830. if (mode64) {
  2831. cmdp->u.raw64.reserved = 0;
  2832. cmdp->u.raw64.mdisc_time = 0;
  2833. cmdp->u.raw64.mcon_time = 0;
  2834. cmdp->u.raw64.clen = scp->cmd_len;
  2835. cmdp->u.raw64.target = t;
  2836. cmdp->u.raw64.lun = l;
  2837. cmdp->u.raw64.bus = b;
  2838. cmdp->u.raw64.priority = 0;
  2839. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2840. cmdp->u.raw64.sense_len = 16;
  2841. cmdp->u.raw64.sense_data = sense_paddr;
  2842. cmdp->u.raw64.direction =
  2843. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2844. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2845. cmdp->u.raw64.sg_ranz = 0;
  2846. } else {
  2847. cmdp->u.raw.reserved = 0;
  2848. cmdp->u.raw.mdisc_time = 0;
  2849. cmdp->u.raw.mcon_time = 0;
  2850. cmdp->u.raw.clen = scp->cmd_len;
  2851. cmdp->u.raw.target = t;
  2852. cmdp->u.raw.lun = l;
  2853. cmdp->u.raw.bus = b;
  2854. cmdp->u.raw.priority = 0;
  2855. cmdp->u.raw.link_p = 0;
  2856. cmdp->u.raw.sdlen = scp->request_bufflen;
  2857. cmdp->u.raw.sense_len = 16;
  2858. cmdp->u.raw.sense_data = sense_paddr;
  2859. cmdp->u.raw.direction =
  2860. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2861. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2862. cmdp->u.raw.sg_ranz = 0;
  2863. }
  2864. if (scp->use_sg) {
  2865. sl = (struct scatterlist *)scp->request_buffer;
  2866. sgcnt = scp->use_sg;
  2867. scp->SCp.Status = GDTH_MAP_SG;
  2868. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2869. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2870. if (mode64) {
  2871. cmdp->u.raw64.sdata = (ulong64)-1;
  2872. cmdp->u.raw64.sg_ranz = sgcnt;
  2873. for (i=0; i<sgcnt; ++i,++sl) {
  2874. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2875. #ifdef GDTH_DMA_STATISTICS
  2876. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2877. ha->dma64_cnt++;
  2878. else
  2879. ha->dma32_cnt++;
  2880. #endif
  2881. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2882. }
  2883. } else {
  2884. cmdp->u.raw.sdata = 0xffffffff;
  2885. cmdp->u.raw.sg_ranz = sgcnt;
  2886. for (i=0; i<sgcnt; ++i,++sl) {
  2887. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2888. #ifdef GDTH_DMA_STATISTICS
  2889. ha->dma32_cnt++;
  2890. #endif
  2891. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2892. }
  2893. }
  2894. #ifdef GDTH_STATISTICS
  2895. if (max_sg < sgcnt) {
  2896. max_sg = sgcnt;
  2897. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2898. }
  2899. #endif
  2900. } else if (scp->request_bufflen) {
  2901. scp->SCp.Status = GDTH_MAP_SINGLE;
  2902. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2903. page = virt_to_page(scp->request_buffer);
  2904. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2905. phys_addr = pci_map_page(ha->pdev,page,offset,
  2906. scp->request_bufflen,scp->SCp.Message);
  2907. scp->SCp.dma_handle = phys_addr;
  2908. if (mode64) {
  2909. if (ha->raw_feat & SCATTER_GATHER) {
  2910. cmdp->u.raw64.sdata = (ulong64)-1;
  2911. cmdp->u.raw64.sg_ranz= 1;
  2912. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2913. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2914. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2915. } else {
  2916. cmdp->u.raw64.sdata = phys_addr;
  2917. cmdp->u.raw64.sg_ranz= 0;
  2918. }
  2919. } else {
  2920. if (ha->raw_feat & SCATTER_GATHER) {
  2921. cmdp->u.raw.sdata = 0xffffffff;
  2922. cmdp->u.raw.sg_ranz= 1;
  2923. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2924. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2925. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2926. } else {
  2927. cmdp->u.raw.sdata = phys_addr;
  2928. cmdp->u.raw.sg_ranz= 0;
  2929. }
  2930. }
  2931. }
  2932. if (mode64) {
  2933. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2934. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2935. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2936. cmdp->u.raw64.sg_lst[0].sg_len));
  2937. /* evaluate command size */
  2938. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2939. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2940. } else {
  2941. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2942. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2943. cmdp->u.raw.sg_lst[0].sg_ptr,
  2944. cmdp->u.raw.sg_lst[0].sg_len));
  2945. /* evaluate command size */
  2946. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2947. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2948. }
  2949. }
  2950. /* check space */
  2951. if (ha->cmd_len & 3)
  2952. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2953. if (ha->cmd_cnt > 0) {
  2954. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2955. ha->ic_all_size) {
  2956. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2957. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2958. return 0;
  2959. }
  2960. }
  2961. /* copy command */
  2962. gdth_copy_command(hanum);
  2963. return cmd_index;
  2964. }
  2965. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2966. {
  2967. register gdth_ha_str *ha;
  2968. register gdth_cmd_str *cmdp;
  2969. int cmd_index;
  2970. ha = HADATA(gdth_ctr_tab[hanum]);
  2971. cmdp= ha->pccb;
  2972. TRACE2(("gdth_special_cmd(): "));
  2973. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2974. return 0;
  2975. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2976. cmdp->RequestBuffer = scp;
  2977. /* search free command index */
  2978. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2979. TRACE(("GDT: No free command index found\n"));
  2980. return 0;
  2981. }
  2982. /* if it's the first command, set command semaphore */
  2983. if (ha->cmd_cnt == 0)
  2984. gdth_set_sema0(hanum);
  2985. /* evaluate command size, check space */
  2986. if (cmdp->OpCode == GDT_IOCTL) {
  2987. TRACE2(("IOCTL\n"));
  2988. ha->cmd_len =
  2989. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2990. } else if (cmdp->Service == CACHESERVICE) {
  2991. TRACE2(("cache command %d\n",cmdp->OpCode));
  2992. if (ha->cache_feat & GDT_64BIT)
  2993. ha->cmd_len =
  2994. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2995. else
  2996. ha->cmd_len =
  2997. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2998. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2999. TRACE2(("raw command %d\n",cmdp->OpCode));
  3000. if (ha->raw_feat & GDT_64BIT)
  3001. ha->cmd_len =
  3002. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  3003. else
  3004. ha->cmd_len =
  3005. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  3006. }
  3007. if (ha->cmd_len & 3)
  3008. ha->cmd_len += (4 - (ha->cmd_len & 3));
  3009. if (ha->cmd_cnt > 0) {
  3010. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  3011. ha->ic_all_size) {
  3012. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  3013. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  3014. return 0;
  3015. }
  3016. }
  3017. /* copy command */
  3018. gdth_copy_command(hanum);
  3019. return cmd_index;
  3020. }
  3021. /* Controller event handling functions */
  3022. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  3023. ushort idx, gdth_evt_data *evt)
  3024. {
  3025. gdth_evt_str *e;
  3026. struct timeval tv;
  3027. /* no GDTH_LOCK_HA() ! */
  3028. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  3029. if (source == 0) /* no source -> no event */
  3030. return NULL;
  3031. if (ebuffer[elastidx].event_source == source &&
  3032. ebuffer[elastidx].event_idx == idx &&
  3033. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  3034. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  3035. (char *)&evt->eu, evt->size)) ||
  3036. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  3037. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  3038. (char *)&evt->event_string)))) {
  3039. e = &ebuffer[elastidx];
  3040. do_gettimeofday(&tv);
  3041. e->last_stamp = tv.tv_sec;
  3042. ++e->same_count;
  3043. } else {
  3044. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  3045. ++elastidx;
  3046. if (elastidx == MAX_EVENTS)
  3047. elastidx = 0;
  3048. if (elastidx == eoldidx) { /* reached mark ? */
  3049. ++eoldidx;
  3050. if (eoldidx == MAX_EVENTS)
  3051. eoldidx = 0;
  3052. }
  3053. }
  3054. e = &ebuffer[elastidx];
  3055. e->event_source = source;
  3056. e->event_idx = idx;
  3057. do_gettimeofday(&tv);
  3058. e->first_stamp = e->last_stamp = tv.tv_sec;
  3059. e->same_count = 1;
  3060. e->event_data = *evt;
  3061. e->application = 0;
  3062. }
  3063. return e;
  3064. }
  3065. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  3066. {
  3067. gdth_evt_str *e;
  3068. int eindex;
  3069. ulong flags;
  3070. TRACE2(("gdth_read_event() handle %d\n", handle));
  3071. spin_lock_irqsave(&ha->smp_lock, flags);
  3072. if (handle == -1)
  3073. eindex = eoldidx;
  3074. else
  3075. eindex = handle;
  3076. estr->event_source = 0;
  3077. if (eindex >= MAX_EVENTS) {
  3078. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3079. return eindex;
  3080. }
  3081. e = &ebuffer[eindex];
  3082. if (e->event_source != 0) {
  3083. if (eindex != elastidx) {
  3084. if (++eindex == MAX_EVENTS)
  3085. eindex = 0;
  3086. } else {
  3087. eindex = -1;
  3088. }
  3089. memcpy(estr, e, sizeof(gdth_evt_str));
  3090. }
  3091. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3092. return eindex;
  3093. }
  3094. static void gdth_readapp_event(gdth_ha_str *ha,
  3095. unchar application, gdth_evt_str *estr)
  3096. {
  3097. gdth_evt_str *e;
  3098. int eindex;
  3099. ulong flags;
  3100. unchar found = FALSE;
  3101. TRACE2(("gdth_readapp_event() app. %d\n", application));
  3102. spin_lock_irqsave(&ha->smp_lock, flags);
  3103. eindex = eoldidx;
  3104. for (;;) {
  3105. e = &ebuffer[eindex];
  3106. if (e->event_source == 0)
  3107. break;
  3108. if ((e->application & application) == 0) {
  3109. e->application |= application;
  3110. found = TRUE;
  3111. break;
  3112. }
  3113. if (eindex == elastidx)
  3114. break;
  3115. if (++eindex == MAX_EVENTS)
  3116. eindex = 0;
  3117. }
  3118. if (found)
  3119. memcpy(estr, e, sizeof(gdth_evt_str));
  3120. else
  3121. estr->event_source = 0;
  3122. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3123. }
  3124. static void gdth_clear_events(void)
  3125. {
  3126. TRACE(("gdth_clear_events()"));
  3127. eoldidx = elastidx = 0;
  3128. ebuffer[0].event_source = 0;
  3129. }
  3130. /* SCSI interface functions */
  3131. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  3132. {
  3133. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3134. register gdth_ha_str *ha;
  3135. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3136. gdt6_dpram_str __iomem *dp6_ptr;
  3137. gdt2_dpram_str __iomem *dp2_ptr;
  3138. Scsi_Cmnd *scp;
  3139. int hanum, rval, i;
  3140. unchar IStatus;
  3141. ushort Service;
  3142. ulong flags = 0;
  3143. #ifdef INT_COAL
  3144. int coalesced = FALSE;
  3145. int next = FALSE;
  3146. gdth_coal_status *pcs = NULL;
  3147. int act_int_coal = 0;
  3148. #endif
  3149. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3150. /* if polling and not from gdth_wait() -> return */
  3151. if (gdth_polling) {
  3152. if (!gdth_from_wait) {
  3153. return IRQ_HANDLED;
  3154. }
  3155. }
  3156. if (!gdth_polling)
  3157. spin_lock_irqsave(&ha2->smp_lock, flags);
  3158. wait_index = 0;
  3159. /* search controller */
  3160. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3161. /* spurious interrupt */
  3162. if (!gdth_polling)
  3163. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3164. return IRQ_HANDLED;
  3165. }
  3166. ha = HADATA(gdth_ctr_tab[hanum]);
  3167. #ifdef GDTH_STATISTICS
  3168. ++act_ints;
  3169. #endif
  3170. #ifdef INT_COAL
  3171. /* See if the fw is returning coalesced status */
  3172. if (IStatus == COALINDEX) {
  3173. /* Coalesced status. Setup the initial status
  3174. buffer pointer and flags */
  3175. pcs = ha->coal_stat;
  3176. coalesced = TRUE;
  3177. next = TRUE;
  3178. }
  3179. do {
  3180. if (coalesced) {
  3181. /* For coalesced requests all status
  3182. information is found in the status buffer */
  3183. IStatus = (unchar)(pcs->status & 0xff);
  3184. }
  3185. #endif
  3186. if (ha->type == GDT_EISA) {
  3187. if (IStatus & 0x80) { /* error flag */
  3188. IStatus &= ~0x80;
  3189. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3190. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3191. } else /* no error */
  3192. ha->status = S_OK;
  3193. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3194. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3195. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3196. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3197. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3198. } else if (ha->type == GDT_ISA) {
  3199. dp2_ptr = ha->brd;
  3200. if (IStatus & 0x80) { /* error flag */
  3201. IStatus &= ~0x80;
  3202. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3203. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3204. } else /* no error */
  3205. ha->status = S_OK;
  3206. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3207. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3208. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3209. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3210. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3211. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3212. } else if (ha->type == GDT_PCI) {
  3213. dp6_ptr = ha->brd;
  3214. if (IStatus & 0x80) { /* error flag */
  3215. IStatus &= ~0x80;
  3216. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3217. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3218. } else /* no error */
  3219. ha->status = S_OK;
  3220. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3221. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3222. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3223. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3224. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3225. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3226. } else if (ha->type == GDT_PCINEW) {
  3227. if (IStatus & 0x80) { /* error flag */
  3228. IStatus &= ~0x80;
  3229. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3230. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3231. } else
  3232. ha->status = S_OK;
  3233. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3234. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3235. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3236. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3237. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3238. } else if (ha->type == GDT_PCIMPR) {
  3239. dp6m_ptr = ha->brd;
  3240. if (IStatus & 0x80) { /* error flag */
  3241. IStatus &= ~0x80;
  3242. #ifdef INT_COAL
  3243. if (coalesced)
  3244. ha->status = pcs->ext_status & 0xffff;
  3245. else
  3246. #endif
  3247. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3248. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3249. } else /* no error */
  3250. ha->status = S_OK;
  3251. #ifdef INT_COAL
  3252. /* get information */
  3253. if (coalesced) {
  3254. ha->info = pcs->info0;
  3255. ha->info2 = pcs->info1;
  3256. ha->service = (pcs->ext_status >> 16) & 0xffff;
  3257. } else
  3258. #endif
  3259. {
  3260. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3261. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3262. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3263. }
  3264. /* event string */
  3265. if (IStatus == ASYNCINDEX) {
  3266. if (ha->service != SCREENSERVICE &&
  3267. (ha->fw_vers & 0xff) >= 0x1a) {
  3268. ha->dvr.severity = gdth_readb
  3269. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3270. for (i = 0; i < 256; ++i) {
  3271. ha->dvr.event_string[i] = gdth_readb
  3272. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3273. if (ha->dvr.event_string[i] == 0)
  3274. break;
  3275. }
  3276. }
  3277. }
  3278. #ifdef INT_COAL
  3279. /* Make sure that non coalesced interrupts get cleared
  3280. before being handled by gdth_async_event/gdth_sync_event */
  3281. if (!coalesced)
  3282. #endif
  3283. {
  3284. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3285. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3286. }
  3287. } else {
  3288. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3289. if (!gdth_polling)
  3290. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3291. return IRQ_HANDLED;
  3292. }
  3293. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3294. IStatus,ha->status,ha->info));
  3295. if (gdth_from_wait) {
  3296. wait_hanum = hanum;
  3297. wait_index = (int)IStatus;
  3298. }
  3299. if (IStatus == ASYNCINDEX) {
  3300. TRACE2(("gdth_interrupt() async. event\n"));
  3301. gdth_async_event(hanum);
  3302. if (!gdth_polling)
  3303. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3304. gdth_next(hanum);
  3305. return IRQ_HANDLED;
  3306. }
  3307. if (IStatus == SPEZINDEX) {
  3308. TRACE2(("Service unknown or not initialized !\n"));
  3309. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3310. ha->dvr.eu.driver.ionode = hanum;
  3311. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3312. if (!gdth_polling)
  3313. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3314. return IRQ_HANDLED;
  3315. }
  3316. scp = ha->cmd_tab[IStatus-2].cmnd;
  3317. Service = ha->cmd_tab[IStatus-2].service;
  3318. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3319. if (scp == UNUSED_CMND) {
  3320. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3321. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3322. ha->dvr.eu.driver.ionode = hanum;
  3323. ha->dvr.eu.driver.index = IStatus;
  3324. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3325. if (!gdth_polling)
  3326. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3327. return IRQ_HANDLED;
  3328. }
  3329. if (scp == INTERNAL_CMND) {
  3330. TRACE(("gdth_interrupt() answer to internal command\n"));
  3331. if (!gdth_polling)
  3332. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3333. return IRQ_HANDLED;
  3334. }
  3335. TRACE(("gdth_interrupt() sync. status\n"));
  3336. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3337. if (!gdth_polling)
  3338. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3339. if (rval == 2) {
  3340. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3341. } else if (rval == 1) {
  3342. gdth_scsi_done(scp);
  3343. }
  3344. #ifdef INT_COAL
  3345. if (coalesced) {
  3346. /* go to the next status in the status buffer */
  3347. ++pcs;
  3348. #ifdef GDTH_STATISTICS
  3349. ++act_int_coal;
  3350. if (act_int_coal > max_int_coal) {
  3351. max_int_coal = act_int_coal;
  3352. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3353. }
  3354. #endif
  3355. /* see if there is another status */
  3356. if (pcs->status == 0)
  3357. /* Stop the coalesce loop */
  3358. next = FALSE;
  3359. }
  3360. } while (next);
  3361. /* coalescing only for new GDT_PCIMPR controllers available */
  3362. if (ha->type == GDT_PCIMPR && coalesced) {
  3363. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3364. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3365. }
  3366. #endif
  3367. gdth_next(hanum);
  3368. return IRQ_HANDLED;
  3369. }
  3370. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3371. {
  3372. register gdth_ha_str *ha;
  3373. gdth_msg_str *msg;
  3374. gdth_cmd_str *cmdp;
  3375. unchar b, t;
  3376. ha = HADATA(gdth_ctr_tab[hanum]);
  3377. cmdp = ha->pccb;
  3378. TRACE(("gdth_sync_event() serv %d status %d\n",
  3379. service,ha->status));
  3380. if (service == SCREENSERVICE) {
  3381. msg = ha->pmsg;
  3382. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3383. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3384. if (msg->msg_len > MSGLEN+1)
  3385. msg->msg_len = MSGLEN+1;
  3386. if (msg->msg_len)
  3387. if (!(msg->msg_answer && msg->msg_ext)) {
  3388. msg->msg_text[msg->msg_len] = '\0';
  3389. printk("%s",msg->msg_text);
  3390. }
  3391. if (msg->msg_ext && !msg->msg_answer) {
  3392. while (gdth_test_busy(hanum))
  3393. gdth_delay(0);
  3394. cmdp->Service = SCREENSERVICE;
  3395. cmdp->RequestBuffer = SCREEN_CMND;
  3396. gdth_get_cmd_index(hanum);
  3397. gdth_set_sema0(hanum);
  3398. cmdp->OpCode = GDT_READ;
  3399. cmdp->BoardNode = LOCALBOARD;
  3400. cmdp->u.screen.reserved = 0;
  3401. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3402. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3403. ha->cmd_offs_dpmem = 0;
  3404. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3405. + sizeof(ulong64);
  3406. ha->cmd_cnt = 0;
  3407. gdth_copy_command(hanum);
  3408. gdth_release_event(hanum);
  3409. return 0;
  3410. }
  3411. if (msg->msg_answer && msg->msg_alen) {
  3412. /* default answers (getchar() not possible) */
  3413. if (msg->msg_alen == 1) {
  3414. msg->msg_alen = 0;
  3415. msg->msg_len = 1;
  3416. msg->msg_text[0] = 0;
  3417. } else {
  3418. msg->msg_alen -= 2;
  3419. msg->msg_len = 2;
  3420. msg->msg_text[0] = 1;
  3421. msg->msg_text[1] = 0;
  3422. }
  3423. msg->msg_ext = 0;
  3424. msg->msg_answer = 0;
  3425. while (gdth_test_busy(hanum))
  3426. gdth_delay(0);
  3427. cmdp->Service = SCREENSERVICE;
  3428. cmdp->RequestBuffer = SCREEN_CMND;
  3429. gdth_get_cmd_index(hanum);
  3430. gdth_set_sema0(hanum);
  3431. cmdp->OpCode = GDT_WRITE;
  3432. cmdp->BoardNode = LOCALBOARD;
  3433. cmdp->u.screen.reserved = 0;
  3434. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3435. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3436. ha->cmd_offs_dpmem = 0;
  3437. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3438. + sizeof(ulong64);
  3439. ha->cmd_cnt = 0;
  3440. gdth_copy_command(hanum);
  3441. gdth_release_event(hanum);
  3442. return 0;
  3443. }
  3444. printk("\n");
  3445. } else {
  3446. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3447. t = scp->device->id;
  3448. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3449. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3450. }
  3451. /* cache or raw service */
  3452. if (ha->status == S_BSY) {
  3453. TRACE2(("Controller busy -> retry !\n"));
  3454. if (scp->SCp.sent_command == GDT_MOUNT)
  3455. scp->SCp.sent_command = GDT_CLUST_INFO;
  3456. /* retry */
  3457. return 2;
  3458. }
  3459. if (scp->SCp.Status == GDTH_MAP_SG)
  3460. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3461. scp->use_sg,scp->SCp.Message);
  3462. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3463. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3464. scp->request_bufflen,scp->SCp.Message);
  3465. if (scp->SCp.buffer) {
  3466. dma_addr_t addr;
  3467. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3468. if (scp->host_scribble)
  3469. addr += (dma_addr_t)
  3470. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3471. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3472. }
  3473. if (ha->status == S_OK) {
  3474. scp->SCp.Status = S_OK;
  3475. scp->SCp.Message = ha->info;
  3476. if (scp->SCp.sent_command != -1) {
  3477. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3478. scp->SCp.sent_command));
  3479. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3480. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3481. ha->hdr[t].cluster_type = (unchar)ha->info;
  3482. if (!(ha->hdr[t].cluster_type &
  3483. CLUSTER_MOUNTED)) {
  3484. /* NOT MOUNTED -> MOUNT */
  3485. scp->SCp.sent_command = GDT_MOUNT;
  3486. if (ha->hdr[t].cluster_type &
  3487. CLUSTER_RESERVED) {
  3488. /* cluster drive RESERVED (on the other node) */
  3489. scp->SCp.phase = -2; /* reservation conflict */
  3490. }
  3491. } else {
  3492. scp->SCp.sent_command = -1;
  3493. }
  3494. } else {
  3495. if (scp->SCp.sent_command == GDT_MOUNT) {
  3496. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3497. ha->hdr[t].media_changed = TRUE;
  3498. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3499. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3500. ha->hdr[t].media_changed = TRUE;
  3501. }
  3502. scp->SCp.sent_command = -1;
  3503. }
  3504. /* retry */
  3505. scp->SCp.this_residual = HIGH_PRI;
  3506. return 2;
  3507. } else {
  3508. /* RESERVE/RELEASE ? */
  3509. if (scp->cmnd[0] == RESERVE) {
  3510. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3511. } else if (scp->cmnd[0] == RELEASE) {
  3512. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3513. }
  3514. scp->result = DID_OK << 16;
  3515. scp->sense_buffer[0] = 0;
  3516. }
  3517. } else {
  3518. scp->SCp.Status = ha->status;
  3519. scp->SCp.Message = ha->info;
  3520. if (scp->SCp.sent_command != -1) {
  3521. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3522. scp->SCp.sent_command, ha->status));
  3523. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3524. scp->SCp.sent_command == GDT_SCAN_END) {
  3525. scp->SCp.sent_command = -1;
  3526. /* retry */
  3527. scp->SCp.this_residual = HIGH_PRI;
  3528. return 2;
  3529. }
  3530. memset((char*)scp->sense_buffer,0,16);
  3531. scp->sense_buffer[0] = 0x70;
  3532. scp->sense_buffer[2] = NOT_READY;
  3533. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3534. } else if (service == CACHESERVICE) {
  3535. if (ha->status == S_CACHE_UNKNOWN &&
  3536. (ha->hdr[t].cluster_type &
  3537. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3538. /* bus reset -> force GDT_CLUST_INFO */
  3539. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3540. }
  3541. memset((char*)scp->sense_buffer,0,16);
  3542. if (ha->status == (ushort)S_CACHE_RESERV) {
  3543. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3544. } else {
  3545. scp->sense_buffer[0] = 0x70;
  3546. scp->sense_buffer[2] = NOT_READY;
  3547. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3548. }
  3549. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  3550. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3551. ha->dvr.eu.sync.ionode = hanum;
  3552. ha->dvr.eu.sync.service = service;
  3553. ha->dvr.eu.sync.status = ha->status;
  3554. ha->dvr.eu.sync.info = ha->info;
  3555. ha->dvr.eu.sync.hostdrive = t;
  3556. if (ha->status >= 0x8000)
  3557. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3558. else
  3559. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3560. }
  3561. } else {
  3562. /* sense buffer filled from controller firmware (DMA) */
  3563. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3564. scp->result = DID_BAD_TARGET << 16;
  3565. } else {
  3566. scp->result = (DID_OK << 16) | ha->info;
  3567. }
  3568. }
  3569. }
  3570. if (!scp->SCp.have_data_in)
  3571. scp->SCp.have_data_in++;
  3572. else
  3573. return 1;
  3574. }
  3575. return 0;
  3576. }
  3577. static char *async_cache_tab[] = {
  3578. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3579. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3580. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3581. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3582. /* 2*/ "\005\000\002\006\004"
  3583. "GDT HA %u, Host Drive %lu not ready",
  3584. /* 3*/ "\005\000\002\006\004"
  3585. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3586. /* 4*/ "\005\000\002\006\004"
  3587. "GDT HA %u, mirror update on Host Drive %lu failed",
  3588. /* 5*/ "\005\000\002\006\004"
  3589. "GDT HA %u, Mirror Drive %lu failed",
  3590. /* 6*/ "\005\000\002\006\004"
  3591. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3592. /* 7*/ "\005\000\002\006\004"
  3593. "GDT HA %u, Host Drive %lu write protected",
  3594. /* 8*/ "\005\000\002\006\004"
  3595. "GDT HA %u, media changed in Host Drive %lu",
  3596. /* 9*/ "\005\000\002\006\004"
  3597. "GDT HA %u, Host Drive %lu is offline",
  3598. /*10*/ "\005\000\002\006\004"
  3599. "GDT HA %u, media change of Mirror Drive %lu",
  3600. /*11*/ "\005\000\002\006\004"
  3601. "GDT HA %u, Mirror Drive %lu is write protected",
  3602. /*12*/ "\005\000\002\006\004"
  3603. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3604. /*13*/ "\007\000\002\006\002\010\002"
  3605. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3606. /*14*/ "\005\000\002\006\002"
  3607. "GDT HA %u, Array Drive %u: FAIL state entered",
  3608. /*15*/ "\005\000\002\006\002"
  3609. "GDT HA %u, Array Drive %u: error",
  3610. /*16*/ "\007\000\002\006\002\010\002"
  3611. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3612. /*17*/ "\005\000\002\006\002"
  3613. "GDT HA %u, Array Drive %u: parity build failed",
  3614. /*18*/ "\005\000\002\006\002"
  3615. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3616. /*19*/ "\005\000\002\010\002"
  3617. "GDT HA %u, Test of Hot Fix %u failed",
  3618. /*20*/ "\005\000\002\006\002"
  3619. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3620. /*21*/ "\005\000\002\006\002"
  3621. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3622. /*22*/ "\007\000\002\006\002\010\002"
  3623. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3624. /*23*/ "\005\000\002\006\002"
  3625. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3626. /*24*/ "\005\000\002\010\002"
  3627. "GDT HA %u, mirror update on Cache Drive %u completed",
  3628. /*25*/ "\005\000\002\010\002"
  3629. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3630. /*26*/ "\005\000\002\006\002"
  3631. "GDT HA %u, Array Drive %u: drive rebuild started",
  3632. /*27*/ "\005\000\002\012\001"
  3633. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3634. /*28*/ "\005\000\002\012\001"
  3635. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3636. /*29*/ "\007\000\002\012\001\013\001"
  3637. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3638. /*30*/ "\007\000\002\012\001\013\001"
  3639. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3640. /*31*/ "\007\000\002\012\001\013\001"
  3641. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3642. /*32*/ "\007\000\002\012\001\013\001"
  3643. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3644. /*33*/ "\007\000\002\012\001\013\001"
  3645. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3646. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3647. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3648. /*35*/ "\007\000\002\012\001\013\001"
  3649. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3650. /*36*/ "\007\000\002\012\001\013\001"
  3651. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3652. /*37*/ "\007\000\002\012\001\006\004"
  3653. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3654. /*38*/ "\007\000\002\012\001\013\001"
  3655. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3656. /*39*/ "\007\000\002\012\001\013\001"
  3657. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3658. /*40*/ "\007\000\002\012\001\013\001"
  3659. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3660. /*41*/ "\007\000\002\012\001\013\001"
  3661. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3662. /*42*/ "\005\000\002\006\002"
  3663. "GDT HA %u, Array Drive %u: drive build started",
  3664. /*43*/ "\003\000\002"
  3665. "GDT HA %u, DRAM parity error detected",
  3666. /*44*/ "\005\000\002\006\002"
  3667. "GDT HA %u, Mirror Drive %u: update started",
  3668. /*45*/ "\007\000\002\006\002\010\002"
  3669. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3670. /*46*/ "\005\000\002\006\002"
  3671. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3672. /*47*/ "\005\000\002\006\002"
  3673. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3674. /*48*/ "\005\000\002\006\002"
  3675. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3676. /*49*/ "\005\000\002\006\002"
  3677. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3678. /*50*/ "\007\000\002\012\001\013\001"
  3679. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3680. /*51*/ "\005\000\002\006\002"
  3681. "GDT HA %u, Array Drive %u: expand started",
  3682. /*52*/ "\005\000\002\006\002"
  3683. "GDT HA %u, Array Drive %u: expand finished successfully",
  3684. /*53*/ "\005\000\002\006\002"
  3685. "GDT HA %u, Array Drive %u: expand failed",
  3686. /*54*/ "\003\000\002"
  3687. "GDT HA %u, CPU temperature critical",
  3688. /*55*/ "\003\000\002"
  3689. "GDT HA %u, CPU temperature OK",
  3690. /*56*/ "\005\000\002\006\004"
  3691. "GDT HA %u, Host drive %lu created",
  3692. /*57*/ "\005\000\002\006\002"
  3693. "GDT HA %u, Array Drive %u: expand restarted",
  3694. /*58*/ "\005\000\002\006\002"
  3695. "GDT HA %u, Array Drive %u: expand stopped",
  3696. /*59*/ "\005\000\002\010\002"
  3697. "GDT HA %u, Mirror Drive %u: drive build quited",
  3698. /*60*/ "\005\000\002\006\002"
  3699. "GDT HA %u, Array Drive %u: parity build quited",
  3700. /*61*/ "\005\000\002\006\002"
  3701. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3702. /*62*/ "\005\000\002\006\002"
  3703. "GDT HA %u, Array Drive %u: parity verify started",
  3704. /*63*/ "\005\000\002\006\002"
  3705. "GDT HA %u, Array Drive %u: parity verify done",
  3706. /*64*/ "\005\000\002\006\002"
  3707. "GDT HA %u, Array Drive %u: parity verify failed",
  3708. /*65*/ "\005\000\002\006\002"
  3709. "GDT HA %u, Array Drive %u: parity error detected",
  3710. /*66*/ "\005\000\002\006\002"
  3711. "GDT HA %u, Array Drive %u: parity verify quited",
  3712. /*67*/ "\005\000\002\006\002"
  3713. "GDT HA %u, Host Drive %u reserved",
  3714. /*68*/ "\005\000\002\006\002"
  3715. "GDT HA %u, Host Drive %u mounted and released",
  3716. /*69*/ "\005\000\002\006\002"
  3717. "GDT HA %u, Host Drive %u released",
  3718. /*70*/ "\003\000\002"
  3719. "GDT HA %u, DRAM error detected and corrected with ECC",
  3720. /*71*/ "\003\000\002"
  3721. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3722. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3723. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3724. /*73*/ "\005\000\002\006\002"
  3725. "GDT HA %u, Host drive %u resetted locally",
  3726. /*74*/ "\005\000\002\006\002"
  3727. "GDT HA %u, Host drive %u resetted remotely",
  3728. /*75*/ "\003\000\002"
  3729. "GDT HA %u, async. status 75 unknown",
  3730. };
  3731. static int gdth_async_event(int hanum)
  3732. {
  3733. gdth_ha_str *ha;
  3734. gdth_cmd_str *cmdp;
  3735. int cmd_index;
  3736. ha = HADATA(gdth_ctr_tab[hanum]);
  3737. cmdp= ha->pccb;
  3738. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3739. hanum,ha->service));
  3740. if (ha->service == SCREENSERVICE) {
  3741. if (ha->status == MSG_REQUEST) {
  3742. while (gdth_test_busy(hanum))
  3743. gdth_delay(0);
  3744. cmdp->Service = SCREENSERVICE;
  3745. cmdp->RequestBuffer = SCREEN_CMND;
  3746. cmd_index = gdth_get_cmd_index(hanum);
  3747. gdth_set_sema0(hanum);
  3748. cmdp->OpCode = GDT_READ;
  3749. cmdp->BoardNode = LOCALBOARD;
  3750. cmdp->u.screen.reserved = 0;
  3751. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3752. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3753. ha->cmd_offs_dpmem = 0;
  3754. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3755. + sizeof(ulong64);
  3756. ha->cmd_cnt = 0;
  3757. gdth_copy_command(hanum);
  3758. if (ha->type == GDT_EISA)
  3759. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3760. else if (ha->type == GDT_ISA)
  3761. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3762. else
  3763. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3764. (ushort)((ha->brd_phys>>3)&0x1f));
  3765. gdth_release_event(hanum);
  3766. }
  3767. } else {
  3768. if (ha->type == GDT_PCIMPR &&
  3769. (ha->fw_vers & 0xff) >= 0x1a) {
  3770. ha->dvr.size = 0;
  3771. ha->dvr.eu.async.ionode = hanum;
  3772. ha->dvr.eu.async.status = ha->status;
  3773. /* severity and event_string already set! */
  3774. } else {
  3775. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3776. ha->dvr.eu.async.ionode = hanum;
  3777. ha->dvr.eu.async.service = ha->service;
  3778. ha->dvr.eu.async.status = ha->status;
  3779. ha->dvr.eu.async.info = ha->info;
  3780. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3781. }
  3782. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3783. gdth_log_event( &ha->dvr, NULL );
  3784. /* new host drive from expand? */
  3785. if (ha->service == CACHESERVICE && ha->status == 56) {
  3786. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3787. (ushort)ha->info));
  3788. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3789. }
  3790. }
  3791. return 1;
  3792. }
  3793. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3794. {
  3795. gdth_stackframe stack;
  3796. char *f = NULL;
  3797. int i,j;
  3798. TRACE2(("gdth_log_event()\n"));
  3799. if (dvr->size == 0) {
  3800. if (buffer == NULL) {
  3801. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3802. } else {
  3803. sprintf(buffer,"Adapter %d: %s\n",
  3804. dvr->eu.async.ionode,dvr->event_string);
  3805. }
  3806. } else if (dvr->eu.async.service == CACHESERVICE &&
  3807. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3808. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3809. dvr->eu.async.status));
  3810. f = async_cache_tab[dvr->eu.async.status];
  3811. /* i: parameter to push, j: stack element to fill */
  3812. for (j=0,i=1; i < f[0]; i+=2) {
  3813. switch (f[i+1]) {
  3814. case 4:
  3815. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3816. break;
  3817. case 2:
  3818. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3819. break;
  3820. case 1:
  3821. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3822. break;
  3823. default:
  3824. break;
  3825. }
  3826. }
  3827. if (buffer == NULL) {
  3828. printk(&f[(int)f[0]],stack);
  3829. printk("\n");
  3830. } else {
  3831. sprintf(buffer,&f[(int)f[0]],stack);
  3832. }
  3833. } else {
  3834. if (buffer == NULL) {
  3835. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3836. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3837. } else {
  3838. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3839. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3840. }
  3841. }
  3842. }
  3843. #ifdef GDTH_STATISTICS
  3844. static void gdth_timeout(ulong data)
  3845. {
  3846. ulong32 i;
  3847. Scsi_Cmnd *nscp;
  3848. gdth_ha_str *ha;
  3849. ulong flags;
  3850. int hanum = 0;
  3851. ha = HADATA(gdth_ctr_tab[hanum]);
  3852. spin_lock_irqsave(&ha->smp_lock, flags);
  3853. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3854. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3855. ++act_stats;
  3856. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3857. ++act_rq;
  3858. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3859. act_ints, act_ios, act_stats, act_rq));
  3860. act_ints = act_ios = 0;
  3861. gdth_timer.expires = jiffies + 30 * HZ;
  3862. add_timer(&gdth_timer);
  3863. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3864. }
  3865. #endif
  3866. static void __init internal_setup(char *str,int *ints)
  3867. {
  3868. int i, argc;
  3869. char *cur_str, *argv;
  3870. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3871. str ? str:"NULL", ints ? ints[0]:0));
  3872. /* read irq[] from ints[] */
  3873. if (ints) {
  3874. argc = ints[0];
  3875. if (argc > 0) {
  3876. if (argc > MAXHA)
  3877. argc = MAXHA;
  3878. for (i = 0; i < argc; ++i)
  3879. irq[i] = ints[i+1];
  3880. }
  3881. }
  3882. /* analyse string */
  3883. argv = str;
  3884. while (argv && (cur_str = strchr(argv, ':'))) {
  3885. int val = 0, c = *++cur_str;
  3886. if (c == 'n' || c == 'N')
  3887. val = 0;
  3888. else if (c == 'y' || c == 'Y')
  3889. val = 1;
  3890. else
  3891. val = (int)simple_strtoul(cur_str, NULL, 0);
  3892. if (!strncmp(argv, "disable:", 8))
  3893. disable = val;
  3894. else if (!strncmp(argv, "reserve_mode:", 13))
  3895. reserve_mode = val;
  3896. else if (!strncmp(argv, "reverse_scan:", 13))
  3897. reverse_scan = val;
  3898. else if (!strncmp(argv, "hdr_channel:", 12))
  3899. hdr_channel = val;
  3900. else if (!strncmp(argv, "max_ids:", 8))
  3901. max_ids = val;
  3902. else if (!strncmp(argv, "rescan:", 7))
  3903. rescan = val;
  3904. else if (!strncmp(argv, "virt_ctr:", 9))
  3905. virt_ctr = val;
  3906. else if (!strncmp(argv, "shared_access:", 14))
  3907. shared_access = val;
  3908. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3909. probe_eisa_isa = val;
  3910. else if (!strncmp(argv, "reserve_list:", 13)) {
  3911. reserve_list[0] = val;
  3912. for (i = 1; i < MAX_RES_ARGS; i++) {
  3913. cur_str = strchr(cur_str, ',');
  3914. if (!cur_str)
  3915. break;
  3916. if (!isdigit((int)*++cur_str)) {
  3917. --cur_str;
  3918. break;
  3919. }
  3920. reserve_list[i] =
  3921. (int)simple_strtoul(cur_str, NULL, 0);
  3922. }
  3923. if (!cur_str)
  3924. break;
  3925. argv = ++cur_str;
  3926. continue;
  3927. }
  3928. if ((argv = strchr(argv, ',')))
  3929. ++argv;
  3930. }
  3931. }
  3932. int __init option_setup(char *str)
  3933. {
  3934. int ints[MAXHA];
  3935. char *cur = str;
  3936. int i = 1;
  3937. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3938. while (cur && isdigit(*cur) && i <= MAXHA) {
  3939. ints[i++] = simple_strtoul(cur, NULL, 0);
  3940. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3941. }
  3942. ints[0] = i - 1;
  3943. internal_setup(cur, ints);
  3944. return 1;
  3945. }
  3946. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  3947. static int __init gdth_detect(struct scsi_host_template *shtp)
  3948. #else
  3949. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3950. #endif
  3951. {
  3952. #ifdef DEBUG_GDTH
  3953. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3954. DebugState);
  3955. printk(" Destination of debugging information: ");
  3956. #ifdef __SERIAL__
  3957. #ifdef __COM2__
  3958. printk("Serial port COM2\n");
  3959. #else
  3960. printk("Serial port COM1\n");
  3961. #endif
  3962. #else
  3963. printk("Console\n");
  3964. #endif
  3965. gdth_delay(3000);
  3966. #endif
  3967. TRACE(("gdth_detect()\n"));
  3968. if (disable) {
  3969. printk("GDT-HA: Controller driver disabled from command line !\n");
  3970. return 0;
  3971. }
  3972. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3973. /* initializations */
  3974. gdth_polling = TRUE;
  3975. gdth_clear_events();
  3976. /* As default we do not probe for EISA or ISA controllers */
  3977. if (probe_eisa_isa) {
  3978. /* scanning for controllers, at first: ISA controller */
  3979. #ifdef CONFIG_ISA
  3980. ulong32 isa_bios;
  3981. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  3982. isa_bios += 0x8000UL) {
  3983. if (gdth_ctr_count >= MAXHA)
  3984. break;
  3985. gdth_isa_probe_one(shtp, isa_bios);
  3986. }
  3987. #endif
  3988. #ifdef CONFIG_EISA
  3989. {
  3990. ushort eisa_slot;
  3991. for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) {
  3992. if (gdth_ctr_count >= MAXHA)
  3993. break;
  3994. gdth_eisa_probe_one(shtp, eisa_slot);
  3995. }
  3996. }
  3997. #endif
  3998. }
  3999. #ifdef CONFIG_PCI
  4000. /* scanning for PCI controllers */
  4001. {
  4002. gdth_pci_str pcistr[MAXHA];
  4003. int cnt,ctr;
  4004. cnt = gdth_search_pci(pcistr);
  4005. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4006. gdth_sort_pci(pcistr,cnt);
  4007. for (ctr = 0; ctr < cnt; ++ctr) {
  4008. if (gdth_ctr_count >= MAXHA)
  4009. break;
  4010. gdth_pci_probe_one(shtp, pcistr, ctr);
  4011. }
  4012. }
  4013. #endif /* CONFIG_PCI */
  4014. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4015. if (gdth_ctr_count > 0) {
  4016. #ifdef GDTH_STATISTICS
  4017. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4018. init_timer(&gdth_timer);
  4019. gdth_timer.expires = jiffies + HZ;
  4020. gdth_timer.data = 0L;
  4021. gdth_timer.function = gdth_timeout;
  4022. add_timer(&gdth_timer);
  4023. #endif
  4024. major = register_chrdev(0,"gdth",&gdth_fops);
  4025. notifier_disabled = 0;
  4026. register_reboot_notifier(&gdth_notifier);
  4027. }
  4028. gdth_polling = FALSE;
  4029. return gdth_ctr_vcount;
  4030. }
  4031. static int gdth_release(struct Scsi_Host *shp)
  4032. {
  4033. int hanum;
  4034. gdth_ha_str *ha;
  4035. TRACE2(("gdth_release()\n"));
  4036. if (NUMDATA(shp)->busnum == 0) {
  4037. hanum = NUMDATA(shp)->hanum;
  4038. ha = HADATA(gdth_ctr_tab[hanum]);
  4039. if (ha->sdev) {
  4040. scsi_free_host_dev(ha->sdev);
  4041. ha->sdev = NULL;
  4042. }
  4043. gdth_flush(hanum);
  4044. if (shp->irq) {
  4045. free_irq(shp->irq,ha);
  4046. }
  4047. #ifdef CONFIG_ISA
  4048. if (shp->dma_channel != 0xff) {
  4049. free_dma(shp->dma_channel);
  4050. }
  4051. #endif
  4052. #ifdef INT_COAL
  4053. if (ha->coal_stat)
  4054. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4055. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4056. #endif
  4057. if (ha->pscratch)
  4058. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4059. ha->pscratch, ha->scratch_phys);
  4060. if (ha->pmsg)
  4061. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4062. ha->pmsg, ha->msg_phys);
  4063. if (ha->ccb_phys)
  4064. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4065. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4066. gdth_ctr_released++;
  4067. TRACE2(("gdth_release(): HA %d of %d\n",
  4068. gdth_ctr_released, gdth_ctr_count));
  4069. if (gdth_ctr_released == gdth_ctr_count) {
  4070. #ifdef GDTH_STATISTICS
  4071. del_timer(&gdth_timer);
  4072. #endif
  4073. unregister_chrdev(major,"gdth");
  4074. unregister_reboot_notifier(&gdth_notifier);
  4075. }
  4076. }
  4077. scsi_unregister(shp);
  4078. return 0;
  4079. }
  4080. static const char *gdth_ctr_name(int hanum)
  4081. {
  4082. gdth_ha_str *ha;
  4083. TRACE2(("gdth_ctr_name()\n"));
  4084. ha = HADATA(gdth_ctr_tab[hanum]);
  4085. if (ha->type == GDT_EISA) {
  4086. switch (ha->stype) {
  4087. case GDT3_ID:
  4088. return("GDT3000/3020");
  4089. case GDT3A_ID:
  4090. return("GDT3000A/3020A/3050A");
  4091. case GDT3B_ID:
  4092. return("GDT3000B/3010A");
  4093. }
  4094. } else if (ha->type == GDT_ISA) {
  4095. return("GDT2000/2020");
  4096. } else if (ha->type == GDT_PCI) {
  4097. switch (ha->pdev->device) {
  4098. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4099. return("GDT6000/6020/6050");
  4100. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4101. return("GDT6000B/6010");
  4102. }
  4103. }
  4104. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4105. return("");
  4106. }
  4107. static const char *gdth_info(struct Scsi_Host *shp)
  4108. {
  4109. int hanum;
  4110. gdth_ha_str *ha;
  4111. TRACE2(("gdth_info()\n"));
  4112. hanum = NUMDATA(shp)->hanum;
  4113. ha = HADATA(gdth_ctr_tab[hanum]);
  4114. return ((const char *)ha->binfo.type_string);
  4115. }
  4116. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4117. {
  4118. int i, hanum;
  4119. gdth_ha_str *ha;
  4120. ulong flags;
  4121. Scsi_Cmnd *cmnd;
  4122. unchar b;
  4123. TRACE2(("gdth_eh_bus_reset()\n"));
  4124. hanum = NUMDATA(scp->device->host)->hanum;
  4125. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4126. ha = HADATA(gdth_ctr_tab[hanum]);
  4127. /* clear command tab */
  4128. spin_lock_irqsave(&ha->smp_lock, flags);
  4129. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4130. cmnd = ha->cmd_tab[i].cmnd;
  4131. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4132. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4133. }
  4134. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4135. if (b == ha->virt_bus) {
  4136. /* host drives */
  4137. for (i = 0; i < MAX_HDRIVES; ++i) {
  4138. if (ha->hdr[i].present) {
  4139. spin_lock_irqsave(&ha->smp_lock, flags);
  4140. gdth_polling = TRUE;
  4141. while (gdth_test_busy(hanum))
  4142. gdth_delay(0);
  4143. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4144. GDT_CLUST_RESET, i, 0, 0))
  4145. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4146. gdth_polling = FALSE;
  4147. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4148. }
  4149. }
  4150. } else {
  4151. /* raw devices */
  4152. spin_lock_irqsave(&ha->smp_lock, flags);
  4153. for (i = 0; i < MAXID; ++i)
  4154. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4155. gdth_polling = TRUE;
  4156. while (gdth_test_busy(hanum))
  4157. gdth_delay(0);
  4158. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4159. BUS_L2P(ha,b), 0, 0);
  4160. gdth_polling = FALSE;
  4161. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4162. }
  4163. return SUCCESS;
  4164. }
  4165. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4166. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4167. #else
  4168. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4169. #endif
  4170. {
  4171. unchar b, t;
  4172. int hanum;
  4173. gdth_ha_str *ha;
  4174. struct scsi_device *sd;
  4175. unsigned capacity;
  4176. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4177. sd = sdev;
  4178. capacity = cap;
  4179. #else
  4180. sd = disk->device;
  4181. capacity = disk->capacity;
  4182. #endif
  4183. hanum = NUMDATA(sd->host)->hanum;
  4184. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4185. t = sd->id;
  4186. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4187. ha = HADATA(gdth_ctr_tab[hanum]);
  4188. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4189. /* raw device or host drive without mapping information */
  4190. TRACE2(("Evaluate mapping\n"));
  4191. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4192. } else {
  4193. ip[0] = ha->hdr[t].heads;
  4194. ip[1] = ha->hdr[t].secs;
  4195. ip[2] = capacity / ip[0] / ip[1];
  4196. }
  4197. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4198. ip[0],ip[1],ip[2]));
  4199. return 0;
  4200. }
  4201. static int gdth_queuecommand(struct scsi_cmnd *scp,
  4202. void (*done)(struct scsi_cmnd *))
  4203. {
  4204. int hanum;
  4205. int priority;
  4206. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4207. scp->scsi_done = done;
  4208. scp->SCp.have_data_in = 1;
  4209. scp->SCp.phase = -1;
  4210. scp->SCp.sent_command = -1;
  4211. scp->SCp.Status = GDTH_MAP_NONE;
  4212. scp->SCp.buffer = (struct scatterlist *)NULL;
  4213. hanum = NUMDATA(scp->device->host)->hanum;
  4214. #ifdef GDTH_STATISTICS
  4215. ++act_ios;
  4216. #endif
  4217. priority = DEFAULT_PRI;
  4218. if (IS_GDTH_INTERNAL_CMD(scp))
  4219. priority = scp->SCp.this_residual;
  4220. else
  4221. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4222. gdth_putq( hanum, scp, priority );
  4223. gdth_next( hanum );
  4224. return 0;
  4225. }
  4226. static int gdth_open(struct inode *inode, struct file *filep)
  4227. {
  4228. gdth_ha_str *ha;
  4229. int i;
  4230. for (i = 0; i < gdth_ctr_count; i++) {
  4231. ha = HADATA(gdth_ctr_tab[i]);
  4232. if (!ha->sdev)
  4233. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4234. }
  4235. TRACE(("gdth_open()\n"));
  4236. return 0;
  4237. }
  4238. static int gdth_close(struct inode *inode, struct file *filep)
  4239. {
  4240. TRACE(("gdth_close()\n"));
  4241. return 0;
  4242. }
  4243. static int ioc_event(void __user *arg)
  4244. {
  4245. gdth_ioctl_event evt;
  4246. gdth_ha_str *ha;
  4247. ulong flags;
  4248. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4249. evt.ionode >= gdth_ctr_count)
  4250. return -EFAULT;
  4251. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4252. if (evt.erase == 0xff) {
  4253. if (evt.event.event_source == ES_TEST)
  4254. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4255. else if (evt.event.event_source == ES_DRIVER)
  4256. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4257. else if (evt.event.event_source == ES_SYNC)
  4258. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4259. else
  4260. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4261. spin_lock_irqsave(&ha->smp_lock, flags);
  4262. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4263. &evt.event.event_data);
  4264. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4265. } else if (evt.erase == 0xfe) {
  4266. gdth_clear_events();
  4267. } else if (evt.erase == 0) {
  4268. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4269. } else {
  4270. gdth_readapp_event(ha, evt.erase, &evt.event);
  4271. }
  4272. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4273. return -EFAULT;
  4274. return 0;
  4275. }
  4276. static int ioc_lockdrv(void __user *arg)
  4277. {
  4278. gdth_ioctl_lockdrv ldrv;
  4279. unchar i, j;
  4280. ulong flags;
  4281. gdth_ha_str *ha;
  4282. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4283. ldrv.ionode >= gdth_ctr_count)
  4284. return -EFAULT;
  4285. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4286. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4287. j = ldrv.drives[i];
  4288. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4289. continue;
  4290. if (ldrv.lock) {
  4291. spin_lock_irqsave(&ha->smp_lock, flags);
  4292. ha->hdr[j].lock = 1;
  4293. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4294. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4295. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4296. } else {
  4297. spin_lock_irqsave(&ha->smp_lock, flags);
  4298. ha->hdr[j].lock = 0;
  4299. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4300. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4301. gdth_next(ldrv.ionode);
  4302. }
  4303. }
  4304. return 0;
  4305. }
  4306. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4307. {
  4308. gdth_ioctl_reset res;
  4309. gdth_cmd_str cmd;
  4310. int hanum;
  4311. gdth_ha_str *ha;
  4312. int rval;
  4313. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4314. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4315. return -EFAULT;
  4316. hanum = res.ionode;
  4317. ha = HADATA(gdth_ctr_tab[hanum]);
  4318. if (!ha->hdr[res.number].present)
  4319. return 0;
  4320. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4321. cmd.Service = CACHESERVICE;
  4322. cmd.OpCode = GDT_CLUST_RESET;
  4323. if (ha->cache_feat & GDT_64BIT)
  4324. cmd.u.cache64.DeviceNo = res.number;
  4325. else
  4326. cmd.u.cache.DeviceNo = res.number;
  4327. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  4328. if (rval < 0)
  4329. return rval;
  4330. res.status = rval;
  4331. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4332. return -EFAULT;
  4333. return 0;
  4334. }
  4335. static int ioc_general(void __user *arg, char *cmnd)
  4336. {
  4337. gdth_ioctl_general gen;
  4338. char *buf = NULL;
  4339. ulong64 paddr;
  4340. int hanum;
  4341. gdth_ha_str *ha;
  4342. int rval;
  4343. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4344. gen.ionode >= gdth_ctr_count)
  4345. return -EFAULT;
  4346. hanum = gen.ionode;
  4347. ha = HADATA(gdth_ctr_tab[hanum]);
  4348. if (gen.data_len + gen.sense_len != 0) {
  4349. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4350. FALSE, &paddr)))
  4351. return -EFAULT;
  4352. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4353. gen.data_len + gen.sense_len)) {
  4354. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4355. return -EFAULT;
  4356. }
  4357. if (gen.command.OpCode == GDT_IOCTL) {
  4358. gen.command.u.ioctl.p_param = paddr;
  4359. } else if (gen.command.Service == CACHESERVICE) {
  4360. if (ha->cache_feat & GDT_64BIT) {
  4361. /* copy elements from 32-bit IOCTL structure */
  4362. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4363. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4364. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4365. /* addresses */
  4366. if (ha->cache_feat & SCATTER_GATHER) {
  4367. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4368. gen.command.u.cache64.sg_canz = 1;
  4369. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4370. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4371. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4372. } else {
  4373. gen.command.u.cache64.DestAddr = paddr;
  4374. gen.command.u.cache64.sg_canz = 0;
  4375. }
  4376. } else {
  4377. if (ha->cache_feat & SCATTER_GATHER) {
  4378. gen.command.u.cache.DestAddr = 0xffffffff;
  4379. gen.command.u.cache.sg_canz = 1;
  4380. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4381. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4382. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4383. } else {
  4384. gen.command.u.cache.DestAddr = paddr;
  4385. gen.command.u.cache.sg_canz = 0;
  4386. }
  4387. }
  4388. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4389. if (ha->raw_feat & GDT_64BIT) {
  4390. /* copy elements from 32-bit IOCTL structure */
  4391. char cmd[16];
  4392. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4393. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4394. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4395. gen.command.u.raw64.target = gen.command.u.raw.target;
  4396. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4397. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4398. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4399. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4400. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4401. /* addresses */
  4402. if (ha->raw_feat & SCATTER_GATHER) {
  4403. gen.command.u.raw64.sdata = (ulong64)-1;
  4404. gen.command.u.raw64.sg_ranz = 1;
  4405. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4406. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4407. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4408. } else {
  4409. gen.command.u.raw64.sdata = paddr;
  4410. gen.command.u.raw64.sg_ranz = 0;
  4411. }
  4412. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4413. } else {
  4414. if (ha->raw_feat & SCATTER_GATHER) {
  4415. gen.command.u.raw.sdata = 0xffffffff;
  4416. gen.command.u.raw.sg_ranz = 1;
  4417. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4418. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4419. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4420. } else {
  4421. gen.command.u.raw.sdata = paddr;
  4422. gen.command.u.raw.sg_ranz = 0;
  4423. }
  4424. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4425. }
  4426. } else {
  4427. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4428. return -EFAULT;
  4429. }
  4430. }
  4431. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4432. if (rval < 0)
  4433. return rval;
  4434. gen.status = rval;
  4435. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4436. gen.data_len + gen.sense_len)) {
  4437. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4438. return -EFAULT;
  4439. }
  4440. if (copy_to_user(arg, &gen,
  4441. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4442. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4443. return -EFAULT;
  4444. }
  4445. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4446. return 0;
  4447. }
  4448. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4449. {
  4450. gdth_ioctl_rescan *rsc;
  4451. gdth_cmd_str *cmd;
  4452. gdth_ha_str *ha;
  4453. unchar i;
  4454. int hanum, rc = -ENOMEM;
  4455. u32 cluster_type = 0;
  4456. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4457. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4458. if (!rsc || !cmd)
  4459. goto free_fail;
  4460. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4461. rsc->ionode >= gdth_ctr_count) {
  4462. rc = -EFAULT;
  4463. goto free_fail;
  4464. }
  4465. hanum = rsc->ionode;
  4466. ha = HADATA(gdth_ctr_tab[hanum]);
  4467. memset(cmd, 0, sizeof(gdth_cmd_str));
  4468. for (i = 0; i < MAX_HDRIVES; ++i) {
  4469. if (!ha->hdr[i].present) {
  4470. rsc->hdr_list[i].bus = 0xff;
  4471. continue;
  4472. }
  4473. rsc->hdr_list[i].bus = ha->virt_bus;
  4474. rsc->hdr_list[i].target = i;
  4475. rsc->hdr_list[i].lun = 0;
  4476. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4477. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4478. cmd->Service = CACHESERVICE;
  4479. cmd->OpCode = GDT_CLUST_INFO;
  4480. if (ha->cache_feat & GDT_64BIT)
  4481. cmd->u.cache64.DeviceNo = i;
  4482. else
  4483. cmd->u.cache.DeviceNo = i;
  4484. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4485. rsc->hdr_list[i].cluster_type = cluster_type;
  4486. }
  4487. }
  4488. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4489. rc = -EFAULT;
  4490. else
  4491. rc = 0;
  4492. free_fail:
  4493. kfree(rsc);
  4494. kfree(cmd);
  4495. return rc;
  4496. }
  4497. static int ioc_rescan(void __user *arg, char *cmnd)
  4498. {
  4499. gdth_ioctl_rescan *rsc;
  4500. gdth_cmd_str *cmd;
  4501. ushort i, status, hdr_cnt;
  4502. ulong32 info;
  4503. int hanum, cyls, hds, secs;
  4504. int rc = -ENOMEM;
  4505. ulong flags;
  4506. gdth_ha_str *ha;
  4507. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4508. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4509. if (!cmd || !rsc)
  4510. goto free_fail;
  4511. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4512. rsc->ionode >= gdth_ctr_count) {
  4513. rc = -EFAULT;
  4514. goto free_fail;
  4515. }
  4516. hanum = rsc->ionode;
  4517. ha = HADATA(gdth_ctr_tab[hanum]);
  4518. memset(cmd, 0, sizeof(gdth_cmd_str));
  4519. if (rsc->flag == 0) {
  4520. /* old method: re-init. cache service */
  4521. cmd->Service = CACHESERVICE;
  4522. if (ha->cache_feat & GDT_64BIT) {
  4523. cmd->OpCode = GDT_X_INIT_HOST;
  4524. cmd->u.cache64.DeviceNo = LINUX_OS;
  4525. } else {
  4526. cmd->OpCode = GDT_INIT;
  4527. cmd->u.cache.DeviceNo = LINUX_OS;
  4528. }
  4529. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4530. i = 0;
  4531. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4532. } else {
  4533. i = rsc->hdr_no;
  4534. hdr_cnt = i + 1;
  4535. }
  4536. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4537. cmd->Service = CACHESERVICE;
  4538. cmd->OpCode = GDT_INFO;
  4539. if (ha->cache_feat & GDT_64BIT)
  4540. cmd->u.cache64.DeviceNo = i;
  4541. else
  4542. cmd->u.cache.DeviceNo = i;
  4543. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4544. spin_lock_irqsave(&ha->smp_lock, flags);
  4545. rsc->hdr_list[i].bus = ha->virt_bus;
  4546. rsc->hdr_list[i].target = i;
  4547. rsc->hdr_list[i].lun = 0;
  4548. if (status != S_OK) {
  4549. ha->hdr[i].present = FALSE;
  4550. } else {
  4551. ha->hdr[i].present = TRUE;
  4552. ha->hdr[i].size = info;
  4553. /* evaluate mapping */
  4554. ha->hdr[i].size &= ~SECS32;
  4555. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4556. ha->hdr[i].heads = hds;
  4557. ha->hdr[i].secs = secs;
  4558. /* round size */
  4559. ha->hdr[i].size = cyls * hds * secs;
  4560. }
  4561. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4562. if (status != S_OK)
  4563. continue;
  4564. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4565. /* but we need ha->info2, not yet stored in scp->SCp */
  4566. /* devtype, cluster info, R/W attribs */
  4567. cmd->Service = CACHESERVICE;
  4568. cmd->OpCode = GDT_DEVTYPE;
  4569. if (ha->cache_feat & GDT_64BIT)
  4570. cmd->u.cache64.DeviceNo = i;
  4571. else
  4572. cmd->u.cache.DeviceNo = i;
  4573. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4574. spin_lock_irqsave(&ha->smp_lock, flags);
  4575. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4576. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4577. cmd->Service = CACHESERVICE;
  4578. cmd->OpCode = GDT_CLUST_INFO;
  4579. if (ha->cache_feat & GDT_64BIT)
  4580. cmd->u.cache64.DeviceNo = i;
  4581. else
  4582. cmd->u.cache.DeviceNo = i;
  4583. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4584. spin_lock_irqsave(&ha->smp_lock, flags);
  4585. ha->hdr[i].cluster_type =
  4586. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4587. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4588. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4589. cmd->Service = CACHESERVICE;
  4590. cmd->OpCode = GDT_RW_ATTRIBS;
  4591. if (ha->cache_feat & GDT_64BIT)
  4592. cmd->u.cache64.DeviceNo = i;
  4593. else
  4594. cmd->u.cache.DeviceNo = i;
  4595. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4596. spin_lock_irqsave(&ha->smp_lock, flags);
  4597. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4598. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4599. }
  4600. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4601. rc = -EFAULT;
  4602. else
  4603. rc = 0;
  4604. free_fail:
  4605. kfree(rsc);
  4606. kfree(cmd);
  4607. return rc;
  4608. }
  4609. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4610. unsigned int cmd, unsigned long arg)
  4611. {
  4612. gdth_ha_str *ha;
  4613. Scsi_Cmnd *scp;
  4614. ulong flags;
  4615. char cmnd[MAX_COMMAND_SIZE];
  4616. void __user *argp = (void __user *)arg;
  4617. memset(cmnd, 0xff, 12);
  4618. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4619. switch (cmd) {
  4620. case GDTIOCTL_CTRCNT:
  4621. {
  4622. int cnt = gdth_ctr_count;
  4623. if (put_user(cnt, (int __user *)argp))
  4624. return -EFAULT;
  4625. break;
  4626. }
  4627. case GDTIOCTL_DRVERS:
  4628. {
  4629. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4630. if (put_user(ver, (int __user *)argp))
  4631. return -EFAULT;
  4632. break;
  4633. }
  4634. case GDTIOCTL_OSVERS:
  4635. {
  4636. gdth_ioctl_osvers osv;
  4637. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4638. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4639. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4640. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4641. return -EFAULT;
  4642. break;
  4643. }
  4644. case GDTIOCTL_CTRTYPE:
  4645. {
  4646. gdth_ioctl_ctrtype ctrt;
  4647. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4648. ctrt.ionode >= gdth_ctr_count)
  4649. return -EFAULT;
  4650. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4651. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4652. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4653. } else {
  4654. if (ha->type != GDT_PCIMPR) {
  4655. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4656. } else {
  4657. ctrt.type =
  4658. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4659. if (ha->stype >= 0x300)
  4660. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4661. else
  4662. ctrt.ext_type = 0x6000 | ha->stype;
  4663. }
  4664. ctrt.device_id = ha->pdev->device;
  4665. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4666. }
  4667. ctrt.info = ha->brd_phys;
  4668. ctrt.oem_id = ha->oem_id;
  4669. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4670. return -EFAULT;
  4671. break;
  4672. }
  4673. case GDTIOCTL_GENERAL:
  4674. return ioc_general(argp, cmnd);
  4675. case GDTIOCTL_EVENT:
  4676. return ioc_event(argp);
  4677. case GDTIOCTL_LOCKDRV:
  4678. return ioc_lockdrv(argp);
  4679. case GDTIOCTL_LOCKCHN:
  4680. {
  4681. gdth_ioctl_lockchn lchn;
  4682. unchar i, j;
  4683. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4684. lchn.ionode >= gdth_ctr_count)
  4685. return -EFAULT;
  4686. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4687. i = lchn.channel;
  4688. if (i < ha->bus_cnt) {
  4689. if (lchn.lock) {
  4690. spin_lock_irqsave(&ha->smp_lock, flags);
  4691. ha->raw[i].lock = 1;
  4692. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4693. for (j = 0; j < ha->tid_cnt; ++j) {
  4694. gdth_wait_completion(lchn.ionode, i, j);
  4695. gdth_stop_timeout(lchn.ionode, i, j);
  4696. }
  4697. } else {
  4698. spin_lock_irqsave(&ha->smp_lock, flags);
  4699. ha->raw[i].lock = 0;
  4700. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4701. for (j = 0; j < ha->tid_cnt; ++j) {
  4702. gdth_start_timeout(lchn.ionode, i, j);
  4703. gdth_next(lchn.ionode);
  4704. }
  4705. }
  4706. }
  4707. break;
  4708. }
  4709. case GDTIOCTL_RESCAN:
  4710. return ioc_rescan(argp, cmnd);
  4711. case GDTIOCTL_HDRLIST:
  4712. return ioc_hdrlist(argp, cmnd);
  4713. case GDTIOCTL_RESET_BUS:
  4714. {
  4715. gdth_ioctl_reset res;
  4716. int hanum, rval;
  4717. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4718. res.ionode >= gdth_ctr_count)
  4719. return -EFAULT;
  4720. hanum = res.ionode;
  4721. ha = HADATA(gdth_ctr_tab[hanum]);
  4722. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4723. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4724. if (!scp)
  4725. return -ENOMEM;
  4726. scp->device = ha->sdev;
  4727. scp->cmd_len = 12;
  4728. scp->use_sg = 0;
  4729. scp->device->channel = virt_ctr ? 0 : res.number;
  4730. rval = gdth_eh_bus_reset(scp);
  4731. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4732. kfree(scp);
  4733. #else
  4734. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4735. if (!scp)
  4736. return -ENOMEM;
  4737. scp->cmd_len = 12;
  4738. scp->use_sg = 0;
  4739. scp->channel = virt_ctr ? 0 : res.number;
  4740. rval = gdth_eh_bus_reset(scp);
  4741. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4742. scsi_release_command(scp);
  4743. #endif
  4744. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4745. return -EFAULT;
  4746. break;
  4747. }
  4748. case GDTIOCTL_RESET_DRV:
  4749. return ioc_resetdrv(argp, cmnd);
  4750. default:
  4751. break;
  4752. }
  4753. return 0;
  4754. }
  4755. /* flush routine */
  4756. static void gdth_flush(int hanum)
  4757. {
  4758. int i;
  4759. gdth_ha_str *ha;
  4760. gdth_cmd_str gdtcmd;
  4761. char cmnd[MAX_COMMAND_SIZE];
  4762. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4763. TRACE2(("gdth_flush() hanum %d\n",hanum));
  4764. ha = HADATA(gdth_ctr_tab[hanum]);
  4765. for (i = 0; i < MAX_HDRIVES; ++i) {
  4766. if (ha->hdr[i].present) {
  4767. gdtcmd.BoardNode = LOCALBOARD;
  4768. gdtcmd.Service = CACHESERVICE;
  4769. gdtcmd.OpCode = GDT_FLUSH;
  4770. if (ha->cache_feat & GDT_64BIT) {
  4771. gdtcmd.u.cache64.DeviceNo = i;
  4772. gdtcmd.u.cache64.BlockNo = 1;
  4773. gdtcmd.u.cache64.sg_canz = 0;
  4774. } else {
  4775. gdtcmd.u.cache.DeviceNo = i;
  4776. gdtcmd.u.cache.BlockNo = 1;
  4777. gdtcmd.u.cache.sg_canz = 0;
  4778. }
  4779. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  4780. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  4781. }
  4782. }
  4783. }
  4784. /* shutdown routine */
  4785. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4786. {
  4787. int hanum;
  4788. #ifndef __alpha__
  4789. gdth_cmd_str gdtcmd;
  4790. char cmnd[MAX_COMMAND_SIZE];
  4791. #endif
  4792. if (notifier_disabled)
  4793. return NOTIFY_OK;
  4794. TRACE2(("gdth_halt() event %d\n",(int)event));
  4795. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4796. return NOTIFY_DONE;
  4797. notifier_disabled = 1;
  4798. printk("GDT-HA: Flushing all host drives .. ");
  4799. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  4800. gdth_flush(hanum);
  4801. #ifndef __alpha__
  4802. /* controller reset */
  4803. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4804. gdtcmd.BoardNode = LOCALBOARD;
  4805. gdtcmd.Service = CACHESERVICE;
  4806. gdtcmd.OpCode = GDT_RESET;
  4807. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  4808. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  4809. #endif
  4810. }
  4811. printk("Done.\n");
  4812. #ifdef GDTH_STATISTICS
  4813. del_timer(&gdth_timer);
  4814. #endif
  4815. return NOTIFY_OK;
  4816. }
  4817. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4818. /* configure lun */
  4819. static int gdth_slave_configure(struct scsi_device *sdev)
  4820. {
  4821. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4822. sdev->skip_ms_page_3f = 1;
  4823. sdev->skip_ms_page_8 = 1;
  4824. return 0;
  4825. }
  4826. #endif
  4827. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4828. static struct scsi_host_template driver_template = {
  4829. #else
  4830. static Scsi_Host_Template driver_template = {
  4831. #endif
  4832. .proc_name = "gdth",
  4833. .proc_info = gdth_proc_info,
  4834. .name = "GDT SCSI Disk Array Controller",
  4835. .detect = gdth_detect,
  4836. .release = gdth_release,
  4837. .info = gdth_info,
  4838. .queuecommand = gdth_queuecommand,
  4839. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4840. .bios_param = gdth_bios_param,
  4841. .can_queue = GDTH_MAXCMDS,
  4842. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4843. .slave_configure = gdth_slave_configure,
  4844. #endif
  4845. .this_id = -1,
  4846. .sg_tablesize = GDTH_MAXSG,
  4847. .cmd_per_lun = GDTH_MAXC_P_L,
  4848. .unchecked_isa_dma = 1,
  4849. .use_clustering = ENABLE_CLUSTERING,
  4850. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4851. .use_new_eh_code = 1,
  4852. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  4853. .highmem_io = 1,
  4854. #endif
  4855. #endif
  4856. };
  4857. #ifdef CONFIG_ISA
  4858. static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
  4859. {
  4860. struct Scsi_Host *shp;
  4861. gdth_ha_str *ha;
  4862. dma_addr_t scratch_dma_handle = 0;
  4863. int error, hanum, i;
  4864. u8 b;
  4865. if (!gdth_search_isa(isa_bios))
  4866. return -ENXIO;
  4867. shp = scsi_register(shtp, sizeof(gdth_ext_str));
  4868. if (!shp)
  4869. return -ENOMEM;
  4870. ha = HADATA(shp);
  4871. error = -ENODEV;
  4872. if (!gdth_init_isa(isa_bios,ha))
  4873. goto out_host_put;
  4874. /* controller found and initialized */
  4875. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4876. isa_bios, ha->irq, ha->drq);
  4877. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4878. if (error) {
  4879. printk("GDT-ISA: Unable to allocate IRQ\n");
  4880. goto out_host_put;
  4881. }
  4882. error = request_dma(ha->drq, "gdth");
  4883. if (error) {
  4884. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4885. goto out_free_irq;
  4886. }
  4887. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4888. enable_dma(ha->drq);
  4889. shp->unchecked_isa_dma = 1;
  4890. shp->irq = ha->irq;
  4891. shp->dma_channel = ha->drq;
  4892. hanum = gdth_ctr_count;
  4893. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4894. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4895. NUMDATA(shp)->hanum = (ushort)hanum;
  4896. NUMDATA(shp)->busnum= 0;
  4897. ha->pccb = CMDDATA(shp);
  4898. ha->ccb_phys = 0L;
  4899. ha->pdev = NULL;
  4900. error = -ENOMEM;
  4901. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4902. &scratch_dma_handle);
  4903. if (!ha->pscratch)
  4904. goto out_dec_counters;
  4905. ha->scratch_phys = scratch_dma_handle;
  4906. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4907. &scratch_dma_handle);
  4908. if (!ha->pmsg)
  4909. goto out_free_pscratch;
  4910. ha->msg_phys = scratch_dma_handle;
  4911. #ifdef INT_COAL
  4912. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4913. sizeof(gdth_coal_status) * MAXOFFSETS,
  4914. &scratch_dma_handle);
  4915. if (!ha->coal_stat)
  4916. goto out_free_pmsg;
  4917. ha->coal_stat_phys = scratch_dma_handle;
  4918. #endif
  4919. ha->scratch_busy = FALSE;
  4920. ha->req_first = NULL;
  4921. ha->tid_cnt = MAX_HDRIVES;
  4922. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4923. ha->tid_cnt = max_ids;
  4924. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4925. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4926. ha->scan_mode = rescan ? 0x10 : 0;
  4927. error = -ENODEV;
  4928. if (!gdth_search_drives(hanum)) {
  4929. printk("GDT-ISA: Error during device scan\n");
  4930. goto out_free_coal_stat;
  4931. }
  4932. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4933. hdr_channel = ha->bus_cnt;
  4934. ha->virt_bus = hdr_channel;
  4935. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4936. shp->max_cmd_len = 16;
  4937. shp->max_id = ha->tid_cnt;
  4938. shp->max_lun = MAXLUN;
  4939. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4940. if (virt_ctr) {
  4941. virt_ctr = 1;
  4942. /* register addit. SCSI channels as virtual controllers */
  4943. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4944. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4945. shp->unchecked_isa_dma = 1;
  4946. shp->irq = ha->irq;
  4947. shp->dma_channel = ha->drq;
  4948. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4949. NUMDATA(shp)->hanum = (ushort)hanum;
  4950. NUMDATA(shp)->busnum = b;
  4951. }
  4952. }
  4953. spin_lock_init(&ha->smp_lock);
  4954. gdth_enable_int(hanum);
  4955. return 0;
  4956. out_free_coal_stat:
  4957. #ifdef INT_COAL
  4958. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4959. ha->coal_stat, ha->coal_stat_phys);
  4960. out_free_pmsg:
  4961. #endif
  4962. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4963. ha->pmsg, ha->msg_phys);
  4964. out_free_pscratch:
  4965. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4966. ha->pscratch, ha->scratch_phys);
  4967. out_dec_counters:
  4968. gdth_ctr_count--;
  4969. gdth_ctr_vcount--;
  4970. out_free_irq:
  4971. free_irq(ha->irq, ha);
  4972. out_host_put:
  4973. scsi_unregister(shp);
  4974. return error;
  4975. }
  4976. #endif /* CONFIG_ISA */
  4977. #ifdef CONFIG_EISA
  4978. static int gdth_eisa_probe_one(struct scsi_host_template *shtp,
  4979. ushort eisa_slot)
  4980. {
  4981. struct Scsi_Host *shp;
  4982. gdth_ha_str *ha;
  4983. dma_addr_t scratch_dma_handle = 0;
  4984. int error, hanum, i;
  4985. u8 b;
  4986. if (!gdth_search_eisa(eisa_slot))
  4987. return -ENXIO;
  4988. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4989. if (!shp)
  4990. return -ENOMEM;
  4991. ha = HADATA(shp);
  4992. error = -ENODEV;
  4993. if (!gdth_init_eisa(eisa_slot,ha))
  4994. goto out_host_put;
  4995. /* controller found and initialized */
  4996. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4997. eisa_slot >> 12, ha->irq);
  4998. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4999. if (error) {
  5000. printk("GDT-EISA: Unable to allocate IRQ\n");
  5001. goto out_host_put;
  5002. }
  5003. shp->unchecked_isa_dma = 0;
  5004. shp->irq = ha->irq;
  5005. shp->dma_channel = 0xff;
  5006. hanum = gdth_ctr_count;
  5007. gdth_ctr_tab[gdth_ctr_count++] = shp;
  5008. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5009. NUMDATA(shp)->hanum = (ushort)hanum;
  5010. NUMDATA(shp)->busnum= 0;
  5011. TRACE2(("EISA detect Bus 0: hanum %d\n",
  5012. NUMDATA(shp)->hanum));
  5013. ha->pccb = CMDDATA(shp);
  5014. ha->ccb_phys = 0L;
  5015. error = -ENOMEM;
  5016. ha->pdev = NULL;
  5017. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  5018. &scratch_dma_handle);
  5019. if (!ha->pscratch)
  5020. goto out_free_irq;
  5021. ha->scratch_phys = scratch_dma_handle;
  5022. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  5023. &scratch_dma_handle);
  5024. if (!ha->pmsg)
  5025. goto out_free_pscratch;
  5026. ha->msg_phys = scratch_dma_handle;
  5027. #ifdef INT_COAL
  5028. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  5029. sizeof(gdth_coal_status) * MAXOFFSETS,
  5030. &scratch_dma_handle);
  5031. if (!ha->coal_stat)
  5032. goto out_free_pmsg;
  5033. ha->coal_stat_phys = scratch_dma_handle;
  5034. #endif
  5035. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  5036. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  5037. if (!ha->ccb_phys)
  5038. goto out_free_coal_stat;
  5039. ha->scratch_busy = FALSE;
  5040. ha->req_first = NULL;
  5041. ha->tid_cnt = MAX_HDRIVES;
  5042. if (max_ids > 0 && max_ids < ha->tid_cnt)
  5043. ha->tid_cnt = max_ids;
  5044. for (i = 0; i < GDTH_MAXCMDS; ++i)
  5045. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  5046. ha->scan_mode = rescan ? 0x10 : 0;
  5047. if (!gdth_search_drives(hanum)) {
  5048. printk("GDT-EISA: Error during device scan\n");
  5049. error = -ENODEV;
  5050. goto out_free_ccb_phys;
  5051. }
  5052. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  5053. hdr_channel = ha->bus_cnt;
  5054. ha->virt_bus = hdr_channel;
  5055. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  5056. shp->max_cmd_len = 16;
  5057. shp->max_id = ha->tid_cnt;
  5058. shp->max_lun = MAXLUN;
  5059. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  5060. if (virt_ctr) {
  5061. virt_ctr = 1;
  5062. /* register addit. SCSI channels as virtual controllers */
  5063. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  5064. shp = scsi_register(shtp,sizeof(gdth_num_str));
  5065. shp->unchecked_isa_dma = 0;
  5066. shp->irq = ha->irq;
  5067. shp->dma_channel = 0xff;
  5068. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5069. NUMDATA(shp)->hanum = (ushort)hanum;
  5070. NUMDATA(shp)->busnum = b;
  5071. }
  5072. }
  5073. spin_lock_init(&ha->smp_lock);
  5074. gdth_enable_int(hanum);
  5075. return 0;
  5076. out_free_ccb_phys:
  5077. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  5078. PCI_DMA_BIDIRECTIONAL);
  5079. out_free_coal_stat:
  5080. #ifdef INT_COAL
  5081. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  5082. ha->coal_stat, ha->coal_stat_phys);
  5083. out_free_pmsg:
  5084. #endif
  5085. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  5086. ha->pmsg, ha->msg_phys);
  5087. out_free_pscratch:
  5088. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  5089. ha->pscratch, ha->scratch_phys);
  5090. out_free_irq:
  5091. free_irq(ha->irq, ha);
  5092. gdth_ctr_count--;
  5093. gdth_ctr_vcount--;
  5094. out_host_put:
  5095. scsi_unregister(shp);
  5096. return error;
  5097. }
  5098. #endif /* CONFIG_EISA */
  5099. #ifdef CONFIG_PCI
  5100. static int gdth_pci_probe_one(struct scsi_host_template *shtp,
  5101. gdth_pci_str *pcistr, int ctr)
  5102. {
  5103. struct Scsi_Host *shp;
  5104. gdth_ha_str *ha;
  5105. dma_addr_t scratch_dma_handle = 0;
  5106. int error, hanum, i;
  5107. u8 b;
  5108. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  5109. if (!shp)
  5110. return -ENOMEM;
  5111. ha = HADATA(shp);
  5112. error = -ENODEV;
  5113. if (!gdth_init_pci(&pcistr[ctr],ha))
  5114. goto out_host_put;
  5115. /* controller found and initialized */
  5116. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  5117. pcistr[ctr].pdev->bus->number,
  5118. PCI_SLOT(pcistr[ctr].pdev->devfn),
  5119. ha->irq);
  5120. error = request_irq(ha->irq, gdth_interrupt,
  5121. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  5122. if (error) {
  5123. printk("GDT-PCI: Unable to allocate IRQ\n");
  5124. goto out_host_put;
  5125. }
  5126. shp->unchecked_isa_dma = 0;
  5127. shp->irq = ha->irq;
  5128. shp->dma_channel = 0xff;
  5129. hanum = gdth_ctr_count;
  5130. gdth_ctr_tab[gdth_ctr_count++] = shp;
  5131. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5132. NUMDATA(shp)->hanum = (ushort)hanum;
  5133. NUMDATA(shp)->busnum= 0;
  5134. ha->pccb = CMDDATA(shp);
  5135. ha->ccb_phys = 0L;
  5136. error = -ENOMEM;
  5137. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  5138. &scratch_dma_handle);
  5139. if (!ha->pscratch)
  5140. goto out_free_irq;
  5141. ha->scratch_phys = scratch_dma_handle;
  5142. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  5143. &scratch_dma_handle);
  5144. if (!ha->pmsg)
  5145. goto out_free_pscratch;
  5146. ha->msg_phys = scratch_dma_handle;
  5147. #ifdef INT_COAL
  5148. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  5149. sizeof(gdth_coal_status) * MAXOFFSETS,
  5150. &scratch_dma_handle);
  5151. if (!ha->coal_stat)
  5152. goto out_free_pmsg;
  5153. ha->coal_stat_phys = scratch_dma_handle;
  5154. #endif
  5155. ha->scratch_busy = FALSE;
  5156. ha->req_first = NULL;
  5157. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  5158. if (max_ids > 0 && max_ids < ha->tid_cnt)
  5159. ha->tid_cnt = max_ids;
  5160. for (i = 0; i < GDTH_MAXCMDS; ++i)
  5161. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  5162. ha->scan_mode = rescan ? 0x10 : 0;
  5163. error = -ENODEV;
  5164. if (!gdth_search_drives(hanum)) {
  5165. printk("GDT-PCI %d: Error during device scan\n", hanum);
  5166. goto out_free_coal_stat;
  5167. }
  5168. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  5169. hdr_channel = ha->bus_cnt;
  5170. ha->virt_bus = hdr_channel;
  5171. /* 64-bit DMA only supported from FW >= x.43 */
  5172. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  5173. !ha->dma64_support) {
  5174. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  5175. printk(KERN_WARNING "GDT-PCI %d: "
  5176. "Unable to set 32-bit DMA\n", hanum);
  5177. goto out_free_coal_stat;
  5178. }
  5179. } else {
  5180. shp->max_cmd_len = 16;
  5181. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  5182. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  5183. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  5184. printk(KERN_WARNING "GDT-PCI %d: "
  5185. "Unable to set 64/32-bit DMA\n", hanum);
  5186. goto out_free_coal_stat;
  5187. }
  5188. }
  5189. shp->max_id = ha->tid_cnt;
  5190. shp->max_lun = MAXLUN;
  5191. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  5192. if (virt_ctr) {
  5193. virt_ctr = 1;
  5194. /* register addit. SCSI channels as virtual controllers */
  5195. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  5196. shp = scsi_register(shtp,sizeof(gdth_num_str));
  5197. shp->unchecked_isa_dma = 0;
  5198. shp->irq = ha->irq;
  5199. shp->dma_channel = 0xff;
  5200. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5201. NUMDATA(shp)->hanum = (ushort)hanum;
  5202. NUMDATA(shp)->busnum = b;
  5203. }
  5204. }
  5205. spin_lock_init(&ha->smp_lock);
  5206. gdth_enable_int(hanum);
  5207. return 0;
  5208. out_free_coal_stat:
  5209. #ifdef INT_COAL
  5210. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  5211. ha->coal_stat, ha->coal_stat_phys);
  5212. out_free_pmsg:
  5213. #endif
  5214. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  5215. ha->pmsg, ha->msg_phys);
  5216. out_free_pscratch:
  5217. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  5218. ha->pscratch, ha->scratch_phys);
  5219. out_free_irq:
  5220. free_irq(ha->irq, ha);
  5221. gdth_ctr_count--;
  5222. gdth_ctr_vcount--;
  5223. out_host_put:
  5224. scsi_unregister(shp);
  5225. return error;
  5226. }
  5227. #endif /* CONFIG_PCI */
  5228. #include "scsi_module.c"
  5229. #ifndef MODULE
  5230. __setup("gdth=", option_setup);
  5231. #endif