imx28.dtsi 7.0 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. cpus {
  15. cpu@0 {
  16. compatible = "arm,arm926ejs";
  17. };
  18. };
  19. apb@80000000 {
  20. compatible = "simple-bus";
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. reg = <0x80000000 0x80000>;
  24. ranges;
  25. apbh@80000000 {
  26. compatible = "simple-bus";
  27. #address-cells = <1>;
  28. #size-cells = <1>;
  29. reg = <0x80000000 0x3c900>;
  30. ranges;
  31. icoll: interrupt-controller@80000000 {
  32. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  33. interrupt-controller;
  34. #interrupt-cells = <1>;
  35. reg = <0x80000000 0x2000>;
  36. };
  37. hsadc@80002000 {
  38. reg = <0x80002000 2000>;
  39. interrupts = <13 87>;
  40. status = "disabled";
  41. };
  42. dma-apbh@80004000 {
  43. compatible = "fsl,imx28-dma-apbh";
  44. reg = <0x80004000 2000>;
  45. };
  46. perfmon@80006000 {
  47. reg = <0x80006000 800>;
  48. interrupts = <27>;
  49. status = "disabled";
  50. };
  51. bch@8000a000 {
  52. reg = <0x8000a000 2000>;
  53. interrupts = <41>;
  54. status = "disabled";
  55. };
  56. gpmi@8000c000 {
  57. reg = <0x8000c000 2000>;
  58. interrupts = <42 88>;
  59. status = "disabled";
  60. };
  61. ssp0: ssp@80010000 {
  62. reg = <0x80010000 2000>;
  63. interrupts = <96 82>;
  64. status = "disabled";
  65. };
  66. ssp1: ssp@80012000 {
  67. reg = <0x80012000 2000>;
  68. interrupts = <97 83>;
  69. status = "disabled";
  70. };
  71. ssp2: ssp@80014000 {
  72. reg = <0x80014000 2000>;
  73. interrupts = <98 84>;
  74. status = "disabled";
  75. };
  76. ssp3: ssp@80016000 {
  77. reg = <0x80016000 2000>;
  78. interrupts = <99 85>;
  79. status = "disabled";
  80. };
  81. pinctrl@80018000 {
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. compatible = "fsl,imx28-pinctrl";
  85. reg = <0x80018000 2000>;
  86. duart_pins_a: duart@0 {
  87. reg = <0>;
  88. fsl,pinmux-ids = <0x3102 0x3112>;
  89. fsl,drive-strength = <0>;
  90. fsl,voltage = <1>;
  91. fsl,pull-up = <0>;
  92. };
  93. mac0_pins_a: mac0@0 {
  94. reg = <0>;
  95. fsl,pinmux-ids = <0x4000 0x4010 0x4020
  96. 0x4030 0x4040 0x4060 0x4070
  97. 0x4080 0x4100>;
  98. fsl,drive-strength = <1>;
  99. fsl,voltage = <1>;
  100. fsl,pull-up = <1>;
  101. };
  102. mac1_pins_a: mac1@0 {
  103. reg = <0>;
  104. fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
  105. 0x40e1 0x40b1 0x40c1>;
  106. fsl,drive-strength = <1>;
  107. fsl,voltage = <1>;
  108. fsl,pull-up = <1>;
  109. };
  110. };
  111. digctl@8001c000 {
  112. reg = <0x8001c000 2000>;
  113. interrupts = <89>;
  114. status = "disabled";
  115. };
  116. etm@80022000 {
  117. reg = <0x80022000 2000>;
  118. status = "disabled";
  119. };
  120. dma-apbx@80024000 {
  121. compatible = "fsl,imx28-dma-apbx";
  122. reg = <0x80024000 2000>;
  123. };
  124. dcp@80028000 {
  125. reg = <0x80028000 2000>;
  126. interrupts = <52 53 54>;
  127. status = "disabled";
  128. };
  129. pxp@8002a000 {
  130. reg = <0x8002a000 2000>;
  131. interrupts = <39>;
  132. status = "disabled";
  133. };
  134. ocotp@8002c000 {
  135. reg = <0x8002c000 2000>;
  136. status = "disabled";
  137. };
  138. axi-ahb@8002e000 {
  139. reg = <0x8002e000 2000>;
  140. status = "disabled";
  141. };
  142. lcdif@80030000 {
  143. reg = <0x80030000 2000>;
  144. interrupts = <38 86>;
  145. status = "disabled";
  146. };
  147. can0: can@80032000 {
  148. reg = <0x80032000 2000>;
  149. interrupts = <8>;
  150. status = "disabled";
  151. };
  152. can1: can@80034000 {
  153. reg = <0x80034000 2000>;
  154. interrupts = <9>;
  155. status = "disabled";
  156. };
  157. simdbg@8003c000 {
  158. reg = <0x8003c000 200>;
  159. status = "disabled";
  160. };
  161. simgpmisel@8003c200 {
  162. reg = <0x8003c200 100>;
  163. status = "disabled";
  164. };
  165. simsspsel@8003c300 {
  166. reg = <0x8003c300 100>;
  167. status = "disabled";
  168. };
  169. simmemsel@8003c400 {
  170. reg = <0x8003c400 100>;
  171. status = "disabled";
  172. };
  173. gpiomon@8003c500 {
  174. reg = <0x8003c500 100>;
  175. status = "disabled";
  176. };
  177. simenet@8003c700 {
  178. reg = <0x8003c700 100>;
  179. status = "disabled";
  180. };
  181. armjtag@8003c800 {
  182. reg = <0x8003c800 100>;
  183. status = "disabled";
  184. };
  185. };
  186. apbx@80040000 {
  187. compatible = "simple-bus";
  188. #address-cells = <1>;
  189. #size-cells = <1>;
  190. reg = <0x80040000 0x40000>;
  191. ranges;
  192. clkctl@80040000 {
  193. reg = <0x80040000 2000>;
  194. status = "disabled";
  195. };
  196. saif0: saif@80042000 {
  197. reg = <0x80042000 2000>;
  198. interrupts = <59 80>;
  199. status = "disabled";
  200. };
  201. power@80044000 {
  202. reg = <0x80044000 2000>;
  203. status = "disabled";
  204. };
  205. saif1: saif@80046000 {
  206. reg = <0x80046000 2000>;
  207. interrupts = <58 81>;
  208. status = "disabled";
  209. };
  210. lradc@80050000 {
  211. reg = <0x80050000 2000>;
  212. status = "disabled";
  213. };
  214. spdif@80054000 {
  215. reg = <0x80054000 2000>;
  216. interrupts = <45 66>;
  217. status = "disabled";
  218. };
  219. rtc@80056000 {
  220. reg = <0x80056000 2000>;
  221. interrupts = <28 29>;
  222. status = "disabled";
  223. };
  224. i2c0: i2c@80058000 {
  225. reg = <0x80058000 2000>;
  226. interrupts = <111 68>;
  227. status = "disabled";
  228. };
  229. i2c1: i2c@8005a000 {
  230. reg = <0x8005a000 2000>;
  231. interrupts = <110 69>;
  232. status = "disabled";
  233. };
  234. pwm@80064000 {
  235. reg = <0x80064000 2000>;
  236. status = "disabled";
  237. };
  238. timrot@80068000 {
  239. reg = <0x80068000 2000>;
  240. status = "disabled";
  241. };
  242. auart0: serial@8006a000 {
  243. reg = <0x8006a000 0x2000>;
  244. interrupts = <112 70 71>;
  245. status = "disabled";
  246. };
  247. auart1: serial@8006c000 {
  248. reg = <0x8006c000 0x2000>;
  249. interrupts = <113 72 73>;
  250. status = "disabled";
  251. };
  252. auart2: serial@8006e000 {
  253. reg = <0x8006e000 0x2000>;
  254. interrupts = <114 74 75>;
  255. status = "disabled";
  256. };
  257. auart3: serial@80070000 {
  258. reg = <0x80070000 0x2000>;
  259. interrupts = <115 76 77>;
  260. status = "disabled";
  261. };
  262. auart4: serial@80072000 {
  263. reg = <0x80072000 0x2000>;
  264. interrupts = <116 78 79>;
  265. status = "disabled";
  266. };
  267. duart: serial@80074000 {
  268. compatible = "arm,pl011", "arm,primecell";
  269. reg = <0x80074000 0x1000>;
  270. interrupts = <47>;
  271. status = "disabled";
  272. };
  273. usbphy0: usbphy@8007c000 {
  274. reg = <0x8007c000 0x2000>;
  275. status = "disabled";
  276. };
  277. usbphy1: usbphy@8007e000 {
  278. reg = <0x8007e000 0x2000>;
  279. status = "disabled";
  280. };
  281. };
  282. };
  283. ahb@80080000 {
  284. compatible = "simple-bus";
  285. #address-cells = <1>;
  286. #size-cells = <1>;
  287. reg = <0x80080000 0x80000>;
  288. ranges;
  289. usbctrl0: usbctrl@80080000 {
  290. reg = <0x80080000 0x10000>;
  291. status = "disabled";
  292. };
  293. usbctrl1: usbctrl@80090000 {
  294. reg = <0x80090000 0x10000>;
  295. status = "disabled";
  296. };
  297. dflpt@800c0000 {
  298. reg = <0x800c0000 0x10000>;
  299. status = "disabled";
  300. };
  301. mac0: ethernet@800f0000 {
  302. compatible = "fsl,imx28-fec";
  303. reg = <0x800f0000 0x4000>;
  304. interrupts = <101>;
  305. status = "disabled";
  306. };
  307. mac1: ethernet@800f4000 {
  308. compatible = "fsl,imx28-fec";
  309. reg = <0x800f4000 0x4000>;
  310. interrupts = <102>;
  311. status = "disabled";
  312. };
  313. switch@800f8000 {
  314. reg = <0x800f8000 0x8000>;
  315. status = "disabled";
  316. };
  317. };
  318. };