patch_hdmi.c 45 KB

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  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. *
  10. * Authors:
  11. * Wu Fengguang <wfg@linux.intel.com>
  12. *
  13. * Maintained by:
  14. * Wu Fengguang <wfg@linux.intel.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the Free
  18. * Software Foundation; either version 2 of the License, or (at your option)
  19. * any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful, but
  22. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  23. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  24. * for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software Foundation,
  28. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29. */
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/slab.h>
  33. #include <sound/core.h>
  34. #include "hda_codec.h"
  35. #include "hda_local.h"
  36. /*
  37. * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
  38. * could support two independent pipes, each of them can be connected to one or
  39. * more ports (DVI, HDMI or DisplayPort).
  40. *
  41. * The HDA correspondence of pipes/ports are converter/pin nodes.
  42. */
  43. #define MAX_HDMI_CVTS 3
  44. #define MAX_HDMI_PINS 3
  45. struct hdmi_spec {
  46. int num_cvts;
  47. int num_pins;
  48. hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */
  49. hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */
  50. /*
  51. * source connection for each pin
  52. */
  53. hda_nid_t pin_cvt[MAX_HDMI_PINS+1];
  54. /*
  55. * HDMI sink attached to each pin
  56. */
  57. struct hdmi_eld sink_eld[MAX_HDMI_PINS];
  58. /*
  59. * export one pcm per pipe
  60. */
  61. struct hda_pcm pcm_rec[MAX_HDMI_CVTS];
  62. struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS];
  63. /*
  64. * ati/nvhdmi specific
  65. */
  66. struct hda_multi_out multiout;
  67. struct hda_pcm_stream *pcm_playback;
  68. /* misc flags */
  69. /* PD bit indicates only the update, not the current state */
  70. unsigned int old_pin_detect:1;
  71. };
  72. struct hdmi_audio_infoframe {
  73. u8 type; /* 0x84 */
  74. u8 ver; /* 0x01 */
  75. u8 len; /* 0x0a */
  76. u8 checksum; /* PB0 */
  77. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  78. u8 SS01_SF24;
  79. u8 CXT04;
  80. u8 CA;
  81. u8 LFEPBL01_LSV36_DM_INH7;
  82. u8 reserved[5]; /* PB6 - PB10 */
  83. };
  84. /*
  85. * CEA speaker placement:
  86. *
  87. * FLH FCH FRH
  88. * FLW FL FLC FC FRC FR FRW
  89. *
  90. * LFE
  91. * TC
  92. *
  93. * RL RLC RC RRC RR
  94. *
  95. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  96. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  97. */
  98. enum cea_speaker_placement {
  99. FL = (1 << 0), /* Front Left */
  100. FC = (1 << 1), /* Front Center */
  101. FR = (1 << 2), /* Front Right */
  102. FLC = (1 << 3), /* Front Left Center */
  103. FRC = (1 << 4), /* Front Right Center */
  104. RL = (1 << 5), /* Rear Left */
  105. RC = (1 << 6), /* Rear Center */
  106. RR = (1 << 7), /* Rear Right */
  107. RLC = (1 << 8), /* Rear Left Center */
  108. RRC = (1 << 9), /* Rear Right Center */
  109. LFE = (1 << 10), /* Low Frequency Effect */
  110. FLW = (1 << 11), /* Front Left Wide */
  111. FRW = (1 << 12), /* Front Right Wide */
  112. FLH = (1 << 13), /* Front Left High */
  113. FCH = (1 << 14), /* Front Center High */
  114. FRH = (1 << 15), /* Front Right High */
  115. TC = (1 << 16), /* Top Center */
  116. };
  117. /*
  118. * ELD SA bits in the CEA Speaker Allocation data block
  119. */
  120. static int eld_speaker_allocation_bits[] = {
  121. [0] = FL | FR,
  122. [1] = LFE,
  123. [2] = FC,
  124. [3] = RL | RR,
  125. [4] = RC,
  126. [5] = FLC | FRC,
  127. [6] = RLC | RRC,
  128. /* the following are not defined in ELD yet */
  129. [7] = FLW | FRW,
  130. [8] = FLH | FRH,
  131. [9] = TC,
  132. [10] = FCH,
  133. };
  134. struct cea_channel_speaker_allocation {
  135. int ca_index;
  136. int speakers[8];
  137. /* derived values, just for convenience */
  138. int channels;
  139. int spk_mask;
  140. };
  141. /*
  142. * ALSA sequence is:
  143. *
  144. * surround40 surround41 surround50 surround51 surround71
  145. * ch0 front left = = = =
  146. * ch1 front right = = = =
  147. * ch2 rear left = = = =
  148. * ch3 rear right = = = =
  149. * ch4 LFE center center center
  150. * ch5 LFE LFE
  151. * ch6 side left
  152. * ch7 side right
  153. *
  154. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  155. */
  156. static int hdmi_channel_mapping[0x32][8] = {
  157. /* stereo */
  158. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  159. /* 2.1 */
  160. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  161. /* Dolby Surround */
  162. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  163. /* surround40 */
  164. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  165. /* 4ch */
  166. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  167. /* surround41 */
  168. [0x09] = { 0x00, 0x11, 0x24, 0x34, 0x43, 0xf2, 0xf6, 0xf7 },
  169. /* surround50 */
  170. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  171. /* surround51 */
  172. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  173. /* 7.1 */
  174. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  175. };
  176. /*
  177. * This is an ordered list!
  178. *
  179. * The preceding ones have better chances to be selected by
  180. * hdmi_setup_channel_allocation().
  181. */
  182. static struct cea_channel_speaker_allocation channel_allocations[] = {
  183. /* channel: 7 6 5 4 3 2 1 0 */
  184. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  185. /* 2.1 */
  186. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  187. /* Dolby Surround */
  188. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  189. /* surround40 */
  190. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  191. /* surround41 */
  192. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  193. /* surround50 */
  194. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  195. /* surround51 */
  196. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  197. /* 6.1 */
  198. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  199. /* surround71 */
  200. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  201. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  202. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  203. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  204. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  205. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  206. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  207. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  208. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  209. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  210. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  211. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  212. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  213. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  214. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  215. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  216. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  217. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  218. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  219. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  220. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  221. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  222. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  223. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  224. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  225. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  226. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  227. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  228. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  229. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  230. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  231. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  232. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  233. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  234. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  235. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  236. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  237. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  238. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  239. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  240. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  241. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  242. };
  243. /*
  244. * HDMI routines
  245. */
  246. static int hda_node_index(hda_nid_t *nids, hda_nid_t nid)
  247. {
  248. int i;
  249. for (i = 0; nids[i]; i++)
  250. if (nids[i] == nid)
  251. return i;
  252. snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid);
  253. return -EINVAL;
  254. }
  255. static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid,
  256. struct hdmi_eld *eld)
  257. {
  258. if (!snd_hdmi_get_eld(eld, codec, pin_nid))
  259. snd_hdmi_show_eld(eld);
  260. }
  261. #ifdef BE_PARANOID
  262. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  263. int *packet_index, int *byte_index)
  264. {
  265. int val;
  266. val = snd_hda_codec_read(codec, pin_nid, 0,
  267. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  268. *packet_index = val >> 5;
  269. *byte_index = val & 0x1f;
  270. }
  271. #endif
  272. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  273. int packet_index, int byte_index)
  274. {
  275. int val;
  276. val = (packet_index << 5) | (byte_index & 0x1f);
  277. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  278. }
  279. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  280. unsigned char val)
  281. {
  282. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  283. }
  284. static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid)
  285. {
  286. /* Unmute */
  287. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  288. snd_hda_codec_write(codec, pin_nid, 0,
  289. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  290. /* Enable pin out */
  291. snd_hda_codec_write(codec, pin_nid, 0,
  292. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  293. }
  294. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid)
  295. {
  296. return 1 + snd_hda_codec_read(codec, nid, 0,
  297. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  298. }
  299. static void hdmi_set_channel_count(struct hda_codec *codec,
  300. hda_nid_t nid, int chs)
  301. {
  302. if (chs != hdmi_get_channel_count(codec, nid))
  303. snd_hda_codec_write(codec, nid, 0,
  304. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  305. }
  306. /*
  307. * Channel mapping routines
  308. */
  309. /*
  310. * Compute derived values in channel_allocations[].
  311. */
  312. static void init_channel_allocations(void)
  313. {
  314. int i, j;
  315. struct cea_channel_speaker_allocation *p;
  316. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  317. p = channel_allocations + i;
  318. p->channels = 0;
  319. p->spk_mask = 0;
  320. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  321. if (p->speakers[j]) {
  322. p->channels++;
  323. p->spk_mask |= p->speakers[j];
  324. }
  325. }
  326. }
  327. /*
  328. * The transformation takes two steps:
  329. *
  330. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  331. * spk_mask => (channel_allocations[]) => ai->CA
  332. *
  333. * TODO: it could select the wrong CA from multiple candidates.
  334. */
  335. static int hdmi_setup_channel_allocation(struct hda_codec *codec, hda_nid_t nid,
  336. struct hdmi_audio_infoframe *ai)
  337. {
  338. struct hdmi_spec *spec = codec->spec;
  339. struct hdmi_eld *eld;
  340. int i;
  341. int spk_mask = 0;
  342. int channels = 1 + (ai->CC02_CT47 & 0x7);
  343. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  344. /*
  345. * CA defaults to 0 for basic stereo audio
  346. */
  347. if (channels <= 2)
  348. return 0;
  349. i = hda_node_index(spec->pin_cvt, nid);
  350. if (i < 0)
  351. return 0;
  352. eld = &spec->sink_eld[i];
  353. /*
  354. * HDMI sink's ELD info cannot always be retrieved for now, e.g.
  355. * in console or for audio devices. Assume the highest speakers
  356. * configuration, to _not_ prohibit multi-channel audio playback.
  357. */
  358. if (!eld->spk_alloc)
  359. eld->spk_alloc = 0xffff;
  360. /*
  361. * expand ELD's speaker allocation mask
  362. *
  363. * ELD tells the speaker mask in a compact(paired) form,
  364. * expand ELD's notions to match the ones used by Audio InfoFrame.
  365. */
  366. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  367. if (eld->spk_alloc & (1 << i))
  368. spk_mask |= eld_speaker_allocation_bits[i];
  369. }
  370. /* search for the first working match in the CA table */
  371. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  372. if (channels == channel_allocations[i].channels &&
  373. (spk_mask & channel_allocations[i].spk_mask) ==
  374. channel_allocations[i].spk_mask) {
  375. ai->CA = channel_allocations[i].ca_index;
  376. break;
  377. }
  378. }
  379. snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
  380. snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  381. ai->CA, channels, buf);
  382. return ai->CA;
  383. }
  384. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  385. hda_nid_t pin_nid)
  386. {
  387. #ifdef CONFIG_SND_DEBUG_VERBOSE
  388. int i;
  389. int slot;
  390. for (i = 0; i < 8; i++) {
  391. slot = snd_hda_codec_read(codec, pin_nid, 0,
  392. AC_VERB_GET_HDMI_CHAN_SLOT, i);
  393. printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
  394. slot >> 4, slot & 0xf);
  395. }
  396. #endif
  397. }
  398. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  399. hda_nid_t pin_nid,
  400. struct hdmi_audio_infoframe *ai)
  401. {
  402. int i;
  403. int ca = ai->CA;
  404. int err;
  405. if (hdmi_channel_mapping[ca][1] == 0) {
  406. for (i = 0; i < channel_allocations[ca].channels; i++)
  407. hdmi_channel_mapping[ca][i] = i | (i << 4);
  408. for (; i < 8; i++)
  409. hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
  410. }
  411. for (i = 0; i < 8; i++) {
  412. err = snd_hda_codec_write(codec, pin_nid, 0,
  413. AC_VERB_SET_HDMI_CHAN_SLOT,
  414. hdmi_channel_mapping[ca][i]);
  415. if (err) {
  416. snd_printdd(KERN_NOTICE
  417. "HDMI: channel mapping failed\n");
  418. break;
  419. }
  420. }
  421. hdmi_debug_channel_mapping(codec, pin_nid);
  422. }
  423. /*
  424. * Audio InfoFrame routines
  425. */
  426. /*
  427. * Enable Audio InfoFrame Transmission
  428. */
  429. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  430. hda_nid_t pin_nid)
  431. {
  432. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  433. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  434. AC_DIPXMIT_BEST);
  435. }
  436. /*
  437. * Disable Audio InfoFrame Transmission
  438. */
  439. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  440. hda_nid_t pin_nid)
  441. {
  442. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  443. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  444. AC_DIPXMIT_DISABLE);
  445. }
  446. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  447. {
  448. #ifdef CONFIG_SND_DEBUG_VERBOSE
  449. int i;
  450. int size;
  451. size = snd_hdmi_get_eld_size(codec, pin_nid);
  452. printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
  453. for (i = 0; i < 8; i++) {
  454. size = snd_hda_codec_read(codec, pin_nid, 0,
  455. AC_VERB_GET_HDMI_DIP_SIZE, i);
  456. printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  457. }
  458. #endif
  459. }
  460. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  461. {
  462. #ifdef BE_PARANOID
  463. int i, j;
  464. int size;
  465. int pi, bi;
  466. for (i = 0; i < 8; i++) {
  467. size = snd_hda_codec_read(codec, pin_nid, 0,
  468. AC_VERB_GET_HDMI_DIP_SIZE, i);
  469. if (size == 0)
  470. continue;
  471. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  472. for (j = 1; j < 1000; j++) {
  473. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  474. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  475. if (pi != i)
  476. snd_printd(KERN_INFO "dip index %d: %d != %d\n",
  477. bi, pi, i);
  478. if (bi == 0) /* byte index wrapped around */
  479. break;
  480. }
  481. snd_printd(KERN_INFO
  482. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  483. i, size, j);
  484. }
  485. #endif
  486. }
  487. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *ai)
  488. {
  489. u8 *bytes = (u8 *)ai;
  490. u8 sum = 0;
  491. int i;
  492. ai->checksum = 0;
  493. for (i = 0; i < sizeof(*ai); i++)
  494. sum += bytes[i];
  495. ai->checksum = -sum;
  496. }
  497. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  498. hda_nid_t pin_nid,
  499. struct hdmi_audio_infoframe *ai)
  500. {
  501. u8 *bytes = (u8 *)ai;
  502. int i;
  503. hdmi_debug_dip_size(codec, pin_nid);
  504. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  505. hdmi_checksum_audio_infoframe(ai);
  506. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  507. for (i = 0; i < sizeof(*ai); i++)
  508. hdmi_write_dip_byte(codec, pin_nid, bytes[i]);
  509. }
  510. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  511. struct hdmi_audio_infoframe *ai)
  512. {
  513. u8 *bytes = (u8 *)ai;
  514. u8 val;
  515. int i;
  516. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  517. != AC_DIPXMIT_BEST)
  518. return false;
  519. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  520. for (i = 0; i < sizeof(*ai); i++) {
  521. val = snd_hda_codec_read(codec, pin_nid, 0,
  522. AC_VERB_GET_HDMI_DIP_DATA, 0);
  523. if (val != bytes[i])
  524. return false;
  525. }
  526. return true;
  527. }
  528. static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid,
  529. struct snd_pcm_substream *substream)
  530. {
  531. struct hdmi_spec *spec = codec->spec;
  532. hda_nid_t pin_nid;
  533. int i;
  534. struct hdmi_audio_infoframe ai = {
  535. .type = 0x84,
  536. .ver = 0x01,
  537. .len = 0x0a,
  538. .CC02_CT47 = substream->runtime->channels - 1,
  539. };
  540. hdmi_setup_channel_allocation(codec, nid, &ai);
  541. for (i = 0; i < spec->num_pins; i++) {
  542. if (spec->pin_cvt[i] != nid)
  543. continue;
  544. if (!spec->sink_eld[i].monitor_present)
  545. continue;
  546. pin_nid = spec->pin[i];
  547. if (!hdmi_infoframe_uptodate(codec, pin_nid, &ai)) {
  548. snd_printdd("hdmi_setup_audio_infoframe: "
  549. "cvt=%d pin=%d channels=%d\n",
  550. nid, pin_nid,
  551. substream->runtime->channels);
  552. hdmi_setup_channel_mapping(codec, pin_nid, &ai);
  553. hdmi_stop_infoframe_trans(codec, pin_nid);
  554. hdmi_fill_audio_infoframe(codec, pin_nid, &ai);
  555. hdmi_start_infoframe_trans(codec, pin_nid);
  556. }
  557. }
  558. }
  559. /*
  560. * Unsolicited events
  561. */
  562. static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
  563. struct hdmi_eld *eld);
  564. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  565. {
  566. struct hdmi_spec *spec = codec->spec;
  567. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  568. int pind = !!(res & AC_UNSOL_RES_PD);
  569. int eldv = !!(res & AC_UNSOL_RES_ELDV);
  570. int index;
  571. printk(KERN_INFO
  572. "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  573. tag, pind, eldv);
  574. index = hda_node_index(spec->pin, tag);
  575. if (index < 0)
  576. return;
  577. if (spec->old_pin_detect) {
  578. if (pind)
  579. hdmi_present_sense(codec, tag, &spec->sink_eld[index]);
  580. pind = spec->sink_eld[index].monitor_present;
  581. }
  582. spec->sink_eld[index].monitor_present = pind;
  583. spec->sink_eld[index].eld_valid = eldv;
  584. if (pind && eldv) {
  585. hdmi_get_show_eld(codec, spec->pin[index],
  586. &spec->sink_eld[index]);
  587. /* TODO: do real things about ELD */
  588. }
  589. }
  590. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  591. {
  592. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  593. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  594. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  595. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  596. printk(KERN_INFO
  597. "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  598. tag,
  599. subtag,
  600. cp_state,
  601. cp_ready);
  602. /* TODO */
  603. if (cp_state)
  604. ;
  605. if (cp_ready)
  606. ;
  607. }
  608. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  609. {
  610. struct hdmi_spec *spec = codec->spec;
  611. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  612. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  613. if (hda_node_index(spec->pin, tag) < 0) {
  614. snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
  615. return;
  616. }
  617. if (subtag == 0)
  618. hdmi_intrinsic_event(codec, res);
  619. else
  620. hdmi_non_intrinsic_event(codec, res);
  621. }
  622. /*
  623. * Callbacks
  624. */
  625. /* HBR should be Non-PCM, 8 channels */
  626. #define is_hbr_format(format) \
  627. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  628. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid,
  629. u32 stream_tag, int format)
  630. {
  631. struct hdmi_spec *spec = codec->spec;
  632. int pinctl;
  633. int new_pinctl = 0;
  634. int i;
  635. for (i = 0; i < spec->num_pins; i++) {
  636. if (spec->pin_cvt[i] != nid)
  637. continue;
  638. if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR))
  639. continue;
  640. pinctl = snd_hda_codec_read(codec, spec->pin[i], 0,
  641. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  642. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  643. if (is_hbr_format(format))
  644. new_pinctl |= AC_PINCTL_EPT_HBR;
  645. else
  646. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  647. snd_printdd("hdmi_setup_stream: "
  648. "NID=0x%x, %spinctl=0x%x\n",
  649. spec->pin[i],
  650. pinctl == new_pinctl ? "" : "new-",
  651. new_pinctl);
  652. if (pinctl != new_pinctl)
  653. snd_hda_codec_write(codec, spec->pin[i], 0,
  654. AC_VERB_SET_PIN_WIDGET_CONTROL,
  655. new_pinctl);
  656. }
  657. if (is_hbr_format(format) && !new_pinctl) {
  658. snd_printdd("hdmi_setup_stream: HBR is not supported\n");
  659. return -EINVAL;
  660. }
  661. snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format);
  662. return 0;
  663. }
  664. /*
  665. * HDA PCM callbacks
  666. */
  667. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  668. struct hda_codec *codec,
  669. struct snd_pcm_substream *substream)
  670. {
  671. struct hdmi_spec *spec = codec->spec;
  672. struct hdmi_eld *eld;
  673. struct hda_pcm_stream *codec_pars;
  674. unsigned int idx;
  675. for (idx = 0; idx < spec->num_cvts; idx++)
  676. if (hinfo->nid == spec->cvt[idx])
  677. break;
  678. if (snd_BUG_ON(idx >= spec->num_cvts) ||
  679. snd_BUG_ON(idx >= spec->num_pins))
  680. return -EINVAL;
  681. /* save the PCM info the codec provides */
  682. codec_pars = &spec->codec_pcm_pars[idx];
  683. if (!codec_pars->rates)
  684. *codec_pars = *hinfo;
  685. eld = &spec->sink_eld[idx];
  686. if (eld->sad_count > 0) {
  687. hdmi_eld_update_pcm_info(eld, hinfo, codec_pars);
  688. if (hinfo->channels_min > hinfo->channels_max ||
  689. !hinfo->rates || !hinfo->formats)
  690. return -ENODEV;
  691. } else {
  692. /* fallback to the codec default */
  693. hinfo->channels_min = codec_pars->channels_min;
  694. hinfo->channels_max = codec_pars->channels_max;
  695. hinfo->rates = codec_pars->rates;
  696. hinfo->formats = codec_pars->formats;
  697. hinfo->maxbps = codec_pars->maxbps;
  698. }
  699. return 0;
  700. }
  701. /*
  702. * HDA/HDMI auto parsing
  703. */
  704. static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid)
  705. {
  706. struct hdmi_spec *spec = codec->spec;
  707. hda_nid_t conn_list[HDA_MAX_CONNECTIONS];
  708. int conn_len, curr;
  709. int index;
  710. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  711. snd_printk(KERN_WARNING
  712. "HDMI: pin %d wcaps %#x "
  713. "does not support connection list\n",
  714. pin_nid, get_wcaps(codec, pin_nid));
  715. return -EINVAL;
  716. }
  717. conn_len = snd_hda_get_connections(codec, pin_nid, conn_list,
  718. HDA_MAX_CONNECTIONS);
  719. if (conn_len > 1)
  720. curr = snd_hda_codec_read(codec, pin_nid, 0,
  721. AC_VERB_GET_CONNECT_SEL, 0);
  722. else
  723. curr = 0;
  724. index = hda_node_index(spec->pin, pin_nid);
  725. if (index < 0)
  726. return -EINVAL;
  727. spec->pin_cvt[index] = conn_list[curr];
  728. return 0;
  729. }
  730. static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
  731. struct hdmi_eld *eld)
  732. {
  733. int present = snd_hda_pin_sense(codec, pin_nid);
  734. eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  735. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  736. if (present & AC_PINSENSE_ELDV)
  737. hdmi_get_show_eld(codec, pin_nid, eld);
  738. }
  739. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  740. {
  741. struct hdmi_spec *spec = codec->spec;
  742. if (spec->num_pins >= MAX_HDMI_PINS) {
  743. snd_printk(KERN_WARNING
  744. "HDMI: no space for pin %d\n", pin_nid);
  745. return -E2BIG;
  746. }
  747. hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]);
  748. spec->pin[spec->num_pins] = pin_nid;
  749. spec->num_pins++;
  750. /*
  751. * It is assumed that converter nodes come first in the node list and
  752. * hence have been registered and usable now.
  753. */
  754. return hdmi_read_pin_conn(codec, pin_nid);
  755. }
  756. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid)
  757. {
  758. struct hdmi_spec *spec = codec->spec;
  759. if (spec->num_cvts >= MAX_HDMI_CVTS) {
  760. snd_printk(KERN_WARNING
  761. "HDMI: no space for converter %d\n", nid);
  762. return -E2BIG;
  763. }
  764. spec->cvt[spec->num_cvts] = nid;
  765. spec->num_cvts++;
  766. return 0;
  767. }
  768. static int hdmi_parse_codec(struct hda_codec *codec)
  769. {
  770. hda_nid_t nid;
  771. int i, nodes;
  772. nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
  773. if (!nid || nodes < 0) {
  774. snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
  775. return -EINVAL;
  776. }
  777. for (i = 0; i < nodes; i++, nid++) {
  778. unsigned int caps;
  779. unsigned int type;
  780. caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
  781. type = get_wcaps_type(caps);
  782. if (!(caps & AC_WCAP_DIGITAL))
  783. continue;
  784. switch (type) {
  785. case AC_WID_AUD_OUT:
  786. hdmi_add_cvt(codec, nid);
  787. break;
  788. case AC_WID_PIN:
  789. caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP);
  790. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  791. continue;
  792. hdmi_add_pin(codec, nid);
  793. break;
  794. }
  795. }
  796. /*
  797. * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
  798. * can be lost and presence sense verb will become inaccurate if the
  799. * HDA link is powered off at hot plug or hw initialization time.
  800. */
  801. #ifdef CONFIG_SND_HDA_POWER_SAVE
  802. if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
  803. AC_PWRST_EPSS))
  804. codec->bus->power_keep_link_on = 1;
  805. #endif
  806. return 0;
  807. }
  808. /*
  809. */
  810. static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = {
  811. "HDMI 0",
  812. "HDMI 1",
  813. "HDMI 2",
  814. };
  815. /*
  816. * HDMI callbacks
  817. */
  818. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  819. struct hda_codec *codec,
  820. unsigned int stream_tag,
  821. unsigned int format,
  822. struct snd_pcm_substream *substream)
  823. {
  824. hdmi_set_channel_count(codec, hinfo->nid,
  825. substream->runtime->channels);
  826. hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
  827. return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format);
  828. }
  829. static struct hda_pcm_stream generic_hdmi_pcm_playback = {
  830. .substreams = 1,
  831. .channels_min = 2,
  832. .ops = {
  833. .open = hdmi_pcm_open,
  834. .prepare = generic_hdmi_playback_pcm_prepare,
  835. },
  836. };
  837. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  838. {
  839. struct hdmi_spec *spec = codec->spec;
  840. struct hda_pcm *info = spec->pcm_rec;
  841. int i;
  842. codec->num_pcms = spec->num_cvts;
  843. codec->pcm_info = info;
  844. for (i = 0; i < codec->num_pcms; i++, info++) {
  845. unsigned int chans;
  846. struct hda_pcm_stream *pstr;
  847. chans = get_wcaps(codec, spec->cvt[i]);
  848. chans = get_wcaps_channels(chans);
  849. info->name = generic_hdmi_pcm_names[i];
  850. info->pcm_type = HDA_PCM_TYPE_HDMI;
  851. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  852. if (spec->pcm_playback)
  853. *pstr = *spec->pcm_playback;
  854. else
  855. *pstr = generic_hdmi_pcm_playback;
  856. pstr->nid = spec->cvt[i];
  857. if (pstr->channels_max <= 2 && chans && chans <= 16)
  858. pstr->channels_max = chans;
  859. }
  860. return 0;
  861. }
  862. static int generic_hdmi_build_controls(struct hda_codec *codec)
  863. {
  864. struct hdmi_spec *spec = codec->spec;
  865. int err;
  866. int i;
  867. for (i = 0; i < codec->num_pcms; i++) {
  868. err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]);
  869. if (err < 0)
  870. return err;
  871. }
  872. return 0;
  873. }
  874. static int generic_hdmi_init(struct hda_codec *codec)
  875. {
  876. struct hdmi_spec *spec = codec->spec;
  877. int i;
  878. for (i = 0; spec->pin[i]; i++) {
  879. hdmi_enable_output(codec, spec->pin[i]);
  880. snd_hda_codec_write(codec, spec->pin[i], 0,
  881. AC_VERB_SET_UNSOLICITED_ENABLE,
  882. AC_USRSP_EN | spec->pin[i]);
  883. }
  884. return 0;
  885. }
  886. static void generic_hdmi_free(struct hda_codec *codec)
  887. {
  888. struct hdmi_spec *spec = codec->spec;
  889. int i;
  890. for (i = 0; i < spec->num_pins; i++)
  891. snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
  892. kfree(spec);
  893. }
  894. static struct hda_codec_ops generic_hdmi_patch_ops = {
  895. .init = generic_hdmi_init,
  896. .free = generic_hdmi_free,
  897. .build_pcms = generic_hdmi_build_pcms,
  898. .build_controls = generic_hdmi_build_controls,
  899. .unsol_event = hdmi_unsol_event,
  900. };
  901. static int patch_generic_hdmi(struct hda_codec *codec)
  902. {
  903. struct hdmi_spec *spec;
  904. int i;
  905. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  906. if (spec == NULL)
  907. return -ENOMEM;
  908. codec->spec = spec;
  909. if (hdmi_parse_codec(codec) < 0) {
  910. codec->spec = NULL;
  911. kfree(spec);
  912. return -EINVAL;
  913. }
  914. codec->patch_ops = generic_hdmi_patch_ops;
  915. for (i = 0; i < spec->num_pins; i++)
  916. snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
  917. init_channel_allocations();
  918. return 0;
  919. }
  920. /*
  921. * Nvidia specific implementations
  922. */
  923. #define Nv_VERB_SET_Channel_Allocation 0xF79
  924. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  925. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  926. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  927. #define nvhdmi_master_con_nid_7x 0x04
  928. #define nvhdmi_master_pin_nid_7x 0x05
  929. static hda_nid_t nvhdmi_con_nids_7x[4] = {
  930. /*front, rear, clfe, rear_surr */
  931. 0x6, 0x8, 0xa, 0xc,
  932. };
  933. static struct hda_verb nvhdmi_basic_init_7x[] = {
  934. /* set audio protect on */
  935. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  936. /* enable digital output on pin widget */
  937. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  938. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  939. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  940. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  941. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  942. {} /* terminator */
  943. };
  944. #ifdef LIMITED_RATE_FMT_SUPPORT
  945. /* support only the safe format and rate */
  946. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  947. #define SUPPORTED_MAXBPS 16
  948. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  949. #else
  950. /* support all rates and formats */
  951. #define SUPPORTED_RATES \
  952. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  953. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  954. SNDRV_PCM_RATE_192000)
  955. #define SUPPORTED_MAXBPS 24
  956. #define SUPPORTED_FORMATS \
  957. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  958. #endif
  959. static int nvhdmi_7x_init(struct hda_codec *codec)
  960. {
  961. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
  962. return 0;
  963. }
  964. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  965. struct hda_codec *codec,
  966. struct snd_pcm_substream *substream)
  967. {
  968. struct hdmi_spec *spec = codec->spec;
  969. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  970. }
  971. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  972. struct hda_codec *codec,
  973. struct snd_pcm_substream *substream)
  974. {
  975. struct hdmi_spec *spec = codec->spec;
  976. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  977. }
  978. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  979. struct hda_codec *codec,
  980. unsigned int stream_tag,
  981. unsigned int format,
  982. struct snd_pcm_substream *substream)
  983. {
  984. struct hdmi_spec *spec = codec->spec;
  985. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  986. stream_tag, format, substream);
  987. }
  988. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  989. struct hda_codec *codec,
  990. struct snd_pcm_substream *substream)
  991. {
  992. struct hdmi_spec *spec = codec->spec;
  993. int i;
  994. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  995. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  996. for (i = 0; i < 4; i++) {
  997. /* set the stream id */
  998. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  999. AC_VERB_SET_CHANNEL_STREAMID, 0);
  1000. /* set the stream format */
  1001. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1002. AC_VERB_SET_STREAM_FORMAT, 0);
  1003. }
  1004. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1005. }
  1006. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  1007. struct hda_codec *codec,
  1008. unsigned int stream_tag,
  1009. unsigned int format,
  1010. struct snd_pcm_substream *substream)
  1011. {
  1012. int chs;
  1013. unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
  1014. int i;
  1015. mutex_lock(&codec->spdif_mutex);
  1016. chs = substream->runtime->channels;
  1017. chan = chs ? (chs - 1) : 1;
  1018. switch (chs) {
  1019. default:
  1020. case 0:
  1021. case 2:
  1022. chanmask = 0x00;
  1023. break;
  1024. case 4:
  1025. chanmask = 0x08;
  1026. break;
  1027. case 6:
  1028. chanmask = 0x0b;
  1029. break;
  1030. case 8:
  1031. chanmask = 0x13;
  1032. break;
  1033. }
  1034. dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
  1035. dataDCC2 = 0x2;
  1036. /* set the Audio InforFrame Channel Allocation */
  1037. snd_hda_codec_write(codec, 0x1, 0,
  1038. Nv_VERB_SET_Channel_Allocation, chanmask);
  1039. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  1040. if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
  1041. snd_hda_codec_write(codec,
  1042. nvhdmi_master_con_nid_7x,
  1043. 0,
  1044. AC_VERB_SET_DIGI_CONVERT_1,
  1045. codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
  1046. /* set the stream id */
  1047. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1048. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  1049. /* set the stream format */
  1050. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1051. AC_VERB_SET_STREAM_FORMAT, format);
  1052. /* turn on again (if needed) */
  1053. /* enable and set the channel status audio/data flag */
  1054. if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
  1055. snd_hda_codec_write(codec,
  1056. nvhdmi_master_con_nid_7x,
  1057. 0,
  1058. AC_VERB_SET_DIGI_CONVERT_1,
  1059. codec->spdif_ctls & 0xff);
  1060. snd_hda_codec_write(codec,
  1061. nvhdmi_master_con_nid_7x,
  1062. 0,
  1063. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1064. }
  1065. for (i = 0; i < 4; i++) {
  1066. if (chs == 2)
  1067. channel_id = 0;
  1068. else
  1069. channel_id = i * 2;
  1070. /* turn off SPDIF once;
  1071. *otherwise the IEC958 bits won't be updated
  1072. */
  1073. if (codec->spdif_status_reset &&
  1074. (codec->spdif_ctls & AC_DIG1_ENABLE))
  1075. snd_hda_codec_write(codec,
  1076. nvhdmi_con_nids_7x[i],
  1077. 0,
  1078. AC_VERB_SET_DIGI_CONVERT_1,
  1079. codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
  1080. /* set the stream id */
  1081. snd_hda_codec_write(codec,
  1082. nvhdmi_con_nids_7x[i],
  1083. 0,
  1084. AC_VERB_SET_CHANNEL_STREAMID,
  1085. (stream_tag << 4) | channel_id);
  1086. /* set the stream format */
  1087. snd_hda_codec_write(codec,
  1088. nvhdmi_con_nids_7x[i],
  1089. 0,
  1090. AC_VERB_SET_STREAM_FORMAT,
  1091. format);
  1092. /* turn on again (if needed) */
  1093. /* enable and set the channel status audio/data flag */
  1094. if (codec->spdif_status_reset &&
  1095. (codec->spdif_ctls & AC_DIG1_ENABLE)) {
  1096. snd_hda_codec_write(codec,
  1097. nvhdmi_con_nids_7x[i],
  1098. 0,
  1099. AC_VERB_SET_DIGI_CONVERT_1,
  1100. codec->spdif_ctls & 0xff);
  1101. snd_hda_codec_write(codec,
  1102. nvhdmi_con_nids_7x[i],
  1103. 0,
  1104. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1105. }
  1106. }
  1107. /* set the Audio Info Frame Checksum */
  1108. snd_hda_codec_write(codec, 0x1, 0,
  1109. Nv_VERB_SET_Info_Frame_Checksum,
  1110. (0x71 - chan - chanmask));
  1111. mutex_unlock(&codec->spdif_mutex);
  1112. return 0;
  1113. }
  1114. static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  1115. .substreams = 1,
  1116. .channels_min = 2,
  1117. .channels_max = 8,
  1118. .nid = nvhdmi_master_con_nid_7x,
  1119. .rates = SUPPORTED_RATES,
  1120. .maxbps = SUPPORTED_MAXBPS,
  1121. .formats = SUPPORTED_FORMATS,
  1122. .ops = {
  1123. .open = simple_playback_pcm_open,
  1124. .close = nvhdmi_8ch_7x_pcm_close,
  1125. .prepare = nvhdmi_8ch_7x_pcm_prepare
  1126. },
  1127. };
  1128. static struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
  1129. .substreams = 1,
  1130. .channels_min = 2,
  1131. .channels_max = 2,
  1132. .nid = nvhdmi_master_con_nid_7x,
  1133. .rates = SUPPORTED_RATES,
  1134. .maxbps = SUPPORTED_MAXBPS,
  1135. .formats = SUPPORTED_FORMATS,
  1136. .ops = {
  1137. .open = simple_playback_pcm_open,
  1138. .close = simple_playback_pcm_close,
  1139. .prepare = simple_playback_pcm_prepare
  1140. },
  1141. };
  1142. static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
  1143. .build_controls = generic_hdmi_build_controls,
  1144. .build_pcms = generic_hdmi_build_pcms,
  1145. .init = nvhdmi_7x_init,
  1146. .free = generic_hdmi_free,
  1147. };
  1148. static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
  1149. .build_controls = generic_hdmi_build_controls,
  1150. .build_pcms = generic_hdmi_build_pcms,
  1151. .init = nvhdmi_7x_init,
  1152. .free = generic_hdmi_free,
  1153. };
  1154. static int patch_nvhdmi_8ch_89(struct hda_codec *codec)
  1155. {
  1156. struct hdmi_spec *spec;
  1157. int err = patch_generic_hdmi(codec);
  1158. if (err < 0)
  1159. return err;
  1160. spec = codec->spec;
  1161. spec->old_pin_detect = 1;
  1162. return 0;
  1163. }
  1164. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  1165. {
  1166. struct hdmi_spec *spec;
  1167. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1168. if (spec == NULL)
  1169. return -ENOMEM;
  1170. codec->spec = spec;
  1171. spec->multiout.num_dacs = 0; /* no analog */
  1172. spec->multiout.max_channels = 2;
  1173. spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
  1174. spec->old_pin_detect = 1;
  1175. spec->num_cvts = 1;
  1176. spec->cvt[0] = nvhdmi_master_con_nid_7x;
  1177. spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
  1178. codec->patch_ops = nvhdmi_patch_ops_2ch;
  1179. return 0;
  1180. }
  1181. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  1182. {
  1183. struct hdmi_spec *spec;
  1184. int err = patch_nvhdmi_2ch(codec);
  1185. if (err < 0)
  1186. return err;
  1187. spec = codec->spec;
  1188. spec->multiout.max_channels = 8;
  1189. spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
  1190. codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
  1191. return 0;
  1192. }
  1193. /*
  1194. * ATI-specific implementations
  1195. *
  1196. * FIXME: we may omit the whole this and use the generic code once after
  1197. * it's confirmed to work.
  1198. */
  1199. #define ATIHDMI_CVT_NID 0x02 /* audio converter */
  1200. #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
  1201. static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1202. struct hda_codec *codec,
  1203. unsigned int stream_tag,
  1204. unsigned int format,
  1205. struct snd_pcm_substream *substream)
  1206. {
  1207. struct hdmi_spec *spec = codec->spec;
  1208. int chans = substream->runtime->channels;
  1209. int i, err;
  1210. err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
  1211. substream);
  1212. if (err < 0)
  1213. return err;
  1214. snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT,
  1215. chans - 1);
  1216. /* FIXME: XXX */
  1217. for (i = 0; i < chans; i++) {
  1218. snd_hda_codec_write(codec, spec->cvt[0], 0,
  1219. AC_VERB_SET_HDMI_CHAN_SLOT,
  1220. (i << 4) | i);
  1221. }
  1222. return 0;
  1223. }
  1224. static struct hda_pcm_stream atihdmi_pcm_digital_playback = {
  1225. .substreams = 1,
  1226. .channels_min = 2,
  1227. .channels_max = 2,
  1228. .nid = ATIHDMI_CVT_NID,
  1229. .ops = {
  1230. .open = simple_playback_pcm_open,
  1231. .close = simple_playback_pcm_close,
  1232. .prepare = atihdmi_playback_pcm_prepare
  1233. },
  1234. };
  1235. static struct hda_verb atihdmi_basic_init[] = {
  1236. /* enable digital output on pin widget */
  1237. { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
  1238. {} /* terminator */
  1239. };
  1240. static int atihdmi_init(struct hda_codec *codec)
  1241. {
  1242. struct hdmi_spec *spec = codec->spec;
  1243. snd_hda_sequence_write(codec, atihdmi_basic_init);
  1244. /* SI codec requires to unmute the pin */
  1245. if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP)
  1246. snd_hda_codec_write(codec, spec->pin[0], 0,
  1247. AC_VERB_SET_AMP_GAIN_MUTE,
  1248. AMP_OUT_UNMUTE);
  1249. return 0;
  1250. }
  1251. static struct hda_codec_ops atihdmi_patch_ops = {
  1252. .build_controls = generic_hdmi_build_controls,
  1253. .build_pcms = generic_hdmi_build_pcms,
  1254. .init = atihdmi_init,
  1255. .free = generic_hdmi_free,
  1256. };
  1257. static int patch_atihdmi(struct hda_codec *codec)
  1258. {
  1259. struct hdmi_spec *spec;
  1260. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1261. if (spec == NULL)
  1262. return -ENOMEM;
  1263. codec->spec = spec;
  1264. spec->multiout.num_dacs = 0; /* no analog */
  1265. spec->multiout.max_channels = 2;
  1266. spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
  1267. spec->num_cvts = 1;
  1268. spec->cvt[0] = ATIHDMI_CVT_NID;
  1269. spec->pin[0] = ATIHDMI_PIN_NID;
  1270. spec->pcm_playback = &atihdmi_pcm_digital_playback;
  1271. codec->patch_ops = atihdmi_patch_ops;
  1272. return 0;
  1273. }
  1274. /*
  1275. * patch entries
  1276. */
  1277. static struct hda_codec_preset snd_hda_preset_hdmi[] = {
  1278. { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
  1279. { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
  1280. { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
  1281. { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
  1282. { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
  1283. { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
  1284. { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
  1285. { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1286. { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1287. { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1288. { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1289. { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
  1290. { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1291. { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1292. { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi_8ch_89 },
  1293. { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1294. { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1295. { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1296. { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1297. { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1298. { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1299. { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1300. { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1301. { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1302. { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1303. { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1304. { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1305. { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1306. { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1307. { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1308. { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
  1309. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  1310. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  1311. { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  1312. { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
  1313. { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
  1314. { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
  1315. { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  1316. { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
  1317. { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
  1318. {} /* terminator */
  1319. };
  1320. MODULE_ALIAS("snd-hda-codec-id:1002793c");
  1321. MODULE_ALIAS("snd-hda-codec-id:10027919");
  1322. MODULE_ALIAS("snd-hda-codec-id:1002791a");
  1323. MODULE_ALIAS("snd-hda-codec-id:1002aa01");
  1324. MODULE_ALIAS("snd-hda-codec-id:10951390");
  1325. MODULE_ALIAS("snd-hda-codec-id:10951392");
  1326. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  1327. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  1328. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  1329. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  1330. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  1331. MODULE_ALIAS("snd-hda-codec-id:10de000a");
  1332. MODULE_ALIAS("snd-hda-codec-id:10de000b");
  1333. MODULE_ALIAS("snd-hda-codec-id:10de000c");
  1334. MODULE_ALIAS("snd-hda-codec-id:10de000d");
  1335. MODULE_ALIAS("snd-hda-codec-id:10de0010");
  1336. MODULE_ALIAS("snd-hda-codec-id:10de0011");
  1337. MODULE_ALIAS("snd-hda-codec-id:10de0012");
  1338. MODULE_ALIAS("snd-hda-codec-id:10de0013");
  1339. MODULE_ALIAS("snd-hda-codec-id:10de0014");
  1340. MODULE_ALIAS("snd-hda-codec-id:10de0018");
  1341. MODULE_ALIAS("snd-hda-codec-id:10de0019");
  1342. MODULE_ALIAS("snd-hda-codec-id:10de001a");
  1343. MODULE_ALIAS("snd-hda-codec-id:10de001b");
  1344. MODULE_ALIAS("snd-hda-codec-id:10de001c");
  1345. MODULE_ALIAS("snd-hda-codec-id:10de0040");
  1346. MODULE_ALIAS("snd-hda-codec-id:10de0041");
  1347. MODULE_ALIAS("snd-hda-codec-id:10de0042");
  1348. MODULE_ALIAS("snd-hda-codec-id:10de0043");
  1349. MODULE_ALIAS("snd-hda-codec-id:10de0044");
  1350. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  1351. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  1352. MODULE_ALIAS("snd-hda-codec-id:17e80047");
  1353. MODULE_ALIAS("snd-hda-codec-id:80860054");
  1354. MODULE_ALIAS("snd-hda-codec-id:80862801");
  1355. MODULE_ALIAS("snd-hda-codec-id:80862802");
  1356. MODULE_ALIAS("snd-hda-codec-id:80862803");
  1357. MODULE_ALIAS("snd-hda-codec-id:80862804");
  1358. MODULE_ALIAS("snd-hda-codec-id:80862805");
  1359. MODULE_ALIAS("snd-hda-codec-id:808629fb");
  1360. MODULE_LICENSE("GPL");
  1361. MODULE_DESCRIPTION("HDMI HD-audio codec");
  1362. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  1363. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  1364. MODULE_ALIAS("snd-hda-codec-atihdmi");
  1365. static struct hda_codec_preset_list intel_list = {
  1366. .preset = snd_hda_preset_hdmi,
  1367. .owner = THIS_MODULE,
  1368. };
  1369. static int __init patch_hdmi_init(void)
  1370. {
  1371. return snd_hda_add_codec_preset(&intel_list);
  1372. }
  1373. static void __exit patch_hdmi_exit(void)
  1374. {
  1375. snd_hda_delete_codec_preset(&intel_list);
  1376. }
  1377. module_init(patch_hdmi_init)
  1378. module_exit(patch_hdmi_exit)