cputable.c 38 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC32
  30. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  33. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  38. #endif /* CONFIG_PPC32 */
  39. #ifdef CONFIG_PPC64
  40. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  43. extern void __restore_cpu_pa6t(void);
  44. extern void __restore_cpu_ppc970(void);
  45. #endif /* CONFIG_PPC64 */
  46. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  47. * ones as well...
  48. */
  49. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  50. PPC_FEATURE_HAS_MMU)
  51. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  52. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  53. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  54. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  55. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  56. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  57. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  58. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  59. PPC_FEATURE_TRUE_LE)
  60. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  61. PPC_FEATURE_TRUE_LE | \
  62. PPC_FEATURE_HAS_ALTIVEC_COMP)
  63. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  64. PPC_FEATURE_BOOKE)
  65. static struct cpu_spec cpu_specs[] = {
  66. #ifdef CONFIG_PPC64
  67. { /* Power3 */
  68. .pvr_mask = 0xffff0000,
  69. .pvr_value = 0x00400000,
  70. .cpu_name = "POWER3 (630)",
  71. .cpu_features = CPU_FTRS_POWER3,
  72. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  73. .icache_bsize = 128,
  74. .dcache_bsize = 128,
  75. .num_pmcs = 8,
  76. .pmc_type = PPC_PMC_IBM,
  77. .oprofile_cpu_type = "ppc64/power3",
  78. .oprofile_type = PPC_OPROFILE_RS64,
  79. .platform = "power3",
  80. },
  81. { /* Power3+ */
  82. .pvr_mask = 0xffff0000,
  83. .pvr_value = 0x00410000,
  84. .cpu_name = "POWER3 (630+)",
  85. .cpu_features = CPU_FTRS_POWER3,
  86. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  87. .icache_bsize = 128,
  88. .dcache_bsize = 128,
  89. .num_pmcs = 8,
  90. .pmc_type = PPC_PMC_IBM,
  91. .oprofile_cpu_type = "ppc64/power3",
  92. .oprofile_type = PPC_OPROFILE_RS64,
  93. .platform = "power3",
  94. },
  95. { /* Northstar */
  96. .pvr_mask = 0xffff0000,
  97. .pvr_value = 0x00330000,
  98. .cpu_name = "RS64-II (northstar)",
  99. .cpu_features = CPU_FTRS_RS64,
  100. .cpu_user_features = COMMON_USER_PPC64,
  101. .icache_bsize = 128,
  102. .dcache_bsize = 128,
  103. .num_pmcs = 8,
  104. .pmc_type = PPC_PMC_IBM,
  105. .oprofile_cpu_type = "ppc64/rs64",
  106. .oprofile_type = PPC_OPROFILE_RS64,
  107. .platform = "rs64",
  108. },
  109. { /* Pulsar */
  110. .pvr_mask = 0xffff0000,
  111. .pvr_value = 0x00340000,
  112. .cpu_name = "RS64-III (pulsar)",
  113. .cpu_features = CPU_FTRS_RS64,
  114. .cpu_user_features = COMMON_USER_PPC64,
  115. .icache_bsize = 128,
  116. .dcache_bsize = 128,
  117. .num_pmcs = 8,
  118. .pmc_type = PPC_PMC_IBM,
  119. .oprofile_cpu_type = "ppc64/rs64",
  120. .oprofile_type = PPC_OPROFILE_RS64,
  121. .platform = "rs64",
  122. },
  123. { /* I-star */
  124. .pvr_mask = 0xffff0000,
  125. .pvr_value = 0x00360000,
  126. .cpu_name = "RS64-III (icestar)",
  127. .cpu_features = CPU_FTRS_RS64,
  128. .cpu_user_features = COMMON_USER_PPC64,
  129. .icache_bsize = 128,
  130. .dcache_bsize = 128,
  131. .num_pmcs = 8,
  132. .pmc_type = PPC_PMC_IBM,
  133. .oprofile_cpu_type = "ppc64/rs64",
  134. .oprofile_type = PPC_OPROFILE_RS64,
  135. .platform = "rs64",
  136. },
  137. { /* S-star */
  138. .pvr_mask = 0xffff0000,
  139. .pvr_value = 0x00370000,
  140. .cpu_name = "RS64-IV (sstar)",
  141. .cpu_features = CPU_FTRS_RS64,
  142. .cpu_user_features = COMMON_USER_PPC64,
  143. .icache_bsize = 128,
  144. .dcache_bsize = 128,
  145. .num_pmcs = 8,
  146. .pmc_type = PPC_PMC_IBM,
  147. .oprofile_cpu_type = "ppc64/rs64",
  148. .oprofile_type = PPC_OPROFILE_RS64,
  149. .platform = "rs64",
  150. },
  151. { /* Power4 */
  152. .pvr_mask = 0xffff0000,
  153. .pvr_value = 0x00350000,
  154. .cpu_name = "POWER4 (gp)",
  155. .cpu_features = CPU_FTRS_POWER4,
  156. .cpu_user_features = COMMON_USER_POWER4,
  157. .icache_bsize = 128,
  158. .dcache_bsize = 128,
  159. .num_pmcs = 8,
  160. .pmc_type = PPC_PMC_IBM,
  161. .oprofile_cpu_type = "ppc64/power4",
  162. .oprofile_type = PPC_OPROFILE_POWER4,
  163. .platform = "power4",
  164. },
  165. { /* Power4+ */
  166. .pvr_mask = 0xffff0000,
  167. .pvr_value = 0x00380000,
  168. .cpu_name = "POWER4+ (gq)",
  169. .cpu_features = CPU_FTRS_POWER4,
  170. .cpu_user_features = COMMON_USER_POWER4,
  171. .icache_bsize = 128,
  172. .dcache_bsize = 128,
  173. .num_pmcs = 8,
  174. .pmc_type = PPC_PMC_IBM,
  175. .oprofile_cpu_type = "ppc64/power4",
  176. .oprofile_type = PPC_OPROFILE_POWER4,
  177. .platform = "power4",
  178. },
  179. { /* PPC970 */
  180. .pvr_mask = 0xffff0000,
  181. .pvr_value = 0x00390000,
  182. .cpu_name = "PPC970",
  183. .cpu_features = CPU_FTRS_PPC970,
  184. .cpu_user_features = COMMON_USER_POWER4 |
  185. PPC_FEATURE_HAS_ALTIVEC_COMP,
  186. .icache_bsize = 128,
  187. .dcache_bsize = 128,
  188. .num_pmcs = 8,
  189. .pmc_type = PPC_PMC_IBM,
  190. .cpu_setup = __setup_cpu_ppc970,
  191. .cpu_restore = __restore_cpu_ppc970,
  192. .oprofile_cpu_type = "ppc64/970",
  193. .oprofile_type = PPC_OPROFILE_POWER4,
  194. .platform = "ppc970",
  195. },
  196. { /* PPC970FX */
  197. .pvr_mask = 0xffff0000,
  198. .pvr_value = 0x003c0000,
  199. .cpu_name = "PPC970FX",
  200. .cpu_features = CPU_FTRS_PPC970,
  201. .cpu_user_features = COMMON_USER_POWER4 |
  202. PPC_FEATURE_HAS_ALTIVEC_COMP,
  203. .icache_bsize = 128,
  204. .dcache_bsize = 128,
  205. .num_pmcs = 8,
  206. .pmc_type = PPC_PMC_IBM,
  207. .cpu_setup = __setup_cpu_ppc970,
  208. .cpu_restore = __restore_cpu_ppc970,
  209. .oprofile_cpu_type = "ppc64/970",
  210. .oprofile_type = PPC_OPROFILE_POWER4,
  211. .platform = "ppc970",
  212. },
  213. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  214. .pvr_mask = 0xffffffff,
  215. .pvr_value = 0x00440100,
  216. .cpu_name = "PPC970MP",
  217. .cpu_features = CPU_FTRS_PPC970,
  218. .cpu_user_features = COMMON_USER_POWER4 |
  219. PPC_FEATURE_HAS_ALTIVEC_COMP,
  220. .icache_bsize = 128,
  221. .dcache_bsize = 128,
  222. .num_pmcs = 8,
  223. .pmc_type = PPC_PMC_IBM,
  224. .cpu_setup = __setup_cpu_ppc970,
  225. .cpu_restore = __restore_cpu_ppc970,
  226. .oprofile_cpu_type = "ppc64/970MP",
  227. .oprofile_type = PPC_OPROFILE_POWER4,
  228. .platform = "ppc970",
  229. },
  230. { /* PPC970MP */
  231. .pvr_mask = 0xffff0000,
  232. .pvr_value = 0x00440000,
  233. .cpu_name = "PPC970MP",
  234. .cpu_features = CPU_FTRS_PPC970,
  235. .cpu_user_features = COMMON_USER_POWER4 |
  236. PPC_FEATURE_HAS_ALTIVEC_COMP,
  237. .icache_bsize = 128,
  238. .dcache_bsize = 128,
  239. .num_pmcs = 8,
  240. .pmc_type = PPC_PMC_IBM,
  241. .cpu_setup = __setup_cpu_ppc970MP,
  242. .cpu_restore = __restore_cpu_ppc970,
  243. .oprofile_cpu_type = "ppc64/970MP",
  244. .oprofile_type = PPC_OPROFILE_POWER4,
  245. .platform = "ppc970",
  246. },
  247. { /* PPC970GX */
  248. .pvr_mask = 0xffff0000,
  249. .pvr_value = 0x00450000,
  250. .cpu_name = "PPC970GX",
  251. .cpu_features = CPU_FTRS_PPC970,
  252. .cpu_user_features = COMMON_USER_POWER4 |
  253. PPC_FEATURE_HAS_ALTIVEC_COMP,
  254. .icache_bsize = 128,
  255. .dcache_bsize = 128,
  256. .num_pmcs = 8,
  257. .pmc_type = PPC_PMC_IBM,
  258. .cpu_setup = __setup_cpu_ppc970,
  259. .oprofile_cpu_type = "ppc64/970",
  260. .oprofile_type = PPC_OPROFILE_POWER4,
  261. .platform = "ppc970",
  262. },
  263. { /* Power5 GR */
  264. .pvr_mask = 0xffff0000,
  265. .pvr_value = 0x003a0000,
  266. .cpu_name = "POWER5 (gr)",
  267. .cpu_features = CPU_FTRS_POWER5,
  268. .cpu_user_features = COMMON_USER_POWER5,
  269. .icache_bsize = 128,
  270. .dcache_bsize = 128,
  271. .num_pmcs = 6,
  272. .pmc_type = PPC_PMC_IBM,
  273. .oprofile_cpu_type = "ppc64/power5",
  274. .oprofile_type = PPC_OPROFILE_POWER4,
  275. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  276. * and above but only works on POWER5 and above
  277. */
  278. .oprofile_mmcra_sihv = MMCRA_SIHV,
  279. .oprofile_mmcra_sipr = MMCRA_SIPR,
  280. .platform = "power5",
  281. },
  282. { /* Power5++ */
  283. .pvr_mask = 0xffffff00,
  284. .pvr_value = 0x003b0300,
  285. .cpu_name = "POWER5+ (gs)",
  286. .cpu_features = CPU_FTRS_POWER5,
  287. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  288. .icache_bsize = 128,
  289. .dcache_bsize = 128,
  290. .num_pmcs = 6,
  291. .oprofile_cpu_type = "ppc64/power5++",
  292. .oprofile_type = PPC_OPROFILE_POWER4,
  293. .oprofile_mmcra_sihv = MMCRA_SIHV,
  294. .oprofile_mmcra_sipr = MMCRA_SIPR,
  295. .platform = "power5+",
  296. },
  297. { /* Power5 GS */
  298. .pvr_mask = 0xffff0000,
  299. .pvr_value = 0x003b0000,
  300. .cpu_name = "POWER5+ (gs)",
  301. .cpu_features = CPU_FTRS_POWER5,
  302. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  303. .icache_bsize = 128,
  304. .dcache_bsize = 128,
  305. .num_pmcs = 6,
  306. .pmc_type = PPC_PMC_IBM,
  307. .oprofile_cpu_type = "ppc64/power5+",
  308. .oprofile_type = PPC_OPROFILE_POWER4,
  309. .oprofile_mmcra_sihv = MMCRA_SIHV,
  310. .oprofile_mmcra_sipr = MMCRA_SIPR,
  311. .platform = "power5+",
  312. },
  313. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  314. .pvr_mask = 0xffffffff,
  315. .pvr_value = 0x0f000001,
  316. .cpu_name = "POWER5+",
  317. .cpu_features = CPU_FTRS_POWER5,
  318. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  319. .icache_bsize = 128,
  320. .dcache_bsize = 128,
  321. .num_pmcs = 6,
  322. .pmc_type = PPC_PMC_IBM,
  323. .oprofile_cpu_type = "ppc64/power6",
  324. .oprofile_type = PPC_OPROFILE_POWER4,
  325. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  326. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  327. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  328. POWER6_MMCRA_OTHER,
  329. .platform = "power5+",
  330. },
  331. { /* Power6 */
  332. .pvr_mask = 0xffff0000,
  333. .pvr_value = 0x003e0000,
  334. .cpu_name = "POWER6 (raw)",
  335. .cpu_features = CPU_FTRS_POWER6,
  336. .cpu_user_features = COMMON_USER_POWER6 |
  337. PPC_FEATURE_POWER6_EXT,
  338. .icache_bsize = 128,
  339. .dcache_bsize = 128,
  340. .num_pmcs = 6,
  341. .pmc_type = PPC_PMC_IBM,
  342. .oprofile_cpu_type = "ppc64/power6",
  343. .oprofile_type = PPC_OPROFILE_POWER4,
  344. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  345. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  346. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  347. POWER6_MMCRA_OTHER,
  348. .platform = "power6x",
  349. },
  350. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  351. .pvr_mask = 0xffffffff,
  352. .pvr_value = 0x0f000002,
  353. .cpu_name = "POWER6 (architected)",
  354. .cpu_features = CPU_FTRS_POWER6,
  355. .cpu_user_features = COMMON_USER_POWER6,
  356. .icache_bsize = 128,
  357. .dcache_bsize = 128,
  358. .num_pmcs = 6,
  359. .pmc_type = PPC_PMC_IBM,
  360. .oprofile_cpu_type = "ppc64/power6",
  361. .oprofile_type = PPC_OPROFILE_POWER4,
  362. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  363. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  364. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  365. POWER6_MMCRA_OTHER,
  366. .platform = "power6",
  367. },
  368. { /* Cell Broadband Engine */
  369. .pvr_mask = 0xffff0000,
  370. .pvr_value = 0x00700000,
  371. .cpu_name = "Cell Broadband Engine",
  372. .cpu_features = CPU_FTRS_CELL,
  373. .cpu_user_features = COMMON_USER_PPC64 |
  374. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  375. PPC_FEATURE_SMT,
  376. .icache_bsize = 128,
  377. .dcache_bsize = 128,
  378. .num_pmcs = 4,
  379. .pmc_type = PPC_PMC_IBM,
  380. .oprofile_cpu_type = "ppc64/cell-be",
  381. .oprofile_type = PPC_OPROFILE_CELL,
  382. .platform = "ppc-cell-be",
  383. },
  384. { /* PA Semi PA6T */
  385. .pvr_mask = 0x7fff0000,
  386. .pvr_value = 0x00900000,
  387. .cpu_name = "PA6T",
  388. .cpu_features = CPU_FTRS_PA6T,
  389. .cpu_user_features = COMMON_USER_PA6T,
  390. .icache_bsize = 64,
  391. .dcache_bsize = 64,
  392. .num_pmcs = 6,
  393. .pmc_type = PPC_PMC_PA6T,
  394. .cpu_setup = __setup_cpu_pa6t,
  395. .cpu_restore = __restore_cpu_pa6t,
  396. .oprofile_cpu_type = "ppc64/pa6t",
  397. .oprofile_type = PPC_OPROFILE_PA6T,
  398. .platform = "pa6t",
  399. },
  400. { /* default match */
  401. .pvr_mask = 0x00000000,
  402. .pvr_value = 0x00000000,
  403. .cpu_name = "POWER4 (compatible)",
  404. .cpu_features = CPU_FTRS_COMPATIBLE,
  405. .cpu_user_features = COMMON_USER_PPC64,
  406. .icache_bsize = 128,
  407. .dcache_bsize = 128,
  408. .num_pmcs = 6,
  409. .pmc_type = PPC_PMC_IBM,
  410. .platform = "power4",
  411. }
  412. #endif /* CONFIG_PPC64 */
  413. #ifdef CONFIG_PPC32
  414. #if CLASSIC_PPC
  415. { /* 601 */
  416. .pvr_mask = 0xffff0000,
  417. .pvr_value = 0x00010000,
  418. .cpu_name = "601",
  419. .cpu_features = CPU_FTRS_PPC601,
  420. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  421. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  422. .icache_bsize = 32,
  423. .dcache_bsize = 32,
  424. .platform = "ppc601",
  425. },
  426. { /* 603 */
  427. .pvr_mask = 0xffff0000,
  428. .pvr_value = 0x00030000,
  429. .cpu_name = "603",
  430. .cpu_features = CPU_FTRS_603,
  431. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  432. .icache_bsize = 32,
  433. .dcache_bsize = 32,
  434. .cpu_setup = __setup_cpu_603,
  435. .platform = "ppc603",
  436. },
  437. { /* 603e */
  438. .pvr_mask = 0xffff0000,
  439. .pvr_value = 0x00060000,
  440. .cpu_name = "603e",
  441. .cpu_features = CPU_FTRS_603,
  442. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  443. .icache_bsize = 32,
  444. .dcache_bsize = 32,
  445. .cpu_setup = __setup_cpu_603,
  446. .platform = "ppc603",
  447. },
  448. { /* 603ev */
  449. .pvr_mask = 0xffff0000,
  450. .pvr_value = 0x00070000,
  451. .cpu_name = "603ev",
  452. .cpu_features = CPU_FTRS_603,
  453. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  454. .icache_bsize = 32,
  455. .dcache_bsize = 32,
  456. .cpu_setup = __setup_cpu_603,
  457. .platform = "ppc603",
  458. },
  459. { /* 604 */
  460. .pvr_mask = 0xffff0000,
  461. .pvr_value = 0x00040000,
  462. .cpu_name = "604",
  463. .cpu_features = CPU_FTRS_604,
  464. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  465. .icache_bsize = 32,
  466. .dcache_bsize = 32,
  467. .num_pmcs = 2,
  468. .cpu_setup = __setup_cpu_604,
  469. .platform = "ppc604",
  470. },
  471. { /* 604e */
  472. .pvr_mask = 0xfffff000,
  473. .pvr_value = 0x00090000,
  474. .cpu_name = "604e",
  475. .cpu_features = CPU_FTRS_604,
  476. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  477. .icache_bsize = 32,
  478. .dcache_bsize = 32,
  479. .num_pmcs = 4,
  480. .cpu_setup = __setup_cpu_604,
  481. .platform = "ppc604",
  482. },
  483. { /* 604r */
  484. .pvr_mask = 0xffff0000,
  485. .pvr_value = 0x00090000,
  486. .cpu_name = "604r",
  487. .cpu_features = CPU_FTRS_604,
  488. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  489. .icache_bsize = 32,
  490. .dcache_bsize = 32,
  491. .num_pmcs = 4,
  492. .cpu_setup = __setup_cpu_604,
  493. .platform = "ppc604",
  494. },
  495. { /* 604ev */
  496. .pvr_mask = 0xffff0000,
  497. .pvr_value = 0x000a0000,
  498. .cpu_name = "604ev",
  499. .cpu_features = CPU_FTRS_604,
  500. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  501. .icache_bsize = 32,
  502. .dcache_bsize = 32,
  503. .num_pmcs = 4,
  504. .cpu_setup = __setup_cpu_604,
  505. .platform = "ppc604",
  506. },
  507. { /* 740/750 (0x4202, don't support TAU ?) */
  508. .pvr_mask = 0xffffffff,
  509. .pvr_value = 0x00084202,
  510. .cpu_name = "740/750",
  511. .cpu_features = CPU_FTRS_740_NOTAU,
  512. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  513. .icache_bsize = 32,
  514. .dcache_bsize = 32,
  515. .num_pmcs = 4,
  516. .cpu_setup = __setup_cpu_750,
  517. .platform = "ppc750",
  518. },
  519. { /* 750CX (80100 and 8010x?) */
  520. .pvr_mask = 0xfffffff0,
  521. .pvr_value = 0x00080100,
  522. .cpu_name = "750CX",
  523. .cpu_features = CPU_FTRS_750,
  524. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  525. .icache_bsize = 32,
  526. .dcache_bsize = 32,
  527. .num_pmcs = 4,
  528. .cpu_setup = __setup_cpu_750cx,
  529. .platform = "ppc750",
  530. },
  531. { /* 750CX (82201 and 82202) */
  532. .pvr_mask = 0xfffffff0,
  533. .pvr_value = 0x00082200,
  534. .cpu_name = "750CX",
  535. .cpu_features = CPU_FTRS_750,
  536. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  537. .icache_bsize = 32,
  538. .dcache_bsize = 32,
  539. .num_pmcs = 4,
  540. .cpu_setup = __setup_cpu_750cx,
  541. .platform = "ppc750",
  542. },
  543. { /* 750CXe (82214) */
  544. .pvr_mask = 0xfffffff0,
  545. .pvr_value = 0x00082210,
  546. .cpu_name = "750CXe",
  547. .cpu_features = CPU_FTRS_750,
  548. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  549. .icache_bsize = 32,
  550. .dcache_bsize = 32,
  551. .num_pmcs = 4,
  552. .cpu_setup = __setup_cpu_750cx,
  553. .platform = "ppc750",
  554. },
  555. { /* 750CXe "Gekko" (83214) */
  556. .pvr_mask = 0xffffffff,
  557. .pvr_value = 0x00083214,
  558. .cpu_name = "750CXe",
  559. .cpu_features = CPU_FTRS_750,
  560. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  561. .icache_bsize = 32,
  562. .dcache_bsize = 32,
  563. .num_pmcs = 4,
  564. .cpu_setup = __setup_cpu_750cx,
  565. .platform = "ppc750",
  566. },
  567. { /* 750CL */
  568. .pvr_mask = 0xfffff0f0,
  569. .pvr_value = 0x00087010,
  570. .cpu_name = "750CL",
  571. .cpu_features = CPU_FTRS_750CL,
  572. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  573. .icache_bsize = 32,
  574. .dcache_bsize = 32,
  575. .num_pmcs = 4,
  576. .cpu_setup = __setup_cpu_750,
  577. .platform = "ppc750",
  578. },
  579. { /* 745/755 */
  580. .pvr_mask = 0xfffff000,
  581. .pvr_value = 0x00083000,
  582. .cpu_name = "745/755",
  583. .cpu_features = CPU_FTRS_750,
  584. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  585. .icache_bsize = 32,
  586. .dcache_bsize = 32,
  587. .num_pmcs = 4,
  588. .cpu_setup = __setup_cpu_750,
  589. .platform = "ppc750",
  590. },
  591. { /* 750FX rev 1.x */
  592. .pvr_mask = 0xffffff00,
  593. .pvr_value = 0x70000100,
  594. .cpu_name = "750FX",
  595. .cpu_features = CPU_FTRS_750FX1,
  596. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  597. .icache_bsize = 32,
  598. .dcache_bsize = 32,
  599. .num_pmcs = 4,
  600. .cpu_setup = __setup_cpu_750,
  601. .platform = "ppc750",
  602. },
  603. { /* 750FX rev 2.0 must disable HID0[DPM] */
  604. .pvr_mask = 0xffffffff,
  605. .pvr_value = 0x70000200,
  606. .cpu_name = "750FX",
  607. .cpu_features = CPU_FTRS_750FX2,
  608. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  609. .icache_bsize = 32,
  610. .dcache_bsize = 32,
  611. .num_pmcs = 4,
  612. .cpu_setup = __setup_cpu_750,
  613. .platform = "ppc750",
  614. },
  615. { /* 750FX (All revs except 2.0) */
  616. .pvr_mask = 0xffff0000,
  617. .pvr_value = 0x70000000,
  618. .cpu_name = "750FX",
  619. .cpu_features = CPU_FTRS_750FX,
  620. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  621. .icache_bsize = 32,
  622. .dcache_bsize = 32,
  623. .num_pmcs = 4,
  624. .cpu_setup = __setup_cpu_750fx,
  625. .platform = "ppc750",
  626. },
  627. { /* 750GX */
  628. .pvr_mask = 0xffff0000,
  629. .pvr_value = 0x70020000,
  630. .cpu_name = "750GX",
  631. .cpu_features = CPU_FTRS_750GX,
  632. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  633. .icache_bsize = 32,
  634. .dcache_bsize = 32,
  635. .num_pmcs = 4,
  636. .cpu_setup = __setup_cpu_750fx,
  637. .platform = "ppc750",
  638. },
  639. { /* 740/750 (L2CR bit need fixup for 740) */
  640. .pvr_mask = 0xffff0000,
  641. .pvr_value = 0x00080000,
  642. .cpu_name = "740/750",
  643. .cpu_features = CPU_FTRS_740,
  644. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  645. .icache_bsize = 32,
  646. .dcache_bsize = 32,
  647. .num_pmcs = 4,
  648. .cpu_setup = __setup_cpu_750,
  649. .platform = "ppc750",
  650. },
  651. { /* 7400 rev 1.1 ? (no TAU) */
  652. .pvr_mask = 0xffffffff,
  653. .pvr_value = 0x000c1101,
  654. .cpu_name = "7400 (1.1)",
  655. .cpu_features = CPU_FTRS_7400_NOTAU,
  656. .cpu_user_features = COMMON_USER |
  657. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  658. .icache_bsize = 32,
  659. .dcache_bsize = 32,
  660. .num_pmcs = 4,
  661. .cpu_setup = __setup_cpu_7400,
  662. .platform = "ppc7400",
  663. },
  664. { /* 7400 */
  665. .pvr_mask = 0xffff0000,
  666. .pvr_value = 0x000c0000,
  667. .cpu_name = "7400",
  668. .cpu_features = CPU_FTRS_7400,
  669. .cpu_user_features = COMMON_USER |
  670. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  671. .icache_bsize = 32,
  672. .dcache_bsize = 32,
  673. .num_pmcs = 4,
  674. .cpu_setup = __setup_cpu_7400,
  675. .platform = "ppc7400",
  676. },
  677. { /* 7410 */
  678. .pvr_mask = 0xffff0000,
  679. .pvr_value = 0x800c0000,
  680. .cpu_name = "7410",
  681. .cpu_features = CPU_FTRS_7400,
  682. .cpu_user_features = COMMON_USER |
  683. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  684. .icache_bsize = 32,
  685. .dcache_bsize = 32,
  686. .num_pmcs = 4,
  687. .cpu_setup = __setup_cpu_7410,
  688. .platform = "ppc7400",
  689. },
  690. { /* 7450 2.0 - no doze/nap */
  691. .pvr_mask = 0xffffffff,
  692. .pvr_value = 0x80000200,
  693. .cpu_name = "7450",
  694. .cpu_features = CPU_FTRS_7450_20,
  695. .cpu_user_features = COMMON_USER |
  696. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  697. .icache_bsize = 32,
  698. .dcache_bsize = 32,
  699. .num_pmcs = 6,
  700. .cpu_setup = __setup_cpu_745x,
  701. .oprofile_cpu_type = "ppc/7450",
  702. .oprofile_type = PPC_OPROFILE_G4,
  703. .platform = "ppc7450",
  704. },
  705. { /* 7450 2.1 */
  706. .pvr_mask = 0xffffffff,
  707. .pvr_value = 0x80000201,
  708. .cpu_name = "7450",
  709. .cpu_features = CPU_FTRS_7450_21,
  710. .cpu_user_features = COMMON_USER |
  711. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  712. .icache_bsize = 32,
  713. .dcache_bsize = 32,
  714. .num_pmcs = 6,
  715. .cpu_setup = __setup_cpu_745x,
  716. .oprofile_cpu_type = "ppc/7450",
  717. .oprofile_type = PPC_OPROFILE_G4,
  718. .platform = "ppc7450",
  719. },
  720. { /* 7450 2.3 and newer */
  721. .pvr_mask = 0xffff0000,
  722. .pvr_value = 0x80000000,
  723. .cpu_name = "7450",
  724. .cpu_features = CPU_FTRS_7450_23,
  725. .cpu_user_features = COMMON_USER |
  726. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  727. .icache_bsize = 32,
  728. .dcache_bsize = 32,
  729. .num_pmcs = 6,
  730. .cpu_setup = __setup_cpu_745x,
  731. .oprofile_cpu_type = "ppc/7450",
  732. .oprofile_type = PPC_OPROFILE_G4,
  733. .platform = "ppc7450",
  734. },
  735. { /* 7455 rev 1.x */
  736. .pvr_mask = 0xffffff00,
  737. .pvr_value = 0x80010100,
  738. .cpu_name = "7455",
  739. .cpu_features = CPU_FTRS_7455_1,
  740. .cpu_user_features = COMMON_USER |
  741. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  742. .icache_bsize = 32,
  743. .dcache_bsize = 32,
  744. .num_pmcs = 6,
  745. .cpu_setup = __setup_cpu_745x,
  746. .oprofile_cpu_type = "ppc/7450",
  747. .oprofile_type = PPC_OPROFILE_G4,
  748. .platform = "ppc7450",
  749. },
  750. { /* 7455 rev 2.0 */
  751. .pvr_mask = 0xffffffff,
  752. .pvr_value = 0x80010200,
  753. .cpu_name = "7455",
  754. .cpu_features = CPU_FTRS_7455_20,
  755. .cpu_user_features = COMMON_USER |
  756. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  757. .icache_bsize = 32,
  758. .dcache_bsize = 32,
  759. .num_pmcs = 6,
  760. .cpu_setup = __setup_cpu_745x,
  761. .oprofile_cpu_type = "ppc/7450",
  762. .oprofile_type = PPC_OPROFILE_G4,
  763. .platform = "ppc7450",
  764. },
  765. { /* 7455 others */
  766. .pvr_mask = 0xffff0000,
  767. .pvr_value = 0x80010000,
  768. .cpu_name = "7455",
  769. .cpu_features = CPU_FTRS_7455,
  770. .cpu_user_features = COMMON_USER |
  771. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  772. .icache_bsize = 32,
  773. .dcache_bsize = 32,
  774. .num_pmcs = 6,
  775. .cpu_setup = __setup_cpu_745x,
  776. .oprofile_cpu_type = "ppc/7450",
  777. .oprofile_type = PPC_OPROFILE_G4,
  778. .platform = "ppc7450",
  779. },
  780. { /* 7447/7457 Rev 1.0 */
  781. .pvr_mask = 0xffffffff,
  782. .pvr_value = 0x80020100,
  783. .cpu_name = "7447/7457",
  784. .cpu_features = CPU_FTRS_7447_10,
  785. .cpu_user_features = COMMON_USER |
  786. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  787. .icache_bsize = 32,
  788. .dcache_bsize = 32,
  789. .num_pmcs = 6,
  790. .cpu_setup = __setup_cpu_745x,
  791. .oprofile_cpu_type = "ppc/7450",
  792. .oprofile_type = PPC_OPROFILE_G4,
  793. .platform = "ppc7450",
  794. },
  795. { /* 7447/7457 Rev 1.1 */
  796. .pvr_mask = 0xffffffff,
  797. .pvr_value = 0x80020101,
  798. .cpu_name = "7447/7457",
  799. .cpu_features = CPU_FTRS_7447_10,
  800. .cpu_user_features = COMMON_USER |
  801. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  802. .icache_bsize = 32,
  803. .dcache_bsize = 32,
  804. .num_pmcs = 6,
  805. .cpu_setup = __setup_cpu_745x,
  806. .oprofile_cpu_type = "ppc/7450",
  807. .oprofile_type = PPC_OPROFILE_G4,
  808. .platform = "ppc7450",
  809. },
  810. { /* 7447/7457 Rev 1.2 and later */
  811. .pvr_mask = 0xffff0000,
  812. .pvr_value = 0x80020000,
  813. .cpu_name = "7447/7457",
  814. .cpu_features = CPU_FTRS_7447,
  815. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  816. .icache_bsize = 32,
  817. .dcache_bsize = 32,
  818. .num_pmcs = 6,
  819. .cpu_setup = __setup_cpu_745x,
  820. .oprofile_cpu_type = "ppc/7450",
  821. .oprofile_type = PPC_OPROFILE_G4,
  822. .platform = "ppc7450",
  823. },
  824. { /* 7447A */
  825. .pvr_mask = 0xffff0000,
  826. .pvr_value = 0x80030000,
  827. .cpu_name = "7447A",
  828. .cpu_features = CPU_FTRS_7447A,
  829. .cpu_user_features = COMMON_USER |
  830. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  831. .icache_bsize = 32,
  832. .dcache_bsize = 32,
  833. .num_pmcs = 6,
  834. .cpu_setup = __setup_cpu_745x,
  835. .oprofile_cpu_type = "ppc/7450",
  836. .oprofile_type = PPC_OPROFILE_G4,
  837. .platform = "ppc7450",
  838. },
  839. { /* 7448 */
  840. .pvr_mask = 0xffff0000,
  841. .pvr_value = 0x80040000,
  842. .cpu_name = "7448",
  843. .cpu_features = CPU_FTRS_7448,
  844. .cpu_user_features = COMMON_USER |
  845. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  846. .icache_bsize = 32,
  847. .dcache_bsize = 32,
  848. .num_pmcs = 6,
  849. .cpu_setup = __setup_cpu_745x,
  850. .oprofile_cpu_type = "ppc/7450",
  851. .oprofile_type = PPC_OPROFILE_G4,
  852. .platform = "ppc7450",
  853. },
  854. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  855. .pvr_mask = 0x7fff0000,
  856. .pvr_value = 0x00810000,
  857. .cpu_name = "82xx",
  858. .cpu_features = CPU_FTRS_82XX,
  859. .cpu_user_features = COMMON_USER,
  860. .icache_bsize = 32,
  861. .dcache_bsize = 32,
  862. .cpu_setup = __setup_cpu_603,
  863. .platform = "ppc603",
  864. },
  865. { /* All G2_LE (603e core, plus some) have the same pvr */
  866. .pvr_mask = 0x7fff0000,
  867. .pvr_value = 0x00820000,
  868. .cpu_name = "G2_LE",
  869. .cpu_features = CPU_FTRS_G2_LE,
  870. .cpu_user_features = COMMON_USER,
  871. .icache_bsize = 32,
  872. .dcache_bsize = 32,
  873. .cpu_setup = __setup_cpu_603,
  874. .platform = "ppc603",
  875. },
  876. { /* e300c1 (a 603e core, plus some) on 83xx */
  877. .pvr_mask = 0x7fff0000,
  878. .pvr_value = 0x00830000,
  879. .cpu_name = "e300c1",
  880. .cpu_features = CPU_FTRS_E300,
  881. .cpu_user_features = COMMON_USER,
  882. .icache_bsize = 32,
  883. .dcache_bsize = 32,
  884. .cpu_setup = __setup_cpu_603,
  885. .platform = "ppc603",
  886. },
  887. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  888. .pvr_mask = 0x7fff0000,
  889. .pvr_value = 0x00840000,
  890. .cpu_name = "e300c2",
  891. .cpu_features = CPU_FTRS_E300C2,
  892. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  893. .icache_bsize = 32,
  894. .dcache_bsize = 32,
  895. .cpu_setup = __setup_cpu_603,
  896. .platform = "ppc603",
  897. },
  898. { /* e300c3 on 83xx */
  899. .pvr_mask = 0x7fff0000,
  900. .pvr_value = 0x00850000,
  901. .cpu_name = "e300c3",
  902. .cpu_features = CPU_FTRS_E300,
  903. .cpu_user_features = COMMON_USER,
  904. .icache_bsize = 32,
  905. .dcache_bsize = 32,
  906. .cpu_setup = __setup_cpu_603,
  907. .platform = "ppc603",
  908. },
  909. { /* default match, we assume split I/D cache & TB (non-601)... */
  910. .pvr_mask = 0x00000000,
  911. .pvr_value = 0x00000000,
  912. .cpu_name = "(generic PPC)",
  913. .cpu_features = CPU_FTRS_CLASSIC32,
  914. .cpu_user_features = COMMON_USER,
  915. .icache_bsize = 32,
  916. .dcache_bsize = 32,
  917. .platform = "ppc603",
  918. },
  919. #endif /* CLASSIC_PPC */
  920. #ifdef CONFIG_8xx
  921. { /* 8xx */
  922. .pvr_mask = 0xffff0000,
  923. .pvr_value = 0x00500000,
  924. .cpu_name = "8xx",
  925. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  926. * if the 8xx code is there.... */
  927. .cpu_features = CPU_FTRS_8XX,
  928. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  929. .icache_bsize = 16,
  930. .dcache_bsize = 16,
  931. .platform = "ppc823",
  932. },
  933. #endif /* CONFIG_8xx */
  934. #ifdef CONFIG_40x
  935. { /* 403GC */
  936. .pvr_mask = 0xffffff00,
  937. .pvr_value = 0x00200200,
  938. .cpu_name = "403GC",
  939. .cpu_features = CPU_FTRS_40X,
  940. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  941. .icache_bsize = 16,
  942. .dcache_bsize = 16,
  943. .platform = "ppc403",
  944. },
  945. { /* 403GCX */
  946. .pvr_mask = 0xffffff00,
  947. .pvr_value = 0x00201400,
  948. .cpu_name = "403GCX",
  949. .cpu_features = CPU_FTRS_40X,
  950. .cpu_user_features = PPC_FEATURE_32 |
  951. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  952. .icache_bsize = 16,
  953. .dcache_bsize = 16,
  954. .platform = "ppc403",
  955. },
  956. { /* 403G ?? */
  957. .pvr_mask = 0xffff0000,
  958. .pvr_value = 0x00200000,
  959. .cpu_name = "403G ??",
  960. .cpu_features = CPU_FTRS_40X,
  961. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  962. .icache_bsize = 16,
  963. .dcache_bsize = 16,
  964. .platform = "ppc403",
  965. },
  966. { /* 405GP */
  967. .pvr_mask = 0xffff0000,
  968. .pvr_value = 0x40110000,
  969. .cpu_name = "405GP",
  970. .cpu_features = CPU_FTRS_40X,
  971. .cpu_user_features = PPC_FEATURE_32 |
  972. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  973. .icache_bsize = 32,
  974. .dcache_bsize = 32,
  975. .platform = "ppc405",
  976. },
  977. { /* STB 03xxx */
  978. .pvr_mask = 0xffff0000,
  979. .pvr_value = 0x40130000,
  980. .cpu_name = "STB03xxx",
  981. .cpu_features = CPU_FTRS_40X,
  982. .cpu_user_features = PPC_FEATURE_32 |
  983. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  984. .icache_bsize = 32,
  985. .dcache_bsize = 32,
  986. .platform = "ppc405",
  987. },
  988. { /* STB 04xxx */
  989. .pvr_mask = 0xffff0000,
  990. .pvr_value = 0x41810000,
  991. .cpu_name = "STB04xxx",
  992. .cpu_features = CPU_FTRS_40X,
  993. .cpu_user_features = PPC_FEATURE_32 |
  994. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  995. .icache_bsize = 32,
  996. .dcache_bsize = 32,
  997. .platform = "ppc405",
  998. },
  999. { /* NP405L */
  1000. .pvr_mask = 0xffff0000,
  1001. .pvr_value = 0x41610000,
  1002. .cpu_name = "NP405L",
  1003. .cpu_features = CPU_FTRS_40X,
  1004. .cpu_user_features = PPC_FEATURE_32 |
  1005. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1006. .icache_bsize = 32,
  1007. .dcache_bsize = 32,
  1008. .platform = "ppc405",
  1009. },
  1010. { /* NP4GS3 */
  1011. .pvr_mask = 0xffff0000,
  1012. .pvr_value = 0x40B10000,
  1013. .cpu_name = "NP4GS3",
  1014. .cpu_features = CPU_FTRS_40X,
  1015. .cpu_user_features = PPC_FEATURE_32 |
  1016. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1017. .icache_bsize = 32,
  1018. .dcache_bsize = 32,
  1019. .platform = "ppc405",
  1020. },
  1021. { /* NP405H */
  1022. .pvr_mask = 0xffff0000,
  1023. .pvr_value = 0x41410000,
  1024. .cpu_name = "NP405H",
  1025. .cpu_features = CPU_FTRS_40X,
  1026. .cpu_user_features = PPC_FEATURE_32 |
  1027. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1028. .icache_bsize = 32,
  1029. .dcache_bsize = 32,
  1030. .platform = "ppc405",
  1031. },
  1032. { /* 405GPr */
  1033. .pvr_mask = 0xffff0000,
  1034. .pvr_value = 0x50910000,
  1035. .cpu_name = "405GPr",
  1036. .cpu_features = CPU_FTRS_40X,
  1037. .cpu_user_features = PPC_FEATURE_32 |
  1038. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1039. .icache_bsize = 32,
  1040. .dcache_bsize = 32,
  1041. .platform = "ppc405",
  1042. },
  1043. { /* STBx25xx */
  1044. .pvr_mask = 0xffff0000,
  1045. .pvr_value = 0x51510000,
  1046. .cpu_name = "STBx25xx",
  1047. .cpu_features = CPU_FTRS_40X,
  1048. .cpu_user_features = PPC_FEATURE_32 |
  1049. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1050. .icache_bsize = 32,
  1051. .dcache_bsize = 32,
  1052. .platform = "ppc405",
  1053. },
  1054. { /* 405LP */
  1055. .pvr_mask = 0xffff0000,
  1056. .pvr_value = 0x41F10000,
  1057. .cpu_name = "405LP",
  1058. .cpu_features = CPU_FTRS_40X,
  1059. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1060. .icache_bsize = 32,
  1061. .dcache_bsize = 32,
  1062. .platform = "ppc405",
  1063. },
  1064. { /* Xilinx Virtex-II Pro */
  1065. .pvr_mask = 0xfffff000,
  1066. .pvr_value = 0x20010000,
  1067. .cpu_name = "Virtex-II Pro",
  1068. .cpu_features = CPU_FTRS_40X,
  1069. .cpu_user_features = PPC_FEATURE_32 |
  1070. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1071. .icache_bsize = 32,
  1072. .dcache_bsize = 32,
  1073. .platform = "ppc405",
  1074. },
  1075. { /* Xilinx Virtex-4 FX */
  1076. .pvr_mask = 0xfffff000,
  1077. .pvr_value = 0x20011000,
  1078. .cpu_name = "Virtex-4 FX",
  1079. .cpu_features = CPU_FTRS_40X,
  1080. .cpu_user_features = PPC_FEATURE_32 |
  1081. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1082. .icache_bsize = 32,
  1083. .dcache_bsize = 32,
  1084. .platform = "ppc405",
  1085. },
  1086. { /* 405EP */
  1087. .pvr_mask = 0xffff0000,
  1088. .pvr_value = 0x51210000,
  1089. .cpu_name = "405EP",
  1090. .cpu_features = CPU_FTRS_40X,
  1091. .cpu_user_features = PPC_FEATURE_32 |
  1092. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1093. .icache_bsize = 32,
  1094. .dcache_bsize = 32,
  1095. .platform = "ppc405",
  1096. },
  1097. #endif /* CONFIG_40x */
  1098. #ifdef CONFIG_44x
  1099. {
  1100. .pvr_mask = 0xf0000fff,
  1101. .pvr_value = 0x40000850,
  1102. .cpu_name = "440EP Rev. A",
  1103. .cpu_features = CPU_FTRS_44X,
  1104. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1105. .icache_bsize = 32,
  1106. .dcache_bsize = 32,
  1107. .platform = "ppc440",
  1108. },
  1109. {
  1110. .pvr_mask = 0xf0000fff,
  1111. .pvr_value = 0x400008d3,
  1112. .cpu_name = "440EP Rev. B",
  1113. .cpu_features = CPU_FTRS_44X,
  1114. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1115. .icache_bsize = 32,
  1116. .dcache_bsize = 32,
  1117. .platform = "ppc440",
  1118. },
  1119. { /* 440EPX */
  1120. .pvr_mask = 0xf0000ffb,
  1121. .pvr_value = 0x200008D0,
  1122. .cpu_name = "440EPX",
  1123. .cpu_features = CPU_FTRS_44X,
  1124. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1125. .icache_bsize = 32,
  1126. .dcache_bsize = 32,
  1127. },
  1128. { /* 440GRX */
  1129. .pvr_mask = 0xf0000ffb,
  1130. .pvr_value = 0x200008D8,
  1131. .cpu_name = "440GRX",
  1132. .cpu_features = CPU_FTRS_44X,
  1133. .cpu_user_features = COMMON_USER_BOOKE,
  1134. .icache_bsize = 32,
  1135. .dcache_bsize = 32,
  1136. },
  1137. { /* 440GP Rev. B */
  1138. .pvr_mask = 0xf0000fff,
  1139. .pvr_value = 0x40000440,
  1140. .cpu_name = "440GP Rev. B",
  1141. .cpu_features = CPU_FTRS_44X,
  1142. .cpu_user_features = COMMON_USER_BOOKE,
  1143. .icache_bsize = 32,
  1144. .dcache_bsize = 32,
  1145. .platform = "ppc440gp",
  1146. },
  1147. { /* 440GP Rev. C */
  1148. .pvr_mask = 0xf0000fff,
  1149. .pvr_value = 0x40000481,
  1150. .cpu_name = "440GP Rev. C",
  1151. .cpu_features = CPU_FTRS_44X,
  1152. .cpu_user_features = COMMON_USER_BOOKE,
  1153. .icache_bsize = 32,
  1154. .dcache_bsize = 32,
  1155. .platform = "ppc440gp",
  1156. },
  1157. { /* 440GX Rev. A */
  1158. .pvr_mask = 0xf0000fff,
  1159. .pvr_value = 0x50000850,
  1160. .cpu_name = "440GX Rev. A",
  1161. .cpu_features = CPU_FTRS_44X,
  1162. .cpu_user_features = COMMON_USER_BOOKE,
  1163. .icache_bsize = 32,
  1164. .dcache_bsize = 32,
  1165. .platform = "ppc440",
  1166. },
  1167. { /* 440GX Rev. B */
  1168. .pvr_mask = 0xf0000fff,
  1169. .pvr_value = 0x50000851,
  1170. .cpu_name = "440GX Rev. B",
  1171. .cpu_features = CPU_FTRS_44X,
  1172. .cpu_user_features = COMMON_USER_BOOKE,
  1173. .icache_bsize = 32,
  1174. .dcache_bsize = 32,
  1175. .platform = "ppc440",
  1176. },
  1177. { /* 440GX Rev. C */
  1178. .pvr_mask = 0xf0000fff,
  1179. .pvr_value = 0x50000892,
  1180. .cpu_name = "440GX Rev. C",
  1181. .cpu_features = CPU_FTRS_44X,
  1182. .cpu_user_features = COMMON_USER_BOOKE,
  1183. .icache_bsize = 32,
  1184. .dcache_bsize = 32,
  1185. .platform = "ppc440",
  1186. },
  1187. { /* 440GX Rev. F */
  1188. .pvr_mask = 0xf0000fff,
  1189. .pvr_value = 0x50000894,
  1190. .cpu_name = "440GX Rev. F",
  1191. .cpu_features = CPU_FTRS_44X,
  1192. .cpu_user_features = COMMON_USER_BOOKE,
  1193. .icache_bsize = 32,
  1194. .dcache_bsize = 32,
  1195. .platform = "ppc440",
  1196. },
  1197. { /* 440SP Rev. A */
  1198. .pvr_mask = 0xfff00fff,
  1199. .pvr_value = 0x53200891,
  1200. .cpu_name = "440SP Rev. A",
  1201. .cpu_features = CPU_FTRS_44X,
  1202. .cpu_user_features = COMMON_USER_BOOKE,
  1203. .icache_bsize = 32,
  1204. .dcache_bsize = 32,
  1205. .platform = "ppc440",
  1206. },
  1207. { /* 440SPe Rev. A */
  1208. .pvr_mask = 0xfff00fff,
  1209. .pvr_value = 0x53400890,
  1210. .cpu_name = "440SPe Rev. A",
  1211. .cpu_features = CPU_FTRS_44X,
  1212. .cpu_user_features = COMMON_USER_BOOKE,
  1213. .icache_bsize = 32,
  1214. .dcache_bsize = 32,
  1215. .platform = "ppc440",
  1216. },
  1217. { /* 440SPe Rev. B */
  1218. .pvr_mask = 0xfff00fff,
  1219. .pvr_value = 0x53400891,
  1220. .cpu_name = "440SPe Rev. B",
  1221. .cpu_features = CPU_FTRS_44X,
  1222. .cpu_user_features = COMMON_USER_BOOKE,
  1223. .icache_bsize = 32,
  1224. .dcache_bsize = 32,
  1225. .platform = "ppc440",
  1226. },
  1227. #endif /* CONFIG_44x */
  1228. #ifdef CONFIG_FSL_BOOKE
  1229. { /* e200z5 */
  1230. .pvr_mask = 0xfff00000,
  1231. .pvr_value = 0x81000000,
  1232. .cpu_name = "e200z5",
  1233. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1234. .cpu_features = CPU_FTRS_E200,
  1235. .cpu_user_features = COMMON_USER_BOOKE |
  1236. PPC_FEATURE_HAS_EFP_SINGLE |
  1237. PPC_FEATURE_UNIFIED_CACHE,
  1238. .dcache_bsize = 32,
  1239. .platform = "ppc5554",
  1240. },
  1241. { /* e200z6 */
  1242. .pvr_mask = 0xfff00000,
  1243. .pvr_value = 0x81100000,
  1244. .cpu_name = "e200z6",
  1245. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1246. .cpu_features = CPU_FTRS_E200,
  1247. .cpu_user_features = COMMON_USER_BOOKE |
  1248. PPC_FEATURE_HAS_SPE_COMP |
  1249. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1250. PPC_FEATURE_UNIFIED_CACHE,
  1251. .dcache_bsize = 32,
  1252. .platform = "ppc5554",
  1253. },
  1254. { /* e500 */
  1255. .pvr_mask = 0xffff0000,
  1256. .pvr_value = 0x80200000,
  1257. .cpu_name = "e500",
  1258. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1259. .cpu_features = CPU_FTRS_E500,
  1260. .cpu_user_features = COMMON_USER_BOOKE |
  1261. PPC_FEATURE_HAS_SPE_COMP |
  1262. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1263. .icache_bsize = 32,
  1264. .dcache_bsize = 32,
  1265. .num_pmcs = 4,
  1266. .oprofile_cpu_type = "ppc/e500",
  1267. .oprofile_type = PPC_OPROFILE_BOOKE,
  1268. .platform = "ppc8540",
  1269. },
  1270. { /* e500v2 */
  1271. .pvr_mask = 0xffff0000,
  1272. .pvr_value = 0x80210000,
  1273. .cpu_name = "e500v2",
  1274. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1275. .cpu_features = CPU_FTRS_E500_2,
  1276. .cpu_user_features = COMMON_USER_BOOKE |
  1277. PPC_FEATURE_HAS_SPE_COMP |
  1278. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1279. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  1280. .icache_bsize = 32,
  1281. .dcache_bsize = 32,
  1282. .num_pmcs = 4,
  1283. .oprofile_cpu_type = "ppc/e500",
  1284. .oprofile_type = PPC_OPROFILE_BOOKE,
  1285. .platform = "ppc8548",
  1286. },
  1287. #endif
  1288. #if !CLASSIC_PPC
  1289. { /* default match */
  1290. .pvr_mask = 0x00000000,
  1291. .pvr_value = 0x00000000,
  1292. .cpu_name = "(generic PPC)",
  1293. .cpu_features = CPU_FTRS_GENERIC_32,
  1294. .cpu_user_features = PPC_FEATURE_32,
  1295. .icache_bsize = 32,
  1296. .dcache_bsize = 32,
  1297. .platform = "powerpc",
  1298. }
  1299. #endif /* !CLASSIC_PPC */
  1300. #endif /* CONFIG_PPC32 */
  1301. };
  1302. struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr)
  1303. {
  1304. struct cpu_spec *s = cpu_specs;
  1305. struct cpu_spec **cur = &cur_cpu_spec;
  1306. int i;
  1307. s = PTRRELOC(s);
  1308. cur = PTRRELOC(cur);
  1309. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++)
  1310. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1311. *cur = cpu_specs + i;
  1312. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  1313. /* ppc64 and booke expect identify_cpu to also call
  1314. * setup_cpu for that processor. I will consolidate
  1315. * that at a later time, for now, just use #ifdef.
  1316. * we also don't need to PTRRELOC the function pointer
  1317. * on ppc64 and booke as we are running at 0 in real
  1318. * mode on ppc64 and reloc_offset is always 0 on booke.
  1319. */
  1320. if (s->cpu_setup) {
  1321. s->cpu_setup(offset, s);
  1322. }
  1323. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  1324. return s;
  1325. }
  1326. BUG();
  1327. return NULL;
  1328. }
  1329. void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
  1330. {
  1331. struct fixup_entry {
  1332. unsigned long mask;
  1333. unsigned long value;
  1334. long start_off;
  1335. long end_off;
  1336. } *fcur, *fend;
  1337. fcur = fixup_start;
  1338. fend = fixup_end;
  1339. for (; fcur < fend; fcur++) {
  1340. unsigned int *pstart, *pend, *p;
  1341. if ((value & fcur->mask) == fcur->value)
  1342. continue;
  1343. /* These PTRRELOCs will disappear once the new scheme for
  1344. * modules and vdso is implemented
  1345. */
  1346. pstart = ((unsigned int *)fcur) + (fcur->start_off / 4);
  1347. pend = ((unsigned int *)fcur) + (fcur->end_off / 4);
  1348. for (p = pstart; p < pend; p++) {
  1349. *p = 0x60000000u;
  1350. asm volatile ("dcbst 0, %0" : : "r" (p));
  1351. }
  1352. asm volatile ("sync" : : : "memory");
  1353. for (p = pstart; p < pend; p++)
  1354. asm volatile ("icbi 0,%0" : : "r" (p));
  1355. asm volatile ("sync; isync" : : : "memory");
  1356. }
  1357. }