pt1.c 22 KB

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  1. /*
  2. * driver for Earthsoft PT1
  3. *
  4. * Copyright (C) 2009 HIRANO Takahito <hiranotaka@zng.info>
  5. *
  6. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  7. * by Tomoaki Ishikawa <tomy@users.sourceforge.jp>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/pci.h>
  26. #include <linux/kthread.h>
  27. #include <linux/freezer.h>
  28. #include "dvbdev.h"
  29. #include "dvb_demux.h"
  30. #include "dmxdev.h"
  31. #include "dvb_net.h"
  32. #include "dvb_frontend.h"
  33. #include "va1j5jf8007t.h"
  34. #include "va1j5jf8007s.h"
  35. #define DRIVER_NAME "earth-pt1"
  36. #define PT1_PAGE_SHIFT 12
  37. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  38. #define PT1_NR_UPACKETS 1024
  39. #define PT1_NR_BUFS 511
  40. struct pt1_buffer_page {
  41. __le32 upackets[PT1_NR_UPACKETS];
  42. };
  43. struct pt1_table_page {
  44. __le32 next_pfn;
  45. __le32 buf_pfns[PT1_NR_BUFS];
  46. };
  47. struct pt1_buffer {
  48. struct pt1_buffer_page *page;
  49. dma_addr_t addr;
  50. };
  51. struct pt1_table {
  52. struct pt1_table_page *page;
  53. dma_addr_t addr;
  54. struct pt1_buffer bufs[PT1_NR_BUFS];
  55. };
  56. #define PT1_NR_ADAPS 4
  57. struct pt1_adapter;
  58. struct pt1 {
  59. struct pci_dev *pdev;
  60. void __iomem *regs;
  61. struct i2c_adapter i2c_adap;
  62. int i2c_running;
  63. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  64. struct pt1_table *tables;
  65. struct task_struct *kthread;
  66. };
  67. struct pt1_adapter {
  68. struct pt1 *pt1;
  69. int index;
  70. u8 *buf;
  71. int upacket_count;
  72. int packet_count;
  73. struct dvb_adapter adap;
  74. struct dvb_demux demux;
  75. int users;
  76. struct dmxdev dmxdev;
  77. struct dvb_net net;
  78. struct dvb_frontend *fe;
  79. int (*orig_set_voltage)(struct dvb_frontend *fe,
  80. fe_sec_voltage_t voltage);
  81. };
  82. #define pt1_printk(level, pt1, format, arg...) \
  83. dev_printk(level, &(pt1)->pdev->dev, format, ##arg)
  84. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  85. {
  86. writel(data, pt1->regs + reg * 4);
  87. }
  88. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  89. {
  90. return readl(pt1->regs + reg * 4);
  91. }
  92. static int pt1_nr_tables = 64;
  93. module_param_named(nr_tables, pt1_nr_tables, int, 0);
  94. static void pt1_increment_table_count(struct pt1 *pt1)
  95. {
  96. pt1_write_reg(pt1, 0, 0x00000020);
  97. }
  98. static void pt1_init_table_count(struct pt1 *pt1)
  99. {
  100. pt1_write_reg(pt1, 0, 0x00000010);
  101. }
  102. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  103. {
  104. pt1_write_reg(pt1, 5, first_pfn);
  105. pt1_write_reg(pt1, 0, 0x0c000040);
  106. }
  107. static void pt1_unregister_tables(struct pt1 *pt1)
  108. {
  109. pt1_write_reg(pt1, 0, 0x08080000);
  110. }
  111. static int pt1_sync(struct pt1 *pt1)
  112. {
  113. int i;
  114. for (i = 0; i < 57; i++) {
  115. if (pt1_read_reg(pt1, 0) & 0x20000000)
  116. return 0;
  117. pt1_write_reg(pt1, 0, 0x00000008);
  118. }
  119. pt1_printk(KERN_ERR, pt1, "could not sync\n");
  120. return -EIO;
  121. }
  122. static u64 pt1_identify(struct pt1 *pt1)
  123. {
  124. int i;
  125. u64 id;
  126. id = 0;
  127. for (i = 0; i < 57; i++) {
  128. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  129. pt1_write_reg(pt1, 0, 0x00000008);
  130. }
  131. return id;
  132. }
  133. static int pt1_unlock(struct pt1 *pt1)
  134. {
  135. int i;
  136. pt1_write_reg(pt1, 0, 0x00000008);
  137. for (i = 0; i < 3; i++) {
  138. if (pt1_read_reg(pt1, 0) & 0x80000000)
  139. return 0;
  140. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  141. }
  142. pt1_printk(KERN_ERR, pt1, "could not unlock\n");
  143. return -EIO;
  144. }
  145. static int pt1_reset_pci(struct pt1 *pt1)
  146. {
  147. int i;
  148. pt1_write_reg(pt1, 0, 0x01010000);
  149. pt1_write_reg(pt1, 0, 0x01000000);
  150. for (i = 0; i < 10; i++) {
  151. if (pt1_read_reg(pt1, 0) & 0x00000001)
  152. return 0;
  153. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  154. }
  155. pt1_printk(KERN_ERR, pt1, "could not reset PCI\n");
  156. return -EIO;
  157. }
  158. static int pt1_reset_ram(struct pt1 *pt1)
  159. {
  160. int i;
  161. pt1_write_reg(pt1, 0, 0x02020000);
  162. pt1_write_reg(pt1, 0, 0x02000000);
  163. for (i = 0; i < 10; i++) {
  164. if (pt1_read_reg(pt1, 0) & 0x00000002)
  165. return 0;
  166. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  167. }
  168. pt1_printk(KERN_ERR, pt1, "could not reset RAM\n");
  169. return -EIO;
  170. }
  171. static int pt1_do_enable_ram(struct pt1 *pt1)
  172. {
  173. int i, j;
  174. u32 status;
  175. status = pt1_read_reg(pt1, 0) & 0x00000004;
  176. pt1_write_reg(pt1, 0, 0x00000002);
  177. for (i = 0; i < 10; i++) {
  178. for (j = 0; j < 1024; j++) {
  179. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  180. return 0;
  181. }
  182. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  183. }
  184. pt1_printk(KERN_ERR, pt1, "could not enable RAM\n");
  185. return -EIO;
  186. }
  187. static int pt1_enable_ram(struct pt1 *pt1)
  188. {
  189. int i, ret;
  190. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  191. for (i = 0; i < 10; i++) {
  192. ret = pt1_do_enable_ram(pt1);
  193. if (ret < 0)
  194. return ret;
  195. }
  196. return 0;
  197. }
  198. static void pt1_disable_ram(struct pt1 *pt1)
  199. {
  200. pt1_write_reg(pt1, 0, 0x0b0b0000);
  201. }
  202. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  203. {
  204. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  205. }
  206. static void pt1_init_streams(struct pt1 *pt1)
  207. {
  208. int i;
  209. for (i = 0; i < PT1_NR_ADAPS; i++)
  210. pt1_set_stream(pt1, i, 0);
  211. }
  212. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  213. {
  214. u32 upacket;
  215. int i;
  216. int index;
  217. struct pt1_adapter *adap;
  218. int offset;
  219. u8 *buf;
  220. if (!page->upackets[PT1_NR_UPACKETS - 1])
  221. return 0;
  222. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  223. upacket = le32_to_cpu(page->upackets[i]);
  224. index = (upacket >> 29) - 1;
  225. if (index < 0 || index >= PT1_NR_ADAPS)
  226. continue;
  227. adap = pt1->adaps[index];
  228. if (upacket >> 25 & 1)
  229. adap->upacket_count = 0;
  230. else if (!adap->upacket_count)
  231. continue;
  232. buf = adap->buf;
  233. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  234. buf[offset] = upacket >> 16;
  235. buf[offset + 1] = upacket >> 8;
  236. if (adap->upacket_count != 62)
  237. buf[offset + 2] = upacket;
  238. if (++adap->upacket_count >= 63) {
  239. adap->upacket_count = 0;
  240. if (++adap->packet_count >= 21) {
  241. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  242. adap->packet_count = 0;
  243. }
  244. }
  245. }
  246. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  247. return 1;
  248. }
  249. static int pt1_thread(void *data)
  250. {
  251. struct pt1 *pt1;
  252. int table_index;
  253. int buf_index;
  254. struct pt1_buffer_page *page;
  255. pt1 = data;
  256. set_freezable();
  257. table_index = 0;
  258. buf_index = 0;
  259. while (!kthread_should_stop()) {
  260. try_to_freeze();
  261. page = pt1->tables[table_index].bufs[buf_index].page;
  262. if (!pt1_filter(pt1, page)) {
  263. schedule_timeout_interruptible((HZ + 999) / 1000);
  264. continue;
  265. }
  266. if (++buf_index >= PT1_NR_BUFS) {
  267. pt1_increment_table_count(pt1);
  268. buf_index = 0;
  269. if (++table_index >= pt1_nr_tables)
  270. table_index = 0;
  271. }
  272. }
  273. return 0;
  274. }
  275. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  276. {
  277. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  278. }
  279. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  280. {
  281. void *page;
  282. dma_addr_t addr;
  283. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  284. GFP_KERNEL);
  285. if (page == NULL)
  286. return NULL;
  287. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  288. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  289. *addrp = addr;
  290. *pfnp = addr >> PT1_PAGE_SHIFT;
  291. return page;
  292. }
  293. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  294. {
  295. pt1_free_page(pt1, buf->page, buf->addr);
  296. }
  297. static int
  298. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  299. {
  300. struct pt1_buffer_page *page;
  301. dma_addr_t addr;
  302. page = pt1_alloc_page(pt1, &addr, pfnp);
  303. if (page == NULL)
  304. return -ENOMEM;
  305. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  306. buf->page = page;
  307. buf->addr = addr;
  308. return 0;
  309. }
  310. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  311. {
  312. int i;
  313. for (i = 0; i < PT1_NR_BUFS; i++)
  314. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  315. pt1_free_page(pt1, table->page, table->addr);
  316. }
  317. static int
  318. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  319. {
  320. struct pt1_table_page *page;
  321. dma_addr_t addr;
  322. int i, ret;
  323. u32 buf_pfn;
  324. page = pt1_alloc_page(pt1, &addr, pfnp);
  325. if (page == NULL)
  326. return -ENOMEM;
  327. for (i = 0; i < PT1_NR_BUFS; i++) {
  328. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  329. if (ret < 0)
  330. goto err;
  331. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  332. }
  333. pt1_increment_table_count(pt1);
  334. table->page = page;
  335. table->addr = addr;
  336. return 0;
  337. err:
  338. while (i--)
  339. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  340. pt1_free_page(pt1, page, addr);
  341. return ret;
  342. }
  343. static void pt1_cleanup_tables(struct pt1 *pt1)
  344. {
  345. struct pt1_table *tables;
  346. int i;
  347. tables = pt1->tables;
  348. pt1_unregister_tables(pt1);
  349. for (i = 0; i < pt1_nr_tables; i++)
  350. pt1_cleanup_table(pt1, &tables[i]);
  351. vfree(tables);
  352. }
  353. static int pt1_init_tables(struct pt1 *pt1)
  354. {
  355. struct pt1_table *tables;
  356. int i, ret;
  357. u32 first_pfn, pfn;
  358. tables = vmalloc(sizeof(struct pt1_table) * pt1_nr_tables);
  359. if (tables == NULL)
  360. return -ENOMEM;
  361. pt1_init_table_count(pt1);
  362. i = 0;
  363. if (pt1_nr_tables) {
  364. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  365. if (ret)
  366. goto err;
  367. i++;
  368. }
  369. while (i < pt1_nr_tables) {
  370. ret = pt1_init_table(pt1, &tables[i], &pfn);
  371. if (ret)
  372. goto err;
  373. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  374. i++;
  375. }
  376. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  377. pt1_register_tables(pt1, first_pfn);
  378. pt1->tables = tables;
  379. return 0;
  380. err:
  381. while (i--)
  382. pt1_cleanup_table(pt1, &tables[i]);
  383. vfree(tables);
  384. return ret;
  385. }
  386. static int pt1_start_feed(struct dvb_demux_feed *feed)
  387. {
  388. struct pt1_adapter *adap;
  389. adap = container_of(feed->demux, struct pt1_adapter, demux);
  390. if (!adap->users++)
  391. pt1_set_stream(adap->pt1, adap->index, 1);
  392. return 0;
  393. }
  394. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  395. {
  396. struct pt1_adapter *adap;
  397. adap = container_of(feed->demux, struct pt1_adapter, demux);
  398. if (!--adap->users)
  399. pt1_set_stream(adap->pt1, adap->index, 0);
  400. return 0;
  401. }
  402. static void
  403. pt1_set_power(struct pt1 *pt1, int power, int lnb, int reset)
  404. {
  405. pt1_write_reg(pt1, 1, power | lnb << 1 | !reset << 3);
  406. }
  407. static int pt1_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  408. {
  409. struct pt1_adapter *adap;
  410. int lnb;
  411. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  412. switch (voltage) {
  413. case SEC_VOLTAGE_13: /* actually 11V */
  414. lnb = 2;
  415. break;
  416. case SEC_VOLTAGE_18: /* actually 15V */
  417. lnb = 3;
  418. break;
  419. case SEC_VOLTAGE_OFF:
  420. lnb = 0;
  421. break;
  422. default:
  423. return -EINVAL;
  424. }
  425. pt1_set_power(adap->pt1, 1, lnb, 0);
  426. if (adap->orig_set_voltage)
  427. return adap->orig_set_voltage(fe, voltage);
  428. else
  429. return 0;
  430. }
  431. static void pt1_free_adapter(struct pt1_adapter *adap)
  432. {
  433. dvb_unregister_frontend(adap->fe);
  434. dvb_net_release(&adap->net);
  435. adap->demux.dmx.close(&adap->demux.dmx);
  436. dvb_dmxdev_release(&adap->dmxdev);
  437. dvb_dmx_release(&adap->demux);
  438. dvb_unregister_adapter(&adap->adap);
  439. free_page((unsigned long)adap->buf);
  440. kfree(adap);
  441. }
  442. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  443. static struct pt1_adapter *
  444. pt1_alloc_adapter(struct pt1 *pt1, struct dvb_frontend *fe)
  445. {
  446. struct pt1_adapter *adap;
  447. void *buf;
  448. struct dvb_adapter *dvb_adap;
  449. struct dvb_demux *demux;
  450. struct dmxdev *dmxdev;
  451. int ret;
  452. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  453. if (!adap) {
  454. ret = -ENOMEM;
  455. goto err;
  456. }
  457. adap->pt1 = pt1;
  458. adap->orig_set_voltage = fe->ops.set_voltage;
  459. fe->ops.set_voltage = pt1_set_voltage;
  460. buf = (u8 *)__get_free_page(GFP_KERNEL);
  461. if (!buf) {
  462. ret = -ENOMEM;
  463. goto err_kfree;
  464. }
  465. adap->buf = buf;
  466. adap->upacket_count = 0;
  467. adap->packet_count = 0;
  468. dvb_adap = &adap->adap;
  469. dvb_adap->priv = adap;
  470. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  471. &pt1->pdev->dev, adapter_nr);
  472. if (ret < 0)
  473. goto err_free_page;
  474. demux = &adap->demux;
  475. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  476. demux->priv = adap;
  477. demux->feednum = 256;
  478. demux->filternum = 256;
  479. demux->start_feed = pt1_start_feed;
  480. demux->stop_feed = pt1_stop_feed;
  481. demux->write_to_decoder = NULL;
  482. ret = dvb_dmx_init(demux);
  483. if (ret < 0)
  484. goto err_unregister_adapter;
  485. dmxdev = &adap->dmxdev;
  486. dmxdev->filternum = 256;
  487. dmxdev->demux = &demux->dmx;
  488. dmxdev->capabilities = 0;
  489. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  490. if (ret < 0)
  491. goto err_dmx_release;
  492. dvb_net_init(dvb_adap, &adap->net, &demux->dmx);
  493. ret = dvb_register_frontend(dvb_adap, fe);
  494. if (ret < 0)
  495. goto err_net_release;
  496. adap->fe = fe;
  497. return adap;
  498. err_net_release:
  499. dvb_net_release(&adap->net);
  500. adap->demux.dmx.close(&adap->demux.dmx);
  501. dvb_dmxdev_release(&adap->dmxdev);
  502. err_dmx_release:
  503. dvb_dmx_release(demux);
  504. err_unregister_adapter:
  505. dvb_unregister_adapter(dvb_adap);
  506. err_free_page:
  507. free_page((unsigned long)buf);
  508. err_kfree:
  509. kfree(adap);
  510. err:
  511. return ERR_PTR(ret);
  512. }
  513. static void pt1_cleanup_adapters(struct pt1 *pt1)
  514. {
  515. int i;
  516. for (i = 0; i < PT1_NR_ADAPS; i++)
  517. pt1_free_adapter(pt1->adaps[i]);
  518. }
  519. struct pt1_config {
  520. struct va1j5jf8007s_config va1j5jf8007s_config;
  521. struct va1j5jf8007t_config va1j5jf8007t_config;
  522. };
  523. static const struct pt1_config pt1_configs[2] = {
  524. {
  525. { .demod_address = 0x1b },
  526. { .demod_address = 0x1a },
  527. }, {
  528. { .demod_address = 0x19 },
  529. { .demod_address = 0x18 },
  530. },
  531. };
  532. static int pt1_init_adapters(struct pt1 *pt1)
  533. {
  534. int i, j;
  535. struct i2c_adapter *i2c_adap;
  536. const struct pt1_config *config;
  537. struct dvb_frontend *fe[4];
  538. struct pt1_adapter *adap;
  539. int ret;
  540. i = 0;
  541. j = 0;
  542. i2c_adap = &pt1->i2c_adap;
  543. do {
  544. config = &pt1_configs[i / 2];
  545. fe[i] = va1j5jf8007s_attach(&config->va1j5jf8007s_config,
  546. i2c_adap);
  547. if (!fe[i]) {
  548. ret = -ENODEV; /* This does not sound nice... */
  549. goto err;
  550. }
  551. i++;
  552. fe[i] = va1j5jf8007t_attach(&config->va1j5jf8007t_config,
  553. i2c_adap);
  554. if (!fe[i]) {
  555. ret = -ENODEV;
  556. goto err;
  557. }
  558. i++;
  559. ret = va1j5jf8007s_prepare(fe[i - 2]);
  560. if (ret < 0)
  561. goto err;
  562. ret = va1j5jf8007t_prepare(fe[i - 1]);
  563. if (ret < 0)
  564. goto err;
  565. } while (i < 4);
  566. do {
  567. adap = pt1_alloc_adapter(pt1, fe[j]);
  568. if (IS_ERR(adap))
  569. goto err;
  570. adap->index = j;
  571. pt1->adaps[j] = adap;
  572. } while (++j < 4);
  573. return 0;
  574. err:
  575. while (i-- > j)
  576. fe[i]->ops.release(fe[i]);
  577. while (j--)
  578. pt1_free_adapter(pt1->adaps[j]);
  579. return ret;
  580. }
  581. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  582. int clock, int data, int next_addr)
  583. {
  584. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  585. !clock << 11 | !data << 10 | next_addr);
  586. }
  587. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  588. {
  589. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  590. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  591. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  592. *addrp = addr + 3;
  593. }
  594. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  595. {
  596. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  597. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  598. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  599. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  600. *addrp = addr + 4;
  601. }
  602. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  603. {
  604. int i;
  605. for (i = 0; i < 8; i++)
  606. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  607. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  608. *addrp = addr;
  609. }
  610. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  611. {
  612. int i;
  613. for (i = 0; i < 8; i++)
  614. pt1_i2c_read_bit(pt1, addr, &addr);
  615. pt1_i2c_write_bit(pt1, addr, &addr, last);
  616. *addrp = addr;
  617. }
  618. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  619. {
  620. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  621. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  622. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  623. *addrp = addr + 3;
  624. }
  625. static void
  626. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  627. {
  628. int i;
  629. pt1_i2c_prepare(pt1, addr, &addr);
  630. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  631. for (i = 0; i < msg->len; i++)
  632. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  633. *addrp = addr;
  634. }
  635. static void
  636. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  637. {
  638. int i;
  639. pt1_i2c_prepare(pt1, addr, &addr);
  640. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  641. for (i = 0; i < msg->len; i++)
  642. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  643. *addrp = addr;
  644. }
  645. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  646. {
  647. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  648. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  649. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  650. pt1_write_reg(pt1, 0, 0x00000004);
  651. do {
  652. if (signal_pending(current))
  653. return -EINTR;
  654. schedule_timeout_interruptible((HZ + 999) / 1000);
  655. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  656. return 0;
  657. }
  658. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  659. {
  660. int addr;
  661. addr = 0;
  662. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  663. addr = addr + 1;
  664. if (!pt1->i2c_running) {
  665. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  666. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  667. addr = addr + 2;
  668. pt1->i2c_running = 1;
  669. }
  670. *addrp = addr;
  671. }
  672. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  673. {
  674. struct pt1 *pt1;
  675. int i;
  676. struct i2c_msg *msg, *next_msg;
  677. int addr, ret;
  678. u16 len;
  679. u32 word;
  680. pt1 = i2c_get_adapdata(adap);
  681. for (i = 0; i < num; i++) {
  682. msg = &msgs[i];
  683. if (msg->flags & I2C_M_RD)
  684. return -ENOTSUPP;
  685. if (i + 1 < num)
  686. next_msg = &msgs[i + 1];
  687. else
  688. next_msg = NULL;
  689. if (next_msg && next_msg->flags & I2C_M_RD) {
  690. i++;
  691. len = next_msg->len;
  692. if (len > 4)
  693. return -ENOTSUPP;
  694. pt1_i2c_begin(pt1, &addr);
  695. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  696. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  697. ret = pt1_i2c_end(pt1, addr);
  698. if (ret < 0)
  699. return ret;
  700. word = pt1_read_reg(pt1, 2);
  701. while (len--) {
  702. next_msg->buf[len] = word;
  703. word >>= 8;
  704. }
  705. } else {
  706. pt1_i2c_begin(pt1, &addr);
  707. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  708. ret = pt1_i2c_end(pt1, addr);
  709. if (ret < 0)
  710. return ret;
  711. }
  712. }
  713. return num;
  714. }
  715. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  716. {
  717. return I2C_FUNC_I2C;
  718. }
  719. static const struct i2c_algorithm pt1_i2c_algo = {
  720. .master_xfer = pt1_i2c_xfer,
  721. .functionality = pt1_i2c_func,
  722. };
  723. static void pt1_i2c_wait(struct pt1 *pt1)
  724. {
  725. int i;
  726. for (i = 0; i < 128; i++)
  727. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  728. }
  729. static void pt1_i2c_init(struct pt1 *pt1)
  730. {
  731. int i;
  732. for (i = 0; i < 1024; i++)
  733. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  734. }
  735. static void __devexit pt1_remove(struct pci_dev *pdev)
  736. {
  737. struct pt1 *pt1;
  738. void __iomem *regs;
  739. pt1 = pci_get_drvdata(pdev);
  740. regs = pt1->regs;
  741. kthread_stop(pt1->kthread);
  742. pt1_cleanup_tables(pt1);
  743. pt1_cleanup_adapters(pt1);
  744. pt1_disable_ram(pt1);
  745. pt1_set_power(pt1, 0, 0, 1);
  746. i2c_del_adapter(&pt1->i2c_adap);
  747. pci_set_drvdata(pdev, NULL);
  748. kfree(pt1);
  749. pci_iounmap(pdev, regs);
  750. pci_release_regions(pdev);
  751. pci_disable_device(pdev);
  752. }
  753. static int __devinit
  754. pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  755. {
  756. int ret;
  757. void __iomem *regs;
  758. struct pt1 *pt1;
  759. struct i2c_adapter *i2c_adap;
  760. struct task_struct *kthread;
  761. ret = pci_enable_device(pdev);
  762. if (ret < 0)
  763. goto err;
  764. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  765. if (ret < 0)
  766. goto err_pci_disable_device;
  767. pci_set_master(pdev);
  768. ret = pci_request_regions(pdev, DRIVER_NAME);
  769. if (ret < 0)
  770. goto err_pci_disable_device;
  771. regs = pci_iomap(pdev, 0, 0);
  772. if (!regs) {
  773. ret = -EIO;
  774. goto err_pci_release_regions;
  775. }
  776. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  777. if (!pt1) {
  778. ret = -ENOMEM;
  779. goto err_pci_iounmap;
  780. }
  781. pt1->pdev = pdev;
  782. pt1->regs = regs;
  783. pci_set_drvdata(pdev, pt1);
  784. i2c_adap = &pt1->i2c_adap;
  785. i2c_adap->class = I2C_CLASS_TV_DIGITAL;
  786. i2c_adap->algo = &pt1_i2c_algo;
  787. i2c_adap->algo_data = NULL;
  788. i2c_adap->dev.parent = &pdev->dev;
  789. i2c_set_adapdata(i2c_adap, pt1);
  790. ret = i2c_add_adapter(i2c_adap);
  791. if (ret < 0)
  792. goto err_kfree;
  793. pt1_set_power(pt1, 0, 0, 1);
  794. pt1_i2c_init(pt1);
  795. pt1_i2c_wait(pt1);
  796. ret = pt1_sync(pt1);
  797. if (ret < 0)
  798. goto err_i2c_del_adapter;
  799. pt1_identify(pt1);
  800. ret = pt1_unlock(pt1);
  801. if (ret < 0)
  802. goto err_i2c_del_adapter;
  803. ret = pt1_reset_pci(pt1);
  804. if (ret < 0)
  805. goto err_i2c_del_adapter;
  806. ret = pt1_reset_ram(pt1);
  807. if (ret < 0)
  808. goto err_i2c_del_adapter;
  809. ret = pt1_enable_ram(pt1);
  810. if (ret < 0)
  811. goto err_i2c_del_adapter;
  812. pt1_init_streams(pt1);
  813. pt1_set_power(pt1, 1, 0, 1);
  814. schedule_timeout_uninterruptible((HZ + 49) / 50);
  815. pt1_set_power(pt1, 1, 0, 0);
  816. schedule_timeout_uninterruptible((HZ + 999) / 1000);
  817. ret = pt1_init_adapters(pt1);
  818. if (ret < 0)
  819. goto err_pt1_disable_ram;
  820. ret = pt1_init_tables(pt1);
  821. if (ret < 0)
  822. goto err_pt1_cleanup_adapters;
  823. kthread = kthread_run(pt1_thread, pt1, "pt1");
  824. if (IS_ERR(kthread)) {
  825. ret = PTR_ERR(kthread);
  826. goto err_pt1_cleanup_tables;
  827. }
  828. pt1->kthread = kthread;
  829. return 0;
  830. err_pt1_cleanup_tables:
  831. pt1_cleanup_tables(pt1);
  832. err_pt1_cleanup_adapters:
  833. pt1_cleanup_adapters(pt1);
  834. err_pt1_disable_ram:
  835. pt1_disable_ram(pt1);
  836. pt1_set_power(pt1, 0, 0, 1);
  837. err_i2c_del_adapter:
  838. i2c_del_adapter(i2c_adap);
  839. err_kfree:
  840. pci_set_drvdata(pdev, NULL);
  841. kfree(pt1);
  842. err_pci_iounmap:
  843. pci_iounmap(pdev, regs);
  844. err_pci_release_regions:
  845. pci_release_regions(pdev);
  846. err_pci_disable_device:
  847. pci_disable_device(pdev);
  848. err:
  849. return ret;
  850. }
  851. static struct pci_device_id pt1_id_table[] = {
  852. { PCI_DEVICE(0x10ee, 0x211a) },
  853. { },
  854. };
  855. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  856. static struct pci_driver pt1_driver = {
  857. .name = DRIVER_NAME,
  858. .probe = pt1_probe,
  859. .remove = __devexit_p(pt1_remove),
  860. .id_table = pt1_id_table,
  861. };
  862. static int __init pt1_init(void)
  863. {
  864. return pci_register_driver(&pt1_driver);
  865. }
  866. static void __exit pt1_cleanup(void)
  867. {
  868. pci_unregister_driver(&pt1_driver);
  869. }
  870. module_init(pt1_init);
  871. module_exit(pt1_cleanup);
  872. MODULE_AUTHOR("Takahito HIRANO <hiranotaka@zng.info>");
  873. MODULE_DESCRIPTION("Earthsoft PT1 Driver");
  874. MODULE_LICENSE("GPL");