uhci-q.c 36 KB

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  1. /*
  2. * Universal Host Controller Interface driver for USB.
  3. *
  4. * Maintainer: Alan Stern <stern@rowland.harvard.edu>
  5. *
  6. * (C) Copyright 1999 Linus Torvalds
  7. * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
  8. * (C) Copyright 1999 Randy Dunlap
  9. * (C) Copyright 1999 Georg Acher, acher@in.tum.de
  10. * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
  11. * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
  12. * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
  13. * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
  14. * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
  15. * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
  16. * (C) Copyright 2004-2005 Alan Stern, stern@rowland.harvard.edu
  17. */
  18. /*
  19. * Technically, updating td->status here is a race, but it's not really a
  20. * problem. The worst that can happen is that we set the IOC bit again
  21. * generating a spurious interrupt. We could fix this by creating another
  22. * QH and leaving the IOC bit always set, but then we would have to play
  23. * games with the FSBR code to make sure we get the correct order in all
  24. * the cases. I don't think it's worth the effort
  25. */
  26. static void uhci_set_next_interrupt(struct uhci_hcd *uhci)
  27. {
  28. if (uhci->is_stopped)
  29. mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
  30. uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
  31. }
  32. static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
  33. {
  34. uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
  35. }
  36. /*
  37. * Full-Speed Bandwidth Reclamation (FSBR).
  38. * We turn on FSBR whenever a queue that wants it is advancing,
  39. * and leave it on for a short time thereafter.
  40. */
  41. static void uhci_fsbr_on(struct uhci_hcd *uhci)
  42. {
  43. uhci->fsbr_is_on = 1;
  44. uhci->skel_term_qh->link = cpu_to_le32(
  45. uhci->skel_fs_control_qh->dma_handle) | UHCI_PTR_QH;
  46. }
  47. static void uhci_fsbr_off(struct uhci_hcd *uhci)
  48. {
  49. uhci->fsbr_is_on = 0;
  50. uhci->skel_term_qh->link = UHCI_PTR_TERM;
  51. }
  52. static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
  53. {
  54. struct urb_priv *urbp = urb->hcpriv;
  55. if (!(urb->transfer_flags & URB_NO_FSBR))
  56. urbp->fsbr = 1;
  57. }
  58. static void uhci_qh_wants_fsbr(struct uhci_hcd *uhci, struct uhci_qh *qh)
  59. {
  60. struct urb_priv *urbp =
  61. list_entry(qh->queue.next, struct urb_priv, node);
  62. if (urbp->fsbr) {
  63. uhci->fsbr_jiffies = jiffies;
  64. if (!uhci->fsbr_is_on)
  65. uhci_fsbr_on(uhci);
  66. }
  67. }
  68. static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci)
  69. {
  70. dma_addr_t dma_handle;
  71. struct uhci_td *td;
  72. td = dma_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
  73. if (!td)
  74. return NULL;
  75. td->dma_handle = dma_handle;
  76. td->frame = -1;
  77. INIT_LIST_HEAD(&td->list);
  78. INIT_LIST_HEAD(&td->fl_list);
  79. return td;
  80. }
  81. static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
  82. {
  83. if (!list_empty(&td->list))
  84. dev_warn(uhci_dev(uhci), "td %p still in list!\n", td);
  85. if (!list_empty(&td->fl_list))
  86. dev_warn(uhci_dev(uhci), "td %p still in fl_list!\n", td);
  87. dma_pool_free(uhci->td_pool, td, td->dma_handle);
  88. }
  89. static inline void uhci_fill_td(struct uhci_td *td, u32 status,
  90. u32 token, u32 buffer)
  91. {
  92. td->status = cpu_to_le32(status);
  93. td->token = cpu_to_le32(token);
  94. td->buffer = cpu_to_le32(buffer);
  95. }
  96. static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
  97. {
  98. list_add_tail(&td->list, &urbp->td_list);
  99. }
  100. static void uhci_remove_td_from_urbp(struct uhci_td *td)
  101. {
  102. list_del_init(&td->list);
  103. }
  104. /*
  105. * We insert Isochronous URBs directly into the frame list at the beginning
  106. */
  107. static inline void uhci_insert_td_in_frame_list(struct uhci_hcd *uhci,
  108. struct uhci_td *td, unsigned framenum)
  109. {
  110. framenum &= (UHCI_NUMFRAMES - 1);
  111. td->frame = framenum;
  112. /* Is there a TD already mapped there? */
  113. if (uhci->frame_cpu[framenum]) {
  114. struct uhci_td *ftd, *ltd;
  115. ftd = uhci->frame_cpu[framenum];
  116. ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
  117. list_add_tail(&td->fl_list, &ftd->fl_list);
  118. td->link = ltd->link;
  119. wmb();
  120. ltd->link = cpu_to_le32(td->dma_handle);
  121. } else {
  122. td->link = uhci->frame[framenum];
  123. wmb();
  124. uhci->frame[framenum] = cpu_to_le32(td->dma_handle);
  125. uhci->frame_cpu[framenum] = td;
  126. }
  127. }
  128. static inline void uhci_remove_td_from_frame_list(struct uhci_hcd *uhci,
  129. struct uhci_td *td)
  130. {
  131. /* If it's not inserted, don't remove it */
  132. if (td->frame == -1) {
  133. WARN_ON(!list_empty(&td->fl_list));
  134. return;
  135. }
  136. if (uhci->frame_cpu[td->frame] == td) {
  137. if (list_empty(&td->fl_list)) {
  138. uhci->frame[td->frame] = td->link;
  139. uhci->frame_cpu[td->frame] = NULL;
  140. } else {
  141. struct uhci_td *ntd;
  142. ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
  143. uhci->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
  144. uhci->frame_cpu[td->frame] = ntd;
  145. }
  146. } else {
  147. struct uhci_td *ptd;
  148. ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
  149. ptd->link = td->link;
  150. }
  151. list_del_init(&td->fl_list);
  152. td->frame = -1;
  153. }
  154. /*
  155. * Remove all the TDs for an Isochronous URB from the frame list
  156. */
  157. static void uhci_unlink_isochronous_tds(struct uhci_hcd *uhci, struct urb *urb)
  158. {
  159. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  160. struct uhci_td *td;
  161. list_for_each_entry(td, &urbp->td_list, list)
  162. uhci_remove_td_from_frame_list(uhci, td);
  163. wmb();
  164. }
  165. static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
  166. struct usb_device *udev, struct usb_host_endpoint *hep)
  167. {
  168. dma_addr_t dma_handle;
  169. struct uhci_qh *qh;
  170. qh = dma_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
  171. if (!qh)
  172. return NULL;
  173. memset(qh, 0, sizeof(*qh));
  174. qh->dma_handle = dma_handle;
  175. qh->element = UHCI_PTR_TERM;
  176. qh->link = UHCI_PTR_TERM;
  177. INIT_LIST_HEAD(&qh->queue);
  178. INIT_LIST_HEAD(&qh->node);
  179. if (udev) { /* Normal QH */
  180. qh->dummy_td = uhci_alloc_td(uhci);
  181. if (!qh->dummy_td) {
  182. dma_pool_free(uhci->qh_pool, qh, dma_handle);
  183. return NULL;
  184. }
  185. qh->state = QH_STATE_IDLE;
  186. qh->hep = hep;
  187. qh->udev = udev;
  188. hep->hcpriv = qh;
  189. qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
  190. } else { /* Skeleton QH */
  191. qh->state = QH_STATE_ACTIVE;
  192. qh->type = -1;
  193. }
  194. return qh;
  195. }
  196. static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  197. {
  198. WARN_ON(qh->state != QH_STATE_IDLE && qh->udev);
  199. if (!list_empty(&qh->queue))
  200. dev_warn(uhci_dev(uhci), "qh %p list not empty!\n", qh);
  201. list_del(&qh->node);
  202. if (qh->udev) {
  203. qh->hep->hcpriv = NULL;
  204. uhci_free_td(uhci, qh->dummy_td);
  205. }
  206. dma_pool_free(uhci->qh_pool, qh, qh->dma_handle);
  207. }
  208. /*
  209. * When a queue is stopped and a dequeued URB is given back, adjust
  210. * the previous TD link (if the URB isn't first on the queue) or
  211. * save its toggle value (if it is first and is currently executing).
  212. */
  213. static void uhci_cleanup_queue(struct uhci_qh *qh,
  214. struct urb *urb)
  215. {
  216. struct urb_priv *urbp = urb->hcpriv;
  217. struct uhci_td *td;
  218. /* Isochronous pipes don't use toggles and their TD link pointers
  219. * get adjusted during uhci_urb_dequeue(). */
  220. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  221. return;
  222. /* If the URB isn't first on its queue, adjust the link pointer
  223. * of the last TD in the previous URB. The toggle doesn't need
  224. * to be saved since this URB can't be executing yet. */
  225. if (qh->queue.next != &urbp->node) {
  226. struct urb_priv *purbp;
  227. struct uhci_td *ptd;
  228. purbp = list_entry(urbp->node.prev, struct urb_priv, node);
  229. WARN_ON(list_empty(&purbp->td_list));
  230. ptd = list_entry(purbp->td_list.prev, struct uhci_td,
  231. list);
  232. td = list_entry(urbp->td_list.prev, struct uhci_td,
  233. list);
  234. ptd->link = td->link;
  235. return;
  236. }
  237. /* If the QH element pointer is UHCI_PTR_TERM then then currently
  238. * executing URB has already been unlinked, so this one isn't it. */
  239. if (qh_element(qh) == UHCI_PTR_TERM)
  240. return;
  241. qh->element = UHCI_PTR_TERM;
  242. /* Control pipes have to worry about toggles */
  243. if (qh->type == USB_ENDPOINT_XFER_CONTROL)
  244. return;
  245. /* Save the next toggle value */
  246. WARN_ON(list_empty(&urbp->td_list));
  247. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  248. qh->needs_fixup = 1;
  249. qh->initial_toggle = uhci_toggle(td_token(td));
  250. }
  251. /*
  252. * Fix up the data toggles for URBs in a queue, when one of them
  253. * terminates early (short transfer, error, or dequeued).
  254. */
  255. static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
  256. {
  257. struct urb_priv *urbp = NULL;
  258. struct uhci_td *td;
  259. unsigned int toggle = qh->initial_toggle;
  260. unsigned int pipe;
  261. /* Fixups for a short transfer start with the second URB in the
  262. * queue (the short URB is the first). */
  263. if (skip_first)
  264. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  265. /* When starting with the first URB, if the QH element pointer is
  266. * still valid then we know the URB's toggles are okay. */
  267. else if (qh_element(qh) != UHCI_PTR_TERM)
  268. toggle = 2;
  269. /* Fix up the toggle for the URBs in the queue. Normally this
  270. * loop won't run more than once: When an error or short transfer
  271. * occurs, the queue usually gets emptied. */
  272. urbp = list_prepare_entry(urbp, &qh->queue, node);
  273. list_for_each_entry_continue(urbp, &qh->queue, node) {
  274. /* If the first TD has the right toggle value, we don't
  275. * need to change any toggles in this URB */
  276. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  277. if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
  278. td = list_entry(urbp->td_list.next, struct uhci_td,
  279. list);
  280. toggle = uhci_toggle(td_token(td)) ^ 1;
  281. /* Otherwise all the toggles in the URB have to be switched */
  282. } else {
  283. list_for_each_entry(td, &urbp->td_list, list) {
  284. td->token ^= __constant_cpu_to_le32(
  285. TD_TOKEN_TOGGLE);
  286. toggle ^= 1;
  287. }
  288. }
  289. }
  290. wmb();
  291. pipe = list_entry(qh->queue.next, struct urb_priv, node)->urb->pipe;
  292. usb_settoggle(qh->udev, usb_pipeendpoint(pipe),
  293. usb_pipeout(pipe), toggle);
  294. qh->needs_fixup = 0;
  295. }
  296. /*
  297. * Put a QH on the schedule in both hardware and software
  298. */
  299. static void uhci_activate_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  300. {
  301. struct uhci_qh *pqh;
  302. WARN_ON(list_empty(&qh->queue));
  303. /* Set the element pointer if it isn't set already.
  304. * This isn't needed for Isochronous queues, but it doesn't hurt. */
  305. if (qh_element(qh) == UHCI_PTR_TERM) {
  306. struct urb_priv *urbp = list_entry(qh->queue.next,
  307. struct urb_priv, node);
  308. struct uhci_td *td = list_entry(urbp->td_list.next,
  309. struct uhci_td, list);
  310. qh->element = cpu_to_le32(td->dma_handle);
  311. }
  312. /* Treat the queue as if it has just advanced */
  313. qh->wait_expired = 0;
  314. qh->advance_jiffies = jiffies;
  315. if (qh->state == QH_STATE_ACTIVE)
  316. return;
  317. qh->state = QH_STATE_ACTIVE;
  318. /* Move the QH from its old list to the end of the appropriate
  319. * skeleton's list */
  320. if (qh == uhci->next_qh)
  321. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  322. node);
  323. list_move_tail(&qh->node, &qh->skel->node);
  324. /* Link it into the schedule */
  325. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  326. qh->link = pqh->link;
  327. wmb();
  328. pqh->link = UHCI_PTR_QH | cpu_to_le32(qh->dma_handle);
  329. }
  330. /*
  331. * Take a QH off the hardware schedule
  332. */
  333. static void uhci_unlink_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
  334. {
  335. struct uhci_qh *pqh;
  336. if (qh->state == QH_STATE_UNLINKING)
  337. return;
  338. WARN_ON(qh->state != QH_STATE_ACTIVE || !qh->udev);
  339. qh->state = QH_STATE_UNLINKING;
  340. /* Unlink the QH from the schedule and record when we did it */
  341. pqh = list_entry(qh->node.prev, struct uhci_qh, node);
  342. pqh->link = qh->link;
  343. mb();
  344. uhci_get_current_frame_number(uhci);
  345. qh->unlink_frame = uhci->frame_number;
  346. /* Force an interrupt so we know when the QH is fully unlinked */
  347. if (list_empty(&uhci->skel_unlink_qh->node))
  348. uhci_set_next_interrupt(uhci);
  349. /* Move the QH from its old list to the end of the unlinking list */
  350. if (qh == uhci->next_qh)
  351. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  352. node);
  353. list_move_tail(&qh->node, &uhci->skel_unlink_qh->node);
  354. }
  355. /*
  356. * When we and the controller are through with a QH, it becomes IDLE.
  357. * This happens when a QH has been off the schedule (on the unlinking
  358. * list) for more than one frame, or when an error occurs while adding
  359. * the first URB onto a new QH.
  360. */
  361. static void uhci_make_qh_idle(struct uhci_hcd *uhci, struct uhci_qh *qh)
  362. {
  363. WARN_ON(qh->state == QH_STATE_ACTIVE);
  364. if (qh == uhci->next_qh)
  365. uhci->next_qh = list_entry(qh->node.next, struct uhci_qh,
  366. node);
  367. list_move(&qh->node, &uhci->idle_qh_list);
  368. qh->state = QH_STATE_IDLE;
  369. /* Now that the QH is idle, its post_td isn't being used */
  370. if (qh->post_td) {
  371. uhci_free_td(uhci, qh->post_td);
  372. qh->post_td = NULL;
  373. }
  374. /* If anyone is waiting for a QH to become idle, wake them up */
  375. if (uhci->num_waiting)
  376. wake_up_all(&uhci->waitqh);
  377. }
  378. static inline struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci,
  379. struct urb *urb)
  380. {
  381. struct urb_priv *urbp;
  382. urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
  383. if (!urbp)
  384. return NULL;
  385. memset((void *)urbp, 0, sizeof(*urbp));
  386. urbp->urb = urb;
  387. urb->hcpriv = urbp;
  388. INIT_LIST_HEAD(&urbp->node);
  389. INIT_LIST_HEAD(&urbp->td_list);
  390. return urbp;
  391. }
  392. static void uhci_free_urb_priv(struct uhci_hcd *uhci,
  393. struct urb_priv *urbp)
  394. {
  395. struct uhci_td *td, *tmp;
  396. if (!list_empty(&urbp->node))
  397. dev_warn(uhci_dev(uhci), "urb %p still on QH's list!\n",
  398. urbp->urb);
  399. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  400. uhci_remove_td_from_urbp(td);
  401. uhci_free_td(uhci, td);
  402. }
  403. urbp->urb->hcpriv = NULL;
  404. kmem_cache_free(uhci_up_cachep, urbp);
  405. }
  406. /*
  407. * Map status to standard result codes
  408. *
  409. * <status> is (td_status(td) & 0xF60000), a.k.a.
  410. * uhci_status_bits(td_status(td)).
  411. * Note: <status> does not include the TD_CTRL_NAK bit.
  412. * <dir_out> is True for output TDs and False for input TDs.
  413. */
  414. static int uhci_map_status(int status, int dir_out)
  415. {
  416. if (!status)
  417. return 0;
  418. if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
  419. return -EPROTO;
  420. if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
  421. if (dir_out)
  422. return -EPROTO;
  423. else
  424. return -EILSEQ;
  425. }
  426. if (status & TD_CTRL_BABBLE) /* Babble */
  427. return -EOVERFLOW;
  428. if (status & TD_CTRL_DBUFERR) /* Buffer error */
  429. return -ENOSR;
  430. if (status & TD_CTRL_STALLED) /* Stalled */
  431. return -EPIPE;
  432. WARN_ON(status & TD_CTRL_ACTIVE); /* Active */
  433. return 0;
  434. }
  435. /*
  436. * Control transfers
  437. */
  438. static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb,
  439. struct uhci_qh *qh)
  440. {
  441. struct uhci_td *td;
  442. unsigned long destination, status;
  443. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  444. int len = urb->transfer_buffer_length;
  445. dma_addr_t data = urb->transfer_dma;
  446. __le32 *plink;
  447. struct urb_priv *urbp = urb->hcpriv;
  448. /* The "pipe" thing contains the destination in bits 8--18 */
  449. destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
  450. /* 3 errors, dummy TD remains inactive */
  451. status = uhci_maxerr(3);
  452. if (urb->dev->speed == USB_SPEED_LOW)
  453. status |= TD_CTRL_LS;
  454. /*
  455. * Build the TD for the control request setup packet
  456. */
  457. td = qh->dummy_td;
  458. uhci_add_td_to_urbp(td, urbp);
  459. uhci_fill_td(td, status, destination | uhci_explen(8),
  460. urb->setup_dma);
  461. plink = &td->link;
  462. status |= TD_CTRL_ACTIVE;
  463. /*
  464. * If direction is "send", change the packet ID from SETUP (0x2D)
  465. * to OUT (0xE1). Else change it from SETUP to IN (0x69) and
  466. * set Short Packet Detect (SPD) for all data packets.
  467. */
  468. if (usb_pipeout(urb->pipe))
  469. destination ^= (USB_PID_SETUP ^ USB_PID_OUT);
  470. else {
  471. destination ^= (USB_PID_SETUP ^ USB_PID_IN);
  472. status |= TD_CTRL_SPD;
  473. }
  474. /*
  475. * Build the DATA TDs
  476. */
  477. while (len > 0) {
  478. int pktsze = min(len, maxsze);
  479. td = uhci_alloc_td(uhci);
  480. if (!td)
  481. goto nomem;
  482. *plink = cpu_to_le32(td->dma_handle);
  483. /* Alternate Data0/1 (start with Data1) */
  484. destination ^= TD_TOKEN_TOGGLE;
  485. uhci_add_td_to_urbp(td, urbp);
  486. uhci_fill_td(td, status, destination | uhci_explen(pktsze),
  487. data);
  488. plink = &td->link;
  489. data += pktsze;
  490. len -= pktsze;
  491. }
  492. /*
  493. * Build the final TD for control status
  494. */
  495. td = uhci_alloc_td(uhci);
  496. if (!td)
  497. goto nomem;
  498. *plink = cpu_to_le32(td->dma_handle);
  499. /*
  500. * It's IN if the pipe is an output pipe or we're not expecting
  501. * data back.
  502. */
  503. destination &= ~TD_TOKEN_PID_MASK;
  504. if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
  505. destination |= USB_PID_IN;
  506. else
  507. destination |= USB_PID_OUT;
  508. destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
  509. status &= ~TD_CTRL_SPD;
  510. uhci_add_td_to_urbp(td, urbp);
  511. uhci_fill_td(td, status | TD_CTRL_IOC,
  512. destination | uhci_explen(0), 0);
  513. plink = &td->link;
  514. /*
  515. * Build the new dummy TD and activate the old one
  516. */
  517. td = uhci_alloc_td(uhci);
  518. if (!td)
  519. goto nomem;
  520. *plink = cpu_to_le32(td->dma_handle);
  521. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  522. wmb();
  523. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  524. qh->dummy_td = td;
  525. /* Low-speed transfers get a different queue, and won't hog the bus.
  526. * Also, some devices enumerate better without FSBR; the easiest way
  527. * to do that is to put URBs on the low-speed queue while the device
  528. * isn't in the CONFIGURED state. */
  529. if (urb->dev->speed == USB_SPEED_LOW ||
  530. urb->dev->state != USB_STATE_CONFIGURED)
  531. qh->skel = uhci->skel_ls_control_qh;
  532. else {
  533. qh->skel = uhci->skel_fs_control_qh;
  534. uhci_add_fsbr(uhci, urb);
  535. }
  536. urb->actual_length = -8; /* Account for the SETUP packet */
  537. return 0;
  538. nomem:
  539. /* Remove the dummy TD from the td_list so it doesn't get freed */
  540. uhci_remove_td_from_urbp(qh->dummy_td);
  541. return -ENOMEM;
  542. }
  543. /*
  544. * Common submit for bulk and interrupt
  545. */
  546. static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb,
  547. struct uhci_qh *qh)
  548. {
  549. struct uhci_td *td;
  550. unsigned long destination, status;
  551. int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
  552. int len = urb->transfer_buffer_length;
  553. dma_addr_t data = urb->transfer_dma;
  554. __le32 *plink;
  555. struct urb_priv *urbp = urb->hcpriv;
  556. unsigned int toggle;
  557. if (len < 0)
  558. return -EINVAL;
  559. /* The "pipe" thing contains the destination in bits 8--18 */
  560. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  561. toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  562. usb_pipeout(urb->pipe));
  563. /* 3 errors, dummy TD remains inactive */
  564. status = uhci_maxerr(3);
  565. if (urb->dev->speed == USB_SPEED_LOW)
  566. status |= TD_CTRL_LS;
  567. if (usb_pipein(urb->pipe))
  568. status |= TD_CTRL_SPD;
  569. /*
  570. * Build the DATA TDs
  571. */
  572. plink = NULL;
  573. td = qh->dummy_td;
  574. do { /* Allow zero length packets */
  575. int pktsze = maxsze;
  576. if (len <= pktsze) { /* The last packet */
  577. pktsze = len;
  578. if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
  579. status &= ~TD_CTRL_SPD;
  580. }
  581. if (plink) {
  582. td = uhci_alloc_td(uhci);
  583. if (!td)
  584. goto nomem;
  585. *plink = cpu_to_le32(td->dma_handle);
  586. }
  587. uhci_add_td_to_urbp(td, urbp);
  588. uhci_fill_td(td, status,
  589. destination | uhci_explen(pktsze) |
  590. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  591. data);
  592. plink = &td->link;
  593. status |= TD_CTRL_ACTIVE;
  594. data += pktsze;
  595. len -= maxsze;
  596. toggle ^= 1;
  597. } while (len > 0);
  598. /*
  599. * URB_ZERO_PACKET means adding a 0-length packet, if direction
  600. * is OUT and the transfer_length was an exact multiple of maxsze,
  601. * hence (len = transfer_length - N * maxsze) == 0
  602. * however, if transfer_length == 0, the zero packet was already
  603. * prepared above.
  604. */
  605. if ((urb->transfer_flags & URB_ZERO_PACKET) &&
  606. usb_pipeout(urb->pipe) && len == 0 &&
  607. urb->transfer_buffer_length > 0) {
  608. td = uhci_alloc_td(uhci);
  609. if (!td)
  610. goto nomem;
  611. *plink = cpu_to_le32(td->dma_handle);
  612. uhci_add_td_to_urbp(td, urbp);
  613. uhci_fill_td(td, status,
  614. destination | uhci_explen(0) |
  615. (toggle << TD_TOKEN_TOGGLE_SHIFT),
  616. data);
  617. plink = &td->link;
  618. toggle ^= 1;
  619. }
  620. /* Set the interrupt-on-completion flag on the last packet.
  621. * A more-or-less typical 4 KB URB (= size of one memory page)
  622. * will require about 3 ms to transfer; that's a little on the
  623. * fast side but not enough to justify delaying an interrupt
  624. * more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
  625. * flag setting. */
  626. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  627. /*
  628. * Build the new dummy TD and activate the old one
  629. */
  630. td = uhci_alloc_td(uhci);
  631. if (!td)
  632. goto nomem;
  633. *plink = cpu_to_le32(td->dma_handle);
  634. uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
  635. wmb();
  636. qh->dummy_td->status |= __constant_cpu_to_le32(TD_CTRL_ACTIVE);
  637. qh->dummy_td = td;
  638. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  639. usb_pipeout(urb->pipe), toggle);
  640. return 0;
  641. nomem:
  642. /* Remove the dummy TD from the td_list so it doesn't get freed */
  643. uhci_remove_td_from_urbp(qh->dummy_td);
  644. return -ENOMEM;
  645. }
  646. static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb,
  647. struct uhci_qh *qh)
  648. {
  649. int ret;
  650. /* Can't have low-speed bulk transfers */
  651. if (urb->dev->speed == USB_SPEED_LOW)
  652. return -EINVAL;
  653. qh->skel = uhci->skel_bulk_qh;
  654. ret = uhci_submit_common(uhci, urb, qh);
  655. if (ret == 0)
  656. uhci_add_fsbr(uhci, urb);
  657. return ret;
  658. }
  659. static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb,
  660. struct uhci_qh *qh)
  661. {
  662. /* USB 1.1 interrupt transfers only involve one packet per interval.
  663. * Drivers can submit URBs of any length, but longer ones will need
  664. * multiple intervals to complete.
  665. */
  666. qh->skel = uhci->skelqh[__interval_to_skel(urb->interval)];
  667. return uhci_submit_common(uhci, urb, qh);
  668. }
  669. /*
  670. * Fix up the data structures following a short transfer
  671. */
  672. static int uhci_fixup_short_transfer(struct uhci_hcd *uhci,
  673. struct uhci_qh *qh, struct urb_priv *urbp)
  674. {
  675. struct uhci_td *td;
  676. struct list_head *tmp;
  677. int ret;
  678. td = list_entry(urbp->td_list.prev, struct uhci_td, list);
  679. if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
  680. /* When a control transfer is short, we have to restart
  681. * the queue at the status stage transaction, which is
  682. * the last TD. */
  683. WARN_ON(list_empty(&urbp->td_list));
  684. qh->element = cpu_to_le32(td->dma_handle);
  685. tmp = td->list.prev;
  686. ret = -EINPROGRESS;
  687. } else {
  688. /* When a bulk/interrupt transfer is short, we have to
  689. * fix up the toggles of the following URBs on the queue
  690. * before restarting the queue at the next URB. */
  691. qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
  692. uhci_fixup_toggles(qh, 1);
  693. if (list_empty(&urbp->td_list))
  694. td = qh->post_td;
  695. qh->element = td->link;
  696. tmp = urbp->td_list.prev;
  697. ret = 0;
  698. }
  699. /* Remove all the TDs we skipped over, from tmp back to the start */
  700. while (tmp != &urbp->td_list) {
  701. td = list_entry(tmp, struct uhci_td, list);
  702. tmp = tmp->prev;
  703. uhci_remove_td_from_urbp(td);
  704. uhci_free_td(uhci, td);
  705. }
  706. return ret;
  707. }
  708. /*
  709. * Common result for control, bulk, and interrupt
  710. */
  711. static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
  712. {
  713. struct urb_priv *urbp = urb->hcpriv;
  714. struct uhci_qh *qh = urbp->qh;
  715. struct uhci_td *td, *tmp;
  716. unsigned status;
  717. int ret = 0;
  718. list_for_each_entry_safe(td, tmp, &urbp->td_list, list) {
  719. unsigned int ctrlstat;
  720. int len;
  721. ctrlstat = td_status(td);
  722. status = uhci_status_bits(ctrlstat);
  723. if (status & TD_CTRL_ACTIVE)
  724. return -EINPROGRESS;
  725. len = uhci_actual_length(ctrlstat);
  726. urb->actual_length += len;
  727. if (status) {
  728. ret = uhci_map_status(status,
  729. uhci_packetout(td_token(td)));
  730. if ((debug == 1 && ret != -EPIPE) || debug > 1) {
  731. /* Some debugging code */
  732. dev_dbg(uhci_dev(uhci),
  733. "%s: failed with status %x\n",
  734. __FUNCTION__, status);
  735. if (debug > 1 && errbuf) {
  736. /* Print the chain for debugging */
  737. uhci_show_qh(urbp->qh, errbuf,
  738. ERRBUF_LEN, 0);
  739. lprintk(errbuf);
  740. }
  741. }
  742. } else if (len < uhci_expected_length(td_token(td))) {
  743. /* We received a short packet */
  744. if (urb->transfer_flags & URB_SHORT_NOT_OK)
  745. ret = -EREMOTEIO;
  746. else if (ctrlstat & TD_CTRL_SPD)
  747. ret = 1;
  748. }
  749. uhci_remove_td_from_urbp(td);
  750. if (qh->post_td)
  751. uhci_free_td(uhci, qh->post_td);
  752. qh->post_td = td;
  753. if (ret != 0)
  754. goto err;
  755. }
  756. return ret;
  757. err:
  758. if (ret < 0) {
  759. /* In case a control transfer gets an error
  760. * during the setup stage */
  761. urb->actual_length = max(urb->actual_length, 0);
  762. /* Note that the queue has stopped and save
  763. * the next toggle value */
  764. qh->element = UHCI_PTR_TERM;
  765. qh->is_stopped = 1;
  766. qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
  767. qh->initial_toggle = uhci_toggle(td_token(td)) ^
  768. (ret == -EREMOTEIO);
  769. } else /* Short packet received */
  770. ret = uhci_fixup_short_transfer(uhci, qh, urbp);
  771. return ret;
  772. }
  773. /*
  774. * Isochronous transfers
  775. */
  776. static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb,
  777. struct uhci_qh *qh)
  778. {
  779. struct uhci_td *td = NULL; /* Since urb->number_of_packets > 0 */
  780. int i, frame;
  781. unsigned long destination, status;
  782. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  783. if (urb->number_of_packets > 900) /* 900? Why? */
  784. return -EFBIG;
  785. status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
  786. destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
  787. /* Figure out the starting frame number */
  788. if (urb->transfer_flags & URB_ISO_ASAP) {
  789. if (list_empty(&qh->queue)) {
  790. uhci_get_current_frame_number(uhci);
  791. urb->start_frame = (uhci->frame_number + 10);
  792. } else { /* Go right after the last one */
  793. struct urb *last_urb;
  794. last_urb = list_entry(qh->queue.prev,
  795. struct urb_priv, node)->urb;
  796. urb->start_frame = (last_urb->start_frame +
  797. last_urb->number_of_packets *
  798. last_urb->interval);
  799. }
  800. } else {
  801. /* FIXME: Sanity check */
  802. }
  803. urb->start_frame &= (UHCI_NUMFRAMES - 1);
  804. for (i = 0; i < urb->number_of_packets; i++) {
  805. td = uhci_alloc_td(uhci);
  806. if (!td)
  807. return -ENOMEM;
  808. uhci_add_td_to_urbp(td, urbp);
  809. uhci_fill_td(td, status, destination |
  810. uhci_explen(urb->iso_frame_desc[i].length),
  811. urb->transfer_dma +
  812. urb->iso_frame_desc[i].offset);
  813. }
  814. /* Set the interrupt-on-completion flag on the last packet. */
  815. td->status |= __constant_cpu_to_le32(TD_CTRL_IOC);
  816. qh->skel = uhci->skel_iso_qh;
  817. /* Add the TDs to the frame list */
  818. frame = urb->start_frame;
  819. list_for_each_entry(td, &urbp->td_list, list) {
  820. uhci_insert_td_in_frame_list(uhci, td, frame);
  821. frame += urb->interval;
  822. }
  823. return 0;
  824. }
  825. static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
  826. {
  827. struct uhci_td *td;
  828. struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
  829. int status;
  830. int i, ret = 0;
  831. urb->actual_length = urb->error_count = 0;
  832. i = 0;
  833. list_for_each_entry(td, &urbp->td_list, list) {
  834. int actlength;
  835. unsigned int ctrlstat = td_status(td);
  836. if (ctrlstat & TD_CTRL_ACTIVE)
  837. return -EINPROGRESS;
  838. actlength = uhci_actual_length(ctrlstat);
  839. urb->iso_frame_desc[i].actual_length = actlength;
  840. urb->actual_length += actlength;
  841. status = uhci_map_status(uhci_status_bits(ctrlstat),
  842. usb_pipeout(urb->pipe));
  843. urb->iso_frame_desc[i].status = status;
  844. if (status) {
  845. urb->error_count++;
  846. ret = status;
  847. }
  848. i++;
  849. }
  850. return ret;
  851. }
  852. static int uhci_urb_enqueue(struct usb_hcd *hcd,
  853. struct usb_host_endpoint *hep,
  854. struct urb *urb, gfp_t mem_flags)
  855. {
  856. int ret;
  857. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  858. unsigned long flags;
  859. struct urb_priv *urbp;
  860. struct uhci_qh *qh;
  861. int bustime;
  862. spin_lock_irqsave(&uhci->lock, flags);
  863. ret = urb->status;
  864. if (ret != -EINPROGRESS) /* URB already unlinked! */
  865. goto done;
  866. ret = -ENOMEM;
  867. urbp = uhci_alloc_urb_priv(uhci, urb);
  868. if (!urbp)
  869. goto done;
  870. if (hep->hcpriv)
  871. qh = (struct uhci_qh *) hep->hcpriv;
  872. else {
  873. qh = uhci_alloc_qh(uhci, urb->dev, hep);
  874. if (!qh)
  875. goto err_no_qh;
  876. }
  877. urbp->qh = qh;
  878. switch (qh->type) {
  879. case USB_ENDPOINT_XFER_CONTROL:
  880. ret = uhci_submit_control(uhci, urb, qh);
  881. break;
  882. case USB_ENDPOINT_XFER_BULK:
  883. ret = uhci_submit_bulk(uhci, urb, qh);
  884. break;
  885. case USB_ENDPOINT_XFER_INT:
  886. if (list_empty(&qh->queue)) {
  887. bustime = usb_check_bandwidth(urb->dev, urb);
  888. if (bustime < 0)
  889. ret = bustime;
  890. else {
  891. ret = uhci_submit_interrupt(uhci, urb, qh);
  892. if (ret == 0)
  893. usb_claim_bandwidth(urb->dev, urb, bustime, 0);
  894. }
  895. } else { /* inherit from parent */
  896. struct urb_priv *eurbp;
  897. eurbp = list_entry(qh->queue.prev, struct urb_priv,
  898. node);
  899. urb->bandwidth = eurbp->urb->bandwidth;
  900. ret = uhci_submit_interrupt(uhci, urb, qh);
  901. }
  902. break;
  903. case USB_ENDPOINT_XFER_ISOC:
  904. bustime = usb_check_bandwidth(urb->dev, urb);
  905. if (bustime < 0) {
  906. ret = bustime;
  907. break;
  908. }
  909. ret = uhci_submit_isochronous(uhci, urb, qh);
  910. if (ret == 0)
  911. usb_claim_bandwidth(urb->dev, urb, bustime, 1);
  912. break;
  913. }
  914. if (ret != 0)
  915. goto err_submit_failed;
  916. /* Add this URB to the QH */
  917. urbp->qh = qh;
  918. list_add_tail(&urbp->node, &qh->queue);
  919. /* If the new URB is the first and only one on this QH then either
  920. * the QH is new and idle or else it's unlinked and waiting to
  921. * become idle, so we can activate it right away. But only if the
  922. * queue isn't stopped. */
  923. if (qh->queue.next == &urbp->node && !qh->is_stopped) {
  924. uhci_activate_qh(uhci, qh);
  925. uhci_qh_wants_fsbr(uhci, qh);
  926. }
  927. goto done;
  928. err_submit_failed:
  929. if (qh->state == QH_STATE_IDLE)
  930. uhci_make_qh_idle(uhci, qh); /* Reclaim unused QH */
  931. err_no_qh:
  932. uhci_free_urb_priv(uhci, urbp);
  933. done:
  934. spin_unlock_irqrestore(&uhci->lock, flags);
  935. return ret;
  936. }
  937. static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
  938. {
  939. struct uhci_hcd *uhci = hcd_to_uhci(hcd);
  940. unsigned long flags;
  941. struct urb_priv *urbp;
  942. spin_lock_irqsave(&uhci->lock, flags);
  943. urbp = urb->hcpriv;
  944. if (!urbp) /* URB was never linked! */
  945. goto done;
  946. /* Remove Isochronous TDs from the frame list ASAP */
  947. if (urbp->qh->type == USB_ENDPOINT_XFER_ISOC)
  948. uhci_unlink_isochronous_tds(uhci, urb);
  949. uhci_unlink_qh(uhci, urbp->qh);
  950. done:
  951. spin_unlock_irqrestore(&uhci->lock, flags);
  952. return 0;
  953. }
  954. /*
  955. * Finish unlinking an URB and give it back
  956. */
  957. static void uhci_giveback_urb(struct uhci_hcd *uhci, struct uhci_qh *qh,
  958. struct urb *urb, struct pt_regs *regs)
  959. __releases(uhci->lock)
  960. __acquires(uhci->lock)
  961. {
  962. struct urb_priv *urbp = (struct urb_priv *) urb->hcpriv;
  963. /* Isochronous TDs get unlinked directly from the frame list */
  964. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  965. uhci_unlink_isochronous_tds(uhci, urb);
  966. /* Take the URB off the QH's queue. If the queue is now empty,
  967. * this is a perfect time for a toggle fixup. */
  968. list_del_init(&urbp->node);
  969. if (list_empty(&qh->queue) && qh->needs_fixup) {
  970. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
  971. usb_pipeout(urb->pipe), qh->initial_toggle);
  972. qh->needs_fixup = 0;
  973. }
  974. uhci_free_urb_priv(uhci, urbp);
  975. switch (qh->type) {
  976. case USB_ENDPOINT_XFER_ISOC:
  977. /* Release bandwidth for Interrupt or Isoc. transfers */
  978. if (urb->bandwidth)
  979. usb_release_bandwidth(urb->dev, urb, 1);
  980. break;
  981. case USB_ENDPOINT_XFER_INT:
  982. /* Release bandwidth for Interrupt or Isoc. transfers */
  983. /* Make sure we don't release if we have a queued URB */
  984. if (list_empty(&qh->queue) && urb->bandwidth)
  985. usb_release_bandwidth(urb->dev, urb, 0);
  986. else
  987. /* bandwidth was passed on to queued URB, */
  988. /* so don't let usb_unlink_urb() release it */
  989. urb->bandwidth = 0;
  990. break;
  991. }
  992. spin_unlock(&uhci->lock);
  993. usb_hcd_giveback_urb(uhci_to_hcd(uhci), urb, regs);
  994. spin_lock(&uhci->lock);
  995. /* If the queue is now empty, we can unlink the QH and give up its
  996. * reserved bandwidth. */
  997. if (list_empty(&qh->queue)) {
  998. uhci_unlink_qh(uhci, qh);
  999. /* Bandwidth stuff not yet implemented */
  1000. }
  1001. }
  1002. /*
  1003. * Scan the URBs in a QH's queue
  1004. */
  1005. #define QH_FINISHED_UNLINKING(qh) \
  1006. (qh->state == QH_STATE_UNLINKING && \
  1007. uhci->frame_number + uhci->is_stopped != qh->unlink_frame)
  1008. static void uhci_scan_qh(struct uhci_hcd *uhci, struct uhci_qh *qh,
  1009. struct pt_regs *regs)
  1010. {
  1011. struct urb_priv *urbp;
  1012. struct urb *urb;
  1013. int status;
  1014. while (!list_empty(&qh->queue)) {
  1015. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1016. urb = urbp->urb;
  1017. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1018. status = uhci_result_isochronous(uhci, urb);
  1019. else
  1020. status = uhci_result_common(uhci, urb);
  1021. if (status == -EINPROGRESS)
  1022. break;
  1023. spin_lock(&urb->lock);
  1024. if (urb->status == -EINPROGRESS) /* Not dequeued */
  1025. urb->status = status;
  1026. else
  1027. status = ECONNRESET; /* Not -ECONNRESET */
  1028. spin_unlock(&urb->lock);
  1029. /* Dequeued but completed URBs can't be given back unless
  1030. * the QH is stopped or has finished unlinking. */
  1031. if (status == ECONNRESET) {
  1032. if (QH_FINISHED_UNLINKING(qh))
  1033. qh->is_stopped = 1;
  1034. else if (!qh->is_stopped)
  1035. return;
  1036. }
  1037. uhci_giveback_urb(uhci, qh, urb, regs);
  1038. if (status < 0)
  1039. break;
  1040. }
  1041. /* If the QH is neither stopped nor finished unlinking (normal case),
  1042. * our work here is done. */
  1043. if (QH_FINISHED_UNLINKING(qh))
  1044. qh->is_stopped = 1;
  1045. else if (!qh->is_stopped)
  1046. return;
  1047. /* Otherwise give back each of the dequeued URBs */
  1048. restart:
  1049. list_for_each_entry(urbp, &qh->queue, node) {
  1050. urb = urbp->urb;
  1051. if (urb->status != -EINPROGRESS) {
  1052. uhci_cleanup_queue(qh, urb);
  1053. uhci_giveback_urb(uhci, qh, urb, regs);
  1054. goto restart;
  1055. }
  1056. }
  1057. qh->is_stopped = 0;
  1058. /* There are no more dequeued URBs. If there are still URBs on the
  1059. * queue, the QH can now be re-activated. */
  1060. if (!list_empty(&qh->queue)) {
  1061. if (qh->needs_fixup)
  1062. uhci_fixup_toggles(qh, 0);
  1063. /* If the first URB on the queue wants FSBR but its time
  1064. * limit has expired, set the next TD to interrupt on
  1065. * completion before reactivating the QH. */
  1066. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1067. if (urbp->fsbr && qh->wait_expired) {
  1068. struct uhci_td *td = list_entry(urbp->td_list.next,
  1069. struct uhci_td, list);
  1070. td->status |= __cpu_to_le32(TD_CTRL_IOC);
  1071. }
  1072. uhci_activate_qh(uhci, qh);
  1073. }
  1074. /* The queue is empty. The QH can become idle if it is fully
  1075. * unlinked. */
  1076. else if (QH_FINISHED_UNLINKING(qh))
  1077. uhci_make_qh_idle(uhci, qh);
  1078. }
  1079. /*
  1080. * Check for queues that have made some forward progress.
  1081. * Returns 0 if the queue is not Isochronous, is ACTIVE, and
  1082. * has not advanced since last examined; 1 otherwise.
  1083. */
  1084. static int uhci_advance_check(struct uhci_hcd *uhci, struct uhci_qh *qh)
  1085. {
  1086. struct urb_priv *urbp = NULL;
  1087. struct uhci_td *td;
  1088. int ret = 1;
  1089. unsigned status;
  1090. if (qh->type == USB_ENDPOINT_XFER_ISOC)
  1091. return ret;
  1092. /* Treat an UNLINKING queue as though it hasn't advanced.
  1093. * This is okay because reactivation will treat it as though
  1094. * it has advanced, and if it is going to become IDLE then
  1095. * this doesn't matter anyway. Furthermore it's possible
  1096. * for an UNLINKING queue not to have any URBs at all, or
  1097. * for its first URB not to have any TDs (if it was dequeued
  1098. * just as it completed). So it's not easy in any case to
  1099. * test whether such queues have advanced. */
  1100. if (qh->state != QH_STATE_ACTIVE) {
  1101. urbp = NULL;
  1102. status = 0;
  1103. } else {
  1104. urbp = list_entry(qh->queue.next, struct urb_priv, node);
  1105. td = list_entry(urbp->td_list.next, struct uhci_td, list);
  1106. status = td_status(td);
  1107. if (!(status & TD_CTRL_ACTIVE)) {
  1108. /* We're okay, the queue has advanced */
  1109. qh->wait_expired = 0;
  1110. qh->advance_jiffies = jiffies;
  1111. return ret;
  1112. }
  1113. ret = 0;
  1114. }
  1115. /* The queue hasn't advanced; check for timeout */
  1116. if (!qh->wait_expired && time_after(jiffies,
  1117. qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
  1118. qh->wait_expired = 1;
  1119. /* If the current URB wants FSBR, unlink it temporarily
  1120. * so that we can safely set the next TD to interrupt on
  1121. * completion. That way we'll know as soon as the queue
  1122. * starts moving again. */
  1123. if (urbp && urbp->fsbr && !(status & TD_CTRL_IOC))
  1124. uhci_unlink_qh(uhci, qh);
  1125. }
  1126. return ret;
  1127. }
  1128. /*
  1129. * Process events in the schedule, but only in one thread at a time
  1130. */
  1131. static void uhci_scan_schedule(struct uhci_hcd *uhci, struct pt_regs *regs)
  1132. {
  1133. int i;
  1134. struct uhci_qh *qh;
  1135. /* Don't allow re-entrant calls */
  1136. if (uhci->scan_in_progress) {
  1137. uhci->need_rescan = 1;
  1138. return;
  1139. }
  1140. uhci->scan_in_progress = 1;
  1141. rescan:
  1142. uhci->need_rescan = 0;
  1143. uhci_clear_next_interrupt(uhci);
  1144. uhci_get_current_frame_number(uhci);
  1145. /* Go through all the QH queues and process the URBs in each one */
  1146. for (i = 0; i < UHCI_NUM_SKELQH - 1; ++i) {
  1147. uhci->next_qh = list_entry(uhci->skelqh[i]->node.next,
  1148. struct uhci_qh, node);
  1149. while ((qh = uhci->next_qh) != uhci->skelqh[i]) {
  1150. uhci->next_qh = list_entry(qh->node.next,
  1151. struct uhci_qh, node);
  1152. if (uhci_advance_check(uhci, qh)) {
  1153. uhci_scan_qh(uhci, qh, regs);
  1154. if (qh->state == QH_STATE_ACTIVE)
  1155. uhci_qh_wants_fsbr(uhci, qh);
  1156. }
  1157. }
  1158. }
  1159. if (uhci->need_rescan)
  1160. goto rescan;
  1161. uhci->scan_in_progress = 0;
  1162. if (uhci->fsbr_is_on && time_after(jiffies,
  1163. uhci->fsbr_jiffies + FSBR_OFF_DELAY))
  1164. uhci_fsbr_off(uhci);
  1165. if (list_empty(&uhci->skel_unlink_qh->node))
  1166. uhci_clear_next_interrupt(uhci);
  1167. else
  1168. uhci_set_next_interrupt(uhci);
  1169. }