exynos5250.dtsi 14 KB

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  1. /*
  2. * SAMSUNG EXYNOS5250 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
  8. * EXYNOS5250 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13. * additional nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. /include/ "skeleton.dtsi"
  20. /include/ "exynos5250-pinctrl.dtsi"
  21. / {
  22. compatible = "samsung,exynos5250";
  23. interrupt-parent = <&gic>;
  24. aliases {
  25. spi0 = &spi_0;
  26. spi1 = &spi_1;
  27. spi2 = &spi_2;
  28. gsc0 = &gsc_0;
  29. gsc1 = &gsc_1;
  30. gsc2 = &gsc_2;
  31. gsc3 = &gsc_3;
  32. mshc0 = &dwmmc_0;
  33. mshc1 = &dwmmc_1;
  34. mshc2 = &dwmmc_2;
  35. mshc3 = &dwmmc_3;
  36. i2c0 = &i2c_0;
  37. i2c1 = &i2c_1;
  38. i2c2 = &i2c_2;
  39. i2c3 = &i2c_3;
  40. i2c4 = &i2c_4;
  41. i2c5 = &i2c_5;
  42. i2c6 = &i2c_6;
  43. i2c7 = &i2c_7;
  44. i2c8 = &i2c_8;
  45. pinctrl0 = &pinctrl_0;
  46. pinctrl1 = &pinctrl_1;
  47. pinctrl2 = &pinctrl_2;
  48. pinctrl3 = &pinctrl_3;
  49. };
  50. pd_gsc: gsc-power-domain@0x10044000 {
  51. compatible = "samsung,exynos4210-pd";
  52. reg = <0x10044000 0x20>;
  53. };
  54. pd_mfc: mfc-power-domain@0x10044040 {
  55. compatible = "samsung,exynos4210-pd";
  56. reg = <0x10044040 0x20>;
  57. };
  58. clock: clock-controller@0x10010000 {
  59. compatible = "samsung,exynos5250-clock";
  60. reg = <0x10010000 0x30000>;
  61. #clock-cells = <1>;
  62. };
  63. gic:interrupt-controller@10481000 {
  64. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  65. #interrupt-cells = <3>;
  66. interrupt-controller;
  67. reg = <0x10481000 0x1000>,
  68. <0x10482000 0x1000>,
  69. <0x10484000 0x2000>,
  70. <0x10486000 0x2000>;
  71. interrupts = <1 9 0xf04>;
  72. };
  73. combiner:interrupt-controller@10440000 {
  74. compatible = "samsung,exynos4210-combiner";
  75. #interrupt-cells = <2>;
  76. interrupt-controller;
  77. samsung,combiner-nr = <32>;
  78. reg = <0x10440000 0x1000>;
  79. interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  80. <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  81. <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  82. <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  83. <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  84. <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  85. <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  86. <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  87. };
  88. mct@101C0000 {
  89. compatible = "samsung,exynos4210-mct";
  90. reg = <0x101C0000 0x800>;
  91. interrupt-controller;
  92. #interrups-cells = <2>;
  93. interrupt-parent = <&mct_map>;
  94. interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
  95. <4 0>, <5 0>;
  96. clocks = <&clock 1>, <&clock 335>;
  97. clock-names = "fin_pll", "mct";
  98. mct_map: mct-map {
  99. #interrupt-cells = <2>;
  100. #address-cells = <0>;
  101. #size-cells = <0>;
  102. interrupt-map = <0x0 0 &combiner 23 3>,
  103. <0x1 0 &combiner 23 4>,
  104. <0x2 0 &combiner 25 2>,
  105. <0x3 0 &combiner 25 3>,
  106. <0x4 0 &gic 0 120 0>,
  107. <0x5 0 &gic 0 121 0>;
  108. };
  109. };
  110. pinctrl_0: pinctrl@11400000 {
  111. compatible = "samsung,exynos5250-pinctrl";
  112. reg = <0x11400000 0x1000>;
  113. interrupts = <0 46 0>;
  114. wakup_eint: wakeup-interrupt-controller {
  115. compatible = "samsung,exynos4210-wakeup-eint";
  116. interrupt-parent = <&gic>;
  117. interrupts = <0 32 0>;
  118. };
  119. };
  120. pinctrl_1: pinctrl@13400000 {
  121. compatible = "samsung,exynos5250-pinctrl";
  122. reg = <0x13400000 0x1000>;
  123. interrupts = <0 45 0>;
  124. };
  125. pinctrl_2: pinctrl@10d10000 {
  126. compatible = "samsung,exynos5250-pinctrl";
  127. reg = <0x10d10000 0x1000>;
  128. interrupts = <0 50 0>;
  129. };
  130. pinctrl_3: pinctrl@03680000 {
  131. compatible = "samsung,exynos5250-pinctrl";
  132. reg = <0x0368000 0x1000>;
  133. interrupts = <0 47 0>;
  134. };
  135. watchdog {
  136. compatible = "samsung,s3c2410-wdt";
  137. reg = <0x101D0000 0x100>;
  138. interrupts = <0 42 0>;
  139. clocks = <&clock 336>;
  140. clock-names = "watchdog";
  141. };
  142. codec@11000000 {
  143. compatible = "samsung,mfc-v6";
  144. reg = <0x11000000 0x10000>;
  145. interrupts = <0 96 0>;
  146. samsung,power-domain = <&pd_mfc>;
  147. };
  148. rtc {
  149. compatible = "samsung,s3c6410-rtc";
  150. reg = <0x101E0000 0x100>;
  151. interrupts = <0 43 0>, <0 44 0>;
  152. clocks = <&clock 337>;
  153. clock-names = "rtc";
  154. };
  155. tmu@10060000 {
  156. compatible = "samsung,exynos5250-tmu";
  157. reg = <0x10060000 0x100>;
  158. interrupts = <0 65 0>;
  159. clocks = <&clock 338>;
  160. clock-names = "tmu_apbif";
  161. };
  162. serial@12C00000 {
  163. compatible = "samsung,exynos4210-uart";
  164. reg = <0x12C00000 0x100>;
  165. interrupts = <0 51 0>;
  166. clocks = <&clock 289>, <&clock 146>;
  167. clock-names = "uart", "clk_uart_baud0";
  168. };
  169. serial@12C10000 {
  170. compatible = "samsung,exynos4210-uart";
  171. reg = <0x12C10000 0x100>;
  172. interrupts = <0 52 0>;
  173. clocks = <&clock 290>, <&clock 147>;
  174. clock-names = "uart", "clk_uart_baud0";
  175. };
  176. serial@12C20000 {
  177. compatible = "samsung,exynos4210-uart";
  178. reg = <0x12C20000 0x100>;
  179. interrupts = <0 53 0>;
  180. clocks = <&clock 291>, <&clock 148>;
  181. clock-names = "uart", "clk_uart_baud0";
  182. };
  183. serial@12C30000 {
  184. compatible = "samsung,exynos4210-uart";
  185. reg = <0x12C30000 0x100>;
  186. interrupts = <0 54 0>;
  187. clocks = <&clock 292>, <&clock 149>;
  188. clock-names = "uart", "clk_uart_baud0";
  189. };
  190. sata@122F0000 {
  191. compatible = "samsung,exynos5-sata-ahci";
  192. reg = <0x122F0000 0x1ff>;
  193. interrupts = <0 115 0>;
  194. clocks = <&clock 277>, <&clock 143>;
  195. clock-names = "sata", "sclk_sata";
  196. };
  197. sata-phy@12170000 {
  198. compatible = "samsung,exynos5-sata-phy";
  199. reg = <0x12170000 0x1ff>;
  200. };
  201. i2c_0: i2c@12C60000 {
  202. compatible = "samsung,s3c2440-i2c";
  203. reg = <0x12C60000 0x100>;
  204. interrupts = <0 56 0>;
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. clocks = <&clock 294>;
  208. clock-names = "i2c";
  209. pinctrl-names = "default";
  210. pinctrl-0 = <&i2c0_bus>;
  211. };
  212. i2c_1: i2c@12C70000 {
  213. compatible = "samsung,s3c2440-i2c";
  214. reg = <0x12C70000 0x100>;
  215. interrupts = <0 57 0>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. clocks = <&clock 295>;
  219. clock-names = "i2c";
  220. pinctrl-names = "default";
  221. pinctrl-0 = <&i2c1_bus>;
  222. };
  223. i2c_2: i2c@12C80000 {
  224. compatible = "samsung,s3c2440-i2c";
  225. reg = <0x12C80000 0x100>;
  226. interrupts = <0 58 0>;
  227. #address-cells = <1>;
  228. #size-cells = <0>;
  229. clocks = <&clock 296>;
  230. clock-names = "i2c";
  231. pinctrl-names = "default";
  232. pinctrl-0 = <&i2c2_bus>;
  233. };
  234. i2c_3: i2c@12C90000 {
  235. compatible = "samsung,s3c2440-i2c";
  236. reg = <0x12C90000 0x100>;
  237. interrupts = <0 59 0>;
  238. #address-cells = <1>;
  239. #size-cells = <0>;
  240. clocks = <&clock 297>;
  241. clock-names = "i2c";
  242. pinctrl-names = "default";
  243. pinctrl-0 = <&i2c3_bus>;
  244. };
  245. i2c_4: i2c@12CA0000 {
  246. compatible = "samsung,s3c2440-i2c";
  247. reg = <0x12CA0000 0x100>;
  248. interrupts = <0 60 0>;
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251. clocks = <&clock 298>;
  252. clock-names = "i2c";
  253. pinctrl-names = "default";
  254. pinctrl-0 = <&i2c4_bus>;
  255. };
  256. i2c_5: i2c@12CB0000 {
  257. compatible = "samsung,s3c2440-i2c";
  258. reg = <0x12CB0000 0x100>;
  259. interrupts = <0 61 0>;
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. clocks = <&clock 299>;
  263. clock-names = "i2c";
  264. pinctrl-names = "default";
  265. pinctrl-0 = <&i2c5_bus>;
  266. };
  267. i2c_6: i2c@12CC0000 {
  268. compatible = "samsung,s3c2440-i2c";
  269. reg = <0x12CC0000 0x100>;
  270. interrupts = <0 62 0>;
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. clocks = <&clock 300>;
  274. clock-names = "i2c";
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&i2c6_bus>;
  277. };
  278. i2c_7: i2c@12CD0000 {
  279. compatible = "samsung,s3c2440-i2c";
  280. reg = <0x12CD0000 0x100>;
  281. interrupts = <0 63 0>;
  282. #address-cells = <1>;
  283. #size-cells = <0>;
  284. clocks = <&clock 301>;
  285. clock-names = "i2c";
  286. pinctrl-names = "default";
  287. pinctrl-0 = <&i2c7_bus>;
  288. };
  289. i2c_8: i2c@12CE0000 {
  290. compatible = "samsung,s3c2440-hdmiphy-i2c";
  291. reg = <0x12CE0000 0x1000>;
  292. interrupts = <0 64 0>;
  293. #address-cells = <1>;
  294. #size-cells = <0>;
  295. clocks = <&clock 302>;
  296. clock-names = "i2c";
  297. };
  298. i2c@121D0000 {
  299. compatible = "samsung,exynos5-sata-phy-i2c";
  300. reg = <0x121D0000 0x100>;
  301. #address-cells = <1>;
  302. #size-cells = <0>;
  303. clocks = <&clock 288>;
  304. clock-names = "i2c";
  305. };
  306. spi_0: spi@12d20000 {
  307. compatible = "samsung,exynos4210-spi";
  308. reg = <0x12d20000 0x100>;
  309. interrupts = <0 66 0>;
  310. dmas = <&pdma0 5
  311. &pdma0 4>;
  312. dma-names = "tx", "rx";
  313. #address-cells = <1>;
  314. #size-cells = <0>;
  315. clocks = <&clock 304>, <&clock 154>;
  316. clock-names = "spi", "spi_busclk0";
  317. pinctrl-names = "default";
  318. pinctrl-0 = <&spi0_bus>;
  319. };
  320. spi_1: spi@12d30000 {
  321. compatible = "samsung,exynos4210-spi";
  322. reg = <0x12d30000 0x100>;
  323. interrupts = <0 67 0>;
  324. dmas = <&pdma1 5
  325. &pdma1 4>;
  326. dma-names = "tx", "rx";
  327. #address-cells = <1>;
  328. #size-cells = <0>;
  329. clocks = <&clock 305>, <&clock 155>;
  330. clock-names = "spi", "spi_busclk0";
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&spi1_bus>;
  333. };
  334. spi_2: spi@12d40000 {
  335. compatible = "samsung,exynos4210-spi";
  336. reg = <0x12d40000 0x100>;
  337. interrupts = <0 68 0>;
  338. dmas = <&pdma0 7
  339. &pdma0 6>;
  340. dma-names = "tx", "rx";
  341. #address-cells = <1>;
  342. #size-cells = <0>;
  343. clocks = <&clock 306>, <&clock 156>;
  344. clock-names = "spi", "spi_busclk0";
  345. pinctrl-names = "default";
  346. pinctrl-0 = <&spi2_bus>;
  347. };
  348. dwmmc_0: dwmmc0@12200000 {
  349. compatible = "samsung,exynos5250-dw-mshc";
  350. reg = <0x12200000 0x1000>;
  351. interrupts = <0 75 0>;
  352. #address-cells = <1>;
  353. #size-cells = <0>;
  354. clocks = <&clock 280>, <&clock 139>;
  355. clock-names = "biu", "ciu";
  356. };
  357. dwmmc_1: dwmmc1@12210000 {
  358. compatible = "samsung,exynos5250-dw-mshc";
  359. reg = <0x12210000 0x1000>;
  360. interrupts = <0 76 0>;
  361. #address-cells = <1>;
  362. #size-cells = <0>;
  363. clocks = <&clock 281>, <&clock 140>;
  364. clock-names = "biu", "ciu";
  365. };
  366. dwmmc_2: dwmmc2@12220000 {
  367. compatible = "samsung,exynos5250-dw-mshc";
  368. reg = <0x12220000 0x1000>;
  369. interrupts = <0 77 0>;
  370. #address-cells = <1>;
  371. #size-cells = <0>;
  372. clocks = <&clock 282>, <&clock 141>;
  373. clock-names = "biu", "ciu";
  374. };
  375. dwmmc_3: dwmmc3@12230000 {
  376. compatible = "samsung,exynos5250-dw-mshc";
  377. reg = <0x12230000 0x1000>;
  378. interrupts = <0 78 0>;
  379. #address-cells = <1>;
  380. #size-cells = <0>;
  381. clocks = <&clock 283>, <&clock 142>;
  382. clock-names = "biu", "ciu";
  383. };
  384. i2s0: i2s@03830000 {
  385. compatible = "samsung,i2s-v5";
  386. reg = <0x03830000 0x100>;
  387. dmas = <&pdma0 10
  388. &pdma0 9
  389. &pdma0 8>;
  390. dma-names = "tx", "rx", "tx-sec";
  391. samsung,supports-6ch;
  392. samsung,supports-rstclr;
  393. samsung,supports-secdai;
  394. samsung,idma-addr = <0x03000000>;
  395. pinctrl-names = "default";
  396. pinctrl-0 = <&i2s0_bus>;
  397. };
  398. i2s1: i2s@12D60000 {
  399. compatible = "samsung,i2s-v5";
  400. reg = <0x12D60000 0x100>;
  401. dmas = <&pdma1 12
  402. &pdma1 11>;
  403. dma-names = "tx", "rx";
  404. pinctrl-names = "default";
  405. pinctrl-0 = <&i2s1_bus>;
  406. };
  407. i2s2: i2s@12D70000 {
  408. compatible = "samsung,i2s-v5";
  409. reg = <0x12D70000 0x100>;
  410. dmas = <&pdma0 12
  411. &pdma0 11>;
  412. dma-names = "tx", "rx";
  413. pinctrl-names = "default";
  414. pinctrl-0 = <&i2s2_bus>;
  415. };
  416. usb@12110000 {
  417. compatible = "samsung,exynos4210-ehci";
  418. reg = <0x12110000 0x100>;
  419. interrupts = <0 71 0>;
  420. };
  421. usb@12120000 {
  422. compatible = "samsung,exynos4210-ohci";
  423. reg = <0x12120000 0x100>;
  424. interrupts = <0 71 0>;
  425. };
  426. amba {
  427. #address-cells = <1>;
  428. #size-cells = <1>;
  429. compatible = "arm,amba-bus";
  430. interrupt-parent = <&gic>;
  431. ranges;
  432. pdma0: pdma@121A0000 {
  433. compatible = "arm,pl330", "arm,primecell";
  434. reg = <0x121A0000 0x1000>;
  435. interrupts = <0 34 0>;
  436. clocks = <&clock 275>;
  437. clock-names = "apb_pclk";
  438. #dma-cells = <1>;
  439. #dma-channels = <8>;
  440. #dma-requests = <32>;
  441. };
  442. pdma1: pdma@121B0000 {
  443. compatible = "arm,pl330", "arm,primecell";
  444. reg = <0x121B0000 0x1000>;
  445. interrupts = <0 35 0>;
  446. clocks = <&clock 276>;
  447. clock-names = "apb_pclk";
  448. #dma-cells = <1>;
  449. #dma-channels = <8>;
  450. #dma-requests = <32>;
  451. };
  452. mdma0: mdma@10800000 {
  453. compatible = "arm,pl330", "arm,primecell";
  454. reg = <0x10800000 0x1000>;
  455. interrupts = <0 33 0>;
  456. clocks = <&clock 271>;
  457. clock-names = "apb_pclk";
  458. #dma-cells = <1>;
  459. #dma-channels = <8>;
  460. #dma-requests = <1>;
  461. };
  462. mdma1: mdma@11C10000 {
  463. compatible = "arm,pl330", "arm,primecell";
  464. reg = <0x11C10000 0x1000>;
  465. interrupts = <0 124 0>;
  466. clocks = <&clock 271>;
  467. clock-names = "apb_pclk";
  468. #dma-cells = <1>;
  469. #dma-channels = <8>;
  470. #dma-requests = <1>;
  471. };
  472. };
  473. gsc_0: gsc@0x13e00000 {
  474. compatible = "samsung,exynos5-gsc";
  475. reg = <0x13e00000 0x1000>;
  476. interrupts = <0 85 0>;
  477. samsung,power-domain = <&pd_gsc>;
  478. clocks = <&clock 256>;
  479. clock-names = "gscl";
  480. };
  481. gsc_1: gsc@0x13e10000 {
  482. compatible = "samsung,exynos5-gsc";
  483. reg = <0x13e10000 0x1000>;
  484. interrupts = <0 86 0>;
  485. samsung,power-domain = <&pd_gsc>;
  486. clocks = <&clock 257>;
  487. clock-names = "gscl";
  488. };
  489. gsc_2: gsc@0x13e20000 {
  490. compatible = "samsung,exynos5-gsc";
  491. reg = <0x13e20000 0x1000>;
  492. interrupts = <0 87 0>;
  493. samsung,power-domain = <&pd_gsc>;
  494. clocks = <&clock 258>;
  495. clock-names = "gscl";
  496. };
  497. gsc_3: gsc@0x13e30000 {
  498. compatible = "samsung,exynos5-gsc";
  499. reg = <0x13e30000 0x1000>;
  500. interrupts = <0 88 0>;
  501. samsung,power-domain = <&pd_gsc>;
  502. clocks = <&clock 259>;
  503. clock-names = "gscl";
  504. };
  505. hdmi {
  506. compatible = "samsung,exynos5-hdmi";
  507. reg = <0x14530000 0x70000>;
  508. interrupts = <0 95 0>;
  509. clocks = <&clock 333>, <&clock 136>, <&clock 137>,
  510. <&clock 333>, <&clock 333>;
  511. clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
  512. "sclk_hdmiphy", "hdmiphy";
  513. };
  514. mixer {
  515. compatible = "samsung,exynos5-mixer";
  516. reg = <0x14450000 0x10000>;
  517. interrupts = <0 94 0>;
  518. };
  519. dp-controller {
  520. compatible = "samsung,exynos5-dp";
  521. reg = <0x145b0000 0x1000>;
  522. interrupts = <10 3>;
  523. interrupt-parent = <&combiner>;
  524. #address-cells = <1>;
  525. #size-cells = <0>;
  526. dptx-phy {
  527. reg = <0x10040720>;
  528. samsung,enable-mask = <1>;
  529. };
  530. };
  531. };