qeth_core_main.c 131 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_MSG] = {"qeth_msg",
  33. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  34. [QETH_DBF_SENSE] = {"qeth_sense",
  35. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  36. [QETH_DBF_MISC] = {"qeth_misc",
  37. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_CTRL] = {"qeth_control",
  39. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  40. };
  41. EXPORT_SYMBOL_GPL(qeth_dbf);
  42. struct qeth_card_list_struct qeth_core_card_list;
  43. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  44. struct kmem_cache *qeth_core_header_cache;
  45. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  46. static struct device *qeth_core_root_dev;
  47. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  48. static struct lock_class_key qdio_out_skb_queue_key;
  49. static void qeth_send_control_data_cb(struct qeth_channel *,
  50. struct qeth_cmd_buffer *);
  51. static int qeth_issue_next_read(struct qeth_card *);
  52. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  53. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  54. static void qeth_free_buffer_pool(struct qeth_card *);
  55. static int qeth_qdio_establish(struct qeth_card *);
  56. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  57. struct qdio_buffer *buffer, int is_tso,
  58. int *next_element_to_fill)
  59. {
  60. struct skb_frag_struct *frag;
  61. int fragno;
  62. unsigned long addr;
  63. int element, cnt, dlen;
  64. fragno = skb_shinfo(skb)->nr_frags;
  65. element = *next_element_to_fill;
  66. dlen = 0;
  67. if (is_tso)
  68. buffer->element[element].flags =
  69. SBAL_FLAGS_MIDDLE_FRAG;
  70. else
  71. buffer->element[element].flags =
  72. SBAL_FLAGS_FIRST_FRAG;
  73. dlen = skb->len - skb->data_len;
  74. if (dlen) {
  75. buffer->element[element].addr = skb->data;
  76. buffer->element[element].length = dlen;
  77. element++;
  78. }
  79. for (cnt = 0; cnt < fragno; cnt++) {
  80. frag = &skb_shinfo(skb)->frags[cnt];
  81. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  82. frag->page_offset;
  83. buffer->element[element].addr = (char *)addr;
  84. buffer->element[element].length = frag->size;
  85. if (cnt < (fragno - 1))
  86. buffer->element[element].flags =
  87. SBAL_FLAGS_MIDDLE_FRAG;
  88. else
  89. buffer->element[element].flags =
  90. SBAL_FLAGS_LAST_FRAG;
  91. element++;
  92. }
  93. *next_element_to_fill = element;
  94. }
  95. static inline const char *qeth_get_cardname(struct qeth_card *card)
  96. {
  97. if (card->info.guestlan) {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSD:
  100. return " Guest LAN QDIO";
  101. case QETH_CARD_TYPE_IQD:
  102. return " Guest LAN Hiper";
  103. case QETH_CARD_TYPE_OSM:
  104. return " Guest LAN QDIO - OSM";
  105. case QETH_CARD_TYPE_OSX:
  106. return " Guest LAN QDIO - OSX";
  107. default:
  108. return " unknown";
  109. }
  110. } else {
  111. switch (card->info.type) {
  112. case QETH_CARD_TYPE_OSD:
  113. return " OSD Express";
  114. case QETH_CARD_TYPE_IQD:
  115. return " HiperSockets";
  116. case QETH_CARD_TYPE_OSN:
  117. return " OSN QDIO";
  118. case QETH_CARD_TYPE_OSM:
  119. return " OSM QDIO";
  120. case QETH_CARD_TYPE_OSX:
  121. return " OSX QDIO";
  122. default:
  123. return " unknown";
  124. }
  125. }
  126. return " n/a";
  127. }
  128. /* max length to be returned: 14 */
  129. const char *qeth_get_cardname_short(struct qeth_card *card)
  130. {
  131. if (card->info.guestlan) {
  132. switch (card->info.type) {
  133. case QETH_CARD_TYPE_OSD:
  134. return "GuestLAN QDIO";
  135. case QETH_CARD_TYPE_IQD:
  136. return "GuestLAN Hiper";
  137. case QETH_CARD_TYPE_OSM:
  138. return "GuestLAN OSM";
  139. case QETH_CARD_TYPE_OSX:
  140. return "GuestLAN OSX";
  141. default:
  142. return "unknown";
  143. }
  144. } else {
  145. switch (card->info.type) {
  146. case QETH_CARD_TYPE_OSD:
  147. switch (card->info.link_type) {
  148. case QETH_LINK_TYPE_FAST_ETH:
  149. return "OSD_100";
  150. case QETH_LINK_TYPE_HSTR:
  151. return "HSTR";
  152. case QETH_LINK_TYPE_GBIT_ETH:
  153. return "OSD_1000";
  154. case QETH_LINK_TYPE_10GBIT_ETH:
  155. return "OSD_10GIG";
  156. case QETH_LINK_TYPE_LANE_ETH100:
  157. return "OSD_FE_LANE";
  158. case QETH_LINK_TYPE_LANE_TR:
  159. return "OSD_TR_LANE";
  160. case QETH_LINK_TYPE_LANE_ETH1000:
  161. return "OSD_GbE_LANE";
  162. case QETH_LINK_TYPE_LANE:
  163. return "OSD_ATM_LANE";
  164. default:
  165. return "OSD_Express";
  166. }
  167. case QETH_CARD_TYPE_IQD:
  168. return "HiperSockets";
  169. case QETH_CARD_TYPE_OSN:
  170. return "OSN";
  171. case QETH_CARD_TYPE_OSM:
  172. return "OSM_1000";
  173. case QETH_CARD_TYPE_OSX:
  174. return "OSX_10GIG";
  175. default:
  176. return "unknown";
  177. }
  178. }
  179. return "n/a";
  180. }
  181. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  182. int clear_start_mask)
  183. {
  184. unsigned long flags;
  185. spin_lock_irqsave(&card->thread_mask_lock, flags);
  186. card->thread_allowed_mask = threads;
  187. if (clear_start_mask)
  188. card->thread_start_mask &= threads;
  189. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  190. wake_up(&card->wait_q);
  191. }
  192. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  193. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  194. {
  195. unsigned long flags;
  196. int rc = 0;
  197. spin_lock_irqsave(&card->thread_mask_lock, flags);
  198. rc = (card->thread_running_mask & threads);
  199. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  200. return rc;
  201. }
  202. EXPORT_SYMBOL_GPL(qeth_threads_running);
  203. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  204. {
  205. return wait_event_interruptible(card->wait_q,
  206. qeth_threads_running(card, threads) == 0);
  207. }
  208. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  209. void qeth_clear_working_pool_list(struct qeth_card *card)
  210. {
  211. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  212. QETH_CARD_TEXT(card, 5, "clwrklst");
  213. list_for_each_entry_safe(pool_entry, tmp,
  214. &card->qdio.in_buf_pool.entry_list, list){
  215. list_del(&pool_entry->list);
  216. }
  217. }
  218. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  219. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  220. {
  221. struct qeth_buffer_pool_entry *pool_entry;
  222. void *ptr;
  223. int i, j;
  224. QETH_CARD_TEXT(card, 5, "alocpool");
  225. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  226. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  227. if (!pool_entry) {
  228. qeth_free_buffer_pool(card);
  229. return -ENOMEM;
  230. }
  231. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  232. ptr = (void *) __get_free_page(GFP_KERNEL);
  233. if (!ptr) {
  234. while (j > 0)
  235. free_page((unsigned long)
  236. pool_entry->elements[--j]);
  237. kfree(pool_entry);
  238. qeth_free_buffer_pool(card);
  239. return -ENOMEM;
  240. }
  241. pool_entry->elements[j] = ptr;
  242. }
  243. list_add(&pool_entry->init_list,
  244. &card->qdio.init_pool.entry_list);
  245. }
  246. return 0;
  247. }
  248. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  249. {
  250. QETH_CARD_TEXT(card, 2, "realcbp");
  251. if ((card->state != CARD_STATE_DOWN) &&
  252. (card->state != CARD_STATE_RECOVER))
  253. return -EPERM;
  254. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  255. qeth_clear_working_pool_list(card);
  256. qeth_free_buffer_pool(card);
  257. card->qdio.in_buf_pool.buf_count = bufcnt;
  258. card->qdio.init_pool.buf_count = bufcnt;
  259. return qeth_alloc_buffer_pool(card);
  260. }
  261. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  262. static int qeth_issue_next_read(struct qeth_card *card)
  263. {
  264. int rc;
  265. struct qeth_cmd_buffer *iob;
  266. QETH_CARD_TEXT(card, 5, "issnxrd");
  267. if (card->read.state != CH_STATE_UP)
  268. return -EIO;
  269. iob = qeth_get_buffer(&card->read);
  270. if (!iob) {
  271. dev_warn(&card->gdev->dev, "The qeth device driver "
  272. "failed to recover an error on the device\n");
  273. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  274. "available\n", dev_name(&card->gdev->dev));
  275. return -ENOMEM;
  276. }
  277. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  278. QETH_CARD_TEXT(card, 6, "noirqpnd");
  279. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  280. (addr_t) iob, 0, 0);
  281. if (rc) {
  282. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  283. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  284. atomic_set(&card->read.irq_pending, 0);
  285. qeth_schedule_recovery(card);
  286. wake_up(&card->wait_q);
  287. }
  288. return rc;
  289. }
  290. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  291. {
  292. struct qeth_reply *reply;
  293. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  294. if (reply) {
  295. atomic_set(&reply->refcnt, 1);
  296. atomic_set(&reply->received, 0);
  297. reply->card = card;
  298. };
  299. return reply;
  300. }
  301. static void qeth_get_reply(struct qeth_reply *reply)
  302. {
  303. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  304. atomic_inc(&reply->refcnt);
  305. }
  306. static void qeth_put_reply(struct qeth_reply *reply)
  307. {
  308. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  309. if (atomic_dec_and_test(&reply->refcnt))
  310. kfree(reply);
  311. }
  312. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  313. struct qeth_card *card)
  314. {
  315. char *ipa_name;
  316. int com = cmd->hdr.command;
  317. ipa_name = qeth_get_ipa_cmd_name(com);
  318. if (rc)
  319. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  320. ipa_name, com, QETH_CARD_IFNAME(card),
  321. rc, qeth_get_ipa_msg(rc));
  322. else
  323. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  324. ipa_name, com, QETH_CARD_IFNAME(card));
  325. }
  326. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  327. struct qeth_cmd_buffer *iob)
  328. {
  329. struct qeth_ipa_cmd *cmd = NULL;
  330. QETH_CARD_TEXT(card, 5, "chkipad");
  331. if (IS_IPA(iob->data)) {
  332. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  333. if (IS_IPA_REPLY(cmd)) {
  334. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  335. cmd->hdr.command != IPA_CMD_DELCCID &&
  336. cmd->hdr.command != IPA_CMD_MODCCID &&
  337. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  338. qeth_issue_ipa_msg(cmd,
  339. cmd->hdr.return_code, card);
  340. return cmd;
  341. } else {
  342. switch (cmd->hdr.command) {
  343. case IPA_CMD_STOPLAN:
  344. dev_warn(&card->gdev->dev,
  345. "The link for interface %s on CHPID"
  346. " 0x%X failed\n",
  347. QETH_CARD_IFNAME(card),
  348. card->info.chpid);
  349. card->lan_online = 0;
  350. if (card->dev && netif_carrier_ok(card->dev))
  351. netif_carrier_off(card->dev);
  352. return NULL;
  353. case IPA_CMD_STARTLAN:
  354. dev_info(&card->gdev->dev,
  355. "The link for %s on CHPID 0x%X has"
  356. " been restored\n",
  357. QETH_CARD_IFNAME(card),
  358. card->info.chpid);
  359. netif_carrier_on(card->dev);
  360. card->lan_online = 1;
  361. qeth_schedule_recovery(card);
  362. return NULL;
  363. case IPA_CMD_MODCCID:
  364. return cmd;
  365. case IPA_CMD_REGISTER_LOCAL_ADDR:
  366. QETH_CARD_TEXT(card, 3, "irla");
  367. break;
  368. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  369. QETH_CARD_TEXT(card, 3, "urla");
  370. break;
  371. default:
  372. QETH_DBF_MESSAGE(2, "Received data is IPA "
  373. "but not a reply!\n");
  374. break;
  375. }
  376. }
  377. }
  378. return cmd;
  379. }
  380. void qeth_clear_ipacmd_list(struct qeth_card *card)
  381. {
  382. struct qeth_reply *reply, *r;
  383. unsigned long flags;
  384. QETH_CARD_TEXT(card, 4, "clipalst");
  385. spin_lock_irqsave(&card->lock, flags);
  386. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  387. qeth_get_reply(reply);
  388. reply->rc = -EIO;
  389. atomic_inc(&reply->received);
  390. list_del_init(&reply->list);
  391. wake_up(&reply->wait_q);
  392. qeth_put_reply(reply);
  393. }
  394. spin_unlock_irqrestore(&card->lock, flags);
  395. }
  396. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  397. static int qeth_check_idx_response(struct qeth_card *card,
  398. unsigned char *buffer)
  399. {
  400. if (!buffer)
  401. return 0;
  402. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  403. if ((buffer[2] & 0xc0) == 0xc0) {
  404. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  405. "with cause code 0x%02x%s\n",
  406. buffer[4],
  407. ((buffer[4] == 0x22) ?
  408. " -- try another portname" : ""));
  409. QETH_CARD_TEXT(card, 2, "ckidxres");
  410. QETH_CARD_TEXT(card, 2, " idxterm");
  411. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  412. if (buffer[4] == 0xf6) {
  413. dev_err(&card->gdev->dev,
  414. "The qeth device is not configured "
  415. "for the OSI layer required by z/VM\n");
  416. return -EPERM;
  417. }
  418. return -EIO;
  419. }
  420. return 0;
  421. }
  422. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  423. __u32 len)
  424. {
  425. struct qeth_card *card;
  426. card = CARD_FROM_CDEV(channel->ccwdev);
  427. QETH_CARD_TEXT(card, 4, "setupccw");
  428. if (channel == &card->read)
  429. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  430. else
  431. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  432. channel->ccw.count = len;
  433. channel->ccw.cda = (__u32) __pa(iob);
  434. }
  435. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  436. {
  437. __u8 index;
  438. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  439. index = channel->io_buf_no;
  440. do {
  441. if (channel->iob[index].state == BUF_STATE_FREE) {
  442. channel->iob[index].state = BUF_STATE_LOCKED;
  443. channel->io_buf_no = (channel->io_buf_no + 1) %
  444. QETH_CMD_BUFFER_NO;
  445. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  446. return channel->iob + index;
  447. }
  448. index = (index + 1) % QETH_CMD_BUFFER_NO;
  449. } while (index != channel->io_buf_no);
  450. return NULL;
  451. }
  452. void qeth_release_buffer(struct qeth_channel *channel,
  453. struct qeth_cmd_buffer *iob)
  454. {
  455. unsigned long flags;
  456. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  457. spin_lock_irqsave(&channel->iob_lock, flags);
  458. memset(iob->data, 0, QETH_BUFSIZE);
  459. iob->state = BUF_STATE_FREE;
  460. iob->callback = qeth_send_control_data_cb;
  461. iob->rc = 0;
  462. spin_unlock_irqrestore(&channel->iob_lock, flags);
  463. }
  464. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  465. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  466. {
  467. struct qeth_cmd_buffer *buffer = NULL;
  468. unsigned long flags;
  469. spin_lock_irqsave(&channel->iob_lock, flags);
  470. buffer = __qeth_get_buffer(channel);
  471. spin_unlock_irqrestore(&channel->iob_lock, flags);
  472. return buffer;
  473. }
  474. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  475. {
  476. struct qeth_cmd_buffer *buffer;
  477. wait_event(channel->wait_q,
  478. ((buffer = qeth_get_buffer(channel)) != NULL));
  479. return buffer;
  480. }
  481. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  482. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  483. {
  484. int cnt;
  485. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  486. qeth_release_buffer(channel, &channel->iob[cnt]);
  487. channel->buf_no = 0;
  488. channel->io_buf_no = 0;
  489. }
  490. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  491. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  492. struct qeth_cmd_buffer *iob)
  493. {
  494. struct qeth_card *card;
  495. struct qeth_reply *reply, *r;
  496. struct qeth_ipa_cmd *cmd;
  497. unsigned long flags;
  498. int keep_reply;
  499. int rc = 0;
  500. card = CARD_FROM_CDEV(channel->ccwdev);
  501. QETH_CARD_TEXT(card, 4, "sndctlcb");
  502. rc = qeth_check_idx_response(card, iob->data);
  503. switch (rc) {
  504. case 0:
  505. break;
  506. case -EIO:
  507. qeth_clear_ipacmd_list(card);
  508. qeth_schedule_recovery(card);
  509. default:
  510. goto out;
  511. }
  512. cmd = qeth_check_ipa_data(card, iob);
  513. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  514. goto out;
  515. /*in case of OSN : check if cmd is set */
  516. if (card->info.type == QETH_CARD_TYPE_OSN &&
  517. cmd &&
  518. cmd->hdr.command != IPA_CMD_STARTLAN &&
  519. card->osn_info.assist_cb != NULL) {
  520. card->osn_info.assist_cb(card->dev, cmd);
  521. goto out;
  522. }
  523. spin_lock_irqsave(&card->lock, flags);
  524. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  525. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  526. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  527. qeth_get_reply(reply);
  528. list_del_init(&reply->list);
  529. spin_unlock_irqrestore(&card->lock, flags);
  530. keep_reply = 0;
  531. if (reply->callback != NULL) {
  532. if (cmd) {
  533. reply->offset = (__u16)((char *)cmd -
  534. (char *)iob->data);
  535. keep_reply = reply->callback(card,
  536. reply,
  537. (unsigned long)cmd);
  538. } else
  539. keep_reply = reply->callback(card,
  540. reply,
  541. (unsigned long)iob);
  542. }
  543. if (cmd)
  544. reply->rc = (u16) cmd->hdr.return_code;
  545. else if (iob->rc)
  546. reply->rc = iob->rc;
  547. if (keep_reply) {
  548. spin_lock_irqsave(&card->lock, flags);
  549. list_add_tail(&reply->list,
  550. &card->cmd_waiter_list);
  551. spin_unlock_irqrestore(&card->lock, flags);
  552. } else {
  553. atomic_inc(&reply->received);
  554. wake_up(&reply->wait_q);
  555. }
  556. qeth_put_reply(reply);
  557. goto out;
  558. }
  559. }
  560. spin_unlock_irqrestore(&card->lock, flags);
  561. out:
  562. memcpy(&card->seqno.pdu_hdr_ack,
  563. QETH_PDU_HEADER_SEQ_NO(iob->data),
  564. QETH_SEQ_NO_LENGTH);
  565. qeth_release_buffer(channel, iob);
  566. }
  567. static int qeth_setup_channel(struct qeth_channel *channel)
  568. {
  569. int cnt;
  570. QETH_DBF_TEXT(SETUP, 2, "setupch");
  571. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  572. channel->iob[cnt].data =
  573. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  574. if (channel->iob[cnt].data == NULL)
  575. break;
  576. channel->iob[cnt].state = BUF_STATE_FREE;
  577. channel->iob[cnt].channel = channel;
  578. channel->iob[cnt].callback = qeth_send_control_data_cb;
  579. channel->iob[cnt].rc = 0;
  580. }
  581. if (cnt < QETH_CMD_BUFFER_NO) {
  582. while (cnt-- > 0)
  583. kfree(channel->iob[cnt].data);
  584. return -ENOMEM;
  585. }
  586. channel->buf_no = 0;
  587. channel->io_buf_no = 0;
  588. atomic_set(&channel->irq_pending, 0);
  589. spin_lock_init(&channel->iob_lock);
  590. init_waitqueue_head(&channel->wait_q);
  591. return 0;
  592. }
  593. static int qeth_set_thread_start_bit(struct qeth_card *card,
  594. unsigned long thread)
  595. {
  596. unsigned long flags;
  597. spin_lock_irqsave(&card->thread_mask_lock, flags);
  598. if (!(card->thread_allowed_mask & thread) ||
  599. (card->thread_start_mask & thread)) {
  600. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  601. return -EPERM;
  602. }
  603. card->thread_start_mask |= thread;
  604. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  605. return 0;
  606. }
  607. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  608. {
  609. unsigned long flags;
  610. spin_lock_irqsave(&card->thread_mask_lock, flags);
  611. card->thread_start_mask &= ~thread;
  612. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  613. wake_up(&card->wait_q);
  614. }
  615. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  616. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  617. {
  618. unsigned long flags;
  619. spin_lock_irqsave(&card->thread_mask_lock, flags);
  620. card->thread_running_mask &= ~thread;
  621. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  622. wake_up(&card->wait_q);
  623. }
  624. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  625. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  626. {
  627. unsigned long flags;
  628. int rc = 0;
  629. spin_lock_irqsave(&card->thread_mask_lock, flags);
  630. if (card->thread_start_mask & thread) {
  631. if ((card->thread_allowed_mask & thread) &&
  632. !(card->thread_running_mask & thread)) {
  633. rc = 1;
  634. card->thread_start_mask &= ~thread;
  635. card->thread_running_mask |= thread;
  636. } else
  637. rc = -EPERM;
  638. }
  639. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  640. return rc;
  641. }
  642. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  643. {
  644. int rc = 0;
  645. wait_event(card->wait_q,
  646. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  647. return rc;
  648. }
  649. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  650. void qeth_schedule_recovery(struct qeth_card *card)
  651. {
  652. QETH_CARD_TEXT(card, 2, "startrec");
  653. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  654. schedule_work(&card->kernel_thread_starter);
  655. }
  656. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  657. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  658. {
  659. int dstat, cstat;
  660. char *sense;
  661. struct qeth_card *card;
  662. sense = (char *) irb->ecw;
  663. cstat = irb->scsw.cmd.cstat;
  664. dstat = irb->scsw.cmd.dstat;
  665. card = CARD_FROM_CDEV(cdev);
  666. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  667. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  668. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  669. QETH_CARD_TEXT(card, 2, "CGENCHK");
  670. dev_warn(&cdev->dev, "The qeth device driver "
  671. "failed to recover an error on the device\n");
  672. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  673. dev_name(&cdev->dev), dstat, cstat);
  674. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  675. 16, 1, irb, 64, 1);
  676. return 1;
  677. }
  678. if (dstat & DEV_STAT_UNIT_CHECK) {
  679. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  680. SENSE_RESETTING_EVENT_FLAG) {
  681. QETH_CARD_TEXT(card, 2, "REVIND");
  682. return 1;
  683. }
  684. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  685. SENSE_COMMAND_REJECT_FLAG) {
  686. QETH_CARD_TEXT(card, 2, "CMDREJi");
  687. return 1;
  688. }
  689. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  690. QETH_CARD_TEXT(card, 2, "AFFE");
  691. return 1;
  692. }
  693. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  694. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  695. return 0;
  696. }
  697. QETH_CARD_TEXT(card, 2, "DGENCHK");
  698. return 1;
  699. }
  700. return 0;
  701. }
  702. static long __qeth_check_irb_error(struct ccw_device *cdev,
  703. unsigned long intparm, struct irb *irb)
  704. {
  705. struct qeth_card *card;
  706. card = CARD_FROM_CDEV(cdev);
  707. if (!IS_ERR(irb))
  708. return 0;
  709. switch (PTR_ERR(irb)) {
  710. case -EIO:
  711. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  712. dev_name(&cdev->dev));
  713. QETH_CARD_TEXT(card, 2, "ckirberr");
  714. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  715. break;
  716. case -ETIMEDOUT:
  717. dev_warn(&cdev->dev, "A hardware operation timed out"
  718. " on the device\n");
  719. QETH_CARD_TEXT(card, 2, "ckirberr");
  720. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  721. if (intparm == QETH_RCD_PARM) {
  722. if (card && (card->data.ccwdev == cdev)) {
  723. card->data.state = CH_STATE_DOWN;
  724. wake_up(&card->wait_q);
  725. }
  726. }
  727. break;
  728. default:
  729. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  730. dev_name(&cdev->dev), PTR_ERR(irb));
  731. QETH_CARD_TEXT(card, 2, "ckirberr");
  732. QETH_CARD_TEXT(card, 2, " rc???");
  733. }
  734. return PTR_ERR(irb);
  735. }
  736. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  737. struct irb *irb)
  738. {
  739. int rc;
  740. int cstat, dstat;
  741. struct qeth_cmd_buffer *buffer;
  742. struct qeth_channel *channel;
  743. struct qeth_card *card;
  744. struct qeth_cmd_buffer *iob;
  745. __u8 index;
  746. if (__qeth_check_irb_error(cdev, intparm, irb))
  747. return;
  748. cstat = irb->scsw.cmd.cstat;
  749. dstat = irb->scsw.cmd.dstat;
  750. card = CARD_FROM_CDEV(cdev);
  751. if (!card)
  752. return;
  753. QETH_CARD_TEXT(card, 5, "irq");
  754. if (card->read.ccwdev == cdev) {
  755. channel = &card->read;
  756. QETH_CARD_TEXT(card, 5, "read");
  757. } else if (card->write.ccwdev == cdev) {
  758. channel = &card->write;
  759. QETH_CARD_TEXT(card, 5, "write");
  760. } else {
  761. channel = &card->data;
  762. QETH_CARD_TEXT(card, 5, "data");
  763. }
  764. atomic_set(&channel->irq_pending, 0);
  765. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  766. channel->state = CH_STATE_STOPPED;
  767. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  768. channel->state = CH_STATE_HALTED;
  769. /*let's wake up immediately on data channel*/
  770. if ((channel == &card->data) && (intparm != 0) &&
  771. (intparm != QETH_RCD_PARM))
  772. goto out;
  773. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  774. QETH_CARD_TEXT(card, 6, "clrchpar");
  775. /* we don't have to handle this further */
  776. intparm = 0;
  777. }
  778. if (intparm == QETH_HALT_CHANNEL_PARM) {
  779. QETH_CARD_TEXT(card, 6, "hltchpar");
  780. /* we don't have to handle this further */
  781. intparm = 0;
  782. }
  783. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  784. (dstat & DEV_STAT_UNIT_CHECK) ||
  785. (cstat)) {
  786. if (irb->esw.esw0.erw.cons) {
  787. dev_warn(&channel->ccwdev->dev,
  788. "The qeth device driver failed to recover "
  789. "an error on the device\n");
  790. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  791. "0x%X dstat 0x%X\n",
  792. dev_name(&channel->ccwdev->dev), cstat, dstat);
  793. print_hex_dump(KERN_WARNING, "qeth: irb ",
  794. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  795. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  796. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  797. }
  798. if (intparm == QETH_RCD_PARM) {
  799. channel->state = CH_STATE_DOWN;
  800. goto out;
  801. }
  802. rc = qeth_get_problem(cdev, irb);
  803. if (rc) {
  804. qeth_clear_ipacmd_list(card);
  805. qeth_schedule_recovery(card);
  806. goto out;
  807. }
  808. }
  809. if (intparm == QETH_RCD_PARM) {
  810. channel->state = CH_STATE_RCD_DONE;
  811. goto out;
  812. }
  813. if (intparm) {
  814. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  815. buffer->state = BUF_STATE_PROCESSED;
  816. }
  817. if (channel == &card->data)
  818. return;
  819. if (channel == &card->read &&
  820. channel->state == CH_STATE_UP)
  821. qeth_issue_next_read(card);
  822. iob = channel->iob;
  823. index = channel->buf_no;
  824. while (iob[index].state == BUF_STATE_PROCESSED) {
  825. if (iob[index].callback != NULL)
  826. iob[index].callback(channel, iob + index);
  827. index = (index + 1) % QETH_CMD_BUFFER_NO;
  828. }
  829. channel->buf_no = index;
  830. out:
  831. wake_up(&card->wait_q);
  832. return;
  833. }
  834. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  835. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  836. {
  837. int i;
  838. struct sk_buff *skb;
  839. /* is PCI flag set on buffer? */
  840. if (buf->buffer->element[0].flags & 0x40)
  841. atomic_dec(&queue->set_pci_flags_count);
  842. if (!qeth_skip_skb) {
  843. skb = skb_dequeue(&buf->skb_list);
  844. while (skb) {
  845. atomic_dec(&skb->users);
  846. dev_kfree_skb_any(skb);
  847. skb = skb_dequeue(&buf->skb_list);
  848. }
  849. }
  850. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  851. if (buf->buffer->element[i].addr && buf->is_header[i])
  852. kmem_cache_free(qeth_core_header_cache,
  853. buf->buffer->element[i].addr);
  854. buf->is_header[i] = 0;
  855. buf->buffer->element[i].length = 0;
  856. buf->buffer->element[i].addr = NULL;
  857. buf->buffer->element[i].flags = 0;
  858. }
  859. buf->buffer->element[15].flags = 0;
  860. buf->next_element_to_fill = 0;
  861. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  862. }
  863. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  864. struct qeth_qdio_out_buffer *buf)
  865. {
  866. __qeth_clear_output_buffer(queue, buf, 0);
  867. }
  868. void qeth_clear_qdio_buffers(struct qeth_card *card)
  869. {
  870. int i, j;
  871. QETH_CARD_TEXT(card, 2, "clearqdbf");
  872. /* clear outbound buffers to free skbs */
  873. for (i = 0; i < card->qdio.no_out_queues; ++i)
  874. if (card->qdio.out_qs[i]) {
  875. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  876. qeth_clear_output_buffer(card->qdio.out_qs[i],
  877. &card->qdio.out_qs[i]->bufs[j]);
  878. }
  879. }
  880. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  881. static void qeth_free_buffer_pool(struct qeth_card *card)
  882. {
  883. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  884. int i = 0;
  885. QETH_CARD_TEXT(card, 5, "freepool");
  886. list_for_each_entry_safe(pool_entry, tmp,
  887. &card->qdio.init_pool.entry_list, init_list){
  888. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  889. free_page((unsigned long)pool_entry->elements[i]);
  890. list_del(&pool_entry->init_list);
  891. kfree(pool_entry);
  892. }
  893. }
  894. static void qeth_free_qdio_buffers(struct qeth_card *card)
  895. {
  896. int i, j;
  897. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  898. QETH_QDIO_UNINITIALIZED)
  899. return;
  900. kfree(card->qdio.in_q);
  901. card->qdio.in_q = NULL;
  902. /* inbound buffer pool */
  903. qeth_free_buffer_pool(card);
  904. /* free outbound qdio_qs */
  905. if (card->qdio.out_qs) {
  906. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  907. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  908. qeth_clear_output_buffer(card->qdio.out_qs[i],
  909. &card->qdio.out_qs[i]->bufs[j]);
  910. kfree(card->qdio.out_qs[i]);
  911. }
  912. kfree(card->qdio.out_qs);
  913. card->qdio.out_qs = NULL;
  914. }
  915. }
  916. static void qeth_clean_channel(struct qeth_channel *channel)
  917. {
  918. int cnt;
  919. QETH_DBF_TEXT(SETUP, 2, "freech");
  920. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  921. kfree(channel->iob[cnt].data);
  922. }
  923. static void qeth_get_channel_path_desc(struct qeth_card *card)
  924. {
  925. struct ccw_device *ccwdev;
  926. struct channelPath_dsc {
  927. u8 flags;
  928. u8 lsn;
  929. u8 desc;
  930. u8 chpid;
  931. u8 swla;
  932. u8 zeroes;
  933. u8 chla;
  934. u8 chpp;
  935. } *chp_dsc;
  936. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  937. ccwdev = card->data.ccwdev;
  938. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  939. if (chp_dsc != NULL) {
  940. /* CHPP field bit 6 == 1 -> single queue */
  941. if ((chp_dsc->chpp & 0x02) == 0x02)
  942. card->qdio.no_out_queues = 1;
  943. card->info.func_level = 0x4100 + chp_dsc->desc;
  944. kfree(chp_dsc);
  945. }
  946. if (card->qdio.no_out_queues == 1) {
  947. card->qdio.default_out_queue = 0;
  948. dev_info(&card->gdev->dev,
  949. "Priority Queueing not supported\n");
  950. }
  951. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  952. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  953. return;
  954. }
  955. static void qeth_init_qdio_info(struct qeth_card *card)
  956. {
  957. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  958. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  959. /* inbound */
  960. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  961. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  962. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  963. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  964. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  965. }
  966. static void qeth_set_intial_options(struct qeth_card *card)
  967. {
  968. card->options.route4.type = NO_ROUTER;
  969. card->options.route6.type = NO_ROUTER;
  970. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  971. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  972. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  973. card->options.fake_broadcast = 0;
  974. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  975. card->options.performance_stats = 0;
  976. card->options.rx_sg_cb = QETH_RX_SG_CB;
  977. card->options.isolation = ISOLATION_MODE_NONE;
  978. }
  979. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  980. {
  981. unsigned long flags;
  982. int rc = 0;
  983. spin_lock_irqsave(&card->thread_mask_lock, flags);
  984. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  985. (u8) card->thread_start_mask,
  986. (u8) card->thread_allowed_mask,
  987. (u8) card->thread_running_mask);
  988. rc = (card->thread_start_mask & thread);
  989. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  990. return rc;
  991. }
  992. static void qeth_start_kernel_thread(struct work_struct *work)
  993. {
  994. struct qeth_card *card = container_of(work, struct qeth_card,
  995. kernel_thread_starter);
  996. QETH_CARD_TEXT(card , 2, "strthrd");
  997. if (card->read.state != CH_STATE_UP &&
  998. card->write.state != CH_STATE_UP)
  999. return;
  1000. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  1001. kthread_run(card->discipline.recover, (void *) card,
  1002. "qeth_recover");
  1003. }
  1004. static int qeth_setup_card(struct qeth_card *card)
  1005. {
  1006. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1007. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1008. card->read.state = CH_STATE_DOWN;
  1009. card->write.state = CH_STATE_DOWN;
  1010. card->data.state = CH_STATE_DOWN;
  1011. card->state = CARD_STATE_DOWN;
  1012. card->lan_online = 0;
  1013. card->use_hard_stop = 0;
  1014. card->dev = NULL;
  1015. spin_lock_init(&card->vlanlock);
  1016. spin_lock_init(&card->mclock);
  1017. card->vlangrp = NULL;
  1018. spin_lock_init(&card->lock);
  1019. spin_lock_init(&card->ip_lock);
  1020. spin_lock_init(&card->thread_mask_lock);
  1021. mutex_init(&card->conf_mutex);
  1022. card->thread_start_mask = 0;
  1023. card->thread_allowed_mask = 0;
  1024. card->thread_running_mask = 0;
  1025. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1026. INIT_LIST_HEAD(&card->ip_list);
  1027. INIT_LIST_HEAD(card->ip_tbd_list);
  1028. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1029. init_waitqueue_head(&card->wait_q);
  1030. /* intial options */
  1031. qeth_set_intial_options(card);
  1032. /* IP address takeover */
  1033. INIT_LIST_HEAD(&card->ipato.entries);
  1034. card->ipato.enabled = 0;
  1035. card->ipato.invert4 = 0;
  1036. card->ipato.invert6 = 0;
  1037. /* init QDIO stuff */
  1038. qeth_init_qdio_info(card);
  1039. return 0;
  1040. }
  1041. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1042. {
  1043. struct qeth_card *card = container_of(slr, struct qeth_card,
  1044. qeth_service_level);
  1045. if (card->info.mcl_level[0])
  1046. seq_printf(m, "qeth: %s firmware level %s\n",
  1047. CARD_BUS_ID(card), card->info.mcl_level);
  1048. }
  1049. static struct qeth_card *qeth_alloc_card(void)
  1050. {
  1051. struct qeth_card *card;
  1052. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1053. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1054. if (!card)
  1055. goto out;
  1056. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1057. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1058. if (!card->ip_tbd_list) {
  1059. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1060. goto out_card;
  1061. }
  1062. if (qeth_setup_channel(&card->read))
  1063. goto out_ip;
  1064. if (qeth_setup_channel(&card->write))
  1065. goto out_channel;
  1066. card->options.layer2 = -1;
  1067. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1068. register_service_level(&card->qeth_service_level);
  1069. return card;
  1070. out_channel:
  1071. qeth_clean_channel(&card->read);
  1072. out_ip:
  1073. kfree(card->ip_tbd_list);
  1074. out_card:
  1075. kfree(card);
  1076. out:
  1077. return NULL;
  1078. }
  1079. static int qeth_determine_card_type(struct qeth_card *card)
  1080. {
  1081. int i = 0;
  1082. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1083. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1084. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1085. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1086. if ((CARD_RDEV(card)->id.dev_type ==
  1087. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1088. (CARD_RDEV(card)->id.dev_model ==
  1089. known_devices[i][QETH_DEV_MODEL_IND])) {
  1090. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1091. card->qdio.no_out_queues =
  1092. known_devices[i][QETH_QUEUE_NO_IND];
  1093. card->info.is_multicast_different =
  1094. known_devices[i][QETH_MULTICAST_IND];
  1095. qeth_get_channel_path_desc(card);
  1096. return 0;
  1097. }
  1098. i++;
  1099. }
  1100. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1101. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1102. "unknown type\n");
  1103. return -ENOENT;
  1104. }
  1105. static int qeth_clear_channel(struct qeth_channel *channel)
  1106. {
  1107. unsigned long flags;
  1108. struct qeth_card *card;
  1109. int rc;
  1110. card = CARD_FROM_CDEV(channel->ccwdev);
  1111. QETH_CARD_TEXT(card, 3, "clearch");
  1112. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1113. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1114. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1115. if (rc)
  1116. return rc;
  1117. rc = wait_event_interruptible_timeout(card->wait_q,
  1118. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1119. if (rc == -ERESTARTSYS)
  1120. return rc;
  1121. if (channel->state != CH_STATE_STOPPED)
  1122. return -ETIME;
  1123. channel->state = CH_STATE_DOWN;
  1124. return 0;
  1125. }
  1126. static int qeth_halt_channel(struct qeth_channel *channel)
  1127. {
  1128. unsigned long flags;
  1129. struct qeth_card *card;
  1130. int rc;
  1131. card = CARD_FROM_CDEV(channel->ccwdev);
  1132. QETH_CARD_TEXT(card, 3, "haltch");
  1133. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1134. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1135. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1136. if (rc)
  1137. return rc;
  1138. rc = wait_event_interruptible_timeout(card->wait_q,
  1139. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1140. if (rc == -ERESTARTSYS)
  1141. return rc;
  1142. if (channel->state != CH_STATE_HALTED)
  1143. return -ETIME;
  1144. return 0;
  1145. }
  1146. static int qeth_halt_channels(struct qeth_card *card)
  1147. {
  1148. int rc1 = 0, rc2 = 0, rc3 = 0;
  1149. QETH_CARD_TEXT(card, 3, "haltchs");
  1150. rc1 = qeth_halt_channel(&card->read);
  1151. rc2 = qeth_halt_channel(&card->write);
  1152. rc3 = qeth_halt_channel(&card->data);
  1153. if (rc1)
  1154. return rc1;
  1155. if (rc2)
  1156. return rc2;
  1157. return rc3;
  1158. }
  1159. static int qeth_clear_channels(struct qeth_card *card)
  1160. {
  1161. int rc1 = 0, rc2 = 0, rc3 = 0;
  1162. QETH_CARD_TEXT(card, 3, "clearchs");
  1163. rc1 = qeth_clear_channel(&card->read);
  1164. rc2 = qeth_clear_channel(&card->write);
  1165. rc3 = qeth_clear_channel(&card->data);
  1166. if (rc1)
  1167. return rc1;
  1168. if (rc2)
  1169. return rc2;
  1170. return rc3;
  1171. }
  1172. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1173. {
  1174. int rc = 0;
  1175. QETH_CARD_TEXT(card, 3, "clhacrd");
  1176. if (halt)
  1177. rc = qeth_halt_channels(card);
  1178. if (rc)
  1179. return rc;
  1180. return qeth_clear_channels(card);
  1181. }
  1182. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1183. {
  1184. int rc = 0;
  1185. QETH_CARD_TEXT(card, 3, "qdioclr");
  1186. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1187. QETH_QDIO_CLEANING)) {
  1188. case QETH_QDIO_ESTABLISHED:
  1189. if (card->info.type == QETH_CARD_TYPE_IQD)
  1190. rc = qdio_shutdown(CARD_DDEV(card),
  1191. QDIO_FLAG_CLEANUP_USING_HALT);
  1192. else
  1193. rc = qdio_shutdown(CARD_DDEV(card),
  1194. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1195. if (rc)
  1196. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1197. qdio_free(CARD_DDEV(card));
  1198. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1199. break;
  1200. case QETH_QDIO_CLEANING:
  1201. return rc;
  1202. default:
  1203. break;
  1204. }
  1205. rc = qeth_clear_halt_card(card, use_halt);
  1206. if (rc)
  1207. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1208. card->state = CARD_STATE_DOWN;
  1209. return rc;
  1210. }
  1211. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1212. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1213. int *length)
  1214. {
  1215. struct ciw *ciw;
  1216. char *rcd_buf;
  1217. int ret;
  1218. struct qeth_channel *channel = &card->data;
  1219. unsigned long flags;
  1220. /*
  1221. * scan for RCD command in extended SenseID data
  1222. */
  1223. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1224. if (!ciw || ciw->cmd == 0)
  1225. return -EOPNOTSUPP;
  1226. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1227. if (!rcd_buf)
  1228. return -ENOMEM;
  1229. channel->ccw.cmd_code = ciw->cmd;
  1230. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1231. channel->ccw.count = ciw->count;
  1232. channel->ccw.flags = CCW_FLAG_SLI;
  1233. channel->state = CH_STATE_RCD;
  1234. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1235. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1236. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1237. QETH_RCD_TIMEOUT);
  1238. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1239. if (!ret)
  1240. wait_event(card->wait_q,
  1241. (channel->state == CH_STATE_RCD_DONE ||
  1242. channel->state == CH_STATE_DOWN));
  1243. if (channel->state == CH_STATE_DOWN)
  1244. ret = -EIO;
  1245. else
  1246. channel->state = CH_STATE_DOWN;
  1247. if (ret) {
  1248. kfree(rcd_buf);
  1249. *buffer = NULL;
  1250. *length = 0;
  1251. } else {
  1252. *length = ciw->count;
  1253. *buffer = rcd_buf;
  1254. }
  1255. return ret;
  1256. }
  1257. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1258. {
  1259. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1260. card->info.chpid = prcd[30];
  1261. card->info.unit_addr2 = prcd[31];
  1262. card->info.cula = prcd[63];
  1263. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1264. (prcd[0x11] == _ascebc['M']));
  1265. }
  1266. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1267. {
  1268. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1269. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1270. card->info.blkt.time_total = 250;
  1271. card->info.blkt.inter_packet = 5;
  1272. card->info.blkt.inter_packet_jumbo = 15;
  1273. } else {
  1274. card->info.blkt.time_total = 0;
  1275. card->info.blkt.inter_packet = 0;
  1276. card->info.blkt.inter_packet_jumbo = 0;
  1277. }
  1278. }
  1279. static void qeth_init_tokens(struct qeth_card *card)
  1280. {
  1281. card->token.issuer_rm_w = 0x00010103UL;
  1282. card->token.cm_filter_w = 0x00010108UL;
  1283. card->token.cm_connection_w = 0x0001010aUL;
  1284. card->token.ulp_filter_w = 0x0001010bUL;
  1285. card->token.ulp_connection_w = 0x0001010dUL;
  1286. }
  1287. static void qeth_init_func_level(struct qeth_card *card)
  1288. {
  1289. switch (card->info.type) {
  1290. case QETH_CARD_TYPE_IQD:
  1291. if (card->ipato.enabled)
  1292. card->info.func_level =
  1293. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1294. else
  1295. card->info.func_level =
  1296. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1297. break;
  1298. case QETH_CARD_TYPE_OSD:
  1299. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1300. break;
  1301. default:
  1302. break;
  1303. }
  1304. }
  1305. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1306. void (*idx_reply_cb)(struct qeth_channel *,
  1307. struct qeth_cmd_buffer *))
  1308. {
  1309. struct qeth_cmd_buffer *iob;
  1310. unsigned long flags;
  1311. int rc;
  1312. struct qeth_card *card;
  1313. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1314. card = CARD_FROM_CDEV(channel->ccwdev);
  1315. iob = qeth_get_buffer(channel);
  1316. iob->callback = idx_reply_cb;
  1317. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1318. channel->ccw.count = QETH_BUFSIZE;
  1319. channel->ccw.cda = (__u32) __pa(iob->data);
  1320. wait_event(card->wait_q,
  1321. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1322. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1323. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1324. rc = ccw_device_start(channel->ccwdev,
  1325. &channel->ccw, (addr_t) iob, 0, 0);
  1326. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1327. if (rc) {
  1328. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1329. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1330. atomic_set(&channel->irq_pending, 0);
  1331. wake_up(&card->wait_q);
  1332. return rc;
  1333. }
  1334. rc = wait_event_interruptible_timeout(card->wait_q,
  1335. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1336. if (rc == -ERESTARTSYS)
  1337. return rc;
  1338. if (channel->state != CH_STATE_UP) {
  1339. rc = -ETIME;
  1340. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1341. qeth_clear_cmd_buffers(channel);
  1342. } else
  1343. rc = 0;
  1344. return rc;
  1345. }
  1346. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1347. void (*idx_reply_cb)(struct qeth_channel *,
  1348. struct qeth_cmd_buffer *))
  1349. {
  1350. struct qeth_card *card;
  1351. struct qeth_cmd_buffer *iob;
  1352. unsigned long flags;
  1353. __u16 temp;
  1354. __u8 tmp;
  1355. int rc;
  1356. struct ccw_dev_id temp_devid;
  1357. card = CARD_FROM_CDEV(channel->ccwdev);
  1358. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1359. iob = qeth_get_buffer(channel);
  1360. iob->callback = idx_reply_cb;
  1361. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1362. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1363. channel->ccw.cda = (__u32) __pa(iob->data);
  1364. if (channel == &card->write) {
  1365. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1366. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1367. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1368. card->seqno.trans_hdr++;
  1369. } else {
  1370. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1371. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1372. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1373. }
  1374. tmp = ((__u8)card->info.portno) | 0x80;
  1375. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1376. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1377. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1378. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1379. &card->info.func_level, sizeof(__u16));
  1380. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1381. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1382. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1383. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1384. wait_event(card->wait_q,
  1385. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1386. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1387. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1388. rc = ccw_device_start(channel->ccwdev,
  1389. &channel->ccw, (addr_t) iob, 0, 0);
  1390. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1391. if (rc) {
  1392. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1393. rc);
  1394. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1395. atomic_set(&channel->irq_pending, 0);
  1396. wake_up(&card->wait_q);
  1397. return rc;
  1398. }
  1399. rc = wait_event_interruptible_timeout(card->wait_q,
  1400. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1401. if (rc == -ERESTARTSYS)
  1402. return rc;
  1403. if (channel->state != CH_STATE_ACTIVATING) {
  1404. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1405. " failed to recover an error on the device\n");
  1406. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1407. dev_name(&channel->ccwdev->dev));
  1408. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1409. qeth_clear_cmd_buffers(channel);
  1410. return -ETIME;
  1411. }
  1412. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1413. }
  1414. static int qeth_peer_func_level(int level)
  1415. {
  1416. if ((level & 0xff) == 8)
  1417. return (level & 0xff) + 0x400;
  1418. if (((level >> 8) & 3) == 1)
  1419. return (level & 0xff) + 0x200;
  1420. return level;
  1421. }
  1422. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1423. struct qeth_cmd_buffer *iob)
  1424. {
  1425. struct qeth_card *card;
  1426. __u16 temp;
  1427. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1428. if (channel->state == CH_STATE_DOWN) {
  1429. channel->state = CH_STATE_ACTIVATING;
  1430. goto out;
  1431. }
  1432. card = CARD_FROM_CDEV(channel->ccwdev);
  1433. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1434. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1435. dev_err(&card->write.ccwdev->dev,
  1436. "The adapter is used exclusively by another "
  1437. "host\n");
  1438. else
  1439. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1440. " negative reply\n",
  1441. dev_name(&card->write.ccwdev->dev));
  1442. goto out;
  1443. }
  1444. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1445. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1446. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1447. "function level mismatch (sent: 0x%x, received: "
  1448. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1449. card->info.func_level, temp);
  1450. goto out;
  1451. }
  1452. channel->state = CH_STATE_UP;
  1453. out:
  1454. qeth_release_buffer(channel, iob);
  1455. }
  1456. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1457. struct qeth_cmd_buffer *iob)
  1458. {
  1459. struct qeth_card *card;
  1460. __u16 temp;
  1461. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1462. if (channel->state == CH_STATE_DOWN) {
  1463. channel->state = CH_STATE_ACTIVATING;
  1464. goto out;
  1465. }
  1466. card = CARD_FROM_CDEV(channel->ccwdev);
  1467. if (qeth_check_idx_response(card, iob->data))
  1468. goto out;
  1469. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1470. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1471. case QETH_IDX_ACT_ERR_EXCL:
  1472. dev_err(&card->write.ccwdev->dev,
  1473. "The adapter is used exclusively by another "
  1474. "host\n");
  1475. break;
  1476. case QETH_IDX_ACT_ERR_AUTH:
  1477. dev_err(&card->read.ccwdev->dev,
  1478. "Setting the device online failed because of "
  1479. "insufficient LPAR authorization\n");
  1480. break;
  1481. default:
  1482. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1483. " negative reply\n",
  1484. dev_name(&card->read.ccwdev->dev));
  1485. }
  1486. goto out;
  1487. }
  1488. /**
  1489. * * temporary fix for microcode bug
  1490. * * to revert it,replace OR by AND
  1491. * */
  1492. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1493. (card->info.type == QETH_CARD_TYPE_OSD))
  1494. card->info.portname_required = 1;
  1495. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1496. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1497. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1498. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1499. dev_name(&card->read.ccwdev->dev),
  1500. card->info.func_level, temp);
  1501. goto out;
  1502. }
  1503. memcpy(&card->token.issuer_rm_r,
  1504. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1505. QETH_MPC_TOKEN_LENGTH);
  1506. memcpy(&card->info.mcl_level[0],
  1507. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1508. channel->state = CH_STATE_UP;
  1509. out:
  1510. qeth_release_buffer(channel, iob);
  1511. }
  1512. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1513. struct qeth_cmd_buffer *iob)
  1514. {
  1515. qeth_setup_ccw(&card->write, iob->data, len);
  1516. iob->callback = qeth_release_buffer;
  1517. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1518. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1519. card->seqno.trans_hdr++;
  1520. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1521. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1522. card->seqno.pdu_hdr++;
  1523. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1524. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1525. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1526. }
  1527. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1528. int qeth_send_control_data(struct qeth_card *card, int len,
  1529. struct qeth_cmd_buffer *iob,
  1530. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1531. unsigned long),
  1532. void *reply_param)
  1533. {
  1534. int rc;
  1535. unsigned long flags;
  1536. struct qeth_reply *reply = NULL;
  1537. unsigned long timeout, event_timeout;
  1538. struct qeth_ipa_cmd *cmd;
  1539. QETH_CARD_TEXT(card, 2, "sendctl");
  1540. reply = qeth_alloc_reply(card);
  1541. if (!reply) {
  1542. return -ENOMEM;
  1543. }
  1544. reply->callback = reply_cb;
  1545. reply->param = reply_param;
  1546. if (card->state == CARD_STATE_DOWN)
  1547. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1548. else
  1549. reply->seqno = card->seqno.ipa++;
  1550. init_waitqueue_head(&reply->wait_q);
  1551. spin_lock_irqsave(&card->lock, flags);
  1552. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1553. spin_unlock_irqrestore(&card->lock, flags);
  1554. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1555. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1556. qeth_prepare_control_data(card, len, iob);
  1557. if (IS_IPA(iob->data))
  1558. event_timeout = QETH_IPA_TIMEOUT;
  1559. else
  1560. event_timeout = QETH_TIMEOUT;
  1561. timeout = jiffies + event_timeout;
  1562. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1563. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1564. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1565. (addr_t) iob, 0, 0);
  1566. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1567. if (rc) {
  1568. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1569. "ccw_device_start rc = %i\n",
  1570. dev_name(&card->write.ccwdev->dev), rc);
  1571. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1572. spin_lock_irqsave(&card->lock, flags);
  1573. list_del_init(&reply->list);
  1574. qeth_put_reply(reply);
  1575. spin_unlock_irqrestore(&card->lock, flags);
  1576. qeth_release_buffer(iob->channel, iob);
  1577. atomic_set(&card->write.irq_pending, 0);
  1578. wake_up(&card->wait_q);
  1579. return rc;
  1580. }
  1581. /* we have only one long running ipassist, since we can ensure
  1582. process context of this command we can sleep */
  1583. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1584. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1585. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1586. if (!wait_event_timeout(reply->wait_q,
  1587. atomic_read(&reply->received), event_timeout))
  1588. goto time_err;
  1589. } else {
  1590. while (!atomic_read(&reply->received)) {
  1591. if (time_after(jiffies, timeout))
  1592. goto time_err;
  1593. cpu_relax();
  1594. };
  1595. }
  1596. rc = reply->rc;
  1597. qeth_put_reply(reply);
  1598. return rc;
  1599. time_err:
  1600. spin_lock_irqsave(&reply->card->lock, flags);
  1601. list_del_init(&reply->list);
  1602. spin_unlock_irqrestore(&reply->card->lock, flags);
  1603. reply->rc = -ETIME;
  1604. atomic_inc(&reply->received);
  1605. wake_up(&reply->wait_q);
  1606. rc = reply->rc;
  1607. qeth_put_reply(reply);
  1608. return rc;
  1609. }
  1610. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1611. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1612. unsigned long data)
  1613. {
  1614. struct qeth_cmd_buffer *iob;
  1615. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1616. iob = (struct qeth_cmd_buffer *) data;
  1617. memcpy(&card->token.cm_filter_r,
  1618. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1619. QETH_MPC_TOKEN_LENGTH);
  1620. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1621. return 0;
  1622. }
  1623. static int qeth_cm_enable(struct qeth_card *card)
  1624. {
  1625. int rc;
  1626. struct qeth_cmd_buffer *iob;
  1627. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1628. iob = qeth_wait_for_buffer(&card->write);
  1629. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1630. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1631. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1632. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1633. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1634. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1635. qeth_cm_enable_cb, NULL);
  1636. return rc;
  1637. }
  1638. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1639. unsigned long data)
  1640. {
  1641. struct qeth_cmd_buffer *iob;
  1642. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1643. iob = (struct qeth_cmd_buffer *) data;
  1644. memcpy(&card->token.cm_connection_r,
  1645. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1646. QETH_MPC_TOKEN_LENGTH);
  1647. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1648. return 0;
  1649. }
  1650. static int qeth_cm_setup(struct qeth_card *card)
  1651. {
  1652. int rc;
  1653. struct qeth_cmd_buffer *iob;
  1654. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1655. iob = qeth_wait_for_buffer(&card->write);
  1656. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1657. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1658. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1659. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1660. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1661. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1662. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1663. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1664. qeth_cm_setup_cb, NULL);
  1665. return rc;
  1666. }
  1667. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1668. {
  1669. switch (card->info.type) {
  1670. case QETH_CARD_TYPE_UNKNOWN:
  1671. return 1500;
  1672. case QETH_CARD_TYPE_IQD:
  1673. return card->info.max_mtu;
  1674. case QETH_CARD_TYPE_OSD:
  1675. switch (card->info.link_type) {
  1676. case QETH_LINK_TYPE_HSTR:
  1677. case QETH_LINK_TYPE_LANE_TR:
  1678. return 2000;
  1679. default:
  1680. return 1492;
  1681. }
  1682. case QETH_CARD_TYPE_OSM:
  1683. case QETH_CARD_TYPE_OSX:
  1684. return 1492;
  1685. default:
  1686. return 1500;
  1687. }
  1688. }
  1689. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1690. {
  1691. switch (cardtype) {
  1692. case QETH_CARD_TYPE_UNKNOWN:
  1693. case QETH_CARD_TYPE_OSD:
  1694. case QETH_CARD_TYPE_OSN:
  1695. case QETH_CARD_TYPE_OSM:
  1696. case QETH_CARD_TYPE_OSX:
  1697. return 61440;
  1698. case QETH_CARD_TYPE_IQD:
  1699. return 57344;
  1700. default:
  1701. return 1500;
  1702. }
  1703. }
  1704. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1705. {
  1706. switch (cardtype) {
  1707. case QETH_CARD_TYPE_IQD:
  1708. return 1;
  1709. default:
  1710. return 0;
  1711. }
  1712. }
  1713. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1714. {
  1715. switch (framesize) {
  1716. case 0x4000:
  1717. return 8192;
  1718. case 0x6000:
  1719. return 16384;
  1720. case 0xa000:
  1721. return 32768;
  1722. case 0xffff:
  1723. return 57344;
  1724. default:
  1725. return 0;
  1726. }
  1727. }
  1728. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1729. {
  1730. switch (card->info.type) {
  1731. case QETH_CARD_TYPE_OSD:
  1732. case QETH_CARD_TYPE_OSM:
  1733. case QETH_CARD_TYPE_OSX:
  1734. return ((mtu >= 576) && (mtu <= 61440));
  1735. case QETH_CARD_TYPE_IQD:
  1736. return ((mtu >= 576) &&
  1737. (mtu <= card->info.max_mtu + 4096 - 32));
  1738. case QETH_CARD_TYPE_OSN:
  1739. case QETH_CARD_TYPE_UNKNOWN:
  1740. default:
  1741. return 1;
  1742. }
  1743. }
  1744. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1745. unsigned long data)
  1746. {
  1747. __u16 mtu, framesize;
  1748. __u16 len;
  1749. __u8 link_type;
  1750. struct qeth_cmd_buffer *iob;
  1751. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1752. iob = (struct qeth_cmd_buffer *) data;
  1753. memcpy(&card->token.ulp_filter_r,
  1754. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1755. QETH_MPC_TOKEN_LENGTH);
  1756. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1757. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1758. mtu = qeth_get_mtu_outof_framesize(framesize);
  1759. if (!mtu) {
  1760. iob->rc = -EINVAL;
  1761. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1762. return 0;
  1763. }
  1764. card->info.max_mtu = mtu;
  1765. card->info.initial_mtu = mtu;
  1766. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1767. } else {
  1768. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1769. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1770. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1771. }
  1772. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1773. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1774. memcpy(&link_type,
  1775. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1776. card->info.link_type = link_type;
  1777. } else
  1778. card->info.link_type = 0;
  1779. QETH_DBF_TEXT_(SETUP, 2, "link%d", link_type);
  1780. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1781. return 0;
  1782. }
  1783. static int qeth_ulp_enable(struct qeth_card *card)
  1784. {
  1785. int rc;
  1786. char prot_type;
  1787. struct qeth_cmd_buffer *iob;
  1788. /*FIXME: trace view callbacks*/
  1789. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1790. iob = qeth_wait_for_buffer(&card->write);
  1791. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1792. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1793. (__u8) card->info.portno;
  1794. if (card->options.layer2)
  1795. if (card->info.type == QETH_CARD_TYPE_OSN)
  1796. prot_type = QETH_PROT_OSN2;
  1797. else
  1798. prot_type = QETH_PROT_LAYER2;
  1799. else
  1800. prot_type = QETH_PROT_TCPIP;
  1801. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1802. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1803. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1804. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1805. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1806. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1807. card->info.portname, 9);
  1808. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1809. qeth_ulp_enable_cb, NULL);
  1810. return rc;
  1811. }
  1812. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1813. unsigned long data)
  1814. {
  1815. struct qeth_cmd_buffer *iob;
  1816. int rc = 0;
  1817. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1818. iob = (struct qeth_cmd_buffer *) data;
  1819. memcpy(&card->token.ulp_connection_r,
  1820. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1821. QETH_MPC_TOKEN_LENGTH);
  1822. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1823. 3)) {
  1824. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1825. dev_err(&card->gdev->dev, "A connection could not be "
  1826. "established because of an OLM limit\n");
  1827. rc = -EMLINK;
  1828. }
  1829. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1830. return rc;
  1831. }
  1832. static int qeth_ulp_setup(struct qeth_card *card)
  1833. {
  1834. int rc;
  1835. __u16 temp;
  1836. struct qeth_cmd_buffer *iob;
  1837. struct ccw_dev_id dev_id;
  1838. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1839. iob = qeth_wait_for_buffer(&card->write);
  1840. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1841. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1842. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1843. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1844. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1845. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1846. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1847. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1848. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1849. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1850. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1851. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1852. qeth_ulp_setup_cb, NULL);
  1853. return rc;
  1854. }
  1855. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1856. {
  1857. int i, j;
  1858. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1859. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1860. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1861. return 0;
  1862. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1863. GFP_KERNEL);
  1864. if (!card->qdio.in_q)
  1865. goto out_nomem;
  1866. QETH_DBF_TEXT(SETUP, 2, "inq");
  1867. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1868. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1869. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1870. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1871. card->qdio.in_q->bufs[i].buffer =
  1872. &card->qdio.in_q->qdio_bufs[i];
  1873. /* inbound buffer pool */
  1874. if (qeth_alloc_buffer_pool(card))
  1875. goto out_freeinq;
  1876. /* outbound */
  1877. card->qdio.out_qs =
  1878. kmalloc(card->qdio.no_out_queues *
  1879. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1880. if (!card->qdio.out_qs)
  1881. goto out_freepool;
  1882. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1883. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1884. GFP_KERNEL);
  1885. if (!card->qdio.out_qs[i])
  1886. goto out_freeoutq;
  1887. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1888. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1889. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1890. card->qdio.out_qs[i]->queue_no = i;
  1891. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1892. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1893. card->qdio.out_qs[i]->bufs[j].buffer =
  1894. &card->qdio.out_qs[i]->qdio_bufs[j];
  1895. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1896. skb_list);
  1897. lockdep_set_class(
  1898. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1899. &qdio_out_skb_queue_key);
  1900. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1901. }
  1902. }
  1903. return 0;
  1904. out_freeoutq:
  1905. while (i > 0)
  1906. kfree(card->qdio.out_qs[--i]);
  1907. kfree(card->qdio.out_qs);
  1908. card->qdio.out_qs = NULL;
  1909. out_freepool:
  1910. qeth_free_buffer_pool(card);
  1911. out_freeinq:
  1912. kfree(card->qdio.in_q);
  1913. card->qdio.in_q = NULL;
  1914. out_nomem:
  1915. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1916. return -ENOMEM;
  1917. }
  1918. static void qeth_create_qib_param_field(struct qeth_card *card,
  1919. char *param_field)
  1920. {
  1921. param_field[0] = _ascebc['P'];
  1922. param_field[1] = _ascebc['C'];
  1923. param_field[2] = _ascebc['I'];
  1924. param_field[3] = _ascebc['T'];
  1925. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1926. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1927. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1928. }
  1929. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1930. char *param_field)
  1931. {
  1932. param_field[16] = _ascebc['B'];
  1933. param_field[17] = _ascebc['L'];
  1934. param_field[18] = _ascebc['K'];
  1935. param_field[19] = _ascebc['T'];
  1936. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1937. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1938. *((unsigned int *) (&param_field[28])) =
  1939. card->info.blkt.inter_packet_jumbo;
  1940. }
  1941. static int qeth_qdio_activate(struct qeth_card *card)
  1942. {
  1943. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1944. return qdio_activate(CARD_DDEV(card));
  1945. }
  1946. static int qeth_dm_act(struct qeth_card *card)
  1947. {
  1948. int rc;
  1949. struct qeth_cmd_buffer *iob;
  1950. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1951. iob = qeth_wait_for_buffer(&card->write);
  1952. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1953. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1954. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1955. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1956. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1957. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1958. return rc;
  1959. }
  1960. static int qeth_mpc_initialize(struct qeth_card *card)
  1961. {
  1962. int rc;
  1963. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1964. rc = qeth_issue_next_read(card);
  1965. if (rc) {
  1966. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1967. return rc;
  1968. }
  1969. rc = qeth_cm_enable(card);
  1970. if (rc) {
  1971. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1972. goto out_qdio;
  1973. }
  1974. rc = qeth_cm_setup(card);
  1975. if (rc) {
  1976. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1977. goto out_qdio;
  1978. }
  1979. rc = qeth_ulp_enable(card);
  1980. if (rc) {
  1981. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1982. goto out_qdio;
  1983. }
  1984. rc = qeth_ulp_setup(card);
  1985. if (rc) {
  1986. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1987. goto out_qdio;
  1988. }
  1989. rc = qeth_alloc_qdio_buffers(card);
  1990. if (rc) {
  1991. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1992. goto out_qdio;
  1993. }
  1994. rc = qeth_qdio_establish(card);
  1995. if (rc) {
  1996. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1997. qeth_free_qdio_buffers(card);
  1998. goto out_qdio;
  1999. }
  2000. rc = qeth_qdio_activate(card);
  2001. if (rc) {
  2002. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2003. goto out_qdio;
  2004. }
  2005. rc = qeth_dm_act(card);
  2006. if (rc) {
  2007. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2008. goto out_qdio;
  2009. }
  2010. return 0;
  2011. out_qdio:
  2012. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2013. return rc;
  2014. }
  2015. static void qeth_print_status_with_portname(struct qeth_card *card)
  2016. {
  2017. char dbf_text[15];
  2018. int i;
  2019. sprintf(dbf_text, "%s", card->info.portname + 1);
  2020. for (i = 0; i < 8; i++)
  2021. dbf_text[i] =
  2022. (char) _ebcasc[(__u8) dbf_text[i]];
  2023. dbf_text[8] = 0;
  2024. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2025. "with link type %s (portname: %s)\n",
  2026. qeth_get_cardname(card),
  2027. (card->info.mcl_level[0]) ? " (level: " : "",
  2028. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2029. (card->info.mcl_level[0]) ? ")" : "",
  2030. qeth_get_cardname_short(card),
  2031. dbf_text);
  2032. }
  2033. static void qeth_print_status_no_portname(struct qeth_card *card)
  2034. {
  2035. if (card->info.portname[0])
  2036. dev_info(&card->gdev->dev, "Device is a%s "
  2037. "card%s%s%s\nwith link type %s "
  2038. "(no portname needed by interface).\n",
  2039. qeth_get_cardname(card),
  2040. (card->info.mcl_level[0]) ? " (level: " : "",
  2041. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2042. (card->info.mcl_level[0]) ? ")" : "",
  2043. qeth_get_cardname_short(card));
  2044. else
  2045. dev_info(&card->gdev->dev, "Device is a%s "
  2046. "card%s%s%s\nwith link type %s.\n",
  2047. qeth_get_cardname(card),
  2048. (card->info.mcl_level[0]) ? " (level: " : "",
  2049. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2050. (card->info.mcl_level[0]) ? ")" : "",
  2051. qeth_get_cardname_short(card));
  2052. }
  2053. void qeth_print_status_message(struct qeth_card *card)
  2054. {
  2055. switch (card->info.type) {
  2056. case QETH_CARD_TYPE_OSD:
  2057. case QETH_CARD_TYPE_OSM:
  2058. case QETH_CARD_TYPE_OSX:
  2059. /* VM will use a non-zero first character
  2060. * to indicate a HiperSockets like reporting
  2061. * of the level OSA sets the first character to zero
  2062. * */
  2063. if (!card->info.mcl_level[0]) {
  2064. sprintf(card->info.mcl_level, "%02x%02x",
  2065. card->info.mcl_level[2],
  2066. card->info.mcl_level[3]);
  2067. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2068. break;
  2069. }
  2070. /* fallthrough */
  2071. case QETH_CARD_TYPE_IQD:
  2072. if ((card->info.guestlan) ||
  2073. (card->info.mcl_level[0] & 0x80)) {
  2074. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2075. card->info.mcl_level[0]];
  2076. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2077. card->info.mcl_level[1]];
  2078. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2079. card->info.mcl_level[2]];
  2080. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2081. card->info.mcl_level[3]];
  2082. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2083. }
  2084. break;
  2085. default:
  2086. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2087. }
  2088. if (card->info.portname_required)
  2089. qeth_print_status_with_portname(card);
  2090. else
  2091. qeth_print_status_no_portname(card);
  2092. }
  2093. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2094. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2095. {
  2096. struct qeth_buffer_pool_entry *entry;
  2097. QETH_CARD_TEXT(card, 5, "inwrklst");
  2098. list_for_each_entry(entry,
  2099. &card->qdio.init_pool.entry_list, init_list) {
  2100. qeth_put_buffer_pool_entry(card, entry);
  2101. }
  2102. }
  2103. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2104. struct qeth_card *card)
  2105. {
  2106. struct list_head *plh;
  2107. struct qeth_buffer_pool_entry *entry;
  2108. int i, free;
  2109. struct page *page;
  2110. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2111. return NULL;
  2112. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2113. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2114. free = 1;
  2115. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2116. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2117. free = 0;
  2118. break;
  2119. }
  2120. }
  2121. if (free) {
  2122. list_del_init(&entry->list);
  2123. return entry;
  2124. }
  2125. }
  2126. /* no free buffer in pool so take first one and swap pages */
  2127. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2128. struct qeth_buffer_pool_entry, list);
  2129. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2130. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2131. page = alloc_page(GFP_ATOMIC);
  2132. if (!page) {
  2133. return NULL;
  2134. } else {
  2135. free_page((unsigned long)entry->elements[i]);
  2136. entry->elements[i] = page_address(page);
  2137. if (card->options.performance_stats)
  2138. card->perf_stats.sg_alloc_page_rx++;
  2139. }
  2140. }
  2141. }
  2142. list_del_init(&entry->list);
  2143. return entry;
  2144. }
  2145. static int qeth_init_input_buffer(struct qeth_card *card,
  2146. struct qeth_qdio_buffer *buf)
  2147. {
  2148. struct qeth_buffer_pool_entry *pool_entry;
  2149. int i;
  2150. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2151. if (!pool_entry)
  2152. return 1;
  2153. /*
  2154. * since the buffer is accessed only from the input_tasklet
  2155. * there shouldn't be a need to synchronize; also, since we use
  2156. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2157. * buffers
  2158. */
  2159. buf->pool_entry = pool_entry;
  2160. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2161. buf->buffer->element[i].length = PAGE_SIZE;
  2162. buf->buffer->element[i].addr = pool_entry->elements[i];
  2163. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2164. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2165. else
  2166. buf->buffer->element[i].flags = 0;
  2167. }
  2168. return 0;
  2169. }
  2170. int qeth_init_qdio_queues(struct qeth_card *card)
  2171. {
  2172. int i, j;
  2173. int rc;
  2174. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2175. /* inbound queue */
  2176. memset(card->qdio.in_q->qdio_bufs, 0,
  2177. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2178. qeth_initialize_working_pool_list(card);
  2179. /*give only as many buffers to hardware as we have buffer pool entries*/
  2180. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2181. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2182. card->qdio.in_q->next_buf_to_init =
  2183. card->qdio.in_buf_pool.buf_count - 1;
  2184. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2185. card->qdio.in_buf_pool.buf_count - 1);
  2186. if (rc) {
  2187. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2188. return rc;
  2189. }
  2190. /* outbound queue */
  2191. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2192. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2193. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2194. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2195. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2196. &card->qdio.out_qs[i]->bufs[j]);
  2197. }
  2198. card->qdio.out_qs[i]->card = card;
  2199. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2200. card->qdio.out_qs[i]->do_pack = 0;
  2201. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2202. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2203. atomic_set(&card->qdio.out_qs[i]->state,
  2204. QETH_OUT_Q_UNLOCKED);
  2205. }
  2206. return 0;
  2207. }
  2208. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2209. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2210. {
  2211. switch (link_type) {
  2212. case QETH_LINK_TYPE_HSTR:
  2213. return 2;
  2214. default:
  2215. return 1;
  2216. }
  2217. }
  2218. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2219. struct qeth_ipa_cmd *cmd, __u8 command,
  2220. enum qeth_prot_versions prot)
  2221. {
  2222. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2223. cmd->hdr.command = command;
  2224. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2225. cmd->hdr.seqno = card->seqno.ipa;
  2226. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2227. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2228. if (card->options.layer2)
  2229. cmd->hdr.prim_version_no = 2;
  2230. else
  2231. cmd->hdr.prim_version_no = 1;
  2232. cmd->hdr.param_count = 1;
  2233. cmd->hdr.prot_version = prot;
  2234. cmd->hdr.ipa_supported = 0;
  2235. cmd->hdr.ipa_enabled = 0;
  2236. }
  2237. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2238. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2239. {
  2240. struct qeth_cmd_buffer *iob;
  2241. struct qeth_ipa_cmd *cmd;
  2242. iob = qeth_wait_for_buffer(&card->write);
  2243. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2244. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2245. return iob;
  2246. }
  2247. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2248. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2249. char prot_type)
  2250. {
  2251. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2252. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2253. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2254. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2255. }
  2256. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2257. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2258. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2259. unsigned long),
  2260. void *reply_param)
  2261. {
  2262. int rc;
  2263. char prot_type;
  2264. QETH_CARD_TEXT(card, 4, "sendipa");
  2265. if (card->options.layer2)
  2266. if (card->info.type == QETH_CARD_TYPE_OSN)
  2267. prot_type = QETH_PROT_OSN2;
  2268. else
  2269. prot_type = QETH_PROT_LAYER2;
  2270. else
  2271. prot_type = QETH_PROT_TCPIP;
  2272. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2273. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2274. iob, reply_cb, reply_param);
  2275. return rc;
  2276. }
  2277. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2278. static int qeth_send_startstoplan(struct qeth_card *card,
  2279. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2280. {
  2281. int rc;
  2282. struct qeth_cmd_buffer *iob;
  2283. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2284. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2285. return rc;
  2286. }
  2287. int qeth_send_startlan(struct qeth_card *card)
  2288. {
  2289. int rc;
  2290. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2291. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2292. return rc;
  2293. }
  2294. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2295. int qeth_send_stoplan(struct qeth_card *card)
  2296. {
  2297. int rc = 0;
  2298. /*
  2299. * TODO: according to the IPA format document page 14,
  2300. * TCP/IP (we!) never issue a STOPLAN
  2301. * is this right ?!?
  2302. */
  2303. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2304. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2305. return rc;
  2306. }
  2307. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2308. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2309. struct qeth_reply *reply, unsigned long data)
  2310. {
  2311. struct qeth_ipa_cmd *cmd;
  2312. QETH_CARD_TEXT(card, 4, "defadpcb");
  2313. cmd = (struct qeth_ipa_cmd *) data;
  2314. if (cmd->hdr.return_code == 0)
  2315. cmd->hdr.return_code =
  2316. cmd->data.setadapterparms.hdr.return_code;
  2317. return 0;
  2318. }
  2319. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2320. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2321. struct qeth_reply *reply, unsigned long data)
  2322. {
  2323. struct qeth_ipa_cmd *cmd;
  2324. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2325. cmd = (struct qeth_ipa_cmd *) data;
  2326. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2327. card->info.link_type =
  2328. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2329. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2330. }
  2331. card->options.adp.supported_funcs =
  2332. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2333. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2334. }
  2335. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2336. __u32 command, __u32 cmdlen)
  2337. {
  2338. struct qeth_cmd_buffer *iob;
  2339. struct qeth_ipa_cmd *cmd;
  2340. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2341. QETH_PROT_IPV4);
  2342. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2343. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2344. cmd->data.setadapterparms.hdr.command_code = command;
  2345. cmd->data.setadapterparms.hdr.used_total = 1;
  2346. cmd->data.setadapterparms.hdr.seq_no = 1;
  2347. return iob;
  2348. }
  2349. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2350. int qeth_query_setadapterparms(struct qeth_card *card)
  2351. {
  2352. int rc;
  2353. struct qeth_cmd_buffer *iob;
  2354. QETH_CARD_TEXT(card, 3, "queryadp");
  2355. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2356. sizeof(struct qeth_ipacmd_setadpparms));
  2357. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2358. return rc;
  2359. }
  2360. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2361. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2362. unsigned int qdio_error, const char *dbftext)
  2363. {
  2364. if (qdio_error) {
  2365. QETH_CARD_TEXT(card, 2, dbftext);
  2366. QETH_DBF_TEXT(QERR, 2, dbftext);
  2367. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2368. buf->element[15].flags & 0xff);
  2369. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2370. buf->element[14].flags & 0xff);
  2371. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2372. if ((buf->element[15].flags & 0xff) == 0x12) {
  2373. card->stats.rx_dropped++;
  2374. return 0;
  2375. } else
  2376. return 1;
  2377. }
  2378. return 0;
  2379. }
  2380. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2381. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2382. {
  2383. struct qeth_qdio_q *queue = card->qdio.in_q;
  2384. int count;
  2385. int i;
  2386. int rc;
  2387. int newcount = 0;
  2388. count = (index < queue->next_buf_to_init)?
  2389. card->qdio.in_buf_pool.buf_count -
  2390. (queue->next_buf_to_init - index) :
  2391. card->qdio.in_buf_pool.buf_count -
  2392. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2393. /* only requeue at a certain threshold to avoid SIGAs */
  2394. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2395. for (i = queue->next_buf_to_init;
  2396. i < queue->next_buf_to_init + count; ++i) {
  2397. if (qeth_init_input_buffer(card,
  2398. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2399. break;
  2400. } else {
  2401. newcount++;
  2402. }
  2403. }
  2404. if (newcount < count) {
  2405. /* we are in memory shortage so we switch back to
  2406. traditional skb allocation and drop packages */
  2407. atomic_set(&card->force_alloc_skb, 3);
  2408. count = newcount;
  2409. } else {
  2410. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2411. }
  2412. /*
  2413. * according to old code it should be avoided to requeue all
  2414. * 128 buffers in order to benefit from PCI avoidance.
  2415. * this function keeps at least one buffer (the buffer at
  2416. * 'index') un-requeued -> this buffer is the first buffer that
  2417. * will be requeued the next time
  2418. */
  2419. if (card->options.performance_stats) {
  2420. card->perf_stats.inbound_do_qdio_cnt++;
  2421. card->perf_stats.inbound_do_qdio_start_time =
  2422. qeth_get_micros();
  2423. }
  2424. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2425. queue->next_buf_to_init, count);
  2426. if (card->options.performance_stats)
  2427. card->perf_stats.inbound_do_qdio_time +=
  2428. qeth_get_micros() -
  2429. card->perf_stats.inbound_do_qdio_start_time;
  2430. if (rc) {
  2431. dev_warn(&card->gdev->dev,
  2432. "QDIO reported an error, rc=%i\n", rc);
  2433. QETH_CARD_TEXT(card, 2, "qinberr");
  2434. }
  2435. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2436. QDIO_MAX_BUFFERS_PER_Q;
  2437. }
  2438. }
  2439. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2440. static int qeth_handle_send_error(struct qeth_card *card,
  2441. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2442. {
  2443. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2444. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2445. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2446. if (sbalf15 == 0) {
  2447. qdio_err = 0;
  2448. } else {
  2449. qdio_err = 1;
  2450. }
  2451. }
  2452. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2453. if (!qdio_err)
  2454. return QETH_SEND_ERROR_NONE;
  2455. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2456. return QETH_SEND_ERROR_RETRY;
  2457. QETH_CARD_TEXT(card, 1, "lnkfail");
  2458. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2459. (u16)qdio_err, (u8)sbalf15);
  2460. return QETH_SEND_ERROR_LINK_FAILURE;
  2461. }
  2462. /*
  2463. * Switched to packing state if the number of used buffers on a queue
  2464. * reaches a certain limit.
  2465. */
  2466. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2467. {
  2468. if (!queue->do_pack) {
  2469. if (atomic_read(&queue->used_buffers)
  2470. >= QETH_HIGH_WATERMARK_PACK){
  2471. /* switch non-PACKING -> PACKING */
  2472. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2473. if (queue->card->options.performance_stats)
  2474. queue->card->perf_stats.sc_dp_p++;
  2475. queue->do_pack = 1;
  2476. }
  2477. }
  2478. }
  2479. /*
  2480. * Switches from packing to non-packing mode. If there is a packing
  2481. * buffer on the queue this buffer will be prepared to be flushed.
  2482. * In that case 1 is returned to inform the caller. If no buffer
  2483. * has to be flushed, zero is returned.
  2484. */
  2485. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2486. {
  2487. struct qeth_qdio_out_buffer *buffer;
  2488. int flush_count = 0;
  2489. if (queue->do_pack) {
  2490. if (atomic_read(&queue->used_buffers)
  2491. <= QETH_LOW_WATERMARK_PACK) {
  2492. /* switch PACKING -> non-PACKING */
  2493. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2494. if (queue->card->options.performance_stats)
  2495. queue->card->perf_stats.sc_p_dp++;
  2496. queue->do_pack = 0;
  2497. /* flush packing buffers */
  2498. buffer = &queue->bufs[queue->next_buf_to_fill];
  2499. if ((atomic_read(&buffer->state) ==
  2500. QETH_QDIO_BUF_EMPTY) &&
  2501. (buffer->next_element_to_fill > 0)) {
  2502. atomic_set(&buffer->state,
  2503. QETH_QDIO_BUF_PRIMED);
  2504. flush_count++;
  2505. queue->next_buf_to_fill =
  2506. (queue->next_buf_to_fill + 1) %
  2507. QDIO_MAX_BUFFERS_PER_Q;
  2508. }
  2509. }
  2510. }
  2511. return flush_count;
  2512. }
  2513. /*
  2514. * Called to flush a packing buffer if no more pci flags are on the queue.
  2515. * Checks if there is a packing buffer and prepares it to be flushed.
  2516. * In that case returns 1, otherwise zero.
  2517. */
  2518. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2519. {
  2520. struct qeth_qdio_out_buffer *buffer;
  2521. buffer = &queue->bufs[queue->next_buf_to_fill];
  2522. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2523. (buffer->next_element_to_fill > 0)) {
  2524. /* it's a packing buffer */
  2525. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2526. queue->next_buf_to_fill =
  2527. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2528. return 1;
  2529. }
  2530. return 0;
  2531. }
  2532. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2533. int count)
  2534. {
  2535. struct qeth_qdio_out_buffer *buf;
  2536. int rc;
  2537. int i;
  2538. unsigned int qdio_flags;
  2539. for (i = index; i < index + count; ++i) {
  2540. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2541. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2542. SBAL_FLAGS_LAST_ENTRY;
  2543. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2544. continue;
  2545. if (!queue->do_pack) {
  2546. if ((atomic_read(&queue->used_buffers) >=
  2547. (QETH_HIGH_WATERMARK_PACK -
  2548. QETH_WATERMARK_PACK_FUZZ)) &&
  2549. !atomic_read(&queue->set_pci_flags_count)) {
  2550. /* it's likely that we'll go to packing
  2551. * mode soon */
  2552. atomic_inc(&queue->set_pci_flags_count);
  2553. buf->buffer->element[0].flags |= 0x40;
  2554. }
  2555. } else {
  2556. if (!atomic_read(&queue->set_pci_flags_count)) {
  2557. /*
  2558. * there's no outstanding PCI any more, so we
  2559. * have to request a PCI to be sure the the PCI
  2560. * will wake at some time in the future then we
  2561. * can flush packed buffers that might still be
  2562. * hanging around, which can happen if no
  2563. * further send was requested by the stack
  2564. */
  2565. atomic_inc(&queue->set_pci_flags_count);
  2566. buf->buffer->element[0].flags |= 0x40;
  2567. }
  2568. }
  2569. }
  2570. queue->sync_iqdio_error = 0;
  2571. queue->card->dev->trans_start = jiffies;
  2572. if (queue->card->options.performance_stats) {
  2573. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2574. queue->card->perf_stats.outbound_do_qdio_start_time =
  2575. qeth_get_micros();
  2576. }
  2577. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2578. if (atomic_read(&queue->set_pci_flags_count))
  2579. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2580. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2581. queue->queue_no, index, count);
  2582. if (queue->card->options.performance_stats)
  2583. queue->card->perf_stats.outbound_do_qdio_time +=
  2584. qeth_get_micros() -
  2585. queue->card->perf_stats.outbound_do_qdio_start_time;
  2586. if (rc > 0) {
  2587. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2588. queue->sync_iqdio_error = rc & 3;
  2589. }
  2590. if (rc) {
  2591. queue->card->stats.tx_errors += count;
  2592. /* ignore temporary SIGA errors without busy condition */
  2593. if (rc == QDIO_ERROR_SIGA_TARGET)
  2594. return;
  2595. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2596. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2597. /* this must not happen under normal circumstances. if it
  2598. * happens something is really wrong -> recover */
  2599. qeth_schedule_recovery(queue->card);
  2600. return;
  2601. }
  2602. atomic_add(count, &queue->used_buffers);
  2603. if (queue->card->options.performance_stats)
  2604. queue->card->perf_stats.bufs_sent += count;
  2605. }
  2606. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2607. {
  2608. int index;
  2609. int flush_cnt = 0;
  2610. int q_was_packing = 0;
  2611. /*
  2612. * check if weed have to switch to non-packing mode or if
  2613. * we have to get a pci flag out on the queue
  2614. */
  2615. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2616. !atomic_read(&queue->set_pci_flags_count)) {
  2617. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2618. QETH_OUT_Q_UNLOCKED) {
  2619. /*
  2620. * If we get in here, there was no action in
  2621. * do_send_packet. So, we check if there is a
  2622. * packing buffer to be flushed here.
  2623. */
  2624. netif_stop_queue(queue->card->dev);
  2625. index = queue->next_buf_to_fill;
  2626. q_was_packing = queue->do_pack;
  2627. /* queue->do_pack may change */
  2628. barrier();
  2629. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2630. if (!flush_cnt &&
  2631. !atomic_read(&queue->set_pci_flags_count))
  2632. flush_cnt +=
  2633. qeth_flush_buffers_on_no_pci(queue);
  2634. if (queue->card->options.performance_stats &&
  2635. q_was_packing)
  2636. queue->card->perf_stats.bufs_sent_pack +=
  2637. flush_cnt;
  2638. if (flush_cnt)
  2639. qeth_flush_buffers(queue, index, flush_cnt);
  2640. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2641. }
  2642. }
  2643. }
  2644. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2645. unsigned int qdio_error, int __queue, int first_element,
  2646. int count, unsigned long card_ptr)
  2647. {
  2648. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2649. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2650. struct qeth_qdio_out_buffer *buffer;
  2651. int i;
  2652. unsigned qeth_send_err;
  2653. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2654. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2655. QETH_CARD_TEXT(card, 2, "achkcond");
  2656. netif_stop_queue(card->dev);
  2657. qeth_schedule_recovery(card);
  2658. return;
  2659. }
  2660. if (card->options.performance_stats) {
  2661. card->perf_stats.outbound_handler_cnt++;
  2662. card->perf_stats.outbound_handler_start_time =
  2663. qeth_get_micros();
  2664. }
  2665. for (i = first_element; i < (first_element + count); ++i) {
  2666. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2667. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2668. __qeth_clear_output_buffer(queue, buffer,
  2669. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2670. }
  2671. atomic_sub(count, &queue->used_buffers);
  2672. /* check if we need to do something on this outbound queue */
  2673. if (card->info.type != QETH_CARD_TYPE_IQD)
  2674. qeth_check_outbound_queue(queue);
  2675. netif_wake_queue(queue->card->dev);
  2676. if (card->options.performance_stats)
  2677. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2678. card->perf_stats.outbound_handler_start_time;
  2679. }
  2680. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2681. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2682. int ipv, int cast_type)
  2683. {
  2684. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2685. card->info.type == QETH_CARD_TYPE_OSX))
  2686. return card->qdio.default_out_queue;
  2687. switch (card->qdio.no_out_queues) {
  2688. case 4:
  2689. if (cast_type && card->info.is_multicast_different)
  2690. return card->info.is_multicast_different &
  2691. (card->qdio.no_out_queues - 1);
  2692. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2693. const u8 tos = ip_hdr(skb)->tos;
  2694. if (card->qdio.do_prio_queueing ==
  2695. QETH_PRIO_Q_ING_TOS) {
  2696. if (tos & IP_TOS_NOTIMPORTANT)
  2697. return 3;
  2698. if (tos & IP_TOS_HIGHRELIABILITY)
  2699. return 2;
  2700. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2701. return 1;
  2702. if (tos & IP_TOS_LOWDELAY)
  2703. return 0;
  2704. }
  2705. if (card->qdio.do_prio_queueing ==
  2706. QETH_PRIO_Q_ING_PREC)
  2707. return 3 - (tos >> 6);
  2708. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2709. /* TODO: IPv6!!! */
  2710. }
  2711. return card->qdio.default_out_queue;
  2712. case 1: /* fallthrough for single-out-queue 1920-device */
  2713. default:
  2714. return card->qdio.default_out_queue;
  2715. }
  2716. }
  2717. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2718. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2719. struct sk_buff *skb, int elems)
  2720. {
  2721. int elements_needed = 0;
  2722. if (skb_shinfo(skb)->nr_frags > 0)
  2723. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2724. if (elements_needed == 0)
  2725. elements_needed = 1 + (((((unsigned long) skb->data) %
  2726. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2727. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2728. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2729. "(Number=%d / Length=%d). Discarded.\n",
  2730. (elements_needed+elems), skb->len);
  2731. return 0;
  2732. }
  2733. return elements_needed;
  2734. }
  2735. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2736. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2737. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2738. int offset)
  2739. {
  2740. int length = skb->len;
  2741. int length_here;
  2742. int element;
  2743. char *data;
  2744. int first_lap ;
  2745. element = *next_element_to_fill;
  2746. data = skb->data;
  2747. first_lap = (is_tso == 0 ? 1 : 0);
  2748. if (offset >= 0) {
  2749. data = skb->data + offset;
  2750. length -= offset;
  2751. first_lap = 0;
  2752. }
  2753. while (length > 0) {
  2754. /* length_here is the remaining amount of data in this page */
  2755. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2756. if (length < length_here)
  2757. length_here = length;
  2758. buffer->element[element].addr = data;
  2759. buffer->element[element].length = length_here;
  2760. length -= length_here;
  2761. if (!length) {
  2762. if (first_lap)
  2763. buffer->element[element].flags = 0;
  2764. else
  2765. buffer->element[element].flags =
  2766. SBAL_FLAGS_LAST_FRAG;
  2767. } else {
  2768. if (first_lap)
  2769. buffer->element[element].flags =
  2770. SBAL_FLAGS_FIRST_FRAG;
  2771. else
  2772. buffer->element[element].flags =
  2773. SBAL_FLAGS_MIDDLE_FRAG;
  2774. }
  2775. data += length_here;
  2776. element++;
  2777. first_lap = 0;
  2778. }
  2779. *next_element_to_fill = element;
  2780. }
  2781. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2782. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2783. struct qeth_hdr *hdr, int offset, int hd_len)
  2784. {
  2785. struct qdio_buffer *buffer;
  2786. int flush_cnt = 0, hdr_len, large_send = 0;
  2787. buffer = buf->buffer;
  2788. atomic_inc(&skb->users);
  2789. skb_queue_tail(&buf->skb_list, skb);
  2790. /*check first on TSO ....*/
  2791. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2792. int element = buf->next_element_to_fill;
  2793. hdr_len = sizeof(struct qeth_hdr_tso) +
  2794. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2795. /*fill first buffer entry only with header information */
  2796. buffer->element[element].addr = skb->data;
  2797. buffer->element[element].length = hdr_len;
  2798. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2799. buf->next_element_to_fill++;
  2800. skb->data += hdr_len;
  2801. skb->len -= hdr_len;
  2802. large_send = 1;
  2803. }
  2804. if (offset >= 0) {
  2805. int element = buf->next_element_to_fill;
  2806. buffer->element[element].addr = hdr;
  2807. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2808. hd_len;
  2809. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2810. buf->is_header[element] = 1;
  2811. buf->next_element_to_fill++;
  2812. }
  2813. if (skb_shinfo(skb)->nr_frags == 0)
  2814. __qeth_fill_buffer(skb, buffer, large_send,
  2815. (int *)&buf->next_element_to_fill, offset);
  2816. else
  2817. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2818. (int *)&buf->next_element_to_fill);
  2819. if (!queue->do_pack) {
  2820. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2821. /* set state to PRIMED -> will be flushed */
  2822. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2823. flush_cnt = 1;
  2824. } else {
  2825. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2826. if (queue->card->options.performance_stats)
  2827. queue->card->perf_stats.skbs_sent_pack++;
  2828. if (buf->next_element_to_fill >=
  2829. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2830. /*
  2831. * packed buffer if full -> set state PRIMED
  2832. * -> will be flushed
  2833. */
  2834. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2835. flush_cnt = 1;
  2836. }
  2837. }
  2838. return flush_cnt;
  2839. }
  2840. int qeth_do_send_packet_fast(struct qeth_card *card,
  2841. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2842. struct qeth_hdr *hdr, int elements_needed,
  2843. int offset, int hd_len)
  2844. {
  2845. struct qeth_qdio_out_buffer *buffer;
  2846. struct sk_buff *skb1;
  2847. struct qeth_skb_data *retry_ctrl;
  2848. int index;
  2849. int rc;
  2850. /* spin until we get the queue ... */
  2851. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2852. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2853. /* ... now we've got the queue */
  2854. index = queue->next_buf_to_fill;
  2855. buffer = &queue->bufs[queue->next_buf_to_fill];
  2856. /*
  2857. * check if buffer is empty to make sure that we do not 'overtake'
  2858. * ourselves and try to fill a buffer that is already primed
  2859. */
  2860. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2861. goto out;
  2862. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2863. QDIO_MAX_BUFFERS_PER_Q;
  2864. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2865. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2866. qeth_flush_buffers(queue, index, 1);
  2867. if (queue->sync_iqdio_error == 2) {
  2868. skb1 = skb_dequeue(&buffer->skb_list);
  2869. while (skb1) {
  2870. atomic_dec(&skb1->users);
  2871. skb1 = skb_dequeue(&buffer->skb_list);
  2872. }
  2873. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2874. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2875. retry_ctrl->magic = QETH_SKB_MAGIC;
  2876. retry_ctrl->count = 0;
  2877. }
  2878. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2879. retry_ctrl->count++;
  2880. rc = dev_queue_xmit(skb);
  2881. } else {
  2882. dev_kfree_skb_any(skb);
  2883. QETH_DBF_TEXT(QERR, 2, "qrdrop");
  2884. }
  2885. }
  2886. return 0;
  2887. out:
  2888. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2889. return -EBUSY;
  2890. }
  2891. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2892. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2893. struct sk_buff *skb, struct qeth_hdr *hdr,
  2894. int elements_needed)
  2895. {
  2896. struct qeth_qdio_out_buffer *buffer;
  2897. int start_index;
  2898. int flush_count = 0;
  2899. int do_pack = 0;
  2900. int tmp;
  2901. int rc = 0;
  2902. /* spin until we get the queue ... */
  2903. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2904. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2905. start_index = queue->next_buf_to_fill;
  2906. buffer = &queue->bufs[queue->next_buf_to_fill];
  2907. /*
  2908. * check if buffer is empty to make sure that we do not 'overtake'
  2909. * ourselves and try to fill a buffer that is already primed
  2910. */
  2911. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2912. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2913. return -EBUSY;
  2914. }
  2915. /* check if we need to switch packing state of this queue */
  2916. qeth_switch_to_packing_if_needed(queue);
  2917. if (queue->do_pack) {
  2918. do_pack = 1;
  2919. /* does packet fit in current buffer? */
  2920. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2921. buffer->next_element_to_fill) < elements_needed) {
  2922. /* ... no -> set state PRIMED */
  2923. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2924. flush_count++;
  2925. queue->next_buf_to_fill =
  2926. (queue->next_buf_to_fill + 1) %
  2927. QDIO_MAX_BUFFERS_PER_Q;
  2928. buffer = &queue->bufs[queue->next_buf_to_fill];
  2929. /* we did a step forward, so check buffer state
  2930. * again */
  2931. if (atomic_read(&buffer->state) !=
  2932. QETH_QDIO_BUF_EMPTY) {
  2933. qeth_flush_buffers(queue, start_index,
  2934. flush_count);
  2935. atomic_set(&queue->state,
  2936. QETH_OUT_Q_UNLOCKED);
  2937. return -EBUSY;
  2938. }
  2939. }
  2940. }
  2941. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2942. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2943. QDIO_MAX_BUFFERS_PER_Q;
  2944. flush_count += tmp;
  2945. if (flush_count)
  2946. qeth_flush_buffers(queue, start_index, flush_count);
  2947. else if (!atomic_read(&queue->set_pci_flags_count))
  2948. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2949. /*
  2950. * queue->state will go from LOCKED -> UNLOCKED or from
  2951. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2952. * (switch packing state or flush buffer to get another pci flag out).
  2953. * In that case we will enter this loop
  2954. */
  2955. while (atomic_dec_return(&queue->state)) {
  2956. flush_count = 0;
  2957. start_index = queue->next_buf_to_fill;
  2958. /* check if we can go back to non-packing state */
  2959. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2960. /*
  2961. * check if we need to flush a packing buffer to get a pci
  2962. * flag out on the queue
  2963. */
  2964. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2965. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2966. if (flush_count)
  2967. qeth_flush_buffers(queue, start_index, flush_count);
  2968. }
  2969. /* at this point the queue is UNLOCKED again */
  2970. if (queue->card->options.performance_stats && do_pack)
  2971. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2972. return rc;
  2973. }
  2974. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2975. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2976. struct qeth_reply *reply, unsigned long data)
  2977. {
  2978. struct qeth_ipa_cmd *cmd;
  2979. struct qeth_ipacmd_setadpparms *setparms;
  2980. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2981. cmd = (struct qeth_ipa_cmd *) data;
  2982. setparms = &(cmd->data.setadapterparms);
  2983. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2984. if (cmd->hdr.return_code) {
  2985. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2986. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2987. }
  2988. card->info.promisc_mode = setparms->data.mode;
  2989. return 0;
  2990. }
  2991. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2992. {
  2993. enum qeth_ipa_promisc_modes mode;
  2994. struct net_device *dev = card->dev;
  2995. struct qeth_cmd_buffer *iob;
  2996. struct qeth_ipa_cmd *cmd;
  2997. QETH_CARD_TEXT(card, 4, "setprom");
  2998. if (((dev->flags & IFF_PROMISC) &&
  2999. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3000. (!(dev->flags & IFF_PROMISC) &&
  3001. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3002. return;
  3003. mode = SET_PROMISC_MODE_OFF;
  3004. if (dev->flags & IFF_PROMISC)
  3005. mode = SET_PROMISC_MODE_ON;
  3006. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3007. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3008. sizeof(struct qeth_ipacmd_setadpparms));
  3009. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3010. cmd->data.setadapterparms.data.mode = mode;
  3011. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3012. }
  3013. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3014. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3015. {
  3016. struct qeth_card *card;
  3017. char dbf_text[15];
  3018. card = dev->ml_priv;
  3019. QETH_CARD_TEXT(card, 4, "chgmtu");
  3020. sprintf(dbf_text, "%8x", new_mtu);
  3021. QETH_CARD_TEXT(card, 4, dbf_text);
  3022. if (new_mtu < 64)
  3023. return -EINVAL;
  3024. if (new_mtu > 65535)
  3025. return -EINVAL;
  3026. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3027. (!qeth_mtu_is_valid(card, new_mtu)))
  3028. return -EINVAL;
  3029. dev->mtu = new_mtu;
  3030. return 0;
  3031. }
  3032. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3033. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3034. {
  3035. struct qeth_card *card;
  3036. card = dev->ml_priv;
  3037. QETH_CARD_TEXT(card, 5, "getstat");
  3038. return &card->stats;
  3039. }
  3040. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3041. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3042. struct qeth_reply *reply, unsigned long data)
  3043. {
  3044. struct qeth_ipa_cmd *cmd;
  3045. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3046. cmd = (struct qeth_ipa_cmd *) data;
  3047. if (!card->options.layer2 ||
  3048. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3049. memcpy(card->dev->dev_addr,
  3050. &cmd->data.setadapterparms.data.change_addr.addr,
  3051. OSA_ADDR_LEN);
  3052. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3053. }
  3054. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3055. return 0;
  3056. }
  3057. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3058. {
  3059. int rc;
  3060. struct qeth_cmd_buffer *iob;
  3061. struct qeth_ipa_cmd *cmd;
  3062. QETH_CARD_TEXT(card, 4, "chgmac");
  3063. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3064. sizeof(struct qeth_ipacmd_setadpparms));
  3065. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3066. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3067. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3068. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3069. card->dev->dev_addr, OSA_ADDR_LEN);
  3070. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3071. NULL);
  3072. return rc;
  3073. }
  3074. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3075. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3076. struct qeth_reply *reply, unsigned long data)
  3077. {
  3078. struct qeth_ipa_cmd *cmd;
  3079. struct qeth_set_access_ctrl *access_ctrl_req;
  3080. int rc;
  3081. QETH_CARD_TEXT(card, 4, "setaccb");
  3082. cmd = (struct qeth_ipa_cmd *) data;
  3083. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3084. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3085. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3086. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3087. cmd->data.setadapterparms.hdr.return_code);
  3088. switch (cmd->data.setadapterparms.hdr.return_code) {
  3089. case SET_ACCESS_CTRL_RC_SUCCESS:
  3090. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3091. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3092. {
  3093. card->options.isolation = access_ctrl_req->subcmd_code;
  3094. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3095. dev_info(&card->gdev->dev,
  3096. "QDIO data connection isolation is deactivated\n");
  3097. } else {
  3098. dev_info(&card->gdev->dev,
  3099. "QDIO data connection isolation is activated\n");
  3100. }
  3101. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3102. card->gdev->dev.kobj.name,
  3103. access_ctrl_req->subcmd_code,
  3104. cmd->data.setadapterparms.hdr.return_code);
  3105. rc = 0;
  3106. break;
  3107. }
  3108. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3109. {
  3110. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3111. card->gdev->dev.kobj.name,
  3112. access_ctrl_req->subcmd_code,
  3113. cmd->data.setadapterparms.hdr.return_code);
  3114. dev_err(&card->gdev->dev, "Adapter does not "
  3115. "support QDIO data connection isolation\n");
  3116. /* ensure isolation mode is "none" */
  3117. card->options.isolation = ISOLATION_MODE_NONE;
  3118. rc = -EOPNOTSUPP;
  3119. break;
  3120. }
  3121. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3122. {
  3123. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3124. card->gdev->dev.kobj.name,
  3125. access_ctrl_req->subcmd_code,
  3126. cmd->data.setadapterparms.hdr.return_code);
  3127. dev_err(&card->gdev->dev,
  3128. "Adapter is dedicated. "
  3129. "QDIO data connection isolation not supported\n");
  3130. /* ensure isolation mode is "none" */
  3131. card->options.isolation = ISOLATION_MODE_NONE;
  3132. rc = -EOPNOTSUPP;
  3133. break;
  3134. }
  3135. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3136. {
  3137. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3138. card->gdev->dev.kobj.name,
  3139. access_ctrl_req->subcmd_code,
  3140. cmd->data.setadapterparms.hdr.return_code);
  3141. dev_err(&card->gdev->dev,
  3142. "TSO does not permit QDIO data connection isolation\n");
  3143. /* ensure isolation mode is "none" */
  3144. card->options.isolation = ISOLATION_MODE_NONE;
  3145. rc = -EPERM;
  3146. break;
  3147. }
  3148. default:
  3149. {
  3150. /* this should never happen */
  3151. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3152. "==UNKNOWN\n",
  3153. card->gdev->dev.kobj.name,
  3154. access_ctrl_req->subcmd_code,
  3155. cmd->data.setadapterparms.hdr.return_code);
  3156. /* ensure isolation mode is "none" */
  3157. card->options.isolation = ISOLATION_MODE_NONE;
  3158. rc = 0;
  3159. break;
  3160. }
  3161. }
  3162. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3163. return rc;
  3164. }
  3165. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3166. enum qeth_ipa_isolation_modes isolation)
  3167. {
  3168. int rc;
  3169. struct qeth_cmd_buffer *iob;
  3170. struct qeth_ipa_cmd *cmd;
  3171. struct qeth_set_access_ctrl *access_ctrl_req;
  3172. QETH_CARD_TEXT(card, 4, "setacctl");
  3173. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3174. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3175. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3176. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3177. sizeof(struct qeth_set_access_ctrl));
  3178. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3179. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3180. access_ctrl_req->subcmd_code = isolation;
  3181. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3182. NULL);
  3183. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3184. return rc;
  3185. }
  3186. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3187. {
  3188. int rc = 0;
  3189. QETH_CARD_TEXT(card, 4, "setactlo");
  3190. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3191. card->info.type == QETH_CARD_TYPE_OSX) &&
  3192. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3193. rc = qeth_setadpparms_set_access_ctrl(card,
  3194. card->options.isolation);
  3195. if (rc) {
  3196. QETH_DBF_MESSAGE(3,
  3197. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3198. card->gdev->dev.kobj.name,
  3199. rc);
  3200. }
  3201. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3202. card->options.isolation = ISOLATION_MODE_NONE;
  3203. dev_err(&card->gdev->dev, "Adapter does not "
  3204. "support QDIO data connection isolation\n");
  3205. rc = -EOPNOTSUPP;
  3206. }
  3207. return rc;
  3208. }
  3209. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3210. void qeth_tx_timeout(struct net_device *dev)
  3211. {
  3212. struct qeth_card *card;
  3213. card = dev->ml_priv;
  3214. QETH_CARD_TEXT(card, 4, "txtimeo");
  3215. card->stats.tx_errors++;
  3216. qeth_schedule_recovery(card);
  3217. }
  3218. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3219. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3220. {
  3221. struct qeth_card *card = dev->ml_priv;
  3222. int rc = 0;
  3223. switch (regnum) {
  3224. case MII_BMCR: /* Basic mode control register */
  3225. rc = BMCR_FULLDPLX;
  3226. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3227. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3228. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3229. rc |= BMCR_SPEED100;
  3230. break;
  3231. case MII_BMSR: /* Basic mode status register */
  3232. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3233. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3234. BMSR_100BASE4;
  3235. break;
  3236. case MII_PHYSID1: /* PHYS ID 1 */
  3237. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3238. dev->dev_addr[2];
  3239. rc = (rc >> 5) & 0xFFFF;
  3240. break;
  3241. case MII_PHYSID2: /* PHYS ID 2 */
  3242. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3243. break;
  3244. case MII_ADVERTISE: /* Advertisement control reg */
  3245. rc = ADVERTISE_ALL;
  3246. break;
  3247. case MII_LPA: /* Link partner ability reg */
  3248. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3249. LPA_100BASE4 | LPA_LPACK;
  3250. break;
  3251. case MII_EXPANSION: /* Expansion register */
  3252. break;
  3253. case MII_DCOUNTER: /* disconnect counter */
  3254. break;
  3255. case MII_FCSCOUNTER: /* false carrier counter */
  3256. break;
  3257. case MII_NWAYTEST: /* N-way auto-neg test register */
  3258. break;
  3259. case MII_RERRCOUNTER: /* rx error counter */
  3260. rc = card->stats.rx_errors;
  3261. break;
  3262. case MII_SREVISION: /* silicon revision */
  3263. break;
  3264. case MII_RESV1: /* reserved 1 */
  3265. break;
  3266. case MII_LBRERROR: /* loopback, rx, bypass error */
  3267. break;
  3268. case MII_PHYADDR: /* physical address */
  3269. break;
  3270. case MII_RESV2: /* reserved 2 */
  3271. break;
  3272. case MII_TPISTATUS: /* TPI status for 10mbps */
  3273. break;
  3274. case MII_NCONFIG: /* network interface config */
  3275. break;
  3276. default:
  3277. break;
  3278. }
  3279. return rc;
  3280. }
  3281. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3282. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3283. struct qeth_cmd_buffer *iob, int len,
  3284. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3285. unsigned long),
  3286. void *reply_param)
  3287. {
  3288. u16 s1, s2;
  3289. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3290. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3291. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3292. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3293. /* adjust PDU length fields in IPA_PDU_HEADER */
  3294. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3295. s2 = (u32) len;
  3296. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3297. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3298. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3299. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3300. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3301. reply_cb, reply_param);
  3302. }
  3303. static int qeth_snmp_command_cb(struct qeth_card *card,
  3304. struct qeth_reply *reply, unsigned long sdata)
  3305. {
  3306. struct qeth_ipa_cmd *cmd;
  3307. struct qeth_arp_query_info *qinfo;
  3308. struct qeth_snmp_cmd *snmp;
  3309. unsigned char *data;
  3310. __u16 data_len;
  3311. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3312. cmd = (struct qeth_ipa_cmd *) sdata;
  3313. data = (unsigned char *)((char *)cmd - reply->offset);
  3314. qinfo = (struct qeth_arp_query_info *) reply->param;
  3315. snmp = &cmd->data.setadapterparms.data.snmp;
  3316. if (cmd->hdr.return_code) {
  3317. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3318. return 0;
  3319. }
  3320. if (cmd->data.setadapterparms.hdr.return_code) {
  3321. cmd->hdr.return_code =
  3322. cmd->data.setadapterparms.hdr.return_code;
  3323. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3324. return 0;
  3325. }
  3326. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3327. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3328. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3329. else
  3330. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3331. /* check if there is enough room in userspace */
  3332. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3333. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3334. cmd->hdr.return_code = -ENOMEM;
  3335. return 0;
  3336. }
  3337. QETH_CARD_TEXT_(card, 4, "snore%i",
  3338. cmd->data.setadapterparms.hdr.used_total);
  3339. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3340. cmd->data.setadapterparms.hdr.seq_no);
  3341. /*copy entries to user buffer*/
  3342. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3343. memcpy(qinfo->udata + qinfo->udata_offset,
  3344. (char *)snmp,
  3345. data_len + offsetof(struct qeth_snmp_cmd, data));
  3346. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3347. } else {
  3348. memcpy(qinfo->udata + qinfo->udata_offset,
  3349. (char *)&snmp->request, data_len);
  3350. }
  3351. qinfo->udata_offset += data_len;
  3352. /* check if all replies received ... */
  3353. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3354. cmd->data.setadapterparms.hdr.used_total);
  3355. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3356. cmd->data.setadapterparms.hdr.seq_no);
  3357. if (cmd->data.setadapterparms.hdr.seq_no <
  3358. cmd->data.setadapterparms.hdr.used_total)
  3359. return 1;
  3360. return 0;
  3361. }
  3362. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3363. {
  3364. struct qeth_cmd_buffer *iob;
  3365. struct qeth_ipa_cmd *cmd;
  3366. struct qeth_snmp_ureq *ureq;
  3367. int req_len;
  3368. struct qeth_arp_query_info qinfo = {0, };
  3369. int rc = 0;
  3370. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3371. if (card->info.guestlan)
  3372. return -EOPNOTSUPP;
  3373. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3374. (!card->options.layer2)) {
  3375. return -EOPNOTSUPP;
  3376. }
  3377. /* skip 4 bytes (data_len struct member) to get req_len */
  3378. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3379. return -EFAULT;
  3380. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3381. if (!ureq) {
  3382. QETH_CARD_TEXT(card, 2, "snmpnome");
  3383. return -ENOMEM;
  3384. }
  3385. if (copy_from_user(ureq, udata,
  3386. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3387. kfree(ureq);
  3388. return -EFAULT;
  3389. }
  3390. qinfo.udata_len = ureq->hdr.data_len;
  3391. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3392. if (!qinfo.udata) {
  3393. kfree(ureq);
  3394. return -ENOMEM;
  3395. }
  3396. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3397. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3398. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3399. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3400. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3401. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3402. qeth_snmp_command_cb, (void *)&qinfo);
  3403. if (rc)
  3404. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3405. QETH_CARD_IFNAME(card), rc);
  3406. else {
  3407. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3408. rc = -EFAULT;
  3409. }
  3410. kfree(ureq);
  3411. kfree(qinfo.udata);
  3412. return rc;
  3413. }
  3414. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3415. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3416. {
  3417. switch (card->info.type) {
  3418. case QETH_CARD_TYPE_IQD:
  3419. return 2;
  3420. default:
  3421. return 0;
  3422. }
  3423. }
  3424. static int qeth_qdio_establish(struct qeth_card *card)
  3425. {
  3426. struct qdio_initialize init_data;
  3427. char *qib_param_field;
  3428. struct qdio_buffer **in_sbal_ptrs;
  3429. struct qdio_buffer **out_sbal_ptrs;
  3430. int i, j, k;
  3431. int rc = 0;
  3432. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3433. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3434. GFP_KERNEL);
  3435. if (!qib_param_field)
  3436. return -ENOMEM;
  3437. qeth_create_qib_param_field(card, qib_param_field);
  3438. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3439. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3440. GFP_KERNEL);
  3441. if (!in_sbal_ptrs) {
  3442. kfree(qib_param_field);
  3443. return -ENOMEM;
  3444. }
  3445. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3446. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3447. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3448. out_sbal_ptrs =
  3449. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3450. sizeof(void *), GFP_KERNEL);
  3451. if (!out_sbal_ptrs) {
  3452. kfree(in_sbal_ptrs);
  3453. kfree(qib_param_field);
  3454. return -ENOMEM;
  3455. }
  3456. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3457. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3458. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3459. card->qdio.out_qs[i]->bufs[j].buffer);
  3460. }
  3461. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3462. init_data.cdev = CARD_DDEV(card);
  3463. init_data.q_format = qeth_get_qdio_q_format(card);
  3464. init_data.qib_param_field_format = 0;
  3465. init_data.qib_param_field = qib_param_field;
  3466. init_data.no_input_qs = 1;
  3467. init_data.no_output_qs = card->qdio.no_out_queues;
  3468. init_data.input_handler = card->discipline.input_handler;
  3469. init_data.output_handler = card->discipline.output_handler;
  3470. init_data.int_parm = (unsigned long) card;
  3471. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3472. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3473. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3474. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3475. rc = qdio_allocate(&init_data);
  3476. if (rc) {
  3477. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3478. goto out;
  3479. }
  3480. rc = qdio_establish(&init_data);
  3481. if (rc) {
  3482. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3483. qdio_free(CARD_DDEV(card));
  3484. }
  3485. }
  3486. out:
  3487. kfree(out_sbal_ptrs);
  3488. kfree(in_sbal_ptrs);
  3489. kfree(qib_param_field);
  3490. return rc;
  3491. }
  3492. static void qeth_core_free_card(struct qeth_card *card)
  3493. {
  3494. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3495. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3496. qeth_clean_channel(&card->read);
  3497. qeth_clean_channel(&card->write);
  3498. if (card->dev)
  3499. free_netdev(card->dev);
  3500. kfree(card->ip_tbd_list);
  3501. qeth_free_qdio_buffers(card);
  3502. unregister_service_level(&card->qeth_service_level);
  3503. kfree(card);
  3504. }
  3505. static struct ccw_device_id qeth_ids[] = {
  3506. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3507. .driver_info = QETH_CARD_TYPE_OSD},
  3508. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3509. .driver_info = QETH_CARD_TYPE_IQD},
  3510. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3511. .driver_info = QETH_CARD_TYPE_OSN},
  3512. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3513. .driver_info = QETH_CARD_TYPE_OSM},
  3514. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3515. .driver_info = QETH_CARD_TYPE_OSX},
  3516. {},
  3517. };
  3518. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3519. static struct ccw_driver qeth_ccw_driver = {
  3520. .name = "qeth",
  3521. .ids = qeth_ids,
  3522. .probe = ccwgroup_probe_ccwdev,
  3523. .remove = ccwgroup_remove_ccwdev,
  3524. };
  3525. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3526. unsigned long driver_id)
  3527. {
  3528. return ccwgroup_create_from_string(root_dev, driver_id,
  3529. &qeth_ccw_driver, 3, buf);
  3530. }
  3531. int qeth_core_hardsetup_card(struct qeth_card *card)
  3532. {
  3533. int retries = 0;
  3534. int rc;
  3535. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3536. atomic_set(&card->force_alloc_skb, 0);
  3537. retry:
  3538. if (retries)
  3539. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3540. dev_name(&card->gdev->dev));
  3541. ccw_device_set_offline(CARD_DDEV(card));
  3542. ccw_device_set_offline(CARD_WDEV(card));
  3543. ccw_device_set_offline(CARD_RDEV(card));
  3544. rc = ccw_device_set_online(CARD_RDEV(card));
  3545. if (rc)
  3546. goto retriable;
  3547. rc = ccw_device_set_online(CARD_WDEV(card));
  3548. if (rc)
  3549. goto retriable;
  3550. rc = ccw_device_set_online(CARD_DDEV(card));
  3551. if (rc)
  3552. goto retriable;
  3553. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3554. retriable:
  3555. if (rc == -ERESTARTSYS) {
  3556. QETH_DBF_TEXT(SETUP, 2, "break1");
  3557. return rc;
  3558. } else if (rc) {
  3559. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3560. if (++retries > 3)
  3561. goto out;
  3562. else
  3563. goto retry;
  3564. }
  3565. qeth_init_tokens(card);
  3566. qeth_init_func_level(card);
  3567. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3568. if (rc == -ERESTARTSYS) {
  3569. QETH_DBF_TEXT(SETUP, 2, "break2");
  3570. return rc;
  3571. } else if (rc) {
  3572. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3573. if (--retries < 0)
  3574. goto out;
  3575. else
  3576. goto retry;
  3577. }
  3578. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3579. if (rc == -ERESTARTSYS) {
  3580. QETH_DBF_TEXT(SETUP, 2, "break3");
  3581. return rc;
  3582. } else if (rc) {
  3583. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3584. if (--retries < 0)
  3585. goto out;
  3586. else
  3587. goto retry;
  3588. }
  3589. rc = qeth_mpc_initialize(card);
  3590. if (rc) {
  3591. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3592. goto out;
  3593. }
  3594. return 0;
  3595. out:
  3596. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3597. "an error on the device\n");
  3598. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3599. dev_name(&card->gdev->dev), rc);
  3600. return rc;
  3601. }
  3602. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3603. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3604. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3605. {
  3606. struct page *page = virt_to_page(element->addr);
  3607. if (*pskb == NULL) {
  3608. /* the upper protocol layers assume that there is data in the
  3609. * skb itself. Copy a small amount (64 bytes) to make them
  3610. * happy. */
  3611. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3612. if (!(*pskb))
  3613. return -ENOMEM;
  3614. skb_reserve(*pskb, ETH_HLEN);
  3615. if (data_len <= 64) {
  3616. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3617. data_len);
  3618. } else {
  3619. get_page(page);
  3620. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3621. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3622. data_len - 64);
  3623. (*pskb)->data_len += data_len - 64;
  3624. (*pskb)->len += data_len - 64;
  3625. (*pskb)->truesize += data_len - 64;
  3626. (*pfrag)++;
  3627. }
  3628. } else {
  3629. get_page(page);
  3630. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3631. (*pskb)->data_len += data_len;
  3632. (*pskb)->len += data_len;
  3633. (*pskb)->truesize += data_len;
  3634. (*pfrag)++;
  3635. }
  3636. return 0;
  3637. }
  3638. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3639. struct qdio_buffer *buffer,
  3640. struct qdio_buffer_element **__element, int *__offset,
  3641. struct qeth_hdr **hdr)
  3642. {
  3643. struct qdio_buffer_element *element = *__element;
  3644. int offset = *__offset;
  3645. struct sk_buff *skb = NULL;
  3646. int skb_len = 0;
  3647. void *data_ptr;
  3648. int data_len;
  3649. int headroom = 0;
  3650. int use_rx_sg = 0;
  3651. int frag = 0;
  3652. /* qeth_hdr must not cross element boundaries */
  3653. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3654. if (qeth_is_last_sbale(element))
  3655. return NULL;
  3656. element++;
  3657. offset = 0;
  3658. if (element->length < sizeof(struct qeth_hdr))
  3659. return NULL;
  3660. }
  3661. *hdr = element->addr + offset;
  3662. offset += sizeof(struct qeth_hdr);
  3663. switch ((*hdr)->hdr.l2.id) {
  3664. case QETH_HEADER_TYPE_LAYER2:
  3665. skb_len = (*hdr)->hdr.l2.pkt_length;
  3666. break;
  3667. case QETH_HEADER_TYPE_LAYER3:
  3668. skb_len = (*hdr)->hdr.l3.length;
  3669. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3670. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3671. headroom = TR_HLEN;
  3672. else
  3673. headroom = ETH_HLEN;
  3674. break;
  3675. case QETH_HEADER_TYPE_OSN:
  3676. skb_len = (*hdr)->hdr.osn.pdu_length;
  3677. headroom = sizeof(struct qeth_hdr);
  3678. break;
  3679. default:
  3680. break;
  3681. }
  3682. if (!skb_len)
  3683. return NULL;
  3684. if ((skb_len >= card->options.rx_sg_cb) &&
  3685. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3686. (!atomic_read(&card->force_alloc_skb))) {
  3687. use_rx_sg = 1;
  3688. } else {
  3689. skb = dev_alloc_skb(skb_len + headroom);
  3690. if (!skb)
  3691. goto no_mem;
  3692. if (headroom)
  3693. skb_reserve(skb, headroom);
  3694. }
  3695. data_ptr = element->addr + offset;
  3696. while (skb_len) {
  3697. data_len = min(skb_len, (int)(element->length - offset));
  3698. if (data_len) {
  3699. if (use_rx_sg) {
  3700. if (qeth_create_skb_frag(element, &skb, offset,
  3701. &frag, data_len))
  3702. goto no_mem;
  3703. } else {
  3704. memcpy(skb_put(skb, data_len), data_ptr,
  3705. data_len);
  3706. }
  3707. }
  3708. skb_len -= data_len;
  3709. if (skb_len) {
  3710. if (qeth_is_last_sbale(element)) {
  3711. QETH_CARD_TEXT(card, 4, "unexeob");
  3712. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3713. QETH_DBF_TEXT_(QERR, 2, "%s",
  3714. CARD_BUS_ID(card));
  3715. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3716. dev_kfree_skb_any(skb);
  3717. card->stats.rx_errors++;
  3718. return NULL;
  3719. }
  3720. element++;
  3721. offset = 0;
  3722. data_ptr = element->addr;
  3723. } else {
  3724. offset += data_len;
  3725. }
  3726. }
  3727. *__element = element;
  3728. *__offset = offset;
  3729. if (use_rx_sg && card->options.performance_stats) {
  3730. card->perf_stats.sg_skbs_rx++;
  3731. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3732. }
  3733. return skb;
  3734. no_mem:
  3735. if (net_ratelimit()) {
  3736. QETH_CARD_TEXT(card, 2, "noskbmem");
  3737. }
  3738. card->stats.rx_dropped++;
  3739. return NULL;
  3740. }
  3741. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3742. static void qeth_unregister_dbf_views(void)
  3743. {
  3744. int x;
  3745. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3746. debug_unregister(qeth_dbf[x].id);
  3747. qeth_dbf[x].id = NULL;
  3748. }
  3749. }
  3750. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3751. {
  3752. char dbf_txt_buf[32];
  3753. va_list args;
  3754. if (level > id->level)
  3755. return;
  3756. va_start(args, fmt);
  3757. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3758. va_end(args);
  3759. debug_text_event(id, level, dbf_txt_buf);
  3760. }
  3761. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3762. static int qeth_register_dbf_views(void)
  3763. {
  3764. int ret;
  3765. int x;
  3766. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3767. /* register the areas */
  3768. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3769. qeth_dbf[x].pages,
  3770. qeth_dbf[x].areas,
  3771. qeth_dbf[x].len);
  3772. if (qeth_dbf[x].id == NULL) {
  3773. qeth_unregister_dbf_views();
  3774. return -ENOMEM;
  3775. }
  3776. /* register a view */
  3777. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3778. if (ret) {
  3779. qeth_unregister_dbf_views();
  3780. return ret;
  3781. }
  3782. /* set a passing level */
  3783. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3784. }
  3785. return 0;
  3786. }
  3787. int qeth_core_load_discipline(struct qeth_card *card,
  3788. enum qeth_discipline_id discipline)
  3789. {
  3790. int rc = 0;
  3791. switch (discipline) {
  3792. case QETH_DISCIPLINE_LAYER3:
  3793. card->discipline.ccwgdriver = try_then_request_module(
  3794. symbol_get(qeth_l3_ccwgroup_driver),
  3795. "qeth_l3");
  3796. break;
  3797. case QETH_DISCIPLINE_LAYER2:
  3798. card->discipline.ccwgdriver = try_then_request_module(
  3799. symbol_get(qeth_l2_ccwgroup_driver),
  3800. "qeth_l2");
  3801. break;
  3802. }
  3803. if (!card->discipline.ccwgdriver) {
  3804. dev_err(&card->gdev->dev, "There is no kernel module to "
  3805. "support discipline %d\n", discipline);
  3806. rc = -EINVAL;
  3807. }
  3808. return rc;
  3809. }
  3810. void qeth_core_free_discipline(struct qeth_card *card)
  3811. {
  3812. if (card->options.layer2)
  3813. symbol_put(qeth_l2_ccwgroup_driver);
  3814. else
  3815. symbol_put(qeth_l3_ccwgroup_driver);
  3816. card->discipline.ccwgdriver = NULL;
  3817. }
  3818. static void qeth_determine_capabilities(struct qeth_card *card)
  3819. {
  3820. int rc;
  3821. int length;
  3822. char *prcd;
  3823. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3824. rc = ccw_device_set_online(CARD_DDEV(card));
  3825. if (rc) {
  3826. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3827. goto out;
  3828. }
  3829. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3830. if (rc) {
  3831. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3832. dev_name(&card->gdev->dev), rc);
  3833. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3834. goto out_offline;
  3835. }
  3836. qeth_configure_unitaddr(card, prcd);
  3837. qeth_configure_blkt_default(card, prcd);
  3838. kfree(prcd);
  3839. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3840. if (rc)
  3841. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3842. out_offline:
  3843. ccw_device_set_offline(CARD_DDEV(card));
  3844. out:
  3845. return;
  3846. }
  3847. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3848. {
  3849. struct qeth_card *card;
  3850. struct device *dev;
  3851. int rc;
  3852. unsigned long flags;
  3853. char dbf_name[20];
  3854. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3855. dev = &gdev->dev;
  3856. if (!get_device(dev))
  3857. return -ENODEV;
  3858. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3859. card = qeth_alloc_card();
  3860. if (!card) {
  3861. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3862. rc = -ENOMEM;
  3863. goto err_dev;
  3864. }
  3865. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3866. dev_name(&gdev->dev));
  3867. card->debug = debug_register(dbf_name, 2, 1, 8);
  3868. if (!card->debug) {
  3869. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3870. rc = -ENOMEM;
  3871. goto err_card;
  3872. }
  3873. debug_register_view(card->debug, &debug_hex_ascii_view);
  3874. card->read.ccwdev = gdev->cdev[0];
  3875. card->write.ccwdev = gdev->cdev[1];
  3876. card->data.ccwdev = gdev->cdev[2];
  3877. dev_set_drvdata(&gdev->dev, card);
  3878. card->gdev = gdev;
  3879. gdev->cdev[0]->handler = qeth_irq;
  3880. gdev->cdev[1]->handler = qeth_irq;
  3881. gdev->cdev[2]->handler = qeth_irq;
  3882. rc = qeth_determine_card_type(card);
  3883. if (rc) {
  3884. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3885. goto err_dbf;
  3886. }
  3887. rc = qeth_setup_card(card);
  3888. if (rc) {
  3889. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3890. goto err_dbf;
  3891. }
  3892. if (card->info.type == QETH_CARD_TYPE_OSN)
  3893. rc = qeth_core_create_osn_attributes(dev);
  3894. else
  3895. rc = qeth_core_create_device_attributes(dev);
  3896. if (rc)
  3897. goto err_dbf;
  3898. switch (card->info.type) {
  3899. case QETH_CARD_TYPE_OSN:
  3900. case QETH_CARD_TYPE_OSM:
  3901. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3902. if (rc)
  3903. goto err_attr;
  3904. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3905. if (rc)
  3906. goto err_disc;
  3907. case QETH_CARD_TYPE_OSD:
  3908. case QETH_CARD_TYPE_OSX:
  3909. default:
  3910. break;
  3911. }
  3912. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3913. list_add_tail(&card->list, &qeth_core_card_list.list);
  3914. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3915. qeth_determine_capabilities(card);
  3916. return 0;
  3917. err_disc:
  3918. qeth_core_free_discipline(card);
  3919. err_attr:
  3920. if (card->info.type == QETH_CARD_TYPE_OSN)
  3921. qeth_core_remove_osn_attributes(dev);
  3922. else
  3923. qeth_core_remove_device_attributes(dev);
  3924. err_dbf:
  3925. debug_unregister(card->debug);
  3926. err_card:
  3927. qeth_core_free_card(card);
  3928. err_dev:
  3929. put_device(dev);
  3930. return rc;
  3931. }
  3932. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3933. {
  3934. unsigned long flags;
  3935. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3936. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3937. if (card->discipline.ccwgdriver) {
  3938. card->discipline.ccwgdriver->remove(gdev);
  3939. qeth_core_free_discipline(card);
  3940. }
  3941. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3942. qeth_core_remove_osn_attributes(&gdev->dev);
  3943. } else {
  3944. qeth_core_remove_device_attributes(&gdev->dev);
  3945. }
  3946. debug_unregister(card->debug);
  3947. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3948. list_del(&card->list);
  3949. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3950. qeth_core_free_card(card);
  3951. dev_set_drvdata(&gdev->dev, NULL);
  3952. put_device(&gdev->dev);
  3953. return;
  3954. }
  3955. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3956. {
  3957. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3958. int rc = 0;
  3959. int def_discipline;
  3960. if (!card->discipline.ccwgdriver) {
  3961. if (card->info.type == QETH_CARD_TYPE_IQD)
  3962. def_discipline = QETH_DISCIPLINE_LAYER3;
  3963. else
  3964. def_discipline = QETH_DISCIPLINE_LAYER2;
  3965. rc = qeth_core_load_discipline(card, def_discipline);
  3966. if (rc)
  3967. goto err;
  3968. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3969. if (rc)
  3970. goto err;
  3971. }
  3972. rc = card->discipline.ccwgdriver->set_online(gdev);
  3973. err:
  3974. return rc;
  3975. }
  3976. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3977. {
  3978. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3979. return card->discipline.ccwgdriver->set_offline(gdev);
  3980. }
  3981. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3982. {
  3983. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3984. if (card->discipline.ccwgdriver &&
  3985. card->discipline.ccwgdriver->shutdown)
  3986. card->discipline.ccwgdriver->shutdown(gdev);
  3987. }
  3988. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3989. {
  3990. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3991. if (card->discipline.ccwgdriver &&
  3992. card->discipline.ccwgdriver->prepare)
  3993. return card->discipline.ccwgdriver->prepare(gdev);
  3994. return 0;
  3995. }
  3996. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3997. {
  3998. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3999. if (card->discipline.ccwgdriver &&
  4000. card->discipline.ccwgdriver->complete)
  4001. card->discipline.ccwgdriver->complete(gdev);
  4002. }
  4003. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4004. {
  4005. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4006. if (card->discipline.ccwgdriver &&
  4007. card->discipline.ccwgdriver->freeze)
  4008. return card->discipline.ccwgdriver->freeze(gdev);
  4009. return 0;
  4010. }
  4011. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4012. {
  4013. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4014. if (card->discipline.ccwgdriver &&
  4015. card->discipline.ccwgdriver->thaw)
  4016. return card->discipline.ccwgdriver->thaw(gdev);
  4017. return 0;
  4018. }
  4019. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4020. {
  4021. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4022. if (card->discipline.ccwgdriver &&
  4023. card->discipline.ccwgdriver->restore)
  4024. return card->discipline.ccwgdriver->restore(gdev);
  4025. return 0;
  4026. }
  4027. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4028. .owner = THIS_MODULE,
  4029. .name = "qeth",
  4030. .driver_id = 0xD8C5E3C8,
  4031. .probe = qeth_core_probe_device,
  4032. .remove = qeth_core_remove_device,
  4033. .set_online = qeth_core_set_online,
  4034. .set_offline = qeth_core_set_offline,
  4035. .shutdown = qeth_core_shutdown,
  4036. .prepare = qeth_core_prepare,
  4037. .complete = qeth_core_complete,
  4038. .freeze = qeth_core_freeze,
  4039. .thaw = qeth_core_thaw,
  4040. .restore = qeth_core_restore,
  4041. };
  4042. static ssize_t
  4043. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4044. size_t count)
  4045. {
  4046. int err;
  4047. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4048. qeth_core_ccwgroup_driver.driver_id);
  4049. if (err)
  4050. return err;
  4051. else
  4052. return count;
  4053. }
  4054. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4055. static struct {
  4056. const char str[ETH_GSTRING_LEN];
  4057. } qeth_ethtool_stats_keys[] = {
  4058. /* 0 */{"rx skbs"},
  4059. {"rx buffers"},
  4060. {"tx skbs"},
  4061. {"tx buffers"},
  4062. {"tx skbs no packing"},
  4063. {"tx buffers no packing"},
  4064. {"tx skbs packing"},
  4065. {"tx buffers packing"},
  4066. {"tx sg skbs"},
  4067. {"tx sg frags"},
  4068. /* 10 */{"rx sg skbs"},
  4069. {"rx sg frags"},
  4070. {"rx sg page allocs"},
  4071. {"tx large kbytes"},
  4072. {"tx large count"},
  4073. {"tx pk state ch n->p"},
  4074. {"tx pk state ch p->n"},
  4075. {"tx pk watermark low"},
  4076. {"tx pk watermark high"},
  4077. {"queue 0 buffer usage"},
  4078. /* 20 */{"queue 1 buffer usage"},
  4079. {"queue 2 buffer usage"},
  4080. {"queue 3 buffer usage"},
  4081. {"rx handler time"},
  4082. {"rx handler count"},
  4083. {"rx do_QDIO time"},
  4084. {"rx do_QDIO count"},
  4085. {"tx handler time"},
  4086. {"tx handler count"},
  4087. {"tx time"},
  4088. /* 30 */{"tx count"},
  4089. {"tx do_QDIO time"},
  4090. {"tx do_QDIO count"},
  4091. {"tx csum"},
  4092. {"tx lin"},
  4093. };
  4094. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4095. {
  4096. switch (stringset) {
  4097. case ETH_SS_STATS:
  4098. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4099. default:
  4100. return -EINVAL;
  4101. }
  4102. }
  4103. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4104. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4105. struct ethtool_stats *stats, u64 *data)
  4106. {
  4107. struct qeth_card *card = dev->ml_priv;
  4108. data[0] = card->stats.rx_packets -
  4109. card->perf_stats.initial_rx_packets;
  4110. data[1] = card->perf_stats.bufs_rec;
  4111. data[2] = card->stats.tx_packets -
  4112. card->perf_stats.initial_tx_packets;
  4113. data[3] = card->perf_stats.bufs_sent;
  4114. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4115. - card->perf_stats.skbs_sent_pack;
  4116. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4117. data[6] = card->perf_stats.skbs_sent_pack;
  4118. data[7] = card->perf_stats.bufs_sent_pack;
  4119. data[8] = card->perf_stats.sg_skbs_sent;
  4120. data[9] = card->perf_stats.sg_frags_sent;
  4121. data[10] = card->perf_stats.sg_skbs_rx;
  4122. data[11] = card->perf_stats.sg_frags_rx;
  4123. data[12] = card->perf_stats.sg_alloc_page_rx;
  4124. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4125. data[14] = card->perf_stats.large_send_cnt;
  4126. data[15] = card->perf_stats.sc_dp_p;
  4127. data[16] = card->perf_stats.sc_p_dp;
  4128. data[17] = QETH_LOW_WATERMARK_PACK;
  4129. data[18] = QETH_HIGH_WATERMARK_PACK;
  4130. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4131. data[20] = (card->qdio.no_out_queues > 1) ?
  4132. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4133. data[21] = (card->qdio.no_out_queues > 2) ?
  4134. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4135. data[22] = (card->qdio.no_out_queues > 3) ?
  4136. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4137. data[23] = card->perf_stats.inbound_time;
  4138. data[24] = card->perf_stats.inbound_cnt;
  4139. data[25] = card->perf_stats.inbound_do_qdio_time;
  4140. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4141. data[27] = card->perf_stats.outbound_handler_time;
  4142. data[28] = card->perf_stats.outbound_handler_cnt;
  4143. data[29] = card->perf_stats.outbound_time;
  4144. data[30] = card->perf_stats.outbound_cnt;
  4145. data[31] = card->perf_stats.outbound_do_qdio_time;
  4146. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4147. data[33] = card->perf_stats.tx_csum;
  4148. data[34] = card->perf_stats.tx_lin;
  4149. }
  4150. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4151. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4152. {
  4153. switch (stringset) {
  4154. case ETH_SS_STATS:
  4155. memcpy(data, &qeth_ethtool_stats_keys,
  4156. sizeof(qeth_ethtool_stats_keys));
  4157. break;
  4158. default:
  4159. WARN_ON(1);
  4160. break;
  4161. }
  4162. }
  4163. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4164. void qeth_core_get_drvinfo(struct net_device *dev,
  4165. struct ethtool_drvinfo *info)
  4166. {
  4167. struct qeth_card *card = dev->ml_priv;
  4168. if (card->options.layer2)
  4169. strcpy(info->driver, "qeth_l2");
  4170. else
  4171. strcpy(info->driver, "qeth_l3");
  4172. strcpy(info->version, "1.0");
  4173. strcpy(info->fw_version, card->info.mcl_level);
  4174. sprintf(info->bus_info, "%s/%s/%s",
  4175. CARD_RDEV_ID(card),
  4176. CARD_WDEV_ID(card),
  4177. CARD_DDEV_ID(card));
  4178. }
  4179. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4180. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4181. struct ethtool_cmd *ecmd)
  4182. {
  4183. struct qeth_card *card = netdev->ml_priv;
  4184. enum qeth_link_types link_type;
  4185. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4186. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4187. else
  4188. link_type = card->info.link_type;
  4189. ecmd->transceiver = XCVR_INTERNAL;
  4190. ecmd->supported = SUPPORTED_Autoneg;
  4191. ecmd->advertising = ADVERTISED_Autoneg;
  4192. ecmd->duplex = DUPLEX_FULL;
  4193. ecmd->autoneg = AUTONEG_ENABLE;
  4194. switch (link_type) {
  4195. case QETH_LINK_TYPE_FAST_ETH:
  4196. case QETH_LINK_TYPE_LANE_ETH100:
  4197. ecmd->supported |= SUPPORTED_10baseT_Half |
  4198. SUPPORTED_10baseT_Full |
  4199. SUPPORTED_100baseT_Half |
  4200. SUPPORTED_100baseT_Full |
  4201. SUPPORTED_TP;
  4202. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4203. ADVERTISED_10baseT_Full |
  4204. ADVERTISED_100baseT_Half |
  4205. ADVERTISED_100baseT_Full |
  4206. ADVERTISED_TP;
  4207. ecmd->speed = SPEED_100;
  4208. ecmd->port = PORT_TP;
  4209. break;
  4210. case QETH_LINK_TYPE_GBIT_ETH:
  4211. case QETH_LINK_TYPE_LANE_ETH1000:
  4212. ecmd->supported |= SUPPORTED_10baseT_Half |
  4213. SUPPORTED_10baseT_Full |
  4214. SUPPORTED_100baseT_Half |
  4215. SUPPORTED_100baseT_Full |
  4216. SUPPORTED_1000baseT_Half |
  4217. SUPPORTED_1000baseT_Full |
  4218. SUPPORTED_FIBRE;
  4219. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4220. ADVERTISED_10baseT_Full |
  4221. ADVERTISED_100baseT_Half |
  4222. ADVERTISED_100baseT_Full |
  4223. ADVERTISED_1000baseT_Half |
  4224. ADVERTISED_1000baseT_Full |
  4225. ADVERTISED_FIBRE;
  4226. ecmd->speed = SPEED_1000;
  4227. ecmd->port = PORT_FIBRE;
  4228. break;
  4229. case QETH_LINK_TYPE_10GBIT_ETH:
  4230. ecmd->supported |= SUPPORTED_10baseT_Half |
  4231. SUPPORTED_10baseT_Full |
  4232. SUPPORTED_100baseT_Half |
  4233. SUPPORTED_100baseT_Full |
  4234. SUPPORTED_1000baseT_Half |
  4235. SUPPORTED_1000baseT_Full |
  4236. SUPPORTED_10000baseT_Full |
  4237. SUPPORTED_FIBRE;
  4238. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4239. ADVERTISED_10baseT_Full |
  4240. ADVERTISED_100baseT_Half |
  4241. ADVERTISED_100baseT_Full |
  4242. ADVERTISED_1000baseT_Half |
  4243. ADVERTISED_1000baseT_Full |
  4244. ADVERTISED_10000baseT_Full |
  4245. ADVERTISED_FIBRE;
  4246. ecmd->speed = SPEED_10000;
  4247. ecmd->port = PORT_FIBRE;
  4248. break;
  4249. default:
  4250. ecmd->supported |= SUPPORTED_10baseT_Half |
  4251. SUPPORTED_10baseT_Full |
  4252. SUPPORTED_TP;
  4253. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4254. ADVERTISED_10baseT_Full |
  4255. ADVERTISED_TP;
  4256. ecmd->speed = SPEED_10;
  4257. ecmd->port = PORT_TP;
  4258. }
  4259. return 0;
  4260. }
  4261. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4262. static int __init qeth_core_init(void)
  4263. {
  4264. int rc;
  4265. pr_info("loading core functions\n");
  4266. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4267. rwlock_init(&qeth_core_card_list.rwlock);
  4268. rc = qeth_register_dbf_views();
  4269. if (rc)
  4270. goto out_err;
  4271. rc = ccw_driver_register(&qeth_ccw_driver);
  4272. if (rc)
  4273. goto ccw_err;
  4274. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4275. if (rc)
  4276. goto ccwgroup_err;
  4277. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4278. &driver_attr_group);
  4279. if (rc)
  4280. goto driver_err;
  4281. qeth_core_root_dev = root_device_register("qeth");
  4282. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4283. if (rc)
  4284. goto register_err;
  4285. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4286. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4287. if (!qeth_core_header_cache) {
  4288. rc = -ENOMEM;
  4289. goto slab_err;
  4290. }
  4291. return 0;
  4292. slab_err:
  4293. root_device_unregister(qeth_core_root_dev);
  4294. register_err:
  4295. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4296. &driver_attr_group);
  4297. driver_err:
  4298. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4299. ccwgroup_err:
  4300. ccw_driver_unregister(&qeth_ccw_driver);
  4301. ccw_err:
  4302. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4303. qeth_unregister_dbf_views();
  4304. out_err:
  4305. pr_err("Initializing the qeth device driver failed\n");
  4306. return rc;
  4307. }
  4308. static void __exit qeth_core_exit(void)
  4309. {
  4310. root_device_unregister(qeth_core_root_dev);
  4311. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4312. &driver_attr_group);
  4313. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4314. ccw_driver_unregister(&qeth_ccw_driver);
  4315. kmem_cache_destroy(qeth_core_header_cache);
  4316. qeth_unregister_dbf_views();
  4317. pr_info("core functions removed\n");
  4318. }
  4319. module_init(qeth_core_init);
  4320. module_exit(qeth_core_exit);
  4321. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4322. MODULE_DESCRIPTION("qeth core functions");
  4323. MODULE_LICENSE("GPL");