be_main.c 146 KB

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  1. /**
  2. * Copyright (C) 2005 - 2013 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
  145. DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
  146. DEVICE_ATTR(beiscsi_active_cid_count, S_IRUGO, beiscsi_active_cid_disp, NULL);
  147. struct device_attribute *beiscsi_attrs[] = {
  148. &dev_attr_beiscsi_log_enable,
  149. &dev_attr_beiscsi_drvr_ver,
  150. &dev_attr_beiscsi_adapter_family,
  151. &dev_attr_beiscsi_fw_ver,
  152. &dev_attr_beiscsi_active_cid_count,
  153. NULL,
  154. };
  155. static char const *cqe_desc[] = {
  156. "RESERVED_DESC",
  157. "SOL_CMD_COMPLETE",
  158. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  159. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  160. "CXN_KILLED_BURST_LEN_MISMATCH",
  161. "CXN_KILLED_AHS_RCVD",
  162. "CXN_KILLED_HDR_DIGEST_ERR",
  163. "CXN_KILLED_UNKNOWN_HDR",
  164. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  165. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  166. "CXN_KILLED_RST_RCVD",
  167. "CXN_KILLED_TIMED_OUT",
  168. "CXN_KILLED_RST_SENT",
  169. "CXN_KILLED_FIN_RCVD",
  170. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  171. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  172. "CXN_KILLED_OVER_RUN_RESIDUAL",
  173. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  174. "CMD_KILLED_INVALID_STATSN_RCVD",
  175. "CMD_KILLED_INVALID_R2T_RCVD",
  176. "CMD_CXN_KILLED_LUN_INVALID",
  177. "CMD_CXN_KILLED_ICD_INVALID",
  178. "CMD_CXN_KILLED_ITT_INVALID",
  179. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  180. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  181. "CXN_INVALIDATE_NOTIFY",
  182. "CXN_INVALIDATE_INDEX_NOTIFY",
  183. "CMD_INVALIDATED_NOTIFY",
  184. "UNSOL_HDR_NOTIFY",
  185. "UNSOL_DATA_NOTIFY",
  186. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  187. "DRIVERMSG_NOTIFY",
  188. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  189. "SOL_CMD_KILLED_DIF_ERR",
  190. "CXN_KILLED_SYN_RCVD",
  191. "CXN_KILLED_IMM_DATA_RCVD"
  192. };
  193. static int beiscsi_slave_configure(struct scsi_device *sdev)
  194. {
  195. blk_queue_max_segment_size(sdev->request_queue, 65536);
  196. return 0;
  197. }
  198. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  199. {
  200. struct iscsi_cls_session *cls_session;
  201. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  202. struct beiscsi_io_task *aborted_io_task;
  203. struct iscsi_conn *conn;
  204. struct beiscsi_conn *beiscsi_conn;
  205. struct beiscsi_hba *phba;
  206. struct iscsi_session *session;
  207. struct invalidate_command_table *inv_tbl;
  208. struct be_dma_mem nonemb_cmd;
  209. unsigned int cid, tag, num_invalidate;
  210. cls_session = starget_to_session(scsi_target(sc->device));
  211. session = cls_session->dd_data;
  212. spin_lock_bh(&session->lock);
  213. if (!aborted_task || !aborted_task->sc) {
  214. /* we raced */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. aborted_io_task = aborted_task->dd_data;
  219. if (!aborted_io_task->scsi_cmnd) {
  220. /* raced or invalid command */
  221. spin_unlock_bh(&session->lock);
  222. return SUCCESS;
  223. }
  224. spin_unlock_bh(&session->lock);
  225. conn = aborted_task->conn;
  226. beiscsi_conn = conn->dd_data;
  227. phba = beiscsi_conn->phba;
  228. /* invalidate iocb */
  229. cid = beiscsi_conn->beiscsi_conn_cid;
  230. inv_tbl = phba->inv_tbl;
  231. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  232. inv_tbl->cid = cid;
  233. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  234. num_invalidate = 1;
  235. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  236. sizeof(struct invalidate_commands_params_in),
  237. &nonemb_cmd.dma);
  238. if (nonemb_cmd.va == NULL) {
  239. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  240. "BM_%d : Failed to allocate memory for"
  241. "mgmt_invalidate_icds\n");
  242. return FAILED;
  243. }
  244. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  245. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  246. cid, &nonemb_cmd);
  247. if (!tag) {
  248. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  249. "BM_%d : mgmt_invalidate_icds could not be"
  250. "submitted\n");
  251. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  252. nonemb_cmd.va, nonemb_cmd.dma);
  253. return FAILED;
  254. }
  255. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  256. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  257. nonemb_cmd.va, nonemb_cmd.dma);
  258. return iscsi_eh_abort(sc);
  259. }
  260. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  261. {
  262. struct iscsi_task *abrt_task;
  263. struct beiscsi_io_task *abrt_io_task;
  264. struct iscsi_conn *conn;
  265. struct beiscsi_conn *beiscsi_conn;
  266. struct beiscsi_hba *phba;
  267. struct iscsi_session *session;
  268. struct iscsi_cls_session *cls_session;
  269. struct invalidate_command_table *inv_tbl;
  270. struct be_dma_mem nonemb_cmd;
  271. unsigned int cid, tag, i, num_invalidate;
  272. /* invalidate iocbs */
  273. cls_session = starget_to_session(scsi_target(sc->device));
  274. session = cls_session->dd_data;
  275. spin_lock_bh(&session->lock);
  276. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  277. spin_unlock_bh(&session->lock);
  278. return FAILED;
  279. }
  280. conn = session->leadconn;
  281. beiscsi_conn = conn->dd_data;
  282. phba = beiscsi_conn->phba;
  283. cid = beiscsi_conn->beiscsi_conn_cid;
  284. inv_tbl = phba->inv_tbl;
  285. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  286. num_invalidate = 0;
  287. for (i = 0; i < conn->session->cmds_max; i++) {
  288. abrt_task = conn->session->cmds[i];
  289. abrt_io_task = abrt_task->dd_data;
  290. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  291. continue;
  292. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  293. continue;
  294. inv_tbl->cid = cid;
  295. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  296. num_invalidate++;
  297. inv_tbl++;
  298. }
  299. spin_unlock_bh(&session->lock);
  300. inv_tbl = phba->inv_tbl;
  301. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  302. sizeof(struct invalidate_commands_params_in),
  303. &nonemb_cmd.dma);
  304. if (nonemb_cmd.va == NULL) {
  305. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  306. "BM_%d : Failed to allocate memory for"
  307. "mgmt_invalidate_icds\n");
  308. return FAILED;
  309. }
  310. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  311. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  312. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  313. cid, &nonemb_cmd);
  314. if (!tag) {
  315. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  316. "BM_%d : mgmt_invalidate_icds could not be"
  317. " submitted\n");
  318. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  319. nonemb_cmd.va, nonemb_cmd.dma);
  320. return FAILED;
  321. }
  322. beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  484. { 0 }
  485. };
  486. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  487. static struct scsi_host_template beiscsi_sht = {
  488. .module = THIS_MODULE,
  489. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  490. .proc_name = DRV_NAME,
  491. .queuecommand = iscsi_queuecommand,
  492. .change_queue_depth = iscsi_change_queue_depth,
  493. .slave_configure = beiscsi_slave_configure,
  494. .target_alloc = iscsi_target_alloc,
  495. .eh_abort_handler = beiscsi_eh_abort,
  496. .eh_device_reset_handler = beiscsi_eh_device_reset,
  497. .eh_target_reset_handler = iscsi_eh_session_reset,
  498. .shost_attrs = beiscsi_attrs,
  499. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  500. .can_queue = BE2_IO_DEPTH,
  501. .this_id = -1,
  502. .max_sectors = BEISCSI_MAX_SECTORS,
  503. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  504. .use_clustering = ENABLE_CLUSTERING,
  505. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  506. };
  507. static struct scsi_transport_template *beiscsi_scsi_transport;
  508. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  509. {
  510. struct beiscsi_hba *phba;
  511. struct Scsi_Host *shost;
  512. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  513. if (!shost) {
  514. dev_err(&pcidev->dev,
  515. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  516. return NULL;
  517. }
  518. shost->dma_boundary = pcidev->dma_mask;
  519. shost->max_id = BE2_MAX_SESSIONS;
  520. shost->max_channel = 0;
  521. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  522. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  523. shost->transportt = beiscsi_scsi_transport;
  524. phba = iscsi_host_priv(shost);
  525. memset(phba, 0, sizeof(*phba));
  526. phba->shost = shost;
  527. phba->pcidev = pci_dev_get(pcidev);
  528. pci_set_drvdata(pcidev, phba);
  529. phba->interface_handle = 0xFFFFFFFF;
  530. if (iscsi_host_add(shost, &phba->pcidev->dev))
  531. goto free_devices;
  532. return phba;
  533. free_devices:
  534. pci_dev_put(phba->pcidev);
  535. iscsi_host_free(phba->shost);
  536. return NULL;
  537. }
  538. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  539. {
  540. if (phba->csr_va) {
  541. iounmap(phba->csr_va);
  542. phba->csr_va = NULL;
  543. }
  544. if (phba->db_va) {
  545. iounmap(phba->db_va);
  546. phba->db_va = NULL;
  547. }
  548. if (phba->pci_va) {
  549. iounmap(phba->pci_va);
  550. phba->pci_va = NULL;
  551. }
  552. }
  553. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  554. struct pci_dev *pcidev)
  555. {
  556. u8 __iomem *addr;
  557. int pcicfg_reg;
  558. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  559. pci_resource_len(pcidev, 2));
  560. if (addr == NULL)
  561. return -ENOMEM;
  562. phba->ctrl.csr = addr;
  563. phba->csr_va = addr;
  564. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  565. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  566. if (addr == NULL)
  567. goto pci_map_err;
  568. phba->ctrl.db = addr;
  569. phba->db_va = addr;
  570. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  571. if (phba->generation == BE_GEN2)
  572. pcicfg_reg = 1;
  573. else
  574. pcicfg_reg = 0;
  575. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  576. pci_resource_len(pcidev, pcicfg_reg));
  577. if (addr == NULL)
  578. goto pci_map_err;
  579. phba->ctrl.pcicfg = addr;
  580. phba->pci_va = addr;
  581. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  582. return 0;
  583. pci_map_err:
  584. beiscsi_unmap_pci_function(phba);
  585. return -ENOMEM;
  586. }
  587. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  588. {
  589. int ret;
  590. ret = pci_enable_device(pcidev);
  591. if (ret) {
  592. dev_err(&pcidev->dev,
  593. "beiscsi_enable_pci - enable device failed\n");
  594. return ret;
  595. }
  596. pci_set_master(pcidev);
  597. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  598. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  599. if (ret) {
  600. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  601. pci_disable_device(pcidev);
  602. return ret;
  603. }
  604. }
  605. return 0;
  606. }
  607. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  608. {
  609. struct be_ctrl_info *ctrl = &phba->ctrl;
  610. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  611. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  612. int status = 0;
  613. ctrl->pdev = pdev;
  614. status = beiscsi_map_pci_bars(phba, pdev);
  615. if (status)
  616. return status;
  617. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  618. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  619. mbox_mem_alloc->size,
  620. &mbox_mem_alloc->dma);
  621. if (!mbox_mem_alloc->va) {
  622. beiscsi_unmap_pci_function(phba);
  623. return -ENOMEM;
  624. }
  625. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  626. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  627. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  628. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  629. spin_lock_init(&ctrl->mbox_lock);
  630. spin_lock_init(&phba->ctrl.mcc_lock);
  631. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  632. return status;
  633. }
  634. /**
  635. * beiscsi_get_params()- Set the config paramters
  636. * @phba: ptr device priv structure
  637. **/
  638. static void beiscsi_get_params(struct beiscsi_hba *phba)
  639. {
  640. uint32_t total_cid_count = 0;
  641. uint32_t total_icd_count = 0;
  642. uint8_t ulp_num = 0;
  643. total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
  644. BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
  645. for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
  646. if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
  647. total_icd_count = phba->fw_config.
  648. iscsi_icd_count[ulp_num];
  649. break;
  650. }
  651. phba->params.ios_per_ctrl = (total_icd_count -
  652. (total_cid_count +
  653. BE2_TMFS + BE2_NOPOUT_REQ));
  654. phba->params.cxns_per_ctrl = total_cid_count;
  655. phba->params.asyncpdus_per_ctrl = total_cid_count;
  656. phba->params.icds_per_ctrl = total_icd_count;
  657. phba->params.num_sge_per_io = BE2_SGE;
  658. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  659. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  660. phba->params.eq_timer = 64;
  661. phba->params.num_eq_entries = 1024;
  662. phba->params.num_cq_entries = 1024;
  663. phba->params.wrbs_per_cxn = 256;
  664. }
  665. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  666. unsigned int id, unsigned int clr_interrupt,
  667. unsigned int num_processed,
  668. unsigned char rearm, unsigned char event)
  669. {
  670. u32 val = 0;
  671. val |= id & DB_EQ_RING_ID_MASK;
  672. if (rearm)
  673. val |= 1 << DB_EQ_REARM_SHIFT;
  674. if (clr_interrupt)
  675. val |= 1 << DB_EQ_CLR_SHIFT;
  676. if (event)
  677. val |= 1 << DB_EQ_EVNT_SHIFT;
  678. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  679. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  680. }
  681. /**
  682. * be_isr_mcc - The isr routine of the driver.
  683. * @irq: Not used
  684. * @dev_id: Pointer to host adapter structure
  685. */
  686. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  687. {
  688. struct beiscsi_hba *phba;
  689. struct be_eq_entry *eqe = NULL;
  690. struct be_queue_info *eq;
  691. struct be_queue_info *mcc;
  692. unsigned int num_eq_processed;
  693. struct be_eq_obj *pbe_eq;
  694. unsigned long flags;
  695. pbe_eq = dev_id;
  696. eq = &pbe_eq->q;
  697. phba = pbe_eq->phba;
  698. mcc = &phba->ctrl.mcc_obj.cq;
  699. eqe = queue_tail_node(eq);
  700. num_eq_processed = 0;
  701. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  702. & EQE_VALID_MASK) {
  703. if (((eqe->dw[offsetof(struct amap_eq_entry,
  704. resource_id) / 32] &
  705. EQE_RESID_MASK) >> 16) == mcc->id) {
  706. spin_lock_irqsave(&phba->isr_lock, flags);
  707. pbe_eq->todo_mcc_cq = true;
  708. spin_unlock_irqrestore(&phba->isr_lock, flags);
  709. }
  710. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  711. queue_tail_inc(eq);
  712. eqe = queue_tail_node(eq);
  713. num_eq_processed++;
  714. }
  715. if (pbe_eq->todo_mcc_cq)
  716. queue_work(phba->wq, &pbe_eq->work_cqs);
  717. if (num_eq_processed)
  718. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  719. return IRQ_HANDLED;
  720. }
  721. /**
  722. * be_isr_msix - The isr routine of the driver.
  723. * @irq: Not used
  724. * @dev_id: Pointer to host adapter structure
  725. */
  726. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  727. {
  728. struct beiscsi_hba *phba;
  729. struct be_eq_entry *eqe = NULL;
  730. struct be_queue_info *eq;
  731. struct be_queue_info *cq;
  732. unsigned int num_eq_processed;
  733. struct be_eq_obj *pbe_eq;
  734. unsigned long flags;
  735. pbe_eq = dev_id;
  736. eq = &pbe_eq->q;
  737. cq = pbe_eq->cq;
  738. eqe = queue_tail_node(eq);
  739. phba = pbe_eq->phba;
  740. num_eq_processed = 0;
  741. if (blk_iopoll_enabled) {
  742. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  743. & EQE_VALID_MASK) {
  744. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  745. blk_iopoll_sched(&pbe_eq->iopoll);
  746. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  747. queue_tail_inc(eq);
  748. eqe = queue_tail_node(eq);
  749. num_eq_processed++;
  750. }
  751. } else {
  752. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  753. & EQE_VALID_MASK) {
  754. spin_lock_irqsave(&phba->isr_lock, flags);
  755. pbe_eq->todo_cq = true;
  756. spin_unlock_irqrestore(&phba->isr_lock, flags);
  757. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  758. queue_tail_inc(eq);
  759. eqe = queue_tail_node(eq);
  760. num_eq_processed++;
  761. }
  762. if (pbe_eq->todo_cq)
  763. queue_work(phba->wq, &pbe_eq->work_cqs);
  764. }
  765. if (num_eq_processed)
  766. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  767. return IRQ_HANDLED;
  768. }
  769. /**
  770. * be_isr - The isr routine of the driver.
  771. * @irq: Not used
  772. * @dev_id: Pointer to host adapter structure
  773. */
  774. static irqreturn_t be_isr(int irq, void *dev_id)
  775. {
  776. struct beiscsi_hba *phba;
  777. struct hwi_controller *phwi_ctrlr;
  778. struct hwi_context_memory *phwi_context;
  779. struct be_eq_entry *eqe = NULL;
  780. struct be_queue_info *eq;
  781. struct be_queue_info *cq;
  782. struct be_queue_info *mcc;
  783. unsigned long flags, index;
  784. unsigned int num_mcceq_processed, num_ioeq_processed;
  785. struct be_ctrl_info *ctrl;
  786. struct be_eq_obj *pbe_eq;
  787. int isr;
  788. phba = dev_id;
  789. ctrl = &phba->ctrl;
  790. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  791. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  792. if (!isr)
  793. return IRQ_NONE;
  794. phwi_ctrlr = phba->phwi_ctrlr;
  795. phwi_context = phwi_ctrlr->phwi_ctxt;
  796. pbe_eq = &phwi_context->be_eq[0];
  797. eq = &phwi_context->be_eq[0].q;
  798. mcc = &phba->ctrl.mcc_obj.cq;
  799. index = 0;
  800. eqe = queue_tail_node(eq);
  801. num_ioeq_processed = 0;
  802. num_mcceq_processed = 0;
  803. if (blk_iopoll_enabled) {
  804. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  805. & EQE_VALID_MASK) {
  806. if (((eqe->dw[offsetof(struct amap_eq_entry,
  807. resource_id) / 32] &
  808. EQE_RESID_MASK) >> 16) == mcc->id) {
  809. spin_lock_irqsave(&phba->isr_lock, flags);
  810. pbe_eq->todo_mcc_cq = true;
  811. spin_unlock_irqrestore(&phba->isr_lock, flags);
  812. num_mcceq_processed++;
  813. } else {
  814. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  815. blk_iopoll_sched(&pbe_eq->iopoll);
  816. num_ioeq_processed++;
  817. }
  818. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  819. queue_tail_inc(eq);
  820. eqe = queue_tail_node(eq);
  821. }
  822. if (num_ioeq_processed || num_mcceq_processed) {
  823. if (pbe_eq->todo_mcc_cq)
  824. queue_work(phba->wq, &pbe_eq->work_cqs);
  825. if ((num_mcceq_processed) && (!num_ioeq_processed))
  826. hwi_ring_eq_db(phba, eq->id, 0,
  827. (num_ioeq_processed +
  828. num_mcceq_processed) , 1, 1);
  829. else
  830. hwi_ring_eq_db(phba, eq->id, 0,
  831. (num_ioeq_processed +
  832. num_mcceq_processed), 0, 1);
  833. return IRQ_HANDLED;
  834. } else
  835. return IRQ_NONE;
  836. } else {
  837. cq = &phwi_context->be_cq[0];
  838. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  839. & EQE_VALID_MASK) {
  840. if (((eqe->dw[offsetof(struct amap_eq_entry,
  841. resource_id) / 32] &
  842. EQE_RESID_MASK) >> 16) != cq->id) {
  843. spin_lock_irqsave(&phba->isr_lock, flags);
  844. pbe_eq->todo_mcc_cq = true;
  845. spin_unlock_irqrestore(&phba->isr_lock, flags);
  846. } else {
  847. spin_lock_irqsave(&phba->isr_lock, flags);
  848. pbe_eq->todo_cq = true;
  849. spin_unlock_irqrestore(&phba->isr_lock, flags);
  850. }
  851. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  852. queue_tail_inc(eq);
  853. eqe = queue_tail_node(eq);
  854. num_ioeq_processed++;
  855. }
  856. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  857. queue_work(phba->wq, &pbe_eq->work_cqs);
  858. if (num_ioeq_processed) {
  859. hwi_ring_eq_db(phba, eq->id, 0,
  860. num_ioeq_processed, 1, 1);
  861. return IRQ_HANDLED;
  862. } else
  863. return IRQ_NONE;
  864. }
  865. }
  866. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  867. {
  868. struct pci_dev *pcidev = phba->pcidev;
  869. struct hwi_controller *phwi_ctrlr;
  870. struct hwi_context_memory *phwi_context;
  871. int ret, msix_vec, i, j;
  872. phwi_ctrlr = phba->phwi_ctrlr;
  873. phwi_context = phwi_ctrlr->phwi_ctxt;
  874. if (phba->msix_enabled) {
  875. for (i = 0; i < phba->num_cpus; i++) {
  876. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  877. GFP_KERNEL);
  878. if (!phba->msi_name[i]) {
  879. ret = -ENOMEM;
  880. goto free_msix_irqs;
  881. }
  882. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  883. phba->shost->host_no, i);
  884. msix_vec = phba->msix_entries[i].vector;
  885. ret = request_irq(msix_vec, be_isr_msix, 0,
  886. phba->msi_name[i],
  887. &phwi_context->be_eq[i]);
  888. if (ret) {
  889. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  890. "BM_%d : beiscsi_init_irqs-Failed to"
  891. "register msix for i = %d\n",
  892. i);
  893. kfree(phba->msi_name[i]);
  894. goto free_msix_irqs;
  895. }
  896. }
  897. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  898. if (!phba->msi_name[i]) {
  899. ret = -ENOMEM;
  900. goto free_msix_irqs;
  901. }
  902. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  903. phba->shost->host_no);
  904. msix_vec = phba->msix_entries[i].vector;
  905. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  906. &phwi_context->be_eq[i]);
  907. if (ret) {
  908. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  909. "BM_%d : beiscsi_init_irqs-"
  910. "Failed to register beiscsi_msix_mcc\n");
  911. kfree(phba->msi_name[i]);
  912. goto free_msix_irqs;
  913. }
  914. } else {
  915. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  916. "beiscsi", phba);
  917. if (ret) {
  918. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  919. "BM_%d : beiscsi_init_irqs-"
  920. "Failed to register irq\\n");
  921. return ret;
  922. }
  923. }
  924. return 0;
  925. free_msix_irqs:
  926. for (j = i - 1; j >= 0; j--) {
  927. kfree(phba->msi_name[j]);
  928. msix_vec = phba->msix_entries[j].vector;
  929. free_irq(msix_vec, &phwi_context->be_eq[j]);
  930. }
  931. return ret;
  932. }
  933. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  934. unsigned int id, unsigned int num_processed,
  935. unsigned char rearm, unsigned char event)
  936. {
  937. u32 val = 0;
  938. val |= id & DB_CQ_RING_ID_MASK;
  939. if (rearm)
  940. val |= 1 << DB_CQ_REARM_SHIFT;
  941. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  942. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  943. }
  944. static unsigned int
  945. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  946. struct beiscsi_hba *phba,
  947. struct pdu_base *ppdu,
  948. unsigned long pdu_len,
  949. void *pbuffer, unsigned long buf_len)
  950. {
  951. struct iscsi_conn *conn = beiscsi_conn->conn;
  952. struct iscsi_session *session = conn->session;
  953. struct iscsi_task *task;
  954. struct beiscsi_io_task *io_task;
  955. struct iscsi_hdr *login_hdr;
  956. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  957. PDUBASE_OPCODE_MASK) {
  958. case ISCSI_OP_NOOP_IN:
  959. pbuffer = NULL;
  960. buf_len = 0;
  961. break;
  962. case ISCSI_OP_ASYNC_EVENT:
  963. break;
  964. case ISCSI_OP_REJECT:
  965. WARN_ON(!pbuffer);
  966. WARN_ON(!(buf_len == 48));
  967. beiscsi_log(phba, KERN_ERR,
  968. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  969. "BM_%d : In ISCSI_OP_REJECT\n");
  970. break;
  971. case ISCSI_OP_LOGIN_RSP:
  972. case ISCSI_OP_TEXT_RSP:
  973. task = conn->login_task;
  974. io_task = task->dd_data;
  975. login_hdr = (struct iscsi_hdr *)ppdu;
  976. login_hdr->itt = io_task->libiscsi_itt;
  977. break;
  978. default:
  979. beiscsi_log(phba, KERN_WARNING,
  980. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  981. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  982. (ppdu->
  983. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  984. & PDUBASE_OPCODE_MASK));
  985. return 1;
  986. }
  987. spin_lock_bh(&session->lock);
  988. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  989. spin_unlock_bh(&session->lock);
  990. return 0;
  991. }
  992. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  993. {
  994. struct sgl_handle *psgl_handle;
  995. if (phba->io_sgl_hndl_avbl) {
  996. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  997. "BM_%d : In alloc_io_sgl_handle,"
  998. " io_sgl_alloc_index=%d\n",
  999. phba->io_sgl_alloc_index);
  1000. psgl_handle = phba->io_sgl_hndl_base[phba->
  1001. io_sgl_alloc_index];
  1002. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  1003. phba->io_sgl_hndl_avbl--;
  1004. if (phba->io_sgl_alloc_index == (phba->params.
  1005. ios_per_ctrl - 1))
  1006. phba->io_sgl_alloc_index = 0;
  1007. else
  1008. phba->io_sgl_alloc_index++;
  1009. } else
  1010. psgl_handle = NULL;
  1011. return psgl_handle;
  1012. }
  1013. static void
  1014. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1015. {
  1016. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1017. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1018. phba->io_sgl_free_index);
  1019. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1020. /*
  1021. * this can happen if clean_task is called on a task that
  1022. * failed in xmit_task or alloc_pdu.
  1023. */
  1024. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1025. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1026. "value there=%p\n", phba->io_sgl_free_index,
  1027. phba->io_sgl_hndl_base
  1028. [phba->io_sgl_free_index]);
  1029. return;
  1030. }
  1031. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1032. phba->io_sgl_hndl_avbl++;
  1033. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1034. phba->io_sgl_free_index = 0;
  1035. else
  1036. phba->io_sgl_free_index++;
  1037. }
  1038. /**
  1039. * alloc_wrb_handle - To allocate a wrb handle
  1040. * @phba: The hba pointer
  1041. * @cid: The cid to use for allocation
  1042. *
  1043. * This happens under session_lock until submission to chip
  1044. */
  1045. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1046. {
  1047. struct hwi_wrb_context *pwrb_context;
  1048. struct hwi_controller *phwi_ctrlr;
  1049. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1050. uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
  1051. phwi_ctrlr = phba->phwi_ctrlr;
  1052. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1053. if (pwrb_context->wrb_handles_available >= 2) {
  1054. pwrb_handle = pwrb_context->pwrb_handle_base[
  1055. pwrb_context->alloc_index];
  1056. pwrb_context->wrb_handles_available--;
  1057. if (pwrb_context->alloc_index ==
  1058. (phba->params.wrbs_per_cxn - 1))
  1059. pwrb_context->alloc_index = 0;
  1060. else
  1061. pwrb_context->alloc_index++;
  1062. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1063. pwrb_context->alloc_index];
  1064. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1065. } else
  1066. pwrb_handle = NULL;
  1067. return pwrb_handle;
  1068. }
  1069. /**
  1070. * free_wrb_handle - To free the wrb handle back to pool
  1071. * @phba: The hba pointer
  1072. * @pwrb_context: The context to free from
  1073. * @pwrb_handle: The wrb_handle to free
  1074. *
  1075. * This happens under session_lock until submission to chip
  1076. */
  1077. static void
  1078. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1079. struct wrb_handle *pwrb_handle)
  1080. {
  1081. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1082. pwrb_context->wrb_handles_available++;
  1083. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1084. pwrb_context->free_index = 0;
  1085. else
  1086. pwrb_context->free_index++;
  1087. beiscsi_log(phba, KERN_INFO,
  1088. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1089. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1090. "wrb_handles_available=%d\n",
  1091. pwrb_handle, pwrb_context->free_index,
  1092. pwrb_context->wrb_handles_available);
  1093. }
  1094. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1095. {
  1096. struct sgl_handle *psgl_handle;
  1097. if (phba->eh_sgl_hndl_avbl) {
  1098. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1099. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1100. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1101. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1102. phba->eh_sgl_alloc_index,
  1103. phba->eh_sgl_alloc_index);
  1104. phba->eh_sgl_hndl_avbl--;
  1105. if (phba->eh_sgl_alloc_index ==
  1106. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1107. 1))
  1108. phba->eh_sgl_alloc_index = 0;
  1109. else
  1110. phba->eh_sgl_alloc_index++;
  1111. } else
  1112. psgl_handle = NULL;
  1113. return psgl_handle;
  1114. }
  1115. void
  1116. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1117. {
  1118. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1119. "BM_%d : In free_mgmt_sgl_handle,"
  1120. "eh_sgl_free_index=%d\n",
  1121. phba->eh_sgl_free_index);
  1122. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1123. /*
  1124. * this can happen if clean_task is called on a task that
  1125. * failed in xmit_task or alloc_pdu.
  1126. */
  1127. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1128. "BM_%d : Double Free in eh SGL ,"
  1129. "eh_sgl_free_index=%d\n",
  1130. phba->eh_sgl_free_index);
  1131. return;
  1132. }
  1133. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1134. phba->eh_sgl_hndl_avbl++;
  1135. if (phba->eh_sgl_free_index ==
  1136. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1137. phba->eh_sgl_free_index = 0;
  1138. else
  1139. phba->eh_sgl_free_index++;
  1140. }
  1141. static void
  1142. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1143. struct iscsi_task *task,
  1144. struct common_sol_cqe *csol_cqe)
  1145. {
  1146. struct beiscsi_io_task *io_task = task->dd_data;
  1147. struct be_status_bhs *sts_bhs =
  1148. (struct be_status_bhs *)io_task->cmd_bhs;
  1149. struct iscsi_conn *conn = beiscsi_conn->conn;
  1150. unsigned char *sense;
  1151. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1152. u8 rsp, status, flags;
  1153. exp_cmdsn = csol_cqe->exp_cmdsn;
  1154. max_cmdsn = (csol_cqe->exp_cmdsn +
  1155. csol_cqe->cmd_wnd - 1);
  1156. rsp = csol_cqe->i_resp;
  1157. status = csol_cqe->i_sts;
  1158. flags = csol_cqe->i_flags;
  1159. resid = csol_cqe->res_cnt;
  1160. if (!task->sc) {
  1161. if (io_task->scsi_cmnd)
  1162. scsi_dma_unmap(io_task->scsi_cmnd);
  1163. return;
  1164. }
  1165. task->sc->result = (DID_OK << 16) | status;
  1166. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1167. task->sc->result = DID_ERROR << 16;
  1168. goto unmap;
  1169. }
  1170. /* bidi not initially supported */
  1171. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1172. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1173. task->sc->result = DID_ERROR << 16;
  1174. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1175. scsi_set_resid(task->sc, resid);
  1176. if (!status && (scsi_bufflen(task->sc) - resid <
  1177. task->sc->underflow))
  1178. task->sc->result = DID_ERROR << 16;
  1179. }
  1180. }
  1181. if (status == SAM_STAT_CHECK_CONDITION) {
  1182. u16 sense_len;
  1183. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1184. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1185. sense_len = be16_to_cpu(*slen);
  1186. memcpy(task->sc->sense_buffer, sense,
  1187. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1188. }
  1189. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1190. conn->rxdata_octets += resid;
  1191. unmap:
  1192. scsi_dma_unmap(io_task->scsi_cmnd);
  1193. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1194. }
  1195. static void
  1196. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1197. struct iscsi_task *task,
  1198. struct common_sol_cqe *csol_cqe)
  1199. {
  1200. struct iscsi_logout_rsp *hdr;
  1201. struct beiscsi_io_task *io_task = task->dd_data;
  1202. struct iscsi_conn *conn = beiscsi_conn->conn;
  1203. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1204. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1205. hdr->t2wait = 5;
  1206. hdr->t2retain = 0;
  1207. hdr->flags = csol_cqe->i_flags;
  1208. hdr->response = csol_cqe->i_resp;
  1209. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1210. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1211. csol_cqe->cmd_wnd - 1);
  1212. hdr->dlength[0] = 0;
  1213. hdr->dlength[1] = 0;
  1214. hdr->dlength[2] = 0;
  1215. hdr->hlength = 0;
  1216. hdr->itt = io_task->libiscsi_itt;
  1217. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1218. }
  1219. static void
  1220. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1221. struct iscsi_task *task,
  1222. struct common_sol_cqe *csol_cqe)
  1223. {
  1224. struct iscsi_tm_rsp *hdr;
  1225. struct iscsi_conn *conn = beiscsi_conn->conn;
  1226. struct beiscsi_io_task *io_task = task->dd_data;
  1227. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1228. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1229. hdr->flags = csol_cqe->i_flags;
  1230. hdr->response = csol_cqe->i_resp;
  1231. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1232. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1233. csol_cqe->cmd_wnd - 1);
  1234. hdr->itt = io_task->libiscsi_itt;
  1235. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1236. }
  1237. static void
  1238. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1239. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1240. {
  1241. struct hwi_wrb_context *pwrb_context;
  1242. struct wrb_handle *pwrb_handle = NULL;
  1243. struct hwi_controller *phwi_ctrlr;
  1244. struct iscsi_task *task;
  1245. struct beiscsi_io_task *io_task;
  1246. uint16_t wrb_index, cid, cri_index;
  1247. phwi_ctrlr = phba->phwi_ctrlr;
  1248. if (is_chip_be2_be3r(phba)) {
  1249. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1250. wrb_idx, psol);
  1251. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1252. cid, psol);
  1253. } else {
  1254. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1255. wrb_idx, psol);
  1256. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1257. cid, psol);
  1258. }
  1259. cri_index = BE_GET_CRI_FROM_CID(cid);
  1260. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1261. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1262. task = pwrb_handle->pio_handle;
  1263. io_task = task->dd_data;
  1264. memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
  1265. iscsi_put_task(task);
  1266. }
  1267. static void
  1268. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1269. struct iscsi_task *task,
  1270. struct common_sol_cqe *csol_cqe)
  1271. {
  1272. struct iscsi_nopin *hdr;
  1273. struct iscsi_conn *conn = beiscsi_conn->conn;
  1274. struct beiscsi_io_task *io_task = task->dd_data;
  1275. hdr = (struct iscsi_nopin *)task->hdr;
  1276. hdr->flags = csol_cqe->i_flags;
  1277. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1278. hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
  1279. csol_cqe->cmd_wnd - 1);
  1280. hdr->opcode = ISCSI_OP_NOOP_IN;
  1281. hdr->itt = io_task->libiscsi_itt;
  1282. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1283. }
  1284. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1285. struct sol_cqe *psol,
  1286. struct common_sol_cqe *csol_cqe)
  1287. {
  1288. if (is_chip_be2_be3r(phba)) {
  1289. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1290. i_exp_cmd_sn, psol);
  1291. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1292. i_res_cnt, psol);
  1293. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1294. i_cmd_wnd, psol);
  1295. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1296. wrb_index, psol);
  1297. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1298. cid, psol);
  1299. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1300. hw_sts, psol);
  1301. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1302. i_resp, psol);
  1303. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1304. i_sts, psol);
  1305. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1306. i_flags, psol);
  1307. } else {
  1308. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1309. i_exp_cmd_sn, psol);
  1310. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1311. i_res_cnt, psol);
  1312. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1313. wrb_index, psol);
  1314. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1315. cid, psol);
  1316. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1317. hw_sts, psol);
  1318. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1319. i_cmd_wnd, psol);
  1320. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1321. cmd_cmpl, psol))
  1322. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1323. i_sts, psol);
  1324. else
  1325. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1326. i_sts, psol);
  1327. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1328. u, psol))
  1329. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1330. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1331. o, psol))
  1332. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1333. }
  1334. }
  1335. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1336. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1337. {
  1338. struct hwi_wrb_context *pwrb_context;
  1339. struct wrb_handle *pwrb_handle;
  1340. struct iscsi_wrb *pwrb = NULL;
  1341. struct hwi_controller *phwi_ctrlr;
  1342. struct iscsi_task *task;
  1343. unsigned int type;
  1344. struct iscsi_conn *conn = beiscsi_conn->conn;
  1345. struct iscsi_session *session = conn->session;
  1346. struct common_sol_cqe csol_cqe = {0};
  1347. uint16_t cri_index = 0;
  1348. phwi_ctrlr = phba->phwi_ctrlr;
  1349. /* Copy the elements to a common structure */
  1350. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1351. cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
  1352. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  1353. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1354. csol_cqe.wrb_index];
  1355. task = pwrb_handle->pio_handle;
  1356. pwrb = pwrb_handle->pwrb;
  1357. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1358. spin_lock_bh(&session->lock);
  1359. switch (type) {
  1360. case HWH_TYPE_IO:
  1361. case HWH_TYPE_IO_RD:
  1362. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1363. ISCSI_OP_NOOP_OUT)
  1364. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1365. else
  1366. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1367. break;
  1368. case HWH_TYPE_LOGOUT:
  1369. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1370. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1371. else
  1372. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1373. break;
  1374. case HWH_TYPE_LOGIN:
  1375. beiscsi_log(phba, KERN_ERR,
  1376. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1377. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1378. " hwi_complete_cmd- Solicited path\n");
  1379. break;
  1380. case HWH_TYPE_NOP:
  1381. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1382. break;
  1383. default:
  1384. beiscsi_log(phba, KERN_WARNING,
  1385. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1386. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1387. "wrb_index 0x%x CID 0x%x\n", type,
  1388. csol_cqe.wrb_index,
  1389. csol_cqe.cid);
  1390. break;
  1391. }
  1392. spin_unlock_bh(&session->lock);
  1393. }
  1394. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1395. *pasync_ctx, unsigned int is_header,
  1396. unsigned int host_write_ptr)
  1397. {
  1398. if (is_header)
  1399. return &pasync_ctx->async_entry[host_write_ptr].
  1400. header_busy_list;
  1401. else
  1402. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1403. }
  1404. static struct async_pdu_handle *
  1405. hwi_get_async_handle(struct beiscsi_hba *phba,
  1406. struct beiscsi_conn *beiscsi_conn,
  1407. struct hwi_async_pdu_context *pasync_ctx,
  1408. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1409. {
  1410. struct be_bus_address phys_addr;
  1411. struct list_head *pbusy_list;
  1412. struct async_pdu_handle *pasync_handle = NULL;
  1413. unsigned char is_header = 0;
  1414. unsigned int index, dpl;
  1415. if (is_chip_be2_be3r(phba)) {
  1416. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1417. dpl, pdpdu_cqe);
  1418. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1419. index, pdpdu_cqe);
  1420. } else {
  1421. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1422. dpl, pdpdu_cqe);
  1423. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1424. index, pdpdu_cqe);
  1425. }
  1426. phys_addr.u.a32.address_lo =
  1427. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1428. db_addr_lo) / 32] - dpl);
  1429. phys_addr.u.a32.address_hi =
  1430. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1431. db_addr_hi) / 32];
  1432. phys_addr.u.a64.address =
  1433. *((unsigned long long *)(&phys_addr.u.a64.address));
  1434. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1435. & PDUCQE_CODE_MASK) {
  1436. case UNSOL_HDR_NOTIFY:
  1437. is_header = 1;
  1438. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1439. is_header, index);
  1440. break;
  1441. case UNSOL_DATA_NOTIFY:
  1442. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1443. is_header, index);
  1444. break;
  1445. default:
  1446. pbusy_list = NULL;
  1447. beiscsi_log(phba, KERN_WARNING,
  1448. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1449. "BM_%d : Unexpected code=%d\n",
  1450. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1451. code) / 32] & PDUCQE_CODE_MASK);
  1452. return NULL;
  1453. }
  1454. WARN_ON(list_empty(pbusy_list));
  1455. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1456. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1457. break;
  1458. }
  1459. WARN_ON(!pasync_handle);
  1460. pasync_handle->cri =
  1461. BE_GET_CRI_FROM_CID(beiscsi_conn->beiscsi_conn_cid);
  1462. pasync_handle->is_header = is_header;
  1463. pasync_handle->buffer_len = dpl;
  1464. *pcq_index = index;
  1465. return pasync_handle;
  1466. }
  1467. static unsigned int
  1468. hwi_update_async_writables(struct beiscsi_hba *phba,
  1469. struct hwi_async_pdu_context *pasync_ctx,
  1470. unsigned int is_header, unsigned int cq_index)
  1471. {
  1472. struct list_head *pbusy_list;
  1473. struct async_pdu_handle *pasync_handle;
  1474. unsigned int num_entries, writables = 0;
  1475. unsigned int *pep_read_ptr, *pwritables;
  1476. num_entries = pasync_ctx->num_entries;
  1477. if (is_header) {
  1478. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1479. pwritables = &pasync_ctx->async_header.writables;
  1480. } else {
  1481. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1482. pwritables = &pasync_ctx->async_data.writables;
  1483. }
  1484. while ((*pep_read_ptr) != cq_index) {
  1485. (*pep_read_ptr)++;
  1486. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1487. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1488. *pep_read_ptr);
  1489. if (writables == 0)
  1490. WARN_ON(list_empty(pbusy_list));
  1491. if (!list_empty(pbusy_list)) {
  1492. pasync_handle = list_entry(pbusy_list->next,
  1493. struct async_pdu_handle,
  1494. link);
  1495. WARN_ON(!pasync_handle);
  1496. pasync_handle->consumed = 1;
  1497. }
  1498. writables++;
  1499. }
  1500. if (!writables) {
  1501. beiscsi_log(phba, KERN_ERR,
  1502. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1503. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1504. cq_index);
  1505. WARN_ON(1);
  1506. }
  1507. *pwritables = *pwritables + writables;
  1508. return 0;
  1509. }
  1510. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1511. unsigned int cri)
  1512. {
  1513. struct hwi_controller *phwi_ctrlr;
  1514. struct hwi_async_pdu_context *pasync_ctx;
  1515. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1516. struct list_head *plist;
  1517. phwi_ctrlr = phba->phwi_ctrlr;
  1518. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1519. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1520. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1521. list_del(&pasync_handle->link);
  1522. if (pasync_handle->is_header) {
  1523. list_add_tail(&pasync_handle->link,
  1524. &pasync_ctx->async_header.free_list);
  1525. pasync_ctx->async_header.free_entries++;
  1526. } else {
  1527. list_add_tail(&pasync_handle->link,
  1528. &pasync_ctx->async_data.free_list);
  1529. pasync_ctx->async_data.free_entries++;
  1530. }
  1531. }
  1532. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1533. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1534. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1535. }
  1536. static struct phys_addr *
  1537. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1538. unsigned int is_header, unsigned int host_write_ptr)
  1539. {
  1540. struct phys_addr *pasync_sge = NULL;
  1541. if (is_header)
  1542. pasync_sge = pasync_ctx->async_header.ring_base;
  1543. else
  1544. pasync_sge = pasync_ctx->async_data.ring_base;
  1545. return pasync_sge + host_write_ptr;
  1546. }
  1547. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1548. unsigned int is_header)
  1549. {
  1550. struct hwi_controller *phwi_ctrlr;
  1551. struct hwi_async_pdu_context *pasync_ctx;
  1552. struct async_pdu_handle *pasync_handle;
  1553. struct list_head *pfree_link, *pbusy_list;
  1554. struct phys_addr *pasync_sge;
  1555. unsigned int ring_id, num_entries;
  1556. unsigned int host_write_num;
  1557. unsigned int writables;
  1558. unsigned int i = 0;
  1559. u32 doorbell = 0;
  1560. phwi_ctrlr = phba->phwi_ctrlr;
  1561. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1562. num_entries = pasync_ctx->num_entries;
  1563. if (is_header) {
  1564. writables = min(pasync_ctx->async_header.writables,
  1565. pasync_ctx->async_header.free_entries);
  1566. pfree_link = pasync_ctx->async_header.free_list.next;
  1567. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1568. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1569. } else {
  1570. writables = min(pasync_ctx->async_data.writables,
  1571. pasync_ctx->async_data.free_entries);
  1572. pfree_link = pasync_ctx->async_data.free_list.next;
  1573. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1574. ring_id = phwi_ctrlr->default_pdu_data.id;
  1575. }
  1576. writables = (writables / 8) * 8;
  1577. if (writables) {
  1578. for (i = 0; i < writables; i++) {
  1579. pbusy_list =
  1580. hwi_get_async_busy_list(pasync_ctx, is_header,
  1581. host_write_num);
  1582. pasync_handle =
  1583. list_entry(pfree_link, struct async_pdu_handle,
  1584. link);
  1585. WARN_ON(!pasync_handle);
  1586. pasync_handle->consumed = 0;
  1587. pfree_link = pfree_link->next;
  1588. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1589. is_header, host_write_num);
  1590. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1591. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1592. list_move(&pasync_handle->link, pbusy_list);
  1593. host_write_num++;
  1594. host_write_num = host_write_num % num_entries;
  1595. }
  1596. if (is_header) {
  1597. pasync_ctx->async_header.host_write_ptr =
  1598. host_write_num;
  1599. pasync_ctx->async_header.free_entries -= writables;
  1600. pasync_ctx->async_header.writables -= writables;
  1601. pasync_ctx->async_header.busy_entries += writables;
  1602. } else {
  1603. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1604. pasync_ctx->async_data.free_entries -= writables;
  1605. pasync_ctx->async_data.writables -= writables;
  1606. pasync_ctx->async_data.busy_entries += writables;
  1607. }
  1608. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1609. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1610. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1611. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1612. << DB_DEF_PDU_CQPROC_SHIFT;
  1613. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1614. }
  1615. }
  1616. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1617. struct beiscsi_conn *beiscsi_conn,
  1618. struct i_t_dpdu_cqe *pdpdu_cqe)
  1619. {
  1620. struct hwi_controller *phwi_ctrlr;
  1621. struct hwi_async_pdu_context *pasync_ctx;
  1622. struct async_pdu_handle *pasync_handle = NULL;
  1623. unsigned int cq_index = -1;
  1624. phwi_ctrlr = phba->phwi_ctrlr;
  1625. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1626. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1627. pdpdu_cqe, &cq_index);
  1628. BUG_ON(pasync_handle->is_header != 0);
  1629. if (pasync_handle->consumed == 0)
  1630. hwi_update_async_writables(phba, pasync_ctx,
  1631. pasync_handle->is_header, cq_index);
  1632. hwi_free_async_msg(phba, pasync_handle->cri);
  1633. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1634. }
  1635. static unsigned int
  1636. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1637. struct beiscsi_hba *phba,
  1638. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1639. {
  1640. struct list_head *plist;
  1641. struct async_pdu_handle *pasync_handle;
  1642. void *phdr = NULL;
  1643. unsigned int hdr_len = 0, buf_len = 0;
  1644. unsigned int status, index = 0, offset = 0;
  1645. void *pfirst_buffer = NULL;
  1646. unsigned int num_buf = 0;
  1647. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1648. list_for_each_entry(pasync_handle, plist, link) {
  1649. if (index == 0) {
  1650. phdr = pasync_handle->pbuffer;
  1651. hdr_len = pasync_handle->buffer_len;
  1652. } else {
  1653. buf_len = pasync_handle->buffer_len;
  1654. if (!num_buf) {
  1655. pfirst_buffer = pasync_handle->pbuffer;
  1656. num_buf++;
  1657. }
  1658. memcpy(pfirst_buffer + offset,
  1659. pasync_handle->pbuffer, buf_len);
  1660. offset += buf_len;
  1661. }
  1662. index++;
  1663. }
  1664. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1665. phdr, hdr_len, pfirst_buffer,
  1666. offset);
  1667. hwi_free_async_msg(phba, cri);
  1668. return 0;
  1669. }
  1670. static unsigned int
  1671. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1672. struct beiscsi_hba *phba,
  1673. struct async_pdu_handle *pasync_handle)
  1674. {
  1675. struct hwi_async_pdu_context *pasync_ctx;
  1676. struct hwi_controller *phwi_ctrlr;
  1677. unsigned int bytes_needed = 0, status = 0;
  1678. unsigned short cri = pasync_handle->cri;
  1679. struct pdu_base *ppdu;
  1680. phwi_ctrlr = phba->phwi_ctrlr;
  1681. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1682. list_del(&pasync_handle->link);
  1683. if (pasync_handle->is_header) {
  1684. pasync_ctx->async_header.busy_entries--;
  1685. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1686. hwi_free_async_msg(phba, cri);
  1687. BUG();
  1688. }
  1689. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1690. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1691. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1692. (unsigned short)pasync_handle->buffer_len;
  1693. list_add_tail(&pasync_handle->link,
  1694. &pasync_ctx->async_entry[cri].wait_queue.list);
  1695. ppdu = pasync_handle->pbuffer;
  1696. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1697. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1698. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1699. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1700. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1701. if (status == 0) {
  1702. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1703. bytes_needed;
  1704. if (bytes_needed == 0)
  1705. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1706. pasync_ctx, cri);
  1707. }
  1708. } else {
  1709. pasync_ctx->async_data.busy_entries--;
  1710. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1711. list_add_tail(&pasync_handle->link,
  1712. &pasync_ctx->async_entry[cri].wait_queue.
  1713. list);
  1714. pasync_ctx->async_entry[cri].wait_queue.
  1715. bytes_received +=
  1716. (unsigned short)pasync_handle->buffer_len;
  1717. if (pasync_ctx->async_entry[cri].wait_queue.
  1718. bytes_received >=
  1719. pasync_ctx->async_entry[cri].wait_queue.
  1720. bytes_needed)
  1721. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1722. pasync_ctx, cri);
  1723. }
  1724. }
  1725. return status;
  1726. }
  1727. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1728. struct beiscsi_hba *phba,
  1729. struct i_t_dpdu_cqe *pdpdu_cqe)
  1730. {
  1731. struct hwi_controller *phwi_ctrlr;
  1732. struct hwi_async_pdu_context *pasync_ctx;
  1733. struct async_pdu_handle *pasync_handle = NULL;
  1734. unsigned int cq_index = -1;
  1735. phwi_ctrlr = phba->phwi_ctrlr;
  1736. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1737. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1738. pdpdu_cqe, &cq_index);
  1739. if (pasync_handle->consumed == 0)
  1740. hwi_update_async_writables(phba, pasync_ctx,
  1741. pasync_handle->is_header, cq_index);
  1742. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1743. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1744. }
  1745. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1746. {
  1747. struct be_queue_info *mcc_cq;
  1748. struct be_mcc_compl *mcc_compl;
  1749. unsigned int num_processed = 0;
  1750. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1751. mcc_compl = queue_tail_node(mcc_cq);
  1752. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1753. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1754. if (num_processed >= 32) {
  1755. hwi_ring_cq_db(phba, mcc_cq->id,
  1756. num_processed, 0, 0);
  1757. num_processed = 0;
  1758. }
  1759. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1760. /* Interpret flags as an async trailer */
  1761. if (is_link_state_evt(mcc_compl->flags))
  1762. /* Interpret compl as a async link evt */
  1763. beiscsi_async_link_state_process(phba,
  1764. (struct be_async_event_link_state *) mcc_compl);
  1765. else
  1766. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1767. "BM_%d : Unsupported Async Event, flags"
  1768. " = 0x%08x\n",
  1769. mcc_compl->flags);
  1770. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1771. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1772. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1773. }
  1774. mcc_compl->flags = 0;
  1775. queue_tail_inc(mcc_cq);
  1776. mcc_compl = queue_tail_node(mcc_cq);
  1777. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1778. num_processed++;
  1779. }
  1780. if (num_processed > 0)
  1781. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1782. }
  1783. /**
  1784. * beiscsi_process_cq()- Process the Completion Queue
  1785. * @pbe_eq: Event Q on which the Completion has come
  1786. *
  1787. * return
  1788. * Number of Completion Entries processed.
  1789. **/
  1790. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1791. {
  1792. struct be_queue_info *cq;
  1793. struct sol_cqe *sol;
  1794. struct dmsg_cqe *dmsg;
  1795. unsigned int num_processed = 0;
  1796. unsigned int tot_nump = 0;
  1797. unsigned short code = 0, cid = 0;
  1798. uint16_t cri_index = 0;
  1799. struct beiscsi_conn *beiscsi_conn;
  1800. struct beiscsi_endpoint *beiscsi_ep;
  1801. struct iscsi_endpoint *ep;
  1802. struct beiscsi_hba *phba;
  1803. cq = pbe_eq->cq;
  1804. sol = queue_tail_node(cq);
  1805. phba = pbe_eq->phba;
  1806. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1807. CQE_VALID_MASK) {
  1808. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1809. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1810. 32] & CQE_CODE_MASK);
  1811. /* Get the CID */
  1812. if (is_chip_be2_be3r(phba)) {
  1813. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1814. } else {
  1815. if ((code == DRIVERMSG_NOTIFY) ||
  1816. (code == UNSOL_HDR_NOTIFY) ||
  1817. (code == UNSOL_DATA_NOTIFY))
  1818. cid = AMAP_GET_BITS(
  1819. struct amap_i_t_dpdu_cqe_v2,
  1820. cid, sol);
  1821. else
  1822. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1823. cid, sol);
  1824. }
  1825. cri_index = BE_GET_CRI_FROM_CID(cid);
  1826. ep = phba->ep_array[cri_index];
  1827. beiscsi_ep = ep->dd_data;
  1828. beiscsi_conn = beiscsi_ep->conn;
  1829. if (num_processed >= 32) {
  1830. hwi_ring_cq_db(phba, cq->id,
  1831. num_processed, 0, 0);
  1832. tot_nump += num_processed;
  1833. num_processed = 0;
  1834. }
  1835. switch (code) {
  1836. case SOL_CMD_COMPLETE:
  1837. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1838. break;
  1839. case DRIVERMSG_NOTIFY:
  1840. beiscsi_log(phba, KERN_INFO,
  1841. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1842. "BM_%d : Received %s[%d] on CID : %d\n",
  1843. cqe_desc[code], code, cid);
  1844. dmsg = (struct dmsg_cqe *)sol;
  1845. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1846. break;
  1847. case UNSOL_HDR_NOTIFY:
  1848. beiscsi_log(phba, KERN_INFO,
  1849. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1850. "BM_%d : Received %s[%d] on CID : %d\n",
  1851. cqe_desc[code], code, cid);
  1852. spin_lock_bh(&phba->async_pdu_lock);
  1853. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1854. (struct i_t_dpdu_cqe *)sol);
  1855. spin_unlock_bh(&phba->async_pdu_lock);
  1856. break;
  1857. case UNSOL_DATA_NOTIFY:
  1858. beiscsi_log(phba, KERN_INFO,
  1859. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1860. "BM_%d : Received %s[%d] on CID : %d\n",
  1861. cqe_desc[code], code, cid);
  1862. spin_lock_bh(&phba->async_pdu_lock);
  1863. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1864. (struct i_t_dpdu_cqe *)sol);
  1865. spin_unlock_bh(&phba->async_pdu_lock);
  1866. break;
  1867. case CXN_INVALIDATE_INDEX_NOTIFY:
  1868. case CMD_INVALIDATED_NOTIFY:
  1869. case CXN_INVALIDATE_NOTIFY:
  1870. beiscsi_log(phba, KERN_ERR,
  1871. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1872. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1873. cqe_desc[code], code, cid);
  1874. break;
  1875. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1876. case CMD_KILLED_INVALID_STATSN_RCVD:
  1877. case CMD_KILLED_INVALID_R2T_RCVD:
  1878. case CMD_CXN_KILLED_LUN_INVALID:
  1879. case CMD_CXN_KILLED_ICD_INVALID:
  1880. case CMD_CXN_KILLED_ITT_INVALID:
  1881. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1882. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1883. beiscsi_log(phba, KERN_ERR,
  1884. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1885. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1886. cqe_desc[code], code, cid);
  1887. break;
  1888. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1889. beiscsi_log(phba, KERN_ERR,
  1890. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1891. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1892. cqe_desc[code], code, cid);
  1893. spin_lock_bh(&phba->async_pdu_lock);
  1894. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1895. (struct i_t_dpdu_cqe *) sol);
  1896. spin_unlock_bh(&phba->async_pdu_lock);
  1897. break;
  1898. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1899. case CXN_KILLED_BURST_LEN_MISMATCH:
  1900. case CXN_KILLED_AHS_RCVD:
  1901. case CXN_KILLED_HDR_DIGEST_ERR:
  1902. case CXN_KILLED_UNKNOWN_HDR:
  1903. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1904. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1905. case CXN_KILLED_TIMED_OUT:
  1906. case CXN_KILLED_FIN_RCVD:
  1907. case CXN_KILLED_RST_SENT:
  1908. case CXN_KILLED_RST_RCVD:
  1909. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1910. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1911. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1912. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1913. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1914. beiscsi_log(phba, KERN_ERR,
  1915. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1916. "BM_%d : Event %s[%d] received on CID : %d\n",
  1917. cqe_desc[code], code, cid);
  1918. if (beiscsi_conn)
  1919. iscsi_conn_failure(beiscsi_conn->conn,
  1920. ISCSI_ERR_CONN_FAILED);
  1921. break;
  1922. default:
  1923. beiscsi_log(phba, KERN_ERR,
  1924. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1925. "BM_%d : Invalid CQE Event Received Code : %d"
  1926. "CID 0x%x...\n",
  1927. code, cid);
  1928. break;
  1929. }
  1930. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1931. queue_tail_inc(cq);
  1932. sol = queue_tail_node(cq);
  1933. num_processed++;
  1934. }
  1935. if (num_processed > 0) {
  1936. tot_nump += num_processed;
  1937. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1938. }
  1939. return tot_nump;
  1940. }
  1941. void beiscsi_process_all_cqs(struct work_struct *work)
  1942. {
  1943. unsigned long flags;
  1944. struct hwi_controller *phwi_ctrlr;
  1945. struct hwi_context_memory *phwi_context;
  1946. struct beiscsi_hba *phba;
  1947. struct be_eq_obj *pbe_eq =
  1948. container_of(work, struct be_eq_obj, work_cqs);
  1949. phba = pbe_eq->phba;
  1950. phwi_ctrlr = phba->phwi_ctrlr;
  1951. phwi_context = phwi_ctrlr->phwi_ctxt;
  1952. if (pbe_eq->todo_mcc_cq) {
  1953. spin_lock_irqsave(&phba->isr_lock, flags);
  1954. pbe_eq->todo_mcc_cq = false;
  1955. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1956. beiscsi_process_mcc_isr(phba);
  1957. }
  1958. if (pbe_eq->todo_cq) {
  1959. spin_lock_irqsave(&phba->isr_lock, flags);
  1960. pbe_eq->todo_cq = false;
  1961. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1962. beiscsi_process_cq(pbe_eq);
  1963. }
  1964. /* rearm EQ for further interrupts */
  1965. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1966. }
  1967. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1968. {
  1969. unsigned int ret;
  1970. struct beiscsi_hba *phba;
  1971. struct be_eq_obj *pbe_eq;
  1972. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1973. ret = beiscsi_process_cq(pbe_eq);
  1974. if (ret < budget) {
  1975. phba = pbe_eq->phba;
  1976. blk_iopoll_complete(iop);
  1977. beiscsi_log(phba, KERN_INFO,
  1978. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1979. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1980. pbe_eq->q.id);
  1981. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1982. }
  1983. return ret;
  1984. }
  1985. static void
  1986. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1987. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1988. {
  1989. struct iscsi_sge *psgl;
  1990. unsigned int sg_len, index;
  1991. unsigned int sge_len = 0;
  1992. unsigned long long addr;
  1993. struct scatterlist *l_sg;
  1994. unsigned int offset;
  1995. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  1996. io_task->bhs_pa.u.a32.address_lo);
  1997. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  1998. io_task->bhs_pa.u.a32.address_hi);
  1999. l_sg = sg;
  2000. for (index = 0; (index < num_sg) && (index < 2); index++,
  2001. sg = sg_next(sg)) {
  2002. if (index == 0) {
  2003. sg_len = sg_dma_len(sg);
  2004. addr = (u64) sg_dma_address(sg);
  2005. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2006. sge0_addr_lo, pwrb,
  2007. lower_32_bits(addr));
  2008. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2009. sge0_addr_hi, pwrb,
  2010. upper_32_bits(addr));
  2011. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2012. sge0_len, pwrb,
  2013. sg_len);
  2014. sge_len = sg_len;
  2015. } else {
  2016. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2017. pwrb, sge_len);
  2018. sg_len = sg_dma_len(sg);
  2019. addr = (u64) sg_dma_address(sg);
  2020. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2021. sge1_addr_lo, pwrb,
  2022. lower_32_bits(addr));
  2023. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2024. sge1_addr_hi, pwrb,
  2025. upper_32_bits(addr));
  2026. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2027. sge1_len, pwrb,
  2028. sg_len);
  2029. }
  2030. }
  2031. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2032. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2033. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2034. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2035. io_task->bhs_pa.u.a32.address_hi);
  2036. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2037. io_task->bhs_pa.u.a32.address_lo);
  2038. if (num_sg == 1) {
  2039. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2040. 1);
  2041. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2042. 0);
  2043. } else if (num_sg == 2) {
  2044. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2045. 0);
  2046. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2047. 1);
  2048. } else {
  2049. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2050. 0);
  2051. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2052. 0);
  2053. }
  2054. sg = l_sg;
  2055. psgl++;
  2056. psgl++;
  2057. offset = 0;
  2058. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2059. sg_len = sg_dma_len(sg);
  2060. addr = (u64) sg_dma_address(sg);
  2061. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2062. lower_32_bits(addr));
  2063. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2064. upper_32_bits(addr));
  2065. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2066. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2067. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2068. offset += sg_len;
  2069. }
  2070. psgl--;
  2071. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2072. }
  2073. static void
  2074. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2075. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2076. {
  2077. struct iscsi_sge *psgl;
  2078. unsigned int sg_len, index;
  2079. unsigned int sge_len = 0;
  2080. unsigned long long addr;
  2081. struct scatterlist *l_sg;
  2082. unsigned int offset;
  2083. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2084. io_task->bhs_pa.u.a32.address_lo);
  2085. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2086. io_task->bhs_pa.u.a32.address_hi);
  2087. l_sg = sg;
  2088. for (index = 0; (index < num_sg) && (index < 2); index++,
  2089. sg = sg_next(sg)) {
  2090. if (index == 0) {
  2091. sg_len = sg_dma_len(sg);
  2092. addr = (u64) sg_dma_address(sg);
  2093. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2094. ((u32)(addr & 0xFFFFFFFF)));
  2095. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2096. ((u32)(addr >> 32)));
  2097. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2098. sg_len);
  2099. sge_len = sg_len;
  2100. } else {
  2101. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2102. pwrb, sge_len);
  2103. sg_len = sg_dma_len(sg);
  2104. addr = (u64) sg_dma_address(sg);
  2105. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2106. ((u32)(addr & 0xFFFFFFFF)));
  2107. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2108. ((u32)(addr >> 32)));
  2109. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2110. sg_len);
  2111. }
  2112. }
  2113. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2114. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2115. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2116. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2117. io_task->bhs_pa.u.a32.address_hi);
  2118. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2119. io_task->bhs_pa.u.a32.address_lo);
  2120. if (num_sg == 1) {
  2121. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2122. 1);
  2123. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2124. 0);
  2125. } else if (num_sg == 2) {
  2126. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2127. 0);
  2128. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2129. 1);
  2130. } else {
  2131. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2132. 0);
  2133. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2134. 0);
  2135. }
  2136. sg = l_sg;
  2137. psgl++;
  2138. psgl++;
  2139. offset = 0;
  2140. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2141. sg_len = sg_dma_len(sg);
  2142. addr = (u64) sg_dma_address(sg);
  2143. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2144. (addr & 0xFFFFFFFF));
  2145. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2146. (addr >> 32));
  2147. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2148. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2149. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2150. offset += sg_len;
  2151. }
  2152. psgl--;
  2153. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2154. }
  2155. /**
  2156. * hwi_write_buffer()- Populate the WRB with task info
  2157. * @pwrb: ptr to the WRB entry
  2158. * @task: iscsi task which is to be executed
  2159. **/
  2160. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2161. {
  2162. struct iscsi_sge *psgl;
  2163. struct beiscsi_io_task *io_task = task->dd_data;
  2164. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2165. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2166. uint8_t dsp_value = 0;
  2167. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2168. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2169. io_task->bhs_pa.u.a32.address_lo);
  2170. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2171. io_task->bhs_pa.u.a32.address_hi);
  2172. if (task->data) {
  2173. /* Check for the data_count */
  2174. dsp_value = (task->data_count) ? 1 : 0;
  2175. if (is_chip_be2_be3r(phba))
  2176. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2177. pwrb, dsp_value);
  2178. else
  2179. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2180. pwrb, dsp_value);
  2181. /* Map addr only if there is data_count */
  2182. if (dsp_value) {
  2183. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2184. task->data,
  2185. task->data_count,
  2186. PCI_DMA_TODEVICE);
  2187. io_task->mtask_data_count = task->data_count;
  2188. } else
  2189. io_task->mtask_addr = 0;
  2190. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2191. lower_32_bits(io_task->mtask_addr));
  2192. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2193. upper_32_bits(io_task->mtask_addr));
  2194. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2195. task->data_count);
  2196. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2197. } else {
  2198. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2199. io_task->mtask_addr = 0;
  2200. }
  2201. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2202. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2203. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2204. io_task->bhs_pa.u.a32.address_hi);
  2205. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2206. io_task->bhs_pa.u.a32.address_lo);
  2207. if (task->data) {
  2208. psgl++;
  2209. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2210. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2211. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2212. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2213. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2214. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2215. psgl++;
  2216. if (task->data) {
  2217. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2218. lower_32_bits(io_task->mtask_addr));
  2219. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2220. upper_32_bits(io_task->mtask_addr));
  2221. }
  2222. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2223. }
  2224. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2225. }
  2226. /**
  2227. * beiscsi_find_mem_req()- Find mem needed
  2228. * @phba: ptr to HBA struct
  2229. **/
  2230. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2231. {
  2232. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2233. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2234. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2235. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2236. sizeof(struct sol_cqe));
  2237. num_async_pdu_buf_pages =
  2238. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2239. phba->params.defpdu_hdr_sz);
  2240. num_async_pdu_buf_sgl_pages =
  2241. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2242. sizeof(struct phys_addr));
  2243. num_async_pdu_data_pages =
  2244. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2245. phba->params.defpdu_data_sz);
  2246. num_async_pdu_data_sgl_pages =
  2247. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2248. sizeof(struct phys_addr));
  2249. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2250. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2251. BE_ISCSI_PDU_HEADER_SIZE;
  2252. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2253. sizeof(struct hwi_context_memory);
  2254. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2255. * (phba->params.wrbs_per_cxn)
  2256. * phba->params.cxns_per_ctrl;
  2257. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2258. (phba->params.wrbs_per_cxn);
  2259. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2260. phba->params.cxns_per_ctrl);
  2261. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2262. phba->params.icds_per_ctrl;
  2263. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2264. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2265. phba->mem_req[HWI_MEM_TEMPLATE_HDR] = phba->params.cxns_per_ctrl *
  2266. BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
  2267. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2268. num_async_pdu_buf_pages * PAGE_SIZE;
  2269. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2270. num_async_pdu_data_pages * PAGE_SIZE;
  2271. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2272. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2273. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2274. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2275. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2276. phba->params.asyncpdus_per_ctrl *
  2277. sizeof(struct async_pdu_handle);
  2278. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2279. phba->params.asyncpdus_per_ctrl *
  2280. sizeof(struct async_pdu_handle);
  2281. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2282. sizeof(struct hwi_async_pdu_context) +
  2283. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2284. }
  2285. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2286. {
  2287. dma_addr_t bus_add;
  2288. struct hwi_controller *phwi_ctrlr;
  2289. struct be_mem_descriptor *mem_descr;
  2290. struct mem_array *mem_arr, *mem_arr_orig;
  2291. unsigned int i, j, alloc_size, curr_alloc_size;
  2292. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2293. if (!phba->phwi_ctrlr)
  2294. return -ENOMEM;
  2295. /* Allocate memory for wrb_context */
  2296. phwi_ctrlr = phba->phwi_ctrlr;
  2297. phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
  2298. phba->params.cxns_per_ctrl,
  2299. GFP_KERNEL);
  2300. if (!phwi_ctrlr->wrb_context)
  2301. return -ENOMEM;
  2302. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2303. GFP_KERNEL);
  2304. if (!phba->init_mem) {
  2305. kfree(phwi_ctrlr->wrb_context);
  2306. kfree(phba->phwi_ctrlr);
  2307. return -ENOMEM;
  2308. }
  2309. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2310. GFP_KERNEL);
  2311. if (!mem_arr_orig) {
  2312. kfree(phba->init_mem);
  2313. kfree(phwi_ctrlr->wrb_context);
  2314. kfree(phba->phwi_ctrlr);
  2315. return -ENOMEM;
  2316. }
  2317. mem_descr = phba->init_mem;
  2318. for (i = 0; i < SE_MEM_MAX; i++) {
  2319. j = 0;
  2320. mem_arr = mem_arr_orig;
  2321. alloc_size = phba->mem_req[i];
  2322. memset(mem_arr, 0, sizeof(struct mem_array) *
  2323. BEISCSI_MAX_FRAGS_INIT);
  2324. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2325. do {
  2326. mem_arr->virtual_address = pci_alloc_consistent(
  2327. phba->pcidev,
  2328. curr_alloc_size,
  2329. &bus_add);
  2330. if (!mem_arr->virtual_address) {
  2331. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2332. goto free_mem;
  2333. if (curr_alloc_size -
  2334. rounddown_pow_of_two(curr_alloc_size))
  2335. curr_alloc_size = rounddown_pow_of_two
  2336. (curr_alloc_size);
  2337. else
  2338. curr_alloc_size = curr_alloc_size / 2;
  2339. } else {
  2340. mem_arr->bus_address.u.
  2341. a64.address = (__u64) bus_add;
  2342. mem_arr->size = curr_alloc_size;
  2343. alloc_size -= curr_alloc_size;
  2344. curr_alloc_size = min(be_max_phys_size *
  2345. 1024, alloc_size);
  2346. j++;
  2347. mem_arr++;
  2348. }
  2349. } while (alloc_size);
  2350. mem_descr->num_elements = j;
  2351. mem_descr->size_in_bytes = phba->mem_req[i];
  2352. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2353. GFP_KERNEL);
  2354. if (!mem_descr->mem_array)
  2355. goto free_mem;
  2356. memcpy(mem_descr->mem_array, mem_arr_orig,
  2357. sizeof(struct mem_array) * j);
  2358. mem_descr++;
  2359. }
  2360. kfree(mem_arr_orig);
  2361. return 0;
  2362. free_mem:
  2363. mem_descr->num_elements = j;
  2364. while ((i) || (j)) {
  2365. for (j = mem_descr->num_elements; j > 0; j--) {
  2366. pci_free_consistent(phba->pcidev,
  2367. mem_descr->mem_array[j - 1].size,
  2368. mem_descr->mem_array[j - 1].
  2369. virtual_address,
  2370. (unsigned long)mem_descr->
  2371. mem_array[j - 1].
  2372. bus_address.u.a64.address);
  2373. }
  2374. if (i) {
  2375. i--;
  2376. kfree(mem_descr->mem_array);
  2377. mem_descr--;
  2378. }
  2379. }
  2380. kfree(mem_arr_orig);
  2381. kfree(phba->init_mem);
  2382. kfree(phba->phwi_ctrlr->wrb_context);
  2383. kfree(phba->phwi_ctrlr);
  2384. return -ENOMEM;
  2385. }
  2386. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2387. {
  2388. beiscsi_find_mem_req(phba);
  2389. return beiscsi_alloc_mem(phba);
  2390. }
  2391. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2392. {
  2393. struct pdu_data_out *pdata_out;
  2394. struct pdu_nop_out *pnop_out;
  2395. struct be_mem_descriptor *mem_descr;
  2396. mem_descr = phba->init_mem;
  2397. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2398. pdata_out =
  2399. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2400. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2401. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2402. IIOC_SCSI_DATA);
  2403. pnop_out =
  2404. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2405. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2406. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2407. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2408. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2409. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2410. }
  2411. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2412. {
  2413. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2414. struct hwi_context_memory *phwi_ctxt;
  2415. struct wrb_handle *pwrb_handle = NULL;
  2416. struct hwi_controller *phwi_ctrlr;
  2417. struct hwi_wrb_context *pwrb_context;
  2418. struct iscsi_wrb *pwrb = NULL;
  2419. unsigned int num_cxn_wrbh = 0;
  2420. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2421. mem_descr_wrbh = phba->init_mem;
  2422. mem_descr_wrbh += HWI_MEM_WRBH;
  2423. mem_descr_wrb = phba->init_mem;
  2424. mem_descr_wrb += HWI_MEM_WRB;
  2425. phwi_ctrlr = phba->phwi_ctrlr;
  2426. /* Allocate memory for WRBQ */
  2427. phwi_ctxt = phwi_ctrlr->phwi_ctxt;
  2428. phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
  2429. phba->params.cxns_per_ctrl,
  2430. GFP_KERNEL);
  2431. if (!phwi_ctxt->be_wrbq) {
  2432. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2433. "BM_%d : WRBQ Mem Alloc Failed\n");
  2434. return -ENOMEM;
  2435. }
  2436. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2437. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2438. pwrb_context->pwrb_handle_base =
  2439. kzalloc(sizeof(struct wrb_handle *) *
  2440. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2441. if (!pwrb_context->pwrb_handle_base) {
  2442. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2443. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2444. goto init_wrb_hndl_failed;
  2445. }
  2446. pwrb_context->pwrb_handle_basestd =
  2447. kzalloc(sizeof(struct wrb_handle *) *
  2448. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2449. if (!pwrb_context->pwrb_handle_basestd) {
  2450. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2451. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2452. goto init_wrb_hndl_failed;
  2453. }
  2454. if (!num_cxn_wrbh) {
  2455. pwrb_handle =
  2456. mem_descr_wrbh->mem_array[idx].virtual_address;
  2457. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2458. ((sizeof(struct wrb_handle)) *
  2459. phba->params.wrbs_per_cxn));
  2460. idx++;
  2461. }
  2462. pwrb_context->alloc_index = 0;
  2463. pwrb_context->wrb_handles_available = 0;
  2464. pwrb_context->free_index = 0;
  2465. if (num_cxn_wrbh) {
  2466. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2467. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2468. pwrb_context->pwrb_handle_basestd[j] =
  2469. pwrb_handle;
  2470. pwrb_context->wrb_handles_available++;
  2471. pwrb_handle->wrb_index = j;
  2472. pwrb_handle++;
  2473. }
  2474. num_cxn_wrbh--;
  2475. }
  2476. }
  2477. idx = 0;
  2478. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  2479. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2480. if (!num_cxn_wrb) {
  2481. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2482. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2483. ((sizeof(struct iscsi_wrb) *
  2484. phba->params.wrbs_per_cxn));
  2485. idx++;
  2486. }
  2487. if (num_cxn_wrb) {
  2488. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2489. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2490. pwrb_handle->pwrb = pwrb;
  2491. pwrb++;
  2492. }
  2493. num_cxn_wrb--;
  2494. }
  2495. }
  2496. return 0;
  2497. init_wrb_hndl_failed:
  2498. for (j = index; j > 0; j--) {
  2499. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2500. kfree(pwrb_context->pwrb_handle_base);
  2501. kfree(pwrb_context->pwrb_handle_basestd);
  2502. }
  2503. return -ENOMEM;
  2504. }
  2505. static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2506. {
  2507. struct hwi_controller *phwi_ctrlr;
  2508. struct hba_parameters *p = &phba->params;
  2509. struct hwi_async_pdu_context *pasync_ctx;
  2510. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2511. unsigned int index, idx, num_per_mem, num_async_data;
  2512. struct be_mem_descriptor *mem_descr;
  2513. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2514. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2515. phwi_ctrlr = phba->phwi_ctrlr;
  2516. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2517. mem_descr->mem_array[0].virtual_address;
  2518. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2519. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2520. pasync_ctx->async_entry = kzalloc(sizeof(struct hwi_async_entry) *
  2521. phba->params.cxns_per_ctrl,
  2522. GFP_KERNEL);
  2523. if (!pasync_ctx->async_entry) {
  2524. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2525. "BM_%d : hwi_init_async_pdu_ctx Mem Alloc Failed\n");
  2526. return -ENOMEM;
  2527. }
  2528. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2529. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2530. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2531. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2532. if (mem_descr->mem_array[0].virtual_address) {
  2533. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2534. "BM_%d : hwi_init_async_pdu_ctx"
  2535. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2536. mem_descr->mem_array[0].virtual_address);
  2537. } else
  2538. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2539. "BM_%d : No Virtual address\n");
  2540. pasync_ctx->async_header.va_base =
  2541. mem_descr->mem_array[0].virtual_address;
  2542. pasync_ctx->async_header.pa_base.u.a64.address =
  2543. mem_descr->mem_array[0].bus_address.u.a64.address;
  2544. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2545. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2546. if (mem_descr->mem_array[0].virtual_address) {
  2547. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2548. "BM_%d : hwi_init_async_pdu_ctx"
  2549. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2550. mem_descr->mem_array[0].virtual_address);
  2551. } else
  2552. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2553. "BM_%d : No Virtual address\n");
  2554. pasync_ctx->async_header.ring_base =
  2555. mem_descr->mem_array[0].virtual_address;
  2556. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2557. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2558. if (mem_descr->mem_array[0].virtual_address) {
  2559. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2560. "BM_%d : hwi_init_async_pdu_ctx"
  2561. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2562. mem_descr->mem_array[0].virtual_address);
  2563. } else
  2564. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2565. "BM_%d : No Virtual address\n");
  2566. pasync_ctx->async_header.handle_base =
  2567. mem_descr->mem_array[0].virtual_address;
  2568. pasync_ctx->async_header.writables = 0;
  2569. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2570. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2571. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2572. if (mem_descr->mem_array[0].virtual_address) {
  2573. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2574. "BM_%d : hwi_init_async_pdu_ctx"
  2575. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2576. mem_descr->mem_array[0].virtual_address);
  2577. } else
  2578. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2579. "BM_%d : No Virtual address\n");
  2580. pasync_ctx->async_data.ring_base =
  2581. mem_descr->mem_array[0].virtual_address;
  2582. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2583. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2584. if (!mem_descr->mem_array[0].virtual_address)
  2585. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2586. "BM_%d : No Virtual address\n");
  2587. pasync_ctx->async_data.handle_base =
  2588. mem_descr->mem_array[0].virtual_address;
  2589. pasync_ctx->async_data.writables = 0;
  2590. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2591. pasync_header_h =
  2592. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2593. pasync_data_h =
  2594. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2595. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2596. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2597. if (mem_descr->mem_array[0].virtual_address) {
  2598. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2599. "BM_%d : hwi_init_async_pdu_ctx"
  2600. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2601. mem_descr->mem_array[0].virtual_address);
  2602. } else
  2603. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2604. "BM_%d : No Virtual address\n");
  2605. idx = 0;
  2606. pasync_ctx->async_data.va_base =
  2607. mem_descr->mem_array[idx].virtual_address;
  2608. pasync_ctx->async_data.pa_base.u.a64.address =
  2609. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2610. num_async_data = ((mem_descr->mem_array[idx].size) /
  2611. phba->params.defpdu_data_sz);
  2612. num_per_mem = 0;
  2613. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2614. pasync_header_h->cri = -1;
  2615. pasync_header_h->index = (char)index;
  2616. INIT_LIST_HEAD(&pasync_header_h->link);
  2617. pasync_header_h->pbuffer =
  2618. (void *)((unsigned long)
  2619. (pasync_ctx->async_header.va_base) +
  2620. (p->defpdu_hdr_sz * index));
  2621. pasync_header_h->pa.u.a64.address =
  2622. pasync_ctx->async_header.pa_base.u.a64.address +
  2623. (p->defpdu_hdr_sz * index);
  2624. list_add_tail(&pasync_header_h->link,
  2625. &pasync_ctx->async_header.free_list);
  2626. pasync_header_h++;
  2627. pasync_ctx->async_header.free_entries++;
  2628. pasync_ctx->async_header.writables++;
  2629. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2630. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2631. header_busy_list);
  2632. pasync_data_h->cri = -1;
  2633. pasync_data_h->index = (char)index;
  2634. INIT_LIST_HEAD(&pasync_data_h->link);
  2635. if (!num_async_data) {
  2636. num_per_mem = 0;
  2637. idx++;
  2638. pasync_ctx->async_data.va_base =
  2639. mem_descr->mem_array[idx].virtual_address;
  2640. pasync_ctx->async_data.pa_base.u.a64.address =
  2641. mem_descr->mem_array[idx].
  2642. bus_address.u.a64.address;
  2643. num_async_data = ((mem_descr->mem_array[idx].size) /
  2644. phba->params.defpdu_data_sz);
  2645. }
  2646. pasync_data_h->pbuffer =
  2647. (void *)((unsigned long)
  2648. (pasync_ctx->async_data.va_base) +
  2649. (p->defpdu_data_sz * num_per_mem));
  2650. pasync_data_h->pa.u.a64.address =
  2651. pasync_ctx->async_data.pa_base.u.a64.address +
  2652. (p->defpdu_data_sz * num_per_mem);
  2653. num_per_mem++;
  2654. num_async_data--;
  2655. list_add_tail(&pasync_data_h->link,
  2656. &pasync_ctx->async_data.free_list);
  2657. pasync_data_h++;
  2658. pasync_ctx->async_data.free_entries++;
  2659. pasync_ctx->async_data.writables++;
  2660. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2661. }
  2662. pasync_ctx->async_header.host_write_ptr = 0;
  2663. pasync_ctx->async_header.ep_read_ptr = -1;
  2664. pasync_ctx->async_data.host_write_ptr = 0;
  2665. pasync_ctx->async_data.ep_read_ptr = -1;
  2666. return 0;
  2667. }
  2668. static int
  2669. be_sgl_create_contiguous(void *virtual_address,
  2670. u64 physical_address, u32 length,
  2671. struct be_dma_mem *sgl)
  2672. {
  2673. WARN_ON(!virtual_address);
  2674. WARN_ON(!physical_address);
  2675. WARN_ON(!length > 0);
  2676. WARN_ON(!sgl);
  2677. sgl->va = virtual_address;
  2678. sgl->dma = (unsigned long)physical_address;
  2679. sgl->size = length;
  2680. return 0;
  2681. }
  2682. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2683. {
  2684. memset(sgl, 0, sizeof(*sgl));
  2685. }
  2686. static void
  2687. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2688. struct mem_array *pmem, struct be_dma_mem *sgl)
  2689. {
  2690. if (sgl->va)
  2691. be_sgl_destroy_contiguous(sgl);
  2692. be_sgl_create_contiguous(pmem->virtual_address,
  2693. pmem->bus_address.u.a64.address,
  2694. pmem->size, sgl);
  2695. }
  2696. static void
  2697. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2698. struct mem_array *pmem, struct be_dma_mem *sgl)
  2699. {
  2700. if (sgl->va)
  2701. be_sgl_destroy_contiguous(sgl);
  2702. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2703. pmem->bus_address.u.a64.address,
  2704. pmem->size, sgl);
  2705. }
  2706. static int be_fill_queue(struct be_queue_info *q,
  2707. u16 len, u16 entry_size, void *vaddress)
  2708. {
  2709. struct be_dma_mem *mem = &q->dma_mem;
  2710. memset(q, 0, sizeof(*q));
  2711. q->len = len;
  2712. q->entry_size = entry_size;
  2713. mem->size = len * entry_size;
  2714. mem->va = vaddress;
  2715. if (!mem->va)
  2716. return -ENOMEM;
  2717. memset(mem->va, 0, mem->size);
  2718. return 0;
  2719. }
  2720. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2721. struct hwi_context_memory *phwi_context)
  2722. {
  2723. unsigned int i, num_eq_pages;
  2724. int ret = 0, eq_for_mcc;
  2725. struct be_queue_info *eq;
  2726. struct be_dma_mem *mem;
  2727. void *eq_vaddress;
  2728. dma_addr_t paddr;
  2729. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2730. sizeof(struct be_eq_entry));
  2731. if (phba->msix_enabled)
  2732. eq_for_mcc = 1;
  2733. else
  2734. eq_for_mcc = 0;
  2735. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2736. eq = &phwi_context->be_eq[i].q;
  2737. mem = &eq->dma_mem;
  2738. phwi_context->be_eq[i].phba = phba;
  2739. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2740. num_eq_pages * PAGE_SIZE,
  2741. &paddr);
  2742. if (!eq_vaddress)
  2743. goto create_eq_error;
  2744. mem->va = eq_vaddress;
  2745. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2746. sizeof(struct be_eq_entry), eq_vaddress);
  2747. if (ret) {
  2748. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2749. "BM_%d : be_fill_queue Failed for EQ\n");
  2750. goto create_eq_error;
  2751. }
  2752. mem->dma = paddr;
  2753. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2754. phwi_context->cur_eqd);
  2755. if (ret) {
  2756. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2757. "BM_%d : beiscsi_cmd_eq_create"
  2758. "Failed for EQ\n");
  2759. goto create_eq_error;
  2760. }
  2761. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2762. "BM_%d : eqid = %d\n",
  2763. phwi_context->be_eq[i].q.id);
  2764. }
  2765. return 0;
  2766. create_eq_error:
  2767. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2768. eq = &phwi_context->be_eq[i].q;
  2769. mem = &eq->dma_mem;
  2770. if (mem->va)
  2771. pci_free_consistent(phba->pcidev, num_eq_pages
  2772. * PAGE_SIZE,
  2773. mem->va, mem->dma);
  2774. }
  2775. return ret;
  2776. }
  2777. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2778. struct hwi_context_memory *phwi_context)
  2779. {
  2780. unsigned int i, num_cq_pages;
  2781. int ret = 0;
  2782. struct be_queue_info *cq, *eq;
  2783. struct be_dma_mem *mem;
  2784. struct be_eq_obj *pbe_eq;
  2785. void *cq_vaddress;
  2786. dma_addr_t paddr;
  2787. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2788. sizeof(struct sol_cqe));
  2789. for (i = 0; i < phba->num_cpus; i++) {
  2790. cq = &phwi_context->be_cq[i];
  2791. eq = &phwi_context->be_eq[i].q;
  2792. pbe_eq = &phwi_context->be_eq[i];
  2793. pbe_eq->cq = cq;
  2794. pbe_eq->phba = phba;
  2795. mem = &cq->dma_mem;
  2796. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2797. num_cq_pages * PAGE_SIZE,
  2798. &paddr);
  2799. if (!cq_vaddress)
  2800. goto create_cq_error;
  2801. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2802. sizeof(struct sol_cqe), cq_vaddress);
  2803. if (ret) {
  2804. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2805. "BM_%d : be_fill_queue Failed "
  2806. "for ISCSI CQ\n");
  2807. goto create_cq_error;
  2808. }
  2809. mem->dma = paddr;
  2810. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2811. false, 0);
  2812. if (ret) {
  2813. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2814. "BM_%d : beiscsi_cmd_eq_create"
  2815. "Failed for ISCSI CQ\n");
  2816. goto create_cq_error;
  2817. }
  2818. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2819. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2820. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2821. }
  2822. return 0;
  2823. create_cq_error:
  2824. for (i = 0; i < phba->num_cpus; i++) {
  2825. cq = &phwi_context->be_cq[i];
  2826. mem = &cq->dma_mem;
  2827. if (mem->va)
  2828. pci_free_consistent(phba->pcidev, num_cq_pages
  2829. * PAGE_SIZE,
  2830. mem->va, mem->dma);
  2831. }
  2832. return ret;
  2833. }
  2834. static int
  2835. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2836. struct hwi_context_memory *phwi_context,
  2837. struct hwi_controller *phwi_ctrlr,
  2838. unsigned int def_pdu_ring_sz)
  2839. {
  2840. unsigned int idx;
  2841. int ret;
  2842. struct be_queue_info *dq, *cq;
  2843. struct be_dma_mem *mem;
  2844. struct be_mem_descriptor *mem_descr;
  2845. void *dq_vaddress;
  2846. idx = 0;
  2847. dq = &phwi_context->be_def_hdrq;
  2848. cq = &phwi_context->be_cq[0];
  2849. mem = &dq->dma_mem;
  2850. mem_descr = phba->init_mem;
  2851. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2852. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2853. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2854. sizeof(struct phys_addr),
  2855. sizeof(struct phys_addr), dq_vaddress);
  2856. if (ret) {
  2857. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2858. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2859. return ret;
  2860. }
  2861. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2862. bus_address.u.a64.address;
  2863. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2864. def_pdu_ring_sz,
  2865. phba->params.defpdu_hdr_sz);
  2866. if (ret) {
  2867. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2868. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2869. return ret;
  2870. }
  2871. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2872. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2873. "BM_%d : iscsi def pdu id is %d\n",
  2874. phwi_context->be_def_hdrq.id);
  2875. hwi_post_async_buffers(phba, 1);
  2876. return 0;
  2877. }
  2878. static int
  2879. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2880. struct hwi_context_memory *phwi_context,
  2881. struct hwi_controller *phwi_ctrlr,
  2882. unsigned int def_pdu_ring_sz)
  2883. {
  2884. unsigned int idx;
  2885. int ret;
  2886. struct be_queue_info *dataq, *cq;
  2887. struct be_dma_mem *mem;
  2888. struct be_mem_descriptor *mem_descr;
  2889. void *dq_vaddress;
  2890. idx = 0;
  2891. dataq = &phwi_context->be_def_dataq;
  2892. cq = &phwi_context->be_cq[0];
  2893. mem = &dataq->dma_mem;
  2894. mem_descr = phba->init_mem;
  2895. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2896. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2897. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2898. sizeof(struct phys_addr),
  2899. sizeof(struct phys_addr), dq_vaddress);
  2900. if (ret) {
  2901. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2902. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2903. return ret;
  2904. }
  2905. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2906. bus_address.u.a64.address;
  2907. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2908. def_pdu_ring_sz,
  2909. phba->params.defpdu_data_sz);
  2910. if (ret) {
  2911. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2912. "BM_%d be_cmd_create_default_pdu_queue"
  2913. " Failed for DEF PDU DATA\n");
  2914. return ret;
  2915. }
  2916. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2917. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2918. "BM_%d : iscsi def data id is %d\n",
  2919. phwi_context->be_def_dataq.id);
  2920. hwi_post_async_buffers(phba, 0);
  2921. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2922. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2923. return 0;
  2924. }
  2925. static int
  2926. beiscsi_post_template_hdr(struct beiscsi_hba *phba)
  2927. {
  2928. struct be_mem_descriptor *mem_descr;
  2929. struct mem_array *pm_arr;
  2930. struct be_dma_mem sgl;
  2931. int status, i;
  2932. mem_descr = phba->init_mem;
  2933. mem_descr += HWI_MEM_TEMPLATE_HDR;
  2934. pm_arr = mem_descr->mem_array;
  2935. for (i = 0; i < mem_descr->num_elements; i++) {
  2936. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2937. status = be_cmd_iscsi_post_template_hdr(&phba->ctrl, &sgl);
  2938. if (status != 0) {
  2939. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2940. "BM_%d : Post Template HDR Failed\n");
  2941. return status;
  2942. }
  2943. }
  2944. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2945. "BM_%d : Template HDR Pages Posted\n");
  2946. return 0;
  2947. }
  2948. static int
  2949. beiscsi_post_pages(struct beiscsi_hba *phba)
  2950. {
  2951. struct be_mem_descriptor *mem_descr;
  2952. struct mem_array *pm_arr;
  2953. unsigned int page_offset, i;
  2954. struct be_dma_mem sgl;
  2955. int status, ulp_num = 0;
  2956. mem_descr = phba->init_mem;
  2957. mem_descr += HWI_MEM_SGE;
  2958. pm_arr = mem_descr->mem_array;
  2959. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2960. phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
  2961. for (i = 0; i < mem_descr->num_elements; i++) {
  2962. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2963. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2964. page_offset,
  2965. (pm_arr->size / PAGE_SIZE));
  2966. page_offset += pm_arr->size / PAGE_SIZE;
  2967. if (status != 0) {
  2968. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2969. "BM_%d : post sgl failed.\n");
  2970. return status;
  2971. }
  2972. pm_arr++;
  2973. }
  2974. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2975. "BM_%d : POSTED PAGES\n");
  2976. return 0;
  2977. }
  2978. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2979. {
  2980. struct be_dma_mem *mem = &q->dma_mem;
  2981. if (mem->va) {
  2982. pci_free_consistent(phba->pcidev, mem->size,
  2983. mem->va, mem->dma);
  2984. mem->va = NULL;
  2985. }
  2986. }
  2987. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2988. u16 len, u16 entry_size)
  2989. {
  2990. struct be_dma_mem *mem = &q->dma_mem;
  2991. memset(q, 0, sizeof(*q));
  2992. q->len = len;
  2993. q->entry_size = entry_size;
  2994. mem->size = len * entry_size;
  2995. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2996. if (!mem->va)
  2997. return -ENOMEM;
  2998. memset(mem->va, 0, mem->size);
  2999. return 0;
  3000. }
  3001. static int
  3002. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  3003. struct hwi_context_memory *phwi_context,
  3004. struct hwi_controller *phwi_ctrlr)
  3005. {
  3006. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  3007. u64 pa_addr_lo;
  3008. unsigned int idx, num, i;
  3009. struct mem_array *pwrb_arr;
  3010. void *wrb_vaddr;
  3011. struct be_dma_mem sgl;
  3012. struct be_mem_descriptor *mem_descr;
  3013. struct hwi_wrb_context *pwrb_context;
  3014. int status;
  3015. idx = 0;
  3016. mem_descr = phba->init_mem;
  3017. mem_descr += HWI_MEM_WRB;
  3018. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  3019. GFP_KERNEL);
  3020. if (!pwrb_arr) {
  3021. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3022. "BM_%d : Memory alloc failed in create wrb ring.\n");
  3023. return -ENOMEM;
  3024. }
  3025. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3026. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  3027. num_wrb_rings = mem_descr->mem_array[idx].size /
  3028. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  3029. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  3030. if (num_wrb_rings) {
  3031. pwrb_arr[num].virtual_address = wrb_vaddr;
  3032. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  3033. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3034. sizeof(struct iscsi_wrb);
  3035. wrb_vaddr += pwrb_arr[num].size;
  3036. pa_addr_lo += pwrb_arr[num].size;
  3037. num_wrb_rings--;
  3038. } else {
  3039. idx++;
  3040. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  3041. pa_addr_lo = mem_descr->mem_array[idx].\
  3042. bus_address.u.a64.address;
  3043. num_wrb_rings = mem_descr->mem_array[idx].size /
  3044. (phba->params.wrbs_per_cxn *
  3045. sizeof(struct iscsi_wrb));
  3046. pwrb_arr[num].virtual_address = wrb_vaddr;
  3047. pwrb_arr[num].bus_address.u.a64.address\
  3048. = pa_addr_lo;
  3049. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  3050. sizeof(struct iscsi_wrb);
  3051. wrb_vaddr += pwrb_arr[num].size;
  3052. pa_addr_lo += pwrb_arr[num].size;
  3053. num_wrb_rings--;
  3054. }
  3055. }
  3056. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3057. wrb_mem_index = 0;
  3058. offset = 0;
  3059. size = 0;
  3060. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  3061. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  3062. &phwi_context->be_wrbq[i]);
  3063. if (status != 0) {
  3064. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3065. "BM_%d : wrbq create failed.");
  3066. kfree(pwrb_arr);
  3067. return status;
  3068. }
  3069. pwrb_context = &phwi_ctrlr->wrb_context[i];
  3070. pwrb_context->cid = phwi_context->be_wrbq[i].id;
  3071. BE_SET_CID_TO_CRI(i, pwrb_context->cid);
  3072. }
  3073. kfree(pwrb_arr);
  3074. return 0;
  3075. }
  3076. static void free_wrb_handles(struct beiscsi_hba *phba)
  3077. {
  3078. unsigned int index;
  3079. struct hwi_controller *phwi_ctrlr;
  3080. struct hwi_wrb_context *pwrb_context;
  3081. phwi_ctrlr = phba->phwi_ctrlr;
  3082. for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
  3083. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3084. kfree(pwrb_context->pwrb_handle_base);
  3085. kfree(pwrb_context->pwrb_handle_basestd);
  3086. }
  3087. }
  3088. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3089. {
  3090. struct be_queue_info *q;
  3091. struct be_ctrl_info *ctrl = &phba->ctrl;
  3092. q = &phba->ctrl.mcc_obj.q;
  3093. if (q->created)
  3094. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3095. be_queue_free(phba, q);
  3096. q = &phba->ctrl.mcc_obj.cq;
  3097. if (q->created)
  3098. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3099. be_queue_free(phba, q);
  3100. }
  3101. static void hwi_cleanup(struct beiscsi_hba *phba)
  3102. {
  3103. struct be_queue_info *q;
  3104. struct be_ctrl_info *ctrl = &phba->ctrl;
  3105. struct hwi_controller *phwi_ctrlr;
  3106. struct hwi_context_memory *phwi_context;
  3107. struct hwi_async_pdu_context *pasync_ctx;
  3108. int i, eq_num;
  3109. phwi_ctrlr = phba->phwi_ctrlr;
  3110. phwi_context = phwi_ctrlr->phwi_ctxt;
  3111. be_cmd_iscsi_remove_template_hdr(ctrl);
  3112. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3113. q = &phwi_context->be_wrbq[i];
  3114. if (q->created)
  3115. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3116. }
  3117. kfree(phwi_context->be_wrbq);
  3118. free_wrb_handles(phba);
  3119. q = &phwi_context->be_def_hdrq;
  3120. if (q->created)
  3121. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3122. q = &phwi_context->be_def_dataq;
  3123. if (q->created)
  3124. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3125. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3126. for (i = 0; i < (phba->num_cpus); i++) {
  3127. q = &phwi_context->be_cq[i];
  3128. if (q->created)
  3129. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3130. }
  3131. if (phba->msix_enabled)
  3132. eq_num = 1;
  3133. else
  3134. eq_num = 0;
  3135. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3136. q = &phwi_context->be_eq[i].q;
  3137. if (q->created)
  3138. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3139. }
  3140. be_mcc_queues_destroy(phba);
  3141. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  3142. kfree(pasync_ctx->async_entry);
  3143. be_cmd_fw_uninit(ctrl);
  3144. }
  3145. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3146. struct hwi_context_memory *phwi_context)
  3147. {
  3148. struct be_queue_info *q, *cq;
  3149. struct be_ctrl_info *ctrl = &phba->ctrl;
  3150. /* Alloc MCC compl queue */
  3151. cq = &phba->ctrl.mcc_obj.cq;
  3152. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3153. sizeof(struct be_mcc_compl)))
  3154. goto err;
  3155. /* Ask BE to create MCC compl queue; */
  3156. if (phba->msix_enabled) {
  3157. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3158. [phba->num_cpus].q, false, true, 0))
  3159. goto mcc_cq_free;
  3160. } else {
  3161. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3162. false, true, 0))
  3163. goto mcc_cq_free;
  3164. }
  3165. /* Alloc MCC queue */
  3166. q = &phba->ctrl.mcc_obj.q;
  3167. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3168. goto mcc_cq_destroy;
  3169. /* Ask BE to create MCC queue */
  3170. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3171. goto mcc_q_free;
  3172. return 0;
  3173. mcc_q_free:
  3174. be_queue_free(phba, q);
  3175. mcc_cq_destroy:
  3176. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3177. mcc_cq_free:
  3178. be_queue_free(phba, cq);
  3179. err:
  3180. return -ENOMEM;
  3181. }
  3182. /**
  3183. * find_num_cpus()- Get the CPU online count
  3184. * @phba: ptr to priv structure
  3185. *
  3186. * CPU count is used for creating EQ.
  3187. **/
  3188. static void find_num_cpus(struct beiscsi_hba *phba)
  3189. {
  3190. int num_cpus = 0;
  3191. num_cpus = num_online_cpus();
  3192. switch (phba->generation) {
  3193. case BE_GEN2:
  3194. case BE_GEN3:
  3195. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3196. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3197. break;
  3198. case BE_GEN4:
  3199. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3200. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3201. break;
  3202. default:
  3203. phba->num_cpus = 1;
  3204. }
  3205. }
  3206. static int hwi_init_port(struct beiscsi_hba *phba)
  3207. {
  3208. struct hwi_controller *phwi_ctrlr;
  3209. struct hwi_context_memory *phwi_context;
  3210. unsigned int def_pdu_ring_sz;
  3211. struct be_ctrl_info *ctrl = &phba->ctrl;
  3212. int status;
  3213. def_pdu_ring_sz =
  3214. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  3215. phwi_ctrlr = phba->phwi_ctrlr;
  3216. phwi_context = phwi_ctrlr->phwi_ctxt;
  3217. phwi_context->max_eqd = 0;
  3218. phwi_context->min_eqd = 0;
  3219. phwi_context->cur_eqd = 64;
  3220. be_cmd_fw_initialize(&phba->ctrl);
  3221. status = beiscsi_create_eqs(phba, phwi_context);
  3222. if (status != 0) {
  3223. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3224. "BM_%d : EQ not created\n");
  3225. goto error;
  3226. }
  3227. status = be_mcc_queues_create(phba, phwi_context);
  3228. if (status != 0)
  3229. goto error;
  3230. status = mgmt_check_supported_fw(ctrl, phba);
  3231. if (status != 0) {
  3232. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3233. "BM_%d : Unsupported fw version\n");
  3234. goto error;
  3235. }
  3236. status = beiscsi_create_cqs(phba, phwi_context);
  3237. if (status != 0) {
  3238. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3239. "BM_%d : CQ not created\n");
  3240. goto error;
  3241. }
  3242. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3243. def_pdu_ring_sz);
  3244. if (status != 0) {
  3245. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3246. "BM_%d : Default Header not created\n");
  3247. goto error;
  3248. }
  3249. status = beiscsi_create_def_data(phba, phwi_context,
  3250. phwi_ctrlr, def_pdu_ring_sz);
  3251. if (status != 0) {
  3252. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3253. "BM_%d : Default Data not created\n");
  3254. goto error;
  3255. }
  3256. status = beiscsi_post_pages(phba);
  3257. if (status != 0) {
  3258. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3259. "BM_%d : Post SGL Pages Failed\n");
  3260. goto error;
  3261. }
  3262. status = beiscsi_post_template_hdr(phba);
  3263. if (status != 0) {
  3264. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3265. "BM_%d : Template HDR Posting for CXN Failed\n");
  3266. }
  3267. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3268. if (status != 0) {
  3269. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3270. "BM_%d : WRB Rings not created\n");
  3271. goto error;
  3272. }
  3273. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3274. "BM_%d : hwi_init_port success\n");
  3275. return 0;
  3276. error:
  3277. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3278. "BM_%d : hwi_init_port failed");
  3279. hwi_cleanup(phba);
  3280. return status;
  3281. }
  3282. static int hwi_init_controller(struct beiscsi_hba *phba)
  3283. {
  3284. struct hwi_controller *phwi_ctrlr;
  3285. phwi_ctrlr = phba->phwi_ctrlr;
  3286. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3287. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3288. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3289. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3290. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3291. phwi_ctrlr->phwi_ctxt);
  3292. } else {
  3293. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3294. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3295. "than one element.Failing to load\n");
  3296. return -ENOMEM;
  3297. }
  3298. iscsi_init_global_templates(phba);
  3299. if (beiscsi_init_wrb_handle(phba))
  3300. return -ENOMEM;
  3301. if (hwi_init_async_pdu_ctx(phba)) {
  3302. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3303. "BM_%d : hwi_init_async_pdu_ctx failed\n");
  3304. return -ENOMEM;
  3305. }
  3306. if (hwi_init_port(phba) != 0) {
  3307. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3308. "BM_%d : hwi_init_controller failed\n");
  3309. return -ENOMEM;
  3310. }
  3311. return 0;
  3312. }
  3313. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3314. {
  3315. struct be_mem_descriptor *mem_descr;
  3316. int i, j;
  3317. mem_descr = phba->init_mem;
  3318. i = 0;
  3319. j = 0;
  3320. for (i = 0; i < SE_MEM_MAX; i++) {
  3321. for (j = mem_descr->num_elements; j > 0; j--) {
  3322. pci_free_consistent(phba->pcidev,
  3323. mem_descr->mem_array[j - 1].size,
  3324. mem_descr->mem_array[j - 1].virtual_address,
  3325. (unsigned long)mem_descr->mem_array[j - 1].
  3326. bus_address.u.a64.address);
  3327. }
  3328. kfree(mem_descr->mem_array);
  3329. mem_descr++;
  3330. }
  3331. kfree(phba->init_mem);
  3332. kfree(phba->phwi_ctrlr->wrb_context);
  3333. kfree(phba->phwi_ctrlr);
  3334. }
  3335. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3336. {
  3337. int ret = -ENOMEM;
  3338. ret = beiscsi_get_memory(phba);
  3339. if (ret < 0) {
  3340. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3341. "BM_%d : beiscsi_dev_probe -"
  3342. "Failed in beiscsi_alloc_memory\n");
  3343. return ret;
  3344. }
  3345. ret = hwi_init_controller(phba);
  3346. if (ret)
  3347. goto free_init;
  3348. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3349. "BM_%d : Return success from beiscsi_init_controller");
  3350. return 0;
  3351. free_init:
  3352. beiscsi_free_mem(phba);
  3353. return ret;
  3354. }
  3355. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3356. {
  3357. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3358. struct sgl_handle *psgl_handle;
  3359. struct iscsi_sge *pfrag;
  3360. unsigned int arr_index, i, idx, ulp_num = 0;
  3361. phba->io_sgl_hndl_avbl = 0;
  3362. phba->eh_sgl_hndl_avbl = 0;
  3363. mem_descr_sglh = phba->init_mem;
  3364. mem_descr_sglh += HWI_MEM_SGLH;
  3365. if (1 == mem_descr_sglh->num_elements) {
  3366. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3367. phba->params.ios_per_ctrl,
  3368. GFP_KERNEL);
  3369. if (!phba->io_sgl_hndl_base) {
  3370. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3371. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3372. return -ENOMEM;
  3373. }
  3374. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3375. (phba->params.icds_per_ctrl -
  3376. phba->params.ios_per_ctrl),
  3377. GFP_KERNEL);
  3378. if (!phba->eh_sgl_hndl_base) {
  3379. kfree(phba->io_sgl_hndl_base);
  3380. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3381. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3382. return -ENOMEM;
  3383. }
  3384. } else {
  3385. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3386. "BM_%d : HWI_MEM_SGLH is more than one element."
  3387. "Failing to load\n");
  3388. return -ENOMEM;
  3389. }
  3390. arr_index = 0;
  3391. idx = 0;
  3392. while (idx < mem_descr_sglh->num_elements) {
  3393. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3394. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3395. sizeof(struct sgl_handle)); i++) {
  3396. if (arr_index < phba->params.ios_per_ctrl) {
  3397. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3398. phba->io_sgl_hndl_avbl++;
  3399. arr_index++;
  3400. } else {
  3401. phba->eh_sgl_hndl_base[arr_index -
  3402. phba->params.ios_per_ctrl] =
  3403. psgl_handle;
  3404. arr_index++;
  3405. phba->eh_sgl_hndl_avbl++;
  3406. }
  3407. psgl_handle++;
  3408. }
  3409. idx++;
  3410. }
  3411. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3412. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3413. "phba->eh_sgl_hndl_avbl=%d\n",
  3414. phba->io_sgl_hndl_avbl,
  3415. phba->eh_sgl_hndl_avbl);
  3416. mem_descr_sg = phba->init_mem;
  3417. mem_descr_sg += HWI_MEM_SGE;
  3418. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3419. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3420. mem_descr_sg->num_elements);
  3421. arr_index = 0;
  3422. idx = 0;
  3423. while (idx < mem_descr_sg->num_elements) {
  3424. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3425. for (i = 0;
  3426. i < (mem_descr_sg->mem_array[idx].size) /
  3427. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3428. i++) {
  3429. if (arr_index < phba->params.ios_per_ctrl)
  3430. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3431. else
  3432. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3433. phba->params.ios_per_ctrl];
  3434. psgl_handle->pfrag = pfrag;
  3435. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3436. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3437. pfrag += phba->params.num_sge_per_io;
  3438. psgl_handle->sgl_index =
  3439. phba->fw_config.iscsi_icd_start[ulp_num] +
  3440. arr_index++;
  3441. }
  3442. idx++;
  3443. }
  3444. phba->io_sgl_free_index = 0;
  3445. phba->io_sgl_alloc_index = 0;
  3446. phba->eh_sgl_free_index = 0;
  3447. phba->eh_sgl_alloc_index = 0;
  3448. return 0;
  3449. }
  3450. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3451. {
  3452. int i;
  3453. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3454. GFP_KERNEL);
  3455. if (!phba->cid_array) {
  3456. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3457. "BM_%d : Failed to allocate memory in "
  3458. "hba_setup_cid_tbls\n");
  3459. return -ENOMEM;
  3460. }
  3461. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3462. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3463. if (!phba->ep_array) {
  3464. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3465. "BM_%d : Failed to allocate memory in "
  3466. "hba_setup_cid_tbls\n");
  3467. kfree(phba->cid_array);
  3468. phba->cid_array = NULL;
  3469. return -ENOMEM;
  3470. }
  3471. phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
  3472. phba->params.cxns_per_ctrl, GFP_KERNEL);
  3473. if (!phba->conn_table) {
  3474. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3475. "BM_%d : Failed to allocate memory in"
  3476. "hba_setup_cid_tbls\n");
  3477. kfree(phba->cid_array);
  3478. kfree(phba->ep_array);
  3479. phba->cid_array = NULL;
  3480. phba->ep_array = NULL;
  3481. return -ENOMEM;
  3482. }
  3483. for (i = 0; i < phba->params.cxns_per_ctrl; i++)
  3484. phba->cid_array[i] = phba->phwi_ctrlr->wrb_context[i].cid;
  3485. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3486. return 0;
  3487. }
  3488. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3489. {
  3490. struct be_ctrl_info *ctrl = &phba->ctrl;
  3491. struct hwi_controller *phwi_ctrlr;
  3492. struct hwi_context_memory *phwi_context;
  3493. struct be_queue_info *eq;
  3494. u8 __iomem *addr;
  3495. u32 reg, i;
  3496. u32 enabled;
  3497. phwi_ctrlr = phba->phwi_ctrlr;
  3498. phwi_context = phwi_ctrlr->phwi_ctxt;
  3499. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3500. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3501. reg = ioread32(addr);
  3502. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3503. if (!enabled) {
  3504. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3505. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3506. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3507. iowrite32(reg, addr);
  3508. }
  3509. if (!phba->msix_enabled) {
  3510. eq = &phwi_context->be_eq[0].q;
  3511. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3512. "BM_%d : eq->id=%d\n", eq->id);
  3513. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3514. } else {
  3515. for (i = 0; i <= phba->num_cpus; i++) {
  3516. eq = &phwi_context->be_eq[i].q;
  3517. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3518. "BM_%d : eq->id=%d\n", eq->id);
  3519. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3520. }
  3521. }
  3522. }
  3523. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3524. {
  3525. struct be_ctrl_info *ctrl = &phba->ctrl;
  3526. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3527. u32 reg = ioread32(addr);
  3528. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3529. if (enabled) {
  3530. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3531. iowrite32(reg, addr);
  3532. } else
  3533. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3534. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3535. }
  3536. /**
  3537. * beiscsi_get_boot_info()- Get the boot session info
  3538. * @phba: The device priv structure instance
  3539. *
  3540. * Get the boot target info and store in driver priv structure
  3541. *
  3542. * return values
  3543. * Success: 0
  3544. * Failure: Non-Zero Value
  3545. **/
  3546. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3547. {
  3548. struct be_cmd_get_session_resp *session_resp;
  3549. struct be_dma_mem nonemb_cmd;
  3550. unsigned int tag;
  3551. unsigned int s_handle;
  3552. int ret = -ENOMEM;
  3553. /* Get the session handle of the boot target */
  3554. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3555. if (ret) {
  3556. beiscsi_log(phba, KERN_ERR,
  3557. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3558. "BM_%d : No boot session\n");
  3559. return ret;
  3560. }
  3561. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3562. sizeof(*session_resp),
  3563. &nonemb_cmd.dma);
  3564. if (nonemb_cmd.va == NULL) {
  3565. beiscsi_log(phba, KERN_ERR,
  3566. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3567. "BM_%d : Failed to allocate memory for"
  3568. "beiscsi_get_session_info\n");
  3569. return -ENOMEM;
  3570. }
  3571. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3572. tag = mgmt_get_session_info(phba, s_handle,
  3573. &nonemb_cmd);
  3574. if (!tag) {
  3575. beiscsi_log(phba, KERN_ERR,
  3576. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3577. "BM_%d : beiscsi_get_session_info"
  3578. " Failed\n");
  3579. goto boot_freemem;
  3580. }
  3581. ret = beiscsi_mccq_compl(phba, tag, NULL, nonemb_cmd.va);
  3582. if (ret) {
  3583. beiscsi_log(phba, KERN_ERR,
  3584. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3585. "BM_%d : beiscsi_get_session_info Failed");
  3586. goto boot_freemem;
  3587. }
  3588. session_resp = nonemb_cmd.va ;
  3589. memcpy(&phba->boot_sess, &session_resp->session_info,
  3590. sizeof(struct mgmt_session_info));
  3591. ret = 0;
  3592. boot_freemem:
  3593. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3594. nonemb_cmd.va, nonemb_cmd.dma);
  3595. return ret;
  3596. }
  3597. static void beiscsi_boot_release(void *data)
  3598. {
  3599. struct beiscsi_hba *phba = data;
  3600. scsi_host_put(phba->shost);
  3601. }
  3602. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3603. {
  3604. struct iscsi_boot_kobj *boot_kobj;
  3605. /* get boot info using mgmt cmd */
  3606. if (beiscsi_get_boot_info(phba))
  3607. /* Try to see if we can carry on without this */
  3608. return 0;
  3609. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3610. if (!phba->boot_kset)
  3611. return -ENOMEM;
  3612. /* get a ref because the show function will ref the phba */
  3613. if (!scsi_host_get(phba->shost))
  3614. goto free_kset;
  3615. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3616. beiscsi_show_boot_tgt_info,
  3617. beiscsi_tgt_get_attr_visibility,
  3618. beiscsi_boot_release);
  3619. if (!boot_kobj)
  3620. goto put_shost;
  3621. if (!scsi_host_get(phba->shost))
  3622. goto free_kset;
  3623. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3624. beiscsi_show_boot_ini_info,
  3625. beiscsi_ini_get_attr_visibility,
  3626. beiscsi_boot_release);
  3627. if (!boot_kobj)
  3628. goto put_shost;
  3629. if (!scsi_host_get(phba->shost))
  3630. goto free_kset;
  3631. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3632. beiscsi_show_boot_eth_info,
  3633. beiscsi_eth_get_attr_visibility,
  3634. beiscsi_boot_release);
  3635. if (!boot_kobj)
  3636. goto put_shost;
  3637. return 0;
  3638. put_shost:
  3639. scsi_host_put(phba->shost);
  3640. free_kset:
  3641. iscsi_boot_destroy_kset(phba->boot_kset);
  3642. return -ENOMEM;
  3643. }
  3644. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3645. {
  3646. int ret;
  3647. ret = beiscsi_init_controller(phba);
  3648. if (ret < 0) {
  3649. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3650. "BM_%d : beiscsi_dev_probe - Failed in"
  3651. "beiscsi_init_controller\n");
  3652. return ret;
  3653. }
  3654. ret = beiscsi_init_sgl_handle(phba);
  3655. if (ret < 0) {
  3656. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3657. "BM_%d : beiscsi_dev_probe - Failed in"
  3658. "beiscsi_init_sgl_handle\n");
  3659. goto do_cleanup_ctrlr;
  3660. }
  3661. if (hba_setup_cid_tbls(phba)) {
  3662. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3663. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3664. kfree(phba->io_sgl_hndl_base);
  3665. kfree(phba->eh_sgl_hndl_base);
  3666. goto do_cleanup_ctrlr;
  3667. }
  3668. return ret;
  3669. do_cleanup_ctrlr:
  3670. hwi_cleanup(phba);
  3671. return ret;
  3672. }
  3673. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3674. {
  3675. struct hwi_controller *phwi_ctrlr;
  3676. struct hwi_context_memory *phwi_context;
  3677. struct be_queue_info *eq;
  3678. struct be_eq_entry *eqe = NULL;
  3679. int i, eq_msix;
  3680. unsigned int num_processed;
  3681. phwi_ctrlr = phba->phwi_ctrlr;
  3682. phwi_context = phwi_ctrlr->phwi_ctxt;
  3683. if (phba->msix_enabled)
  3684. eq_msix = 1;
  3685. else
  3686. eq_msix = 0;
  3687. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3688. eq = &phwi_context->be_eq[i].q;
  3689. eqe = queue_tail_node(eq);
  3690. num_processed = 0;
  3691. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3692. & EQE_VALID_MASK) {
  3693. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3694. queue_tail_inc(eq);
  3695. eqe = queue_tail_node(eq);
  3696. num_processed++;
  3697. }
  3698. if (num_processed)
  3699. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3700. }
  3701. }
  3702. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3703. {
  3704. int mgmt_status;
  3705. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3706. if (mgmt_status)
  3707. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3708. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3709. hwi_purge_eq(phba);
  3710. hwi_cleanup(phba);
  3711. kfree(phba->io_sgl_hndl_base);
  3712. kfree(phba->eh_sgl_hndl_base);
  3713. kfree(phba->cid_array);
  3714. kfree(phba->ep_array);
  3715. kfree(phba->conn_table);
  3716. }
  3717. /**
  3718. * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
  3719. * @beiscsi_conn: ptr to the conn to be cleaned up
  3720. * @task: ptr to iscsi_task resource to be freed.
  3721. *
  3722. * Free driver mgmt resources binded to CXN.
  3723. **/
  3724. void
  3725. beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
  3726. struct iscsi_task *task)
  3727. {
  3728. struct beiscsi_io_task *io_task;
  3729. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3730. struct hwi_wrb_context *pwrb_context;
  3731. struct hwi_controller *phwi_ctrlr;
  3732. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3733. beiscsi_conn->beiscsi_conn_cid);
  3734. phwi_ctrlr = phba->phwi_ctrlr;
  3735. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3736. io_task = task->dd_data;
  3737. if (io_task->pwrb_handle) {
  3738. memset(io_task->pwrb_handle->pwrb, 0,
  3739. sizeof(struct iscsi_wrb));
  3740. free_wrb_handle(phba, pwrb_context,
  3741. io_task->pwrb_handle);
  3742. io_task->pwrb_handle = NULL;
  3743. }
  3744. if (io_task->psgl_handle) {
  3745. spin_lock_bh(&phba->mgmt_sgl_lock);
  3746. free_mgmt_sgl_handle(phba,
  3747. io_task->psgl_handle);
  3748. io_task->psgl_handle = NULL;
  3749. spin_unlock_bh(&phba->mgmt_sgl_lock);
  3750. }
  3751. if (io_task->mtask_addr)
  3752. pci_unmap_single(phba->pcidev,
  3753. io_task->mtask_addr,
  3754. io_task->mtask_data_count,
  3755. PCI_DMA_TODEVICE);
  3756. }
  3757. /**
  3758. * beiscsi_cleanup_task()- Free driver resources of the task
  3759. * @task: ptr to the iscsi task
  3760. *
  3761. **/
  3762. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3763. {
  3764. struct beiscsi_io_task *io_task = task->dd_data;
  3765. struct iscsi_conn *conn = task->conn;
  3766. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3767. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3768. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3769. struct hwi_wrb_context *pwrb_context;
  3770. struct hwi_controller *phwi_ctrlr;
  3771. uint16_t cri_index = BE_GET_CRI_FROM_CID(
  3772. beiscsi_conn->beiscsi_conn_cid);
  3773. phwi_ctrlr = phba->phwi_ctrlr;
  3774. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3775. if (io_task->cmd_bhs) {
  3776. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3777. io_task->bhs_pa.u.a64.address);
  3778. io_task->cmd_bhs = NULL;
  3779. }
  3780. if (task->sc) {
  3781. if (io_task->pwrb_handle) {
  3782. free_wrb_handle(phba, pwrb_context,
  3783. io_task->pwrb_handle);
  3784. io_task->pwrb_handle = NULL;
  3785. }
  3786. if (io_task->psgl_handle) {
  3787. spin_lock(&phba->io_sgl_lock);
  3788. free_io_sgl_handle(phba, io_task->psgl_handle);
  3789. spin_unlock(&phba->io_sgl_lock);
  3790. io_task->psgl_handle = NULL;
  3791. }
  3792. } else {
  3793. if (!beiscsi_conn->login_in_progress)
  3794. beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
  3795. }
  3796. }
  3797. void
  3798. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3799. struct beiscsi_offload_params *params)
  3800. {
  3801. struct wrb_handle *pwrb_handle;
  3802. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3803. struct iscsi_task *task = beiscsi_conn->task;
  3804. struct iscsi_session *session = task->conn->session;
  3805. u32 doorbell = 0;
  3806. /*
  3807. * We can always use 0 here because it is reserved by libiscsi for
  3808. * login/startup related tasks.
  3809. */
  3810. beiscsi_conn->login_in_progress = 0;
  3811. spin_lock_bh(&session->lock);
  3812. beiscsi_cleanup_task(task);
  3813. spin_unlock_bh(&session->lock);
  3814. pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid);
  3815. /* Check for the adapter family */
  3816. if (is_chip_be2_be3r(phba))
  3817. beiscsi_offload_cxn_v0(params, pwrb_handle,
  3818. phba->init_mem);
  3819. else
  3820. beiscsi_offload_cxn_v2(params, pwrb_handle);
  3821. be_dws_le_to_cpu(pwrb_handle->pwrb,
  3822. sizeof(struct iscsi_target_context_update_wrb));
  3823. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3824. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3825. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3826. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3827. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3828. }
  3829. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3830. int *index, int *age)
  3831. {
  3832. *index = (int)itt;
  3833. if (age)
  3834. *age = conn->session->age;
  3835. }
  3836. /**
  3837. * beiscsi_alloc_pdu - allocates pdu and related resources
  3838. * @task: libiscsi task
  3839. * @opcode: opcode of pdu for task
  3840. *
  3841. * This is called with the session lock held. It will allocate
  3842. * the wrb and sgl if needed for the command. And it will prep
  3843. * the pdu's itt. beiscsi_parse_pdu will later translate
  3844. * the pdu itt to the libiscsi task itt.
  3845. */
  3846. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3847. {
  3848. struct beiscsi_io_task *io_task = task->dd_data;
  3849. struct iscsi_conn *conn = task->conn;
  3850. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3851. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3852. struct hwi_wrb_context *pwrb_context;
  3853. struct hwi_controller *phwi_ctrlr;
  3854. itt_t itt;
  3855. uint16_t cri_index = 0;
  3856. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3857. dma_addr_t paddr;
  3858. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3859. GFP_ATOMIC, &paddr);
  3860. if (!io_task->cmd_bhs)
  3861. return -ENOMEM;
  3862. io_task->bhs_pa.u.a64.address = paddr;
  3863. io_task->libiscsi_itt = (itt_t)task->itt;
  3864. io_task->conn = beiscsi_conn;
  3865. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3866. task->hdr_max = sizeof(struct be_cmd_bhs);
  3867. io_task->psgl_handle = NULL;
  3868. io_task->pwrb_handle = NULL;
  3869. if (task->sc) {
  3870. spin_lock(&phba->io_sgl_lock);
  3871. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3872. spin_unlock(&phba->io_sgl_lock);
  3873. if (!io_task->psgl_handle) {
  3874. beiscsi_log(phba, KERN_ERR,
  3875. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3876. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3877. "for the CID : %d\n",
  3878. beiscsi_conn->beiscsi_conn_cid);
  3879. goto free_hndls;
  3880. }
  3881. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3882. beiscsi_conn->beiscsi_conn_cid);
  3883. if (!io_task->pwrb_handle) {
  3884. beiscsi_log(phba, KERN_ERR,
  3885. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3886. "BM_%d : Alloc of WRB_HANDLE Failed"
  3887. "for the CID : %d\n",
  3888. beiscsi_conn->beiscsi_conn_cid);
  3889. goto free_io_hndls;
  3890. }
  3891. } else {
  3892. io_task->scsi_cmnd = NULL;
  3893. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3894. beiscsi_conn->task = task;
  3895. if (!beiscsi_conn->login_in_progress) {
  3896. spin_lock(&phba->mgmt_sgl_lock);
  3897. io_task->psgl_handle = (struct sgl_handle *)
  3898. alloc_mgmt_sgl_handle(phba);
  3899. spin_unlock(&phba->mgmt_sgl_lock);
  3900. if (!io_task->psgl_handle) {
  3901. beiscsi_log(phba, KERN_ERR,
  3902. BEISCSI_LOG_IO |
  3903. BEISCSI_LOG_CONFIG,
  3904. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3905. "for the CID : %d\n",
  3906. beiscsi_conn->
  3907. beiscsi_conn_cid);
  3908. goto free_hndls;
  3909. }
  3910. beiscsi_conn->login_in_progress = 1;
  3911. beiscsi_conn->plogin_sgl_handle =
  3912. io_task->psgl_handle;
  3913. io_task->pwrb_handle =
  3914. alloc_wrb_handle(phba,
  3915. beiscsi_conn->beiscsi_conn_cid);
  3916. if (!io_task->pwrb_handle) {
  3917. beiscsi_log(phba, KERN_ERR,
  3918. BEISCSI_LOG_IO |
  3919. BEISCSI_LOG_CONFIG,
  3920. "BM_%d : Alloc of WRB_HANDLE Failed"
  3921. "for the CID : %d\n",
  3922. beiscsi_conn->
  3923. beiscsi_conn_cid);
  3924. goto free_mgmt_hndls;
  3925. }
  3926. beiscsi_conn->plogin_wrb_handle =
  3927. io_task->pwrb_handle;
  3928. } else {
  3929. io_task->psgl_handle =
  3930. beiscsi_conn->plogin_sgl_handle;
  3931. io_task->pwrb_handle =
  3932. beiscsi_conn->plogin_wrb_handle;
  3933. }
  3934. } else {
  3935. spin_lock(&phba->mgmt_sgl_lock);
  3936. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3937. spin_unlock(&phba->mgmt_sgl_lock);
  3938. if (!io_task->psgl_handle) {
  3939. beiscsi_log(phba, KERN_ERR,
  3940. BEISCSI_LOG_IO |
  3941. BEISCSI_LOG_CONFIG,
  3942. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3943. "for the CID : %d\n",
  3944. beiscsi_conn->
  3945. beiscsi_conn_cid);
  3946. goto free_hndls;
  3947. }
  3948. io_task->pwrb_handle =
  3949. alloc_wrb_handle(phba,
  3950. beiscsi_conn->beiscsi_conn_cid);
  3951. if (!io_task->pwrb_handle) {
  3952. beiscsi_log(phba, KERN_ERR,
  3953. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3954. "BM_%d : Alloc of WRB_HANDLE Failed"
  3955. "for the CID : %d\n",
  3956. beiscsi_conn->beiscsi_conn_cid);
  3957. goto free_mgmt_hndls;
  3958. }
  3959. }
  3960. }
  3961. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3962. wrb_index << 16) | (unsigned int)
  3963. (io_task->psgl_handle->sgl_index));
  3964. io_task->pwrb_handle->pio_handle = task;
  3965. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3966. return 0;
  3967. free_io_hndls:
  3968. spin_lock(&phba->io_sgl_lock);
  3969. free_io_sgl_handle(phba, io_task->psgl_handle);
  3970. spin_unlock(&phba->io_sgl_lock);
  3971. goto free_hndls;
  3972. free_mgmt_hndls:
  3973. spin_lock(&phba->mgmt_sgl_lock);
  3974. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3975. io_task->psgl_handle = NULL;
  3976. spin_unlock(&phba->mgmt_sgl_lock);
  3977. free_hndls:
  3978. phwi_ctrlr = phba->phwi_ctrlr;
  3979. cri_index = BE_GET_CRI_FROM_CID(
  3980. beiscsi_conn->beiscsi_conn_cid);
  3981. pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
  3982. if (io_task->pwrb_handle)
  3983. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3984. io_task->pwrb_handle = NULL;
  3985. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3986. io_task->bhs_pa.u.a64.address);
  3987. io_task->cmd_bhs = NULL;
  3988. return -ENOMEM;
  3989. }
  3990. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  3991. unsigned int num_sg, unsigned int xferlen,
  3992. unsigned int writedir)
  3993. {
  3994. struct beiscsi_io_task *io_task = task->dd_data;
  3995. struct iscsi_conn *conn = task->conn;
  3996. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3997. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3998. struct iscsi_wrb *pwrb = NULL;
  3999. unsigned int doorbell = 0;
  4000. pwrb = io_task->pwrb_handle->pwrb;
  4001. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4002. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4003. if (writedir) {
  4004. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  4005. INI_WR_CMD);
  4006. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  4007. } else {
  4008. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  4009. INI_RD_CMD);
  4010. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  4011. }
  4012. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  4013. type, pwrb);
  4014. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  4015. cpu_to_be16(*(unsigned short *)
  4016. &io_task->cmd_bhs->iscsi_hdr.lun));
  4017. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  4018. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4019. io_task->pwrb_handle->wrb_index);
  4020. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4021. be32_to_cpu(task->cmdsn));
  4022. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4023. io_task->psgl_handle->sgl_index);
  4024. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  4025. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4026. io_task->pwrb_handle->nxt_wrb_index);
  4027. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4028. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4029. doorbell |= (io_task->pwrb_handle->wrb_index &
  4030. DB_DEF_PDU_WRB_INDEX_MASK) <<
  4031. DB_DEF_PDU_WRB_INDEX_SHIFT;
  4032. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4033. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4034. return 0;
  4035. }
  4036. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  4037. unsigned int num_sg, unsigned int xferlen,
  4038. unsigned int writedir)
  4039. {
  4040. struct beiscsi_io_task *io_task = task->dd_data;
  4041. struct iscsi_conn *conn = task->conn;
  4042. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4043. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4044. struct iscsi_wrb *pwrb = NULL;
  4045. unsigned int doorbell = 0;
  4046. pwrb = io_task->pwrb_handle->pwrb;
  4047. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  4048. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  4049. if (writedir) {
  4050. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4051. INI_WR_CMD);
  4052. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  4053. } else {
  4054. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  4055. INI_RD_CMD);
  4056. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  4057. }
  4058. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  4059. type, pwrb);
  4060. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  4061. cpu_to_be16(*(unsigned short *)
  4062. &io_task->cmd_bhs->iscsi_hdr.lun));
  4063. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  4064. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4065. io_task->pwrb_handle->wrb_index);
  4066. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4067. be32_to_cpu(task->cmdsn));
  4068. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4069. io_task->psgl_handle->sgl_index);
  4070. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  4071. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4072. io_task->pwrb_handle->nxt_wrb_index);
  4073. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  4074. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  4075. doorbell |= (io_task->pwrb_handle->wrb_index &
  4076. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4077. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4078. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4079. return 0;
  4080. }
  4081. static int beiscsi_mtask(struct iscsi_task *task)
  4082. {
  4083. struct beiscsi_io_task *io_task = task->dd_data;
  4084. struct iscsi_conn *conn = task->conn;
  4085. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  4086. struct beiscsi_hba *phba = beiscsi_conn->phba;
  4087. struct iscsi_wrb *pwrb = NULL;
  4088. unsigned int doorbell = 0;
  4089. unsigned int cid;
  4090. unsigned int pwrb_typeoffset = 0;
  4091. cid = beiscsi_conn->beiscsi_conn_cid;
  4092. pwrb = io_task->pwrb_handle->pwrb;
  4093. memset(pwrb, 0, sizeof(*pwrb));
  4094. if (is_chip_be2_be3r(phba)) {
  4095. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4096. be32_to_cpu(task->cmdsn));
  4097. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4098. io_task->pwrb_handle->wrb_index);
  4099. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4100. io_task->psgl_handle->sgl_index);
  4101. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  4102. task->data_count);
  4103. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4104. io_task->pwrb_handle->nxt_wrb_index);
  4105. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  4106. } else {
  4107. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  4108. be32_to_cpu(task->cmdsn));
  4109. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  4110. io_task->pwrb_handle->wrb_index);
  4111. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  4112. io_task->psgl_handle->sgl_index);
  4113. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  4114. task->data_count);
  4115. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  4116. io_task->pwrb_handle->nxt_wrb_index);
  4117. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  4118. }
  4119. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  4120. case ISCSI_OP_LOGIN:
  4121. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4122. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4123. hwi_write_buffer(pwrb, task);
  4124. break;
  4125. case ISCSI_OP_NOOP_OUT:
  4126. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4127. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4128. if (is_chip_be2_be3r(phba))
  4129. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4130. dmsg, pwrb, 1);
  4131. else
  4132. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4133. dmsg, pwrb, 1);
  4134. } else {
  4135. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4136. if (is_chip_be2_be3r(phba))
  4137. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4138. dmsg, pwrb, 0);
  4139. else
  4140. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4141. dmsg, pwrb, 0);
  4142. }
  4143. hwi_write_buffer(pwrb, task);
  4144. break;
  4145. case ISCSI_OP_TEXT:
  4146. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4147. hwi_write_buffer(pwrb, task);
  4148. break;
  4149. case ISCSI_OP_SCSI_TMFUNC:
  4150. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4151. hwi_write_buffer(pwrb, task);
  4152. break;
  4153. case ISCSI_OP_LOGOUT:
  4154. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4155. hwi_write_buffer(pwrb, task);
  4156. break;
  4157. default:
  4158. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4159. "BM_%d : opcode =%d Not supported\n",
  4160. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4161. return -EINVAL;
  4162. }
  4163. /* Set the task type */
  4164. io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
  4165. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
  4166. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
  4167. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4168. doorbell |= (io_task->pwrb_handle->wrb_index &
  4169. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4170. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4171. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4172. return 0;
  4173. }
  4174. static int beiscsi_task_xmit(struct iscsi_task *task)
  4175. {
  4176. struct beiscsi_io_task *io_task = task->dd_data;
  4177. struct scsi_cmnd *sc = task->sc;
  4178. struct beiscsi_hba *phba = NULL;
  4179. struct scatterlist *sg;
  4180. int num_sg;
  4181. unsigned int writedir = 0, xferlen = 0;
  4182. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4183. if (!sc)
  4184. return beiscsi_mtask(task);
  4185. io_task->scsi_cmnd = sc;
  4186. num_sg = scsi_dma_map(sc);
  4187. if (num_sg < 0) {
  4188. struct iscsi_conn *conn = task->conn;
  4189. struct beiscsi_hba *phba = NULL;
  4190. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4191. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4192. "BM_%d : scsi_dma_map Failed\n");
  4193. return num_sg;
  4194. }
  4195. xferlen = scsi_bufflen(sc);
  4196. sg = scsi_sglist(sc);
  4197. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4198. writedir = 1;
  4199. else
  4200. writedir = 0;
  4201. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4202. }
  4203. /**
  4204. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4205. * @job: job to handle
  4206. */
  4207. static int beiscsi_bsg_request(struct bsg_job *job)
  4208. {
  4209. struct Scsi_Host *shost;
  4210. struct beiscsi_hba *phba;
  4211. struct iscsi_bsg_request *bsg_req = job->request;
  4212. int rc = -EINVAL;
  4213. unsigned int tag;
  4214. struct be_dma_mem nonemb_cmd;
  4215. struct be_cmd_resp_hdr *resp;
  4216. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4217. unsigned short status, extd_status;
  4218. shost = iscsi_job_to_shost(job);
  4219. phba = iscsi_host_priv(shost);
  4220. switch (bsg_req->msgcode) {
  4221. case ISCSI_BSG_HST_VENDOR:
  4222. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4223. job->request_payload.payload_len,
  4224. &nonemb_cmd.dma);
  4225. if (nonemb_cmd.va == NULL) {
  4226. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4227. "BM_%d : Failed to allocate memory for "
  4228. "beiscsi_bsg_request\n");
  4229. return -ENOMEM;
  4230. }
  4231. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4232. &nonemb_cmd);
  4233. if (!tag) {
  4234. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4235. "BM_%d : MBX Tag Allocation Failed\n");
  4236. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4237. nonemb_cmd.va, nonemb_cmd.dma);
  4238. return -EAGAIN;
  4239. }
  4240. rc = wait_event_interruptible_timeout(
  4241. phba->ctrl.mcc_wait[tag],
  4242. phba->ctrl.mcc_numtag[tag],
  4243. msecs_to_jiffies(
  4244. BEISCSI_HOST_MBX_TIMEOUT));
  4245. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4246. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4247. free_mcc_tag(&phba->ctrl, tag);
  4248. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4249. sg_copy_from_buffer(job->reply_payload.sg_list,
  4250. job->reply_payload.sg_cnt,
  4251. nonemb_cmd.va, (resp->response_length
  4252. + sizeof(*resp)));
  4253. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4254. bsg_reply->result = status;
  4255. bsg_job_done(job, bsg_reply->result,
  4256. bsg_reply->reply_payload_rcv_len);
  4257. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4258. nonemb_cmd.va, nonemb_cmd.dma);
  4259. if (status || extd_status) {
  4260. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4261. "BM_%d : MBX Cmd Failed"
  4262. " status = %d extd_status = %d\n",
  4263. status, extd_status);
  4264. return -EIO;
  4265. } else {
  4266. rc = 0;
  4267. }
  4268. break;
  4269. default:
  4270. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4271. "BM_%d : Unsupported bsg command: 0x%x\n",
  4272. bsg_req->msgcode);
  4273. break;
  4274. }
  4275. return rc;
  4276. }
  4277. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4278. {
  4279. /* Set the logging parameter */
  4280. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4281. }
  4282. /*
  4283. * beiscsi_quiesce()- Cleanup Driver resources
  4284. * @phba: Instance Priv structure
  4285. *
  4286. * Free the OS and HW resources held by the driver
  4287. **/
  4288. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4289. {
  4290. struct hwi_controller *phwi_ctrlr;
  4291. struct hwi_context_memory *phwi_context;
  4292. struct be_eq_obj *pbe_eq;
  4293. unsigned int i, msix_vec;
  4294. phwi_ctrlr = phba->phwi_ctrlr;
  4295. phwi_context = phwi_ctrlr->phwi_ctxt;
  4296. hwi_disable_intr(phba);
  4297. if (phba->msix_enabled) {
  4298. for (i = 0; i <= phba->num_cpus; i++) {
  4299. msix_vec = phba->msix_entries[i].vector;
  4300. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4301. kfree(phba->msi_name[i]);
  4302. }
  4303. } else
  4304. if (phba->pcidev->irq)
  4305. free_irq(phba->pcidev->irq, phba);
  4306. pci_disable_msix(phba->pcidev);
  4307. destroy_workqueue(phba->wq);
  4308. if (blk_iopoll_enabled)
  4309. for (i = 0; i < phba->num_cpus; i++) {
  4310. pbe_eq = &phwi_context->be_eq[i];
  4311. blk_iopoll_disable(&pbe_eq->iopoll);
  4312. }
  4313. beiscsi_clean_port(phba);
  4314. beiscsi_free_mem(phba);
  4315. beiscsi_unmap_pci_function(phba);
  4316. pci_free_consistent(phba->pcidev,
  4317. phba->ctrl.mbox_mem_alloced.size,
  4318. phba->ctrl.mbox_mem_alloced.va,
  4319. phba->ctrl.mbox_mem_alloced.dma);
  4320. cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
  4321. }
  4322. static void beiscsi_remove(struct pci_dev *pcidev)
  4323. {
  4324. struct beiscsi_hba *phba = NULL;
  4325. phba = pci_get_drvdata(pcidev);
  4326. if (!phba) {
  4327. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4328. return;
  4329. }
  4330. beiscsi_destroy_def_ifaces(phba);
  4331. beiscsi_quiesce(phba);
  4332. iscsi_boot_destroy_kset(phba->boot_kset);
  4333. iscsi_host_remove(phba->shost);
  4334. pci_dev_put(phba->pcidev);
  4335. iscsi_host_free(phba->shost);
  4336. pci_disable_device(pcidev);
  4337. }
  4338. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4339. {
  4340. struct beiscsi_hba *phba = NULL;
  4341. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4342. if (!phba) {
  4343. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4344. return;
  4345. }
  4346. beiscsi_quiesce(phba);
  4347. pci_disable_device(pcidev);
  4348. }
  4349. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4350. {
  4351. int i, status;
  4352. for (i = 0; i <= phba->num_cpus; i++)
  4353. phba->msix_entries[i].entry = i;
  4354. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4355. (phba->num_cpus + 1));
  4356. if (!status)
  4357. phba->msix_enabled = true;
  4358. return;
  4359. }
  4360. /*
  4361. * beiscsi_hw_health_check()- Check adapter health
  4362. * @work: work item to check HW health
  4363. *
  4364. * Check if adapter in an unrecoverable state or not.
  4365. **/
  4366. static void
  4367. beiscsi_hw_health_check(struct work_struct *work)
  4368. {
  4369. struct beiscsi_hba *phba =
  4370. container_of(work, struct beiscsi_hba,
  4371. beiscsi_hw_check_task.work);
  4372. beiscsi_ue_detect(phba);
  4373. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4374. msecs_to_jiffies(1000));
  4375. }
  4376. static int beiscsi_dev_probe(struct pci_dev *pcidev,
  4377. const struct pci_device_id *id)
  4378. {
  4379. struct beiscsi_hba *phba = NULL;
  4380. struct hwi_controller *phwi_ctrlr;
  4381. struct hwi_context_memory *phwi_context;
  4382. struct be_eq_obj *pbe_eq;
  4383. int ret, i;
  4384. ret = beiscsi_enable_pci(pcidev);
  4385. if (ret < 0) {
  4386. dev_err(&pcidev->dev,
  4387. "beiscsi_dev_probe - Failed to enable pci device\n");
  4388. return ret;
  4389. }
  4390. phba = beiscsi_hba_alloc(pcidev);
  4391. if (!phba) {
  4392. dev_err(&pcidev->dev,
  4393. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4394. goto disable_pci;
  4395. }
  4396. /* Initialize Driver configuration Paramters */
  4397. beiscsi_hba_attrs_init(phba);
  4398. phba->fw_timeout = false;
  4399. phba->mac_addr_set = false;
  4400. switch (pcidev->device) {
  4401. case BE_DEVICE_ID1:
  4402. case OC_DEVICE_ID1:
  4403. case OC_DEVICE_ID2:
  4404. phba->generation = BE_GEN2;
  4405. phba->iotask_fn = beiscsi_iotask;
  4406. break;
  4407. case BE_DEVICE_ID2:
  4408. case OC_DEVICE_ID3:
  4409. phba->generation = BE_GEN3;
  4410. phba->iotask_fn = beiscsi_iotask;
  4411. break;
  4412. case OC_SKH_ID1:
  4413. phba->generation = BE_GEN4;
  4414. phba->iotask_fn = beiscsi_iotask_v2;
  4415. break;
  4416. default:
  4417. phba->generation = 0;
  4418. }
  4419. if (enable_msix)
  4420. find_num_cpus(phba);
  4421. else
  4422. phba->num_cpus = 1;
  4423. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4424. "BM_%d : num_cpus = %d\n",
  4425. phba->num_cpus);
  4426. if (enable_msix) {
  4427. beiscsi_msix_enable(phba);
  4428. if (!phba->msix_enabled)
  4429. phba->num_cpus = 1;
  4430. }
  4431. ret = be_ctrl_init(phba, pcidev);
  4432. if (ret) {
  4433. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4434. "BM_%d : beiscsi_dev_probe-"
  4435. "Failed in be_ctrl_init\n");
  4436. goto hba_free;
  4437. }
  4438. ret = beiscsi_cmd_reset_function(phba);
  4439. if (ret) {
  4440. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4441. "BM_%d : Reset Failed\n");
  4442. goto hba_free;
  4443. }
  4444. ret = be_chk_reset_complete(phba);
  4445. if (ret) {
  4446. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4447. "BM_%d : Failed to get out of reset.\n");
  4448. goto hba_free;
  4449. }
  4450. spin_lock_init(&phba->io_sgl_lock);
  4451. spin_lock_init(&phba->mgmt_sgl_lock);
  4452. spin_lock_init(&phba->isr_lock);
  4453. spin_lock_init(&phba->async_pdu_lock);
  4454. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4455. if (ret != 0) {
  4456. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4457. "BM_%d : Error getting fw config\n");
  4458. goto free_port;
  4459. }
  4460. phba->shost->max_id = phba->params.cxns_per_ctrl;
  4461. beiscsi_get_params(phba);
  4462. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4463. ret = beiscsi_init_port(phba);
  4464. if (ret < 0) {
  4465. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4466. "BM_%d : beiscsi_dev_probe-"
  4467. "Failed in beiscsi_init_port\n");
  4468. goto free_port;
  4469. }
  4470. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4471. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4472. phba->ctrl.mcc_tag[i] = i + 1;
  4473. phba->ctrl.mcc_numtag[i + 1] = 0;
  4474. phba->ctrl.mcc_tag_available++;
  4475. }
  4476. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4477. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4478. phba->shost->host_no);
  4479. phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
  4480. if (!phba->wq) {
  4481. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4482. "BM_%d : beiscsi_dev_probe-"
  4483. "Failed to allocate work queue\n");
  4484. goto free_twq;
  4485. }
  4486. INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
  4487. beiscsi_hw_health_check);
  4488. phwi_ctrlr = phba->phwi_ctrlr;
  4489. phwi_context = phwi_ctrlr->phwi_ctxt;
  4490. if (blk_iopoll_enabled) {
  4491. for (i = 0; i < phba->num_cpus; i++) {
  4492. pbe_eq = &phwi_context->be_eq[i];
  4493. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4494. be_iopoll);
  4495. blk_iopoll_enable(&pbe_eq->iopoll);
  4496. }
  4497. i = (phba->msix_enabled) ? i : 0;
  4498. /* Work item for MCC handling */
  4499. pbe_eq = &phwi_context->be_eq[i];
  4500. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4501. } else {
  4502. if (phba->msix_enabled) {
  4503. for (i = 0; i <= phba->num_cpus; i++) {
  4504. pbe_eq = &phwi_context->be_eq[i];
  4505. INIT_WORK(&pbe_eq->work_cqs,
  4506. beiscsi_process_all_cqs);
  4507. }
  4508. } else {
  4509. pbe_eq = &phwi_context->be_eq[0];
  4510. INIT_WORK(&pbe_eq->work_cqs,
  4511. beiscsi_process_all_cqs);
  4512. }
  4513. }
  4514. ret = beiscsi_init_irqs(phba);
  4515. if (ret < 0) {
  4516. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4517. "BM_%d : beiscsi_dev_probe-"
  4518. "Failed to beiscsi_init_irqs\n");
  4519. goto free_blkenbld;
  4520. }
  4521. hwi_enable_intr(phba);
  4522. if (beiscsi_setup_boot_info(phba))
  4523. /*
  4524. * log error but continue, because we may not be using
  4525. * iscsi boot.
  4526. */
  4527. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4528. "BM_%d : Could not set up "
  4529. "iSCSI boot info.\n");
  4530. beiscsi_create_def_ifaces(phba);
  4531. schedule_delayed_work(&phba->beiscsi_hw_check_task,
  4532. msecs_to_jiffies(1000));
  4533. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4534. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4535. return 0;
  4536. free_blkenbld:
  4537. destroy_workqueue(phba->wq);
  4538. if (blk_iopoll_enabled)
  4539. for (i = 0; i < phba->num_cpus; i++) {
  4540. pbe_eq = &phwi_context->be_eq[i];
  4541. blk_iopoll_disable(&pbe_eq->iopoll);
  4542. }
  4543. free_twq:
  4544. beiscsi_clean_port(phba);
  4545. beiscsi_free_mem(phba);
  4546. free_port:
  4547. pci_free_consistent(phba->pcidev,
  4548. phba->ctrl.mbox_mem_alloced.size,
  4549. phba->ctrl.mbox_mem_alloced.va,
  4550. phba->ctrl.mbox_mem_alloced.dma);
  4551. beiscsi_unmap_pci_function(phba);
  4552. hba_free:
  4553. if (phba->msix_enabled)
  4554. pci_disable_msix(phba->pcidev);
  4555. iscsi_host_remove(phba->shost);
  4556. pci_dev_put(phba->pcidev);
  4557. iscsi_host_free(phba->shost);
  4558. disable_pci:
  4559. pci_disable_device(pcidev);
  4560. return ret;
  4561. }
  4562. struct iscsi_transport beiscsi_iscsi_transport = {
  4563. .owner = THIS_MODULE,
  4564. .name = DRV_NAME,
  4565. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4566. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4567. .create_session = beiscsi_session_create,
  4568. .destroy_session = beiscsi_session_destroy,
  4569. .create_conn = beiscsi_conn_create,
  4570. .bind_conn = beiscsi_conn_bind,
  4571. .destroy_conn = iscsi_conn_teardown,
  4572. .attr_is_visible = be2iscsi_attr_is_visible,
  4573. .set_iface_param = be2iscsi_iface_set_param,
  4574. .get_iface_param = be2iscsi_iface_get_param,
  4575. .set_param = beiscsi_set_param,
  4576. .get_conn_param = iscsi_conn_get_param,
  4577. .get_session_param = iscsi_session_get_param,
  4578. .get_host_param = beiscsi_get_host_param,
  4579. .start_conn = beiscsi_conn_start,
  4580. .stop_conn = iscsi_conn_stop,
  4581. .send_pdu = iscsi_conn_send_pdu,
  4582. .xmit_task = beiscsi_task_xmit,
  4583. .cleanup_task = beiscsi_cleanup_task,
  4584. .alloc_pdu = beiscsi_alloc_pdu,
  4585. .parse_pdu_itt = beiscsi_parse_pdu,
  4586. .get_stats = beiscsi_conn_get_stats,
  4587. .get_ep_param = beiscsi_ep_get_param,
  4588. .ep_connect = beiscsi_ep_connect,
  4589. .ep_poll = beiscsi_ep_poll,
  4590. .ep_disconnect = beiscsi_ep_disconnect,
  4591. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4592. .bsg_request = beiscsi_bsg_request,
  4593. };
  4594. static struct pci_driver beiscsi_pci_driver = {
  4595. .name = DRV_NAME,
  4596. .probe = beiscsi_dev_probe,
  4597. .remove = beiscsi_remove,
  4598. .shutdown = beiscsi_shutdown,
  4599. .id_table = beiscsi_pci_id_table
  4600. };
  4601. static int __init beiscsi_module_init(void)
  4602. {
  4603. int ret;
  4604. beiscsi_scsi_transport =
  4605. iscsi_register_transport(&beiscsi_iscsi_transport);
  4606. if (!beiscsi_scsi_transport) {
  4607. printk(KERN_ERR
  4608. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4609. return -ENOMEM;
  4610. }
  4611. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4612. &beiscsi_iscsi_transport);
  4613. ret = pci_register_driver(&beiscsi_pci_driver);
  4614. if (ret) {
  4615. printk(KERN_ERR
  4616. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4617. goto unregister_iscsi_transport;
  4618. }
  4619. return 0;
  4620. unregister_iscsi_transport:
  4621. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4622. return ret;
  4623. }
  4624. static void __exit beiscsi_module_exit(void)
  4625. {
  4626. pci_unregister_driver(&beiscsi_pci_driver);
  4627. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4628. }
  4629. module_init(beiscsi_module_init);
  4630. module_exit(beiscsi_module_exit);