i810_dma.c 33 KB

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  1. /* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. * Keith Whitwell <keith@tungstengraphics.com>
  30. *
  31. */
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "i810_drm.h"
  35. #include "i810_drv.h"
  36. #include <linux/interrupt.h> /* For task queue support */
  37. #include <linux/delay.h>
  38. #include <linux/slab.h>
  39. #include <linux/pagemap.h>
  40. #define I810_BUF_FREE 2
  41. #define I810_BUF_CLIENT 1
  42. #define I810_BUF_HARDWARE 0
  43. #define I810_BUF_UNMAPPED 0
  44. #define I810_BUF_MAPPED 1
  45. static struct drm_buf *i810_freelist_get(struct drm_device * dev)
  46. {
  47. struct drm_device_dma *dma = dev->dma;
  48. int i;
  49. int used;
  50. /* Linear search might not be the best solution */
  51. for (i = 0; i < dma->buf_count; i++) {
  52. struct drm_buf *buf = dma->buflist[i];
  53. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  54. /* In use is already a pointer */
  55. used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
  56. I810_BUF_CLIENT);
  57. if (used == I810_BUF_FREE)
  58. return buf;
  59. }
  60. return NULL;
  61. }
  62. /* This should only be called if the buffer is not sent to the hardware
  63. * yet, the hardware updates in use for us once its on the ring buffer.
  64. */
  65. static int i810_freelist_put(struct drm_device *dev, struct drm_buf *buf)
  66. {
  67. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  68. int used;
  69. /* In use is already a pointer */
  70. used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
  71. if (used != I810_BUF_CLIENT) {
  72. DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
  73. return -EINVAL;
  74. }
  75. return 0;
  76. }
  77. static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
  78. {
  79. struct drm_file *priv = filp->private_data;
  80. struct drm_device *dev;
  81. drm_i810_private_t *dev_priv;
  82. struct drm_buf *buf;
  83. drm_i810_buf_priv_t *buf_priv;
  84. dev = priv->minor->dev;
  85. dev_priv = dev->dev_private;
  86. buf = dev_priv->mmap_buffer;
  87. buf_priv = buf->dev_private;
  88. vma->vm_flags |= (VM_IO | VM_DONTCOPY);
  89. buf_priv->currently_mapped = I810_BUF_MAPPED;
  90. if (io_remap_pfn_range(vma, vma->vm_start,
  91. vma->vm_pgoff,
  92. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  93. return -EAGAIN;
  94. return 0;
  95. }
  96. static const struct file_operations i810_buffer_fops = {
  97. .open = drm_open,
  98. .release = drm_release,
  99. .unlocked_ioctl = drm_ioctl,
  100. .mmap = i810_mmap_buffers,
  101. .fasync = drm_fasync,
  102. #ifdef CONFIG_COMPAT
  103. .compat_ioctl = drm_compat_ioctl,
  104. #endif
  105. .llseek = noop_llseek,
  106. };
  107. static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv)
  108. {
  109. struct drm_device *dev = file_priv->minor->dev;
  110. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  111. drm_i810_private_t *dev_priv = dev->dev_private;
  112. const struct file_operations *old_fops;
  113. int retcode = 0;
  114. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  115. return -EINVAL;
  116. /* This is all entirely broken */
  117. old_fops = file_priv->filp->f_op;
  118. file_priv->filp->f_op = &i810_buffer_fops;
  119. dev_priv->mmap_buffer = buf;
  120. buf_priv->virtual = (void *)vm_mmap(file_priv->filp, 0, buf->total,
  121. PROT_READ | PROT_WRITE,
  122. MAP_SHARED, buf->bus_address);
  123. dev_priv->mmap_buffer = NULL;
  124. file_priv->filp->f_op = old_fops;
  125. if (IS_ERR(buf_priv->virtual)) {
  126. /* Real error */
  127. DRM_ERROR("mmap error\n");
  128. retcode = PTR_ERR(buf_priv->virtual);
  129. buf_priv->virtual = NULL;
  130. }
  131. return retcode;
  132. }
  133. static int i810_unmap_buffer(struct drm_buf *buf)
  134. {
  135. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  136. int retcode = 0;
  137. if (buf_priv->currently_mapped != I810_BUF_MAPPED)
  138. return -EINVAL;
  139. retcode = vm_munmap((unsigned long)buf_priv->virtual,
  140. (size_t) buf->total);
  141. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  142. buf_priv->virtual = NULL;
  143. return retcode;
  144. }
  145. static int i810_dma_get_buffer(struct drm_device *dev, drm_i810_dma_t *d,
  146. struct drm_file *file_priv)
  147. {
  148. struct drm_buf *buf;
  149. drm_i810_buf_priv_t *buf_priv;
  150. int retcode = 0;
  151. buf = i810_freelist_get(dev);
  152. if (!buf) {
  153. retcode = -ENOMEM;
  154. DRM_DEBUG("retcode=%d\n", retcode);
  155. return retcode;
  156. }
  157. retcode = i810_map_buffer(buf, file_priv);
  158. if (retcode) {
  159. i810_freelist_put(dev, buf);
  160. DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
  161. return retcode;
  162. }
  163. buf->file_priv = file_priv;
  164. buf_priv = buf->dev_private;
  165. d->granted = 1;
  166. d->request_idx = buf->idx;
  167. d->request_size = buf->total;
  168. d->virtual = buf_priv->virtual;
  169. return retcode;
  170. }
  171. static int i810_dma_cleanup(struct drm_device *dev)
  172. {
  173. struct drm_device_dma *dma = dev->dma;
  174. /* Make sure interrupts are disabled here because the uninstall ioctl
  175. * may not have been called from userspace and after dev_private
  176. * is freed, it's too late.
  177. */
  178. if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
  179. drm_irq_uninstall(dev);
  180. if (dev->dev_private) {
  181. int i;
  182. drm_i810_private_t *dev_priv =
  183. (drm_i810_private_t *) dev->dev_private;
  184. if (dev_priv->ring.virtual_start)
  185. drm_core_ioremapfree(&dev_priv->ring.map, dev);
  186. if (dev_priv->hw_status_page) {
  187. pci_free_consistent(dev->pdev, PAGE_SIZE,
  188. dev_priv->hw_status_page,
  189. dev_priv->dma_status_page);
  190. }
  191. kfree(dev->dev_private);
  192. dev->dev_private = NULL;
  193. for (i = 0; i < dma->buf_count; i++) {
  194. struct drm_buf *buf = dma->buflist[i];
  195. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  196. if (buf_priv->kernel_virtual && buf->total)
  197. drm_core_ioremapfree(&buf_priv->map, dev);
  198. }
  199. }
  200. return 0;
  201. }
  202. static int i810_wait_ring(struct drm_device *dev, int n)
  203. {
  204. drm_i810_private_t *dev_priv = dev->dev_private;
  205. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  206. int iters = 0;
  207. unsigned long end;
  208. unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  209. end = jiffies + (HZ * 3);
  210. while (ring->space < n) {
  211. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  212. ring->space = ring->head - (ring->tail + 8);
  213. if (ring->space < 0)
  214. ring->space += ring->Size;
  215. if (ring->head != last_head) {
  216. end = jiffies + (HZ * 3);
  217. last_head = ring->head;
  218. }
  219. iters++;
  220. if (time_before(end, jiffies)) {
  221. DRM_ERROR("space: %d wanted %d\n", ring->space, n);
  222. DRM_ERROR("lockup\n");
  223. goto out_wait_ring;
  224. }
  225. udelay(1);
  226. }
  227. out_wait_ring:
  228. return iters;
  229. }
  230. static void i810_kernel_lost_context(struct drm_device *dev)
  231. {
  232. drm_i810_private_t *dev_priv = dev->dev_private;
  233. drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
  234. ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  235. ring->tail = I810_READ(LP_RING + RING_TAIL);
  236. ring->space = ring->head - (ring->tail + 8);
  237. if (ring->space < 0)
  238. ring->space += ring->Size;
  239. }
  240. static int i810_freelist_init(struct drm_device *dev, drm_i810_private_t *dev_priv)
  241. {
  242. struct drm_device_dma *dma = dev->dma;
  243. int my_idx = 24;
  244. u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
  245. int i;
  246. if (dma->buf_count > 1019) {
  247. /* Not enough space in the status page for the freelist */
  248. return -EINVAL;
  249. }
  250. for (i = 0; i < dma->buf_count; i++) {
  251. struct drm_buf *buf = dma->buflist[i];
  252. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  253. buf_priv->in_use = hw_status++;
  254. buf_priv->my_use_idx = my_idx;
  255. my_idx += 4;
  256. *buf_priv->in_use = I810_BUF_FREE;
  257. buf_priv->map.offset = buf->bus_address;
  258. buf_priv->map.size = buf->total;
  259. buf_priv->map.type = _DRM_AGP;
  260. buf_priv->map.flags = 0;
  261. buf_priv->map.mtrr = 0;
  262. drm_core_ioremap(&buf_priv->map, dev);
  263. buf_priv->kernel_virtual = buf_priv->map.handle;
  264. }
  265. return 0;
  266. }
  267. static int i810_dma_initialize(struct drm_device *dev,
  268. drm_i810_private_t *dev_priv,
  269. drm_i810_init_t *init)
  270. {
  271. struct drm_map_list *r_list;
  272. memset(dev_priv, 0, sizeof(drm_i810_private_t));
  273. list_for_each_entry(r_list, &dev->maplist, head) {
  274. if (r_list->map &&
  275. r_list->map->type == _DRM_SHM &&
  276. r_list->map->flags & _DRM_CONTAINS_LOCK) {
  277. dev_priv->sarea_map = r_list->map;
  278. break;
  279. }
  280. }
  281. if (!dev_priv->sarea_map) {
  282. dev->dev_private = (void *)dev_priv;
  283. i810_dma_cleanup(dev);
  284. DRM_ERROR("can not find sarea!\n");
  285. return -EINVAL;
  286. }
  287. dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
  288. if (!dev_priv->mmio_map) {
  289. dev->dev_private = (void *)dev_priv;
  290. i810_dma_cleanup(dev);
  291. DRM_ERROR("can not find mmio map!\n");
  292. return -EINVAL;
  293. }
  294. dev->agp_buffer_token = init->buffers_offset;
  295. dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
  296. if (!dev->agp_buffer_map) {
  297. dev->dev_private = (void *)dev_priv;
  298. i810_dma_cleanup(dev);
  299. DRM_ERROR("can not find dma buffer map!\n");
  300. return -EINVAL;
  301. }
  302. dev_priv->sarea_priv = (drm_i810_sarea_t *)
  303. ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
  304. dev_priv->ring.Start = init->ring_start;
  305. dev_priv->ring.End = init->ring_end;
  306. dev_priv->ring.Size = init->ring_size;
  307. dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
  308. dev_priv->ring.map.size = init->ring_size;
  309. dev_priv->ring.map.type = _DRM_AGP;
  310. dev_priv->ring.map.flags = 0;
  311. dev_priv->ring.map.mtrr = 0;
  312. drm_core_ioremap(&dev_priv->ring.map, dev);
  313. if (dev_priv->ring.map.handle == NULL) {
  314. dev->dev_private = (void *)dev_priv;
  315. i810_dma_cleanup(dev);
  316. DRM_ERROR("can not ioremap virtual address for"
  317. " ring buffer\n");
  318. return -ENOMEM;
  319. }
  320. dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
  321. dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
  322. dev_priv->w = init->w;
  323. dev_priv->h = init->h;
  324. dev_priv->pitch = init->pitch;
  325. dev_priv->back_offset = init->back_offset;
  326. dev_priv->depth_offset = init->depth_offset;
  327. dev_priv->front_offset = init->front_offset;
  328. dev_priv->overlay_offset = init->overlay_offset;
  329. dev_priv->overlay_physical = init->overlay_physical;
  330. dev_priv->front_di1 = init->front_offset | init->pitch_bits;
  331. dev_priv->back_di1 = init->back_offset | init->pitch_bits;
  332. dev_priv->zi1 = init->depth_offset | init->pitch_bits;
  333. /* Program Hardware Status Page */
  334. dev_priv->hw_status_page =
  335. pci_alloc_consistent(dev->pdev, PAGE_SIZE,
  336. &dev_priv->dma_status_page);
  337. if (!dev_priv->hw_status_page) {
  338. dev->dev_private = (void *)dev_priv;
  339. i810_dma_cleanup(dev);
  340. DRM_ERROR("Can not allocate hardware status page\n");
  341. return -ENOMEM;
  342. }
  343. memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  344. DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
  345. I810_WRITE(0x02080, dev_priv->dma_status_page);
  346. DRM_DEBUG("Enabled hardware status page\n");
  347. /* Now we need to init our freelist */
  348. if (i810_freelist_init(dev, dev_priv) != 0) {
  349. dev->dev_private = (void *)dev_priv;
  350. i810_dma_cleanup(dev);
  351. DRM_ERROR("Not enough space in the status page for"
  352. " the freelist\n");
  353. return -ENOMEM;
  354. }
  355. dev->dev_private = (void *)dev_priv;
  356. return 0;
  357. }
  358. static int i810_dma_init(struct drm_device *dev, void *data,
  359. struct drm_file *file_priv)
  360. {
  361. drm_i810_private_t *dev_priv;
  362. drm_i810_init_t *init = data;
  363. int retcode = 0;
  364. switch (init->func) {
  365. case I810_INIT_DMA_1_4:
  366. DRM_INFO("Using v1.4 init.\n");
  367. dev_priv = kmalloc(sizeof(drm_i810_private_t), GFP_KERNEL);
  368. if (dev_priv == NULL)
  369. return -ENOMEM;
  370. retcode = i810_dma_initialize(dev, dev_priv, init);
  371. break;
  372. case I810_CLEANUP_DMA:
  373. DRM_INFO("DMA Cleanup\n");
  374. retcode = i810_dma_cleanup(dev);
  375. break;
  376. default:
  377. return -EINVAL;
  378. }
  379. return retcode;
  380. }
  381. /* Most efficient way to verify state for the i810 is as it is
  382. * emitted. Non-conformant state is silently dropped.
  383. *
  384. * Use 'volatile' & local var tmp to force the emitted values to be
  385. * identical to the verified ones.
  386. */
  387. static void i810EmitContextVerified(struct drm_device *dev,
  388. volatile unsigned int *code)
  389. {
  390. drm_i810_private_t *dev_priv = dev->dev_private;
  391. int i, j = 0;
  392. unsigned int tmp;
  393. RING_LOCALS;
  394. BEGIN_LP_RING(I810_CTX_SETUP_SIZE);
  395. OUT_RING(GFX_OP_COLOR_FACTOR);
  396. OUT_RING(code[I810_CTXREG_CF1]);
  397. OUT_RING(GFX_OP_STIPPLE);
  398. OUT_RING(code[I810_CTXREG_ST1]);
  399. for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
  400. tmp = code[i];
  401. if ((tmp & (7 << 29)) == (3 << 29) &&
  402. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  403. OUT_RING(tmp);
  404. j++;
  405. } else
  406. printk("constext state dropped!!!\n");
  407. }
  408. if (j & 1)
  409. OUT_RING(0);
  410. ADVANCE_LP_RING();
  411. }
  412. static void i810EmitTexVerified(struct drm_device *dev, volatile unsigned int *code)
  413. {
  414. drm_i810_private_t *dev_priv = dev->dev_private;
  415. int i, j = 0;
  416. unsigned int tmp;
  417. RING_LOCALS;
  418. BEGIN_LP_RING(I810_TEX_SETUP_SIZE);
  419. OUT_RING(GFX_OP_MAP_INFO);
  420. OUT_RING(code[I810_TEXREG_MI1]);
  421. OUT_RING(code[I810_TEXREG_MI2]);
  422. OUT_RING(code[I810_TEXREG_MI3]);
  423. for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
  424. tmp = code[i];
  425. if ((tmp & (7 << 29)) == (3 << 29) &&
  426. (tmp & (0x1f << 24)) < (0x1d << 24)) {
  427. OUT_RING(tmp);
  428. j++;
  429. } else
  430. printk("texture state dropped!!!\n");
  431. }
  432. if (j & 1)
  433. OUT_RING(0);
  434. ADVANCE_LP_RING();
  435. }
  436. /* Need to do some additional checking when setting the dest buffer.
  437. */
  438. static void i810EmitDestVerified(struct drm_device *dev,
  439. volatile unsigned int *code)
  440. {
  441. drm_i810_private_t *dev_priv = dev->dev_private;
  442. unsigned int tmp;
  443. RING_LOCALS;
  444. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  445. tmp = code[I810_DESTREG_DI1];
  446. if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
  447. OUT_RING(CMD_OP_DESTBUFFER_INFO);
  448. OUT_RING(tmp);
  449. } else
  450. DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
  451. tmp, dev_priv->front_di1, dev_priv->back_di1);
  452. /* invarient:
  453. */
  454. OUT_RING(CMD_OP_Z_BUFFER_INFO);
  455. OUT_RING(dev_priv->zi1);
  456. OUT_RING(GFX_OP_DESTBUFFER_VARS);
  457. OUT_RING(code[I810_DESTREG_DV1]);
  458. OUT_RING(GFX_OP_DRAWRECT_INFO);
  459. OUT_RING(code[I810_DESTREG_DR1]);
  460. OUT_RING(code[I810_DESTREG_DR2]);
  461. OUT_RING(code[I810_DESTREG_DR3]);
  462. OUT_RING(code[I810_DESTREG_DR4]);
  463. OUT_RING(0);
  464. ADVANCE_LP_RING();
  465. }
  466. static void i810EmitState(struct drm_device *dev)
  467. {
  468. drm_i810_private_t *dev_priv = dev->dev_private;
  469. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  470. unsigned int dirty = sarea_priv->dirty;
  471. DRM_DEBUG("%x\n", dirty);
  472. if (dirty & I810_UPLOAD_BUFFERS) {
  473. i810EmitDestVerified(dev, sarea_priv->BufferState);
  474. sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
  475. }
  476. if (dirty & I810_UPLOAD_CTX) {
  477. i810EmitContextVerified(dev, sarea_priv->ContextState);
  478. sarea_priv->dirty &= ~I810_UPLOAD_CTX;
  479. }
  480. if (dirty & I810_UPLOAD_TEX0) {
  481. i810EmitTexVerified(dev, sarea_priv->TexState[0]);
  482. sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
  483. }
  484. if (dirty & I810_UPLOAD_TEX1) {
  485. i810EmitTexVerified(dev, sarea_priv->TexState[1]);
  486. sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
  487. }
  488. }
  489. /* need to verify
  490. */
  491. static void i810_dma_dispatch_clear(struct drm_device *dev, int flags,
  492. unsigned int clear_color,
  493. unsigned int clear_zval)
  494. {
  495. drm_i810_private_t *dev_priv = dev->dev_private;
  496. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  497. int nbox = sarea_priv->nbox;
  498. struct drm_clip_rect *pbox = sarea_priv->boxes;
  499. int pitch = dev_priv->pitch;
  500. int cpp = 2;
  501. int i;
  502. RING_LOCALS;
  503. if (dev_priv->current_page == 1) {
  504. unsigned int tmp = flags;
  505. flags &= ~(I810_FRONT | I810_BACK);
  506. if (tmp & I810_FRONT)
  507. flags |= I810_BACK;
  508. if (tmp & I810_BACK)
  509. flags |= I810_FRONT;
  510. }
  511. i810_kernel_lost_context(dev);
  512. if (nbox > I810_NR_SAREA_CLIPRECTS)
  513. nbox = I810_NR_SAREA_CLIPRECTS;
  514. for (i = 0; i < nbox; i++, pbox++) {
  515. unsigned int x = pbox->x1;
  516. unsigned int y = pbox->y1;
  517. unsigned int width = (pbox->x2 - x) * cpp;
  518. unsigned int height = pbox->y2 - y;
  519. unsigned int start = y * pitch + x * cpp;
  520. if (pbox->x1 > pbox->x2 ||
  521. pbox->y1 > pbox->y2 ||
  522. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  523. continue;
  524. if (flags & I810_FRONT) {
  525. BEGIN_LP_RING(6);
  526. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  527. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  528. OUT_RING((height << 16) | width);
  529. OUT_RING(start);
  530. OUT_RING(clear_color);
  531. OUT_RING(0);
  532. ADVANCE_LP_RING();
  533. }
  534. if (flags & I810_BACK) {
  535. BEGIN_LP_RING(6);
  536. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  537. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  538. OUT_RING((height << 16) | width);
  539. OUT_RING(dev_priv->back_offset + start);
  540. OUT_RING(clear_color);
  541. OUT_RING(0);
  542. ADVANCE_LP_RING();
  543. }
  544. if (flags & I810_DEPTH) {
  545. BEGIN_LP_RING(6);
  546. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
  547. OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
  548. OUT_RING((height << 16) | width);
  549. OUT_RING(dev_priv->depth_offset + start);
  550. OUT_RING(clear_zval);
  551. OUT_RING(0);
  552. ADVANCE_LP_RING();
  553. }
  554. }
  555. }
  556. static void i810_dma_dispatch_swap(struct drm_device *dev)
  557. {
  558. drm_i810_private_t *dev_priv = dev->dev_private;
  559. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  560. int nbox = sarea_priv->nbox;
  561. struct drm_clip_rect *pbox = sarea_priv->boxes;
  562. int pitch = dev_priv->pitch;
  563. int cpp = 2;
  564. int i;
  565. RING_LOCALS;
  566. DRM_DEBUG("swapbuffers\n");
  567. i810_kernel_lost_context(dev);
  568. if (nbox > I810_NR_SAREA_CLIPRECTS)
  569. nbox = I810_NR_SAREA_CLIPRECTS;
  570. for (i = 0; i < nbox; i++, pbox++) {
  571. unsigned int w = pbox->x2 - pbox->x1;
  572. unsigned int h = pbox->y2 - pbox->y1;
  573. unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
  574. unsigned int start = dst;
  575. if (pbox->x1 > pbox->x2 ||
  576. pbox->y1 > pbox->y2 ||
  577. pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
  578. continue;
  579. BEGIN_LP_RING(6);
  580. OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
  581. OUT_RING(pitch | (0xCC << 16));
  582. OUT_RING((h << 16) | (w * cpp));
  583. if (dev_priv->current_page == 0)
  584. OUT_RING(dev_priv->front_offset + start);
  585. else
  586. OUT_RING(dev_priv->back_offset + start);
  587. OUT_RING(pitch);
  588. if (dev_priv->current_page == 0)
  589. OUT_RING(dev_priv->back_offset + start);
  590. else
  591. OUT_RING(dev_priv->front_offset + start);
  592. ADVANCE_LP_RING();
  593. }
  594. }
  595. static void i810_dma_dispatch_vertex(struct drm_device *dev,
  596. struct drm_buf *buf, int discard, int used)
  597. {
  598. drm_i810_private_t *dev_priv = dev->dev_private;
  599. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  600. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  601. struct drm_clip_rect *box = sarea_priv->boxes;
  602. int nbox = sarea_priv->nbox;
  603. unsigned long address = (unsigned long)buf->bus_address;
  604. unsigned long start = address - dev->agp->base;
  605. int i = 0;
  606. RING_LOCALS;
  607. i810_kernel_lost_context(dev);
  608. if (nbox > I810_NR_SAREA_CLIPRECTS)
  609. nbox = I810_NR_SAREA_CLIPRECTS;
  610. if (used > 4 * 1024)
  611. used = 0;
  612. if (sarea_priv->dirty)
  613. i810EmitState(dev);
  614. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  615. unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
  616. *(u32 *) buf_priv->kernel_virtual =
  617. ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));
  618. if (used & 4) {
  619. *(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
  620. used += 4;
  621. }
  622. i810_unmap_buffer(buf);
  623. }
  624. if (used) {
  625. do {
  626. if (i < nbox) {
  627. BEGIN_LP_RING(4);
  628. OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
  629. SC_ENABLE);
  630. OUT_RING(GFX_OP_SCISSOR_INFO);
  631. OUT_RING(box[i].x1 | (box[i].y1 << 16));
  632. OUT_RING((box[i].x2 -
  633. 1) | ((box[i].y2 - 1) << 16));
  634. ADVANCE_LP_RING();
  635. }
  636. BEGIN_LP_RING(4);
  637. OUT_RING(CMD_OP_BATCH_BUFFER);
  638. OUT_RING(start | BB1_PROTECTED);
  639. OUT_RING(start + used - 4);
  640. OUT_RING(0);
  641. ADVANCE_LP_RING();
  642. } while (++i < nbox);
  643. }
  644. if (discard) {
  645. dev_priv->counter++;
  646. (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  647. I810_BUF_HARDWARE);
  648. BEGIN_LP_RING(8);
  649. OUT_RING(CMD_STORE_DWORD_IDX);
  650. OUT_RING(20);
  651. OUT_RING(dev_priv->counter);
  652. OUT_RING(CMD_STORE_DWORD_IDX);
  653. OUT_RING(buf_priv->my_use_idx);
  654. OUT_RING(I810_BUF_FREE);
  655. OUT_RING(CMD_REPORT_HEAD);
  656. OUT_RING(0);
  657. ADVANCE_LP_RING();
  658. }
  659. }
  660. static void i810_dma_dispatch_flip(struct drm_device *dev)
  661. {
  662. drm_i810_private_t *dev_priv = dev->dev_private;
  663. int pitch = dev_priv->pitch;
  664. RING_LOCALS;
  665. DRM_DEBUG("page=%d pfCurrentPage=%d\n",
  666. dev_priv->current_page,
  667. dev_priv->sarea_priv->pf_current_page);
  668. i810_kernel_lost_context(dev);
  669. BEGIN_LP_RING(2);
  670. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  671. OUT_RING(0);
  672. ADVANCE_LP_RING();
  673. BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
  674. /* On i815 at least ASYNC is buggy */
  675. /* pitch<<5 is from 11.2.8 p158,
  676. its the pitch / 8 then left shifted 8,
  677. so (pitch >> 3) << 8 */
  678. OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
  679. if (dev_priv->current_page == 0) {
  680. OUT_RING(dev_priv->back_offset);
  681. dev_priv->current_page = 1;
  682. } else {
  683. OUT_RING(dev_priv->front_offset);
  684. dev_priv->current_page = 0;
  685. }
  686. OUT_RING(0);
  687. ADVANCE_LP_RING();
  688. BEGIN_LP_RING(2);
  689. OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
  690. OUT_RING(0);
  691. ADVANCE_LP_RING();
  692. /* Increment the frame counter. The client-side 3D driver must
  693. * throttle the framerate by waiting for this value before
  694. * performing the swapbuffer ioctl.
  695. */
  696. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  697. }
  698. static void i810_dma_quiescent(struct drm_device *dev)
  699. {
  700. drm_i810_private_t *dev_priv = dev->dev_private;
  701. RING_LOCALS;
  702. i810_kernel_lost_context(dev);
  703. BEGIN_LP_RING(4);
  704. OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
  705. OUT_RING(CMD_REPORT_HEAD);
  706. OUT_RING(0);
  707. OUT_RING(0);
  708. ADVANCE_LP_RING();
  709. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  710. }
  711. static int i810_flush_queue(struct drm_device *dev)
  712. {
  713. drm_i810_private_t *dev_priv = dev->dev_private;
  714. struct drm_device_dma *dma = dev->dma;
  715. int i, ret = 0;
  716. RING_LOCALS;
  717. i810_kernel_lost_context(dev);
  718. BEGIN_LP_RING(2);
  719. OUT_RING(CMD_REPORT_HEAD);
  720. OUT_RING(0);
  721. ADVANCE_LP_RING();
  722. i810_wait_ring(dev, dev_priv->ring.Size - 8);
  723. for (i = 0; i < dma->buf_count; i++) {
  724. struct drm_buf *buf = dma->buflist[i];
  725. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  726. int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
  727. I810_BUF_FREE);
  728. if (used == I810_BUF_HARDWARE)
  729. DRM_DEBUG("reclaimed from HARDWARE\n");
  730. if (used == I810_BUF_CLIENT)
  731. DRM_DEBUG("still on client\n");
  732. }
  733. return ret;
  734. }
  735. /* Must be called with the lock held */
  736. void i810_driver_reclaim_buffers(struct drm_device *dev,
  737. struct drm_file *file_priv)
  738. {
  739. struct drm_device_dma *dma = dev->dma;
  740. int i;
  741. if (!dma)
  742. return;
  743. if (!dev->dev_private)
  744. return;
  745. if (!dma->buflist)
  746. return;
  747. i810_flush_queue(dev);
  748. for (i = 0; i < dma->buf_count; i++) {
  749. struct drm_buf *buf = dma->buflist[i];
  750. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  751. if (buf->file_priv == file_priv && buf_priv) {
  752. int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
  753. I810_BUF_FREE);
  754. if (used == I810_BUF_CLIENT)
  755. DRM_DEBUG("reclaimed from client\n");
  756. if (buf_priv->currently_mapped == I810_BUF_MAPPED)
  757. buf_priv->currently_mapped = I810_BUF_UNMAPPED;
  758. }
  759. }
  760. }
  761. static int i810_flush_ioctl(struct drm_device *dev, void *data,
  762. struct drm_file *file_priv)
  763. {
  764. LOCK_TEST_WITH_RETURN(dev, file_priv);
  765. i810_flush_queue(dev);
  766. return 0;
  767. }
  768. static int i810_dma_vertex(struct drm_device *dev, void *data,
  769. struct drm_file *file_priv)
  770. {
  771. struct drm_device_dma *dma = dev->dma;
  772. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  773. u32 *hw_status = dev_priv->hw_status_page;
  774. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  775. dev_priv->sarea_priv;
  776. drm_i810_vertex_t *vertex = data;
  777. LOCK_TEST_WITH_RETURN(dev, file_priv);
  778. DRM_DEBUG("idx %d used %d discard %d\n",
  779. vertex->idx, vertex->used, vertex->discard);
  780. if (vertex->idx < 0 || vertex->idx > dma->buf_count)
  781. return -EINVAL;
  782. i810_dma_dispatch_vertex(dev,
  783. dma->buflist[vertex->idx],
  784. vertex->discard, vertex->used);
  785. atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
  786. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  787. sarea_priv->last_enqueue = dev_priv->counter - 1;
  788. sarea_priv->last_dispatch = (int)hw_status[5];
  789. return 0;
  790. }
  791. static int i810_clear_bufs(struct drm_device *dev, void *data,
  792. struct drm_file *file_priv)
  793. {
  794. drm_i810_clear_t *clear = data;
  795. LOCK_TEST_WITH_RETURN(dev, file_priv);
  796. /* GH: Someone's doing nasty things... */
  797. if (!dev->dev_private)
  798. return -EINVAL;
  799. i810_dma_dispatch_clear(dev, clear->flags,
  800. clear->clear_color, clear->clear_depth);
  801. return 0;
  802. }
  803. static int i810_swap_bufs(struct drm_device *dev, void *data,
  804. struct drm_file *file_priv)
  805. {
  806. DRM_DEBUG("\n");
  807. LOCK_TEST_WITH_RETURN(dev, file_priv);
  808. i810_dma_dispatch_swap(dev);
  809. return 0;
  810. }
  811. static int i810_getage(struct drm_device *dev, void *data,
  812. struct drm_file *file_priv)
  813. {
  814. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  815. u32 *hw_status = dev_priv->hw_status_page;
  816. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  817. dev_priv->sarea_priv;
  818. sarea_priv->last_dispatch = (int)hw_status[5];
  819. return 0;
  820. }
  821. static int i810_getbuf(struct drm_device *dev, void *data,
  822. struct drm_file *file_priv)
  823. {
  824. int retcode = 0;
  825. drm_i810_dma_t *d = data;
  826. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  827. u32 *hw_status = dev_priv->hw_status_page;
  828. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  829. dev_priv->sarea_priv;
  830. LOCK_TEST_WITH_RETURN(dev, file_priv);
  831. d->granted = 0;
  832. retcode = i810_dma_get_buffer(dev, d, file_priv);
  833. DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
  834. task_pid_nr(current), retcode, d->granted);
  835. sarea_priv->last_dispatch = (int)hw_status[5];
  836. return retcode;
  837. }
  838. static int i810_copybuf(struct drm_device *dev, void *data,
  839. struct drm_file *file_priv)
  840. {
  841. /* Never copy - 2.4.x doesn't need it */
  842. return 0;
  843. }
  844. static int i810_docopy(struct drm_device *dev, void *data,
  845. struct drm_file *file_priv)
  846. {
  847. /* Never copy - 2.4.x doesn't need it */
  848. return 0;
  849. }
  850. static void i810_dma_dispatch_mc(struct drm_device *dev, struct drm_buf *buf, int used,
  851. unsigned int last_render)
  852. {
  853. drm_i810_private_t *dev_priv = dev->dev_private;
  854. drm_i810_buf_priv_t *buf_priv = buf->dev_private;
  855. drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
  856. unsigned long address = (unsigned long)buf->bus_address;
  857. unsigned long start = address - dev->agp->base;
  858. int u;
  859. RING_LOCALS;
  860. i810_kernel_lost_context(dev);
  861. u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
  862. if (u != I810_BUF_CLIENT)
  863. DRM_DEBUG("MC found buffer that isn't mine!\n");
  864. if (used > 4 * 1024)
  865. used = 0;
  866. sarea_priv->dirty = 0x7f;
  867. DRM_DEBUG("addr 0x%lx, used 0x%x\n", address, used);
  868. dev_priv->counter++;
  869. DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
  870. DRM_DEBUG("start : %lx\n", start);
  871. DRM_DEBUG("used : %d\n", used);
  872. DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
  873. if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
  874. if (used & 4) {
  875. *(u32 *) ((char *) buf_priv->virtual + used) = 0;
  876. used += 4;
  877. }
  878. i810_unmap_buffer(buf);
  879. }
  880. BEGIN_LP_RING(4);
  881. OUT_RING(CMD_OP_BATCH_BUFFER);
  882. OUT_RING(start | BB1_PROTECTED);
  883. OUT_RING(start + used - 4);
  884. OUT_RING(0);
  885. ADVANCE_LP_RING();
  886. BEGIN_LP_RING(8);
  887. OUT_RING(CMD_STORE_DWORD_IDX);
  888. OUT_RING(buf_priv->my_use_idx);
  889. OUT_RING(I810_BUF_FREE);
  890. OUT_RING(0);
  891. OUT_RING(CMD_STORE_DWORD_IDX);
  892. OUT_RING(16);
  893. OUT_RING(last_render);
  894. OUT_RING(0);
  895. ADVANCE_LP_RING();
  896. }
  897. static int i810_dma_mc(struct drm_device *dev, void *data,
  898. struct drm_file *file_priv)
  899. {
  900. struct drm_device_dma *dma = dev->dma;
  901. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  902. u32 *hw_status = dev_priv->hw_status_page;
  903. drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
  904. dev_priv->sarea_priv;
  905. drm_i810_mc_t *mc = data;
  906. LOCK_TEST_WITH_RETURN(dev, file_priv);
  907. if (mc->idx >= dma->buf_count || mc->idx < 0)
  908. return -EINVAL;
  909. i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
  910. mc->last_render);
  911. atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
  912. atomic_inc(&dev->counts[_DRM_STAT_DMA]);
  913. sarea_priv->last_enqueue = dev_priv->counter - 1;
  914. sarea_priv->last_dispatch = (int)hw_status[5];
  915. return 0;
  916. }
  917. static int i810_rstatus(struct drm_device *dev, void *data,
  918. struct drm_file *file_priv)
  919. {
  920. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  921. return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
  922. }
  923. static int i810_ov0_info(struct drm_device *dev, void *data,
  924. struct drm_file *file_priv)
  925. {
  926. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  927. drm_i810_overlay_t *ov = data;
  928. ov->offset = dev_priv->overlay_offset;
  929. ov->physical = dev_priv->overlay_physical;
  930. return 0;
  931. }
  932. static int i810_fstatus(struct drm_device *dev, void *data,
  933. struct drm_file *file_priv)
  934. {
  935. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  936. LOCK_TEST_WITH_RETURN(dev, file_priv);
  937. return I810_READ(0x30008);
  938. }
  939. static int i810_ov0_flip(struct drm_device *dev, void *data,
  940. struct drm_file *file_priv)
  941. {
  942. drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
  943. LOCK_TEST_WITH_RETURN(dev, file_priv);
  944. /* Tell the overlay to update */
  945. I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);
  946. return 0;
  947. }
  948. /* Not sure why this isn't set all the time:
  949. */
  950. static void i810_do_init_pageflip(struct drm_device *dev)
  951. {
  952. drm_i810_private_t *dev_priv = dev->dev_private;
  953. DRM_DEBUG("\n");
  954. dev_priv->page_flipping = 1;
  955. dev_priv->current_page = 0;
  956. dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
  957. }
  958. static int i810_do_cleanup_pageflip(struct drm_device *dev)
  959. {
  960. drm_i810_private_t *dev_priv = dev->dev_private;
  961. DRM_DEBUG("\n");
  962. if (dev_priv->current_page != 0)
  963. i810_dma_dispatch_flip(dev);
  964. dev_priv->page_flipping = 0;
  965. return 0;
  966. }
  967. static int i810_flip_bufs(struct drm_device *dev, void *data,
  968. struct drm_file *file_priv)
  969. {
  970. drm_i810_private_t *dev_priv = dev->dev_private;
  971. DRM_DEBUG("\n");
  972. LOCK_TEST_WITH_RETURN(dev, file_priv);
  973. if (!dev_priv->page_flipping)
  974. i810_do_init_pageflip(dev);
  975. i810_dma_dispatch_flip(dev);
  976. return 0;
  977. }
  978. int i810_driver_load(struct drm_device *dev, unsigned long flags)
  979. {
  980. /* i810 has 4 more counters */
  981. dev->counters += 4;
  982. dev->types[6] = _DRM_STAT_IRQ;
  983. dev->types[7] = _DRM_STAT_PRIMARY;
  984. dev->types[8] = _DRM_STAT_SECONDARY;
  985. dev->types[9] = _DRM_STAT_DMA;
  986. pci_set_master(dev->pdev);
  987. return 0;
  988. }
  989. void i810_driver_lastclose(struct drm_device *dev)
  990. {
  991. i810_dma_cleanup(dev);
  992. }
  993. void i810_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
  994. {
  995. if (dev->dev_private) {
  996. drm_i810_private_t *dev_priv = dev->dev_private;
  997. if (dev_priv->page_flipping)
  998. i810_do_cleanup_pageflip(dev);
  999. }
  1000. if (file_priv->master && file_priv->master->lock.hw_lock) {
  1001. drm_idlelock_take(&file_priv->master->lock);
  1002. i810_driver_reclaim_buffers(dev, file_priv);
  1003. drm_idlelock_release(&file_priv->master->lock);
  1004. } else {
  1005. /* master disappeared, clean up stuff anyway and hope nothing
  1006. * goes wrong */
  1007. i810_driver_reclaim_buffers(dev, file_priv);
  1008. }
  1009. }
  1010. int i810_driver_dma_quiescent(struct drm_device *dev)
  1011. {
  1012. i810_dma_quiescent(dev);
  1013. return 0;
  1014. }
  1015. struct drm_ioctl_desc i810_ioctls[] = {
  1016. DRM_IOCTL_DEF_DRV(I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1017. DRM_IOCTL_DEF_DRV(I810_VERTEX, i810_dma_vertex, DRM_AUTH|DRM_UNLOCKED),
  1018. DRM_IOCTL_DEF_DRV(I810_CLEAR, i810_clear_bufs, DRM_AUTH|DRM_UNLOCKED),
  1019. DRM_IOCTL_DEF_DRV(I810_FLUSH, i810_flush_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1020. DRM_IOCTL_DEF_DRV(I810_GETAGE, i810_getage, DRM_AUTH|DRM_UNLOCKED),
  1021. DRM_IOCTL_DEF_DRV(I810_GETBUF, i810_getbuf, DRM_AUTH|DRM_UNLOCKED),
  1022. DRM_IOCTL_DEF_DRV(I810_SWAP, i810_swap_bufs, DRM_AUTH|DRM_UNLOCKED),
  1023. DRM_IOCTL_DEF_DRV(I810_COPY, i810_copybuf, DRM_AUTH|DRM_UNLOCKED),
  1024. DRM_IOCTL_DEF_DRV(I810_DOCOPY, i810_docopy, DRM_AUTH|DRM_UNLOCKED),
  1025. DRM_IOCTL_DEF_DRV(I810_OV0INFO, i810_ov0_info, DRM_AUTH|DRM_UNLOCKED),
  1026. DRM_IOCTL_DEF_DRV(I810_FSTATUS, i810_fstatus, DRM_AUTH|DRM_UNLOCKED),
  1027. DRM_IOCTL_DEF_DRV(I810_OV0FLIP, i810_ov0_flip, DRM_AUTH|DRM_UNLOCKED),
  1028. DRM_IOCTL_DEF_DRV(I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1029. DRM_IOCTL_DEF_DRV(I810_RSTATUS, i810_rstatus, DRM_AUTH|DRM_UNLOCKED),
  1030. DRM_IOCTL_DEF_DRV(I810_FLIP, i810_flip_bufs, DRM_AUTH|DRM_UNLOCKED),
  1031. };
  1032. int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);
  1033. /**
  1034. * Determine if the device really is AGP or not.
  1035. *
  1036. * All Intel graphics chipsets are treated as AGP, even if they are really
  1037. * PCI-e.
  1038. *
  1039. * \param dev The device to be tested.
  1040. *
  1041. * \returns
  1042. * A value of 1 is always retured to indictate every i810 is AGP.
  1043. */
  1044. int i810_driver_device_is_agp(struct drm_device *dev)
  1045. {
  1046. return 1;
  1047. }