gpio-samsung.c 70 KB

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  1. /*
  2. * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com/
  4. *
  5. * Copyright 2008 Openmoko, Inc.
  6. * Copyright 2008 Simtec Electronics
  7. * Ben Dooks <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * SAMSUNG - GPIOlib support
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/irq.h>
  18. #include <linux/io.h>
  19. #include <linux/gpio.h>
  20. #include <linux/init.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/device.h>
  25. #include <linux/ioport.h>
  26. #include <linux/of.h>
  27. #include <linux/slab.h>
  28. #include <linux/of_address.h>
  29. #include <asm/irq.h>
  30. #include <mach/hardware.h>
  31. #include <mach/map.h>
  32. #include <mach/regs-gpio.h>
  33. #include <plat/cpu.h>
  34. #include <plat/gpio-core.h>
  35. #include <plat/gpio-cfg.h>
  36. #include <plat/gpio-cfg-helpers.h>
  37. #include <plat/gpio-fns.h>
  38. #include <plat/pm.h>
  39. int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
  40. unsigned int off, samsung_gpio_pull_t pull)
  41. {
  42. void __iomem *reg = chip->base + 0x08;
  43. int shift = off * 2;
  44. u32 pup;
  45. pup = __raw_readl(reg);
  46. pup &= ~(3 << shift);
  47. pup |= pull << shift;
  48. __raw_writel(pup, reg);
  49. return 0;
  50. }
  51. samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
  52. unsigned int off)
  53. {
  54. void __iomem *reg = chip->base + 0x08;
  55. int shift = off * 2;
  56. u32 pup = __raw_readl(reg);
  57. pup >>= shift;
  58. pup &= 0x3;
  59. return (__force samsung_gpio_pull_t)pup;
  60. }
  61. int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
  62. unsigned int off, samsung_gpio_pull_t pull)
  63. {
  64. switch (pull) {
  65. case S3C_GPIO_PULL_NONE:
  66. pull = 0x01;
  67. break;
  68. case S3C_GPIO_PULL_UP:
  69. pull = 0x00;
  70. break;
  71. case S3C_GPIO_PULL_DOWN:
  72. pull = 0x02;
  73. break;
  74. }
  75. return samsung_gpio_setpull_updown(chip, off, pull);
  76. }
  77. samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
  78. unsigned int off)
  79. {
  80. samsung_gpio_pull_t pull;
  81. pull = samsung_gpio_getpull_updown(chip, off);
  82. switch (pull) {
  83. case 0x00:
  84. pull = S3C_GPIO_PULL_UP;
  85. break;
  86. case 0x01:
  87. case 0x03:
  88. pull = S3C_GPIO_PULL_NONE;
  89. break;
  90. case 0x02:
  91. pull = S3C_GPIO_PULL_DOWN;
  92. break;
  93. }
  94. return pull;
  95. }
  96. static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
  97. unsigned int off, samsung_gpio_pull_t pull,
  98. samsung_gpio_pull_t updown)
  99. {
  100. void __iomem *reg = chip->base + 0x08;
  101. u32 pup = __raw_readl(reg);
  102. if (pull == updown)
  103. pup &= ~(1 << off);
  104. else if (pull == S3C_GPIO_PULL_NONE)
  105. pup |= (1 << off);
  106. else
  107. return -EINVAL;
  108. __raw_writel(pup, reg);
  109. return 0;
  110. }
  111. static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
  112. unsigned int off,
  113. samsung_gpio_pull_t updown)
  114. {
  115. void __iomem *reg = chip->base + 0x08;
  116. u32 pup = __raw_readl(reg);
  117. pup &= (1 << off);
  118. return pup ? S3C_GPIO_PULL_NONE : updown;
  119. }
  120. samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
  121. unsigned int off)
  122. {
  123. return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
  124. }
  125. int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
  126. unsigned int off, samsung_gpio_pull_t pull)
  127. {
  128. return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
  129. }
  130. samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
  131. unsigned int off)
  132. {
  133. return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
  134. }
  135. int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
  136. unsigned int off, samsung_gpio_pull_t pull)
  137. {
  138. return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
  139. }
  140. static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
  141. unsigned int off, samsung_gpio_pull_t pull)
  142. {
  143. if (pull == S3C_GPIO_PULL_UP)
  144. pull = 3;
  145. return samsung_gpio_setpull_updown(chip, off, pull);
  146. }
  147. static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
  148. unsigned int off)
  149. {
  150. samsung_gpio_pull_t pull;
  151. pull = samsung_gpio_getpull_updown(chip, off);
  152. if (pull == 3)
  153. pull = S3C_GPIO_PULL_UP;
  154. return pull;
  155. }
  156. /*
  157. * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
  158. * @chip: The gpio chip that is being configured.
  159. * @off: The offset for the GPIO being configured.
  160. * @cfg: The configuration value to set.
  161. *
  162. * This helper deal with the GPIO cases where the control register
  163. * has two bits of configuration per gpio, which have the following
  164. * functions:
  165. * 00 = input
  166. * 01 = output
  167. * 1x = special function
  168. */
  169. static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
  170. unsigned int off, unsigned int cfg)
  171. {
  172. void __iomem *reg = chip->base;
  173. unsigned int shift = off * 2;
  174. u32 con;
  175. if (samsung_gpio_is_cfg_special(cfg)) {
  176. cfg &= 0xf;
  177. if (cfg > 3)
  178. return -EINVAL;
  179. cfg <<= shift;
  180. }
  181. con = __raw_readl(reg);
  182. con &= ~(0x3 << shift);
  183. con |= cfg;
  184. __raw_writel(con, reg);
  185. return 0;
  186. }
  187. /*
  188. * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
  189. * @chip: The gpio chip that is being configured.
  190. * @off: The offset for the GPIO being configured.
  191. *
  192. * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
  193. * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
  194. * S3C_GPIO_SPECIAL() macro.
  195. */
  196. static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
  197. unsigned int off)
  198. {
  199. u32 con;
  200. con = __raw_readl(chip->base);
  201. con >>= off * 2;
  202. con &= 3;
  203. /* this conversion works for IN and OUT as well as special mode */
  204. return S3C_GPIO_SPECIAL(con);
  205. }
  206. /*
  207. * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
  208. * @chip: The gpio chip that is being configured.
  209. * @off: The offset for the GPIO being configured.
  210. * @cfg: The configuration value to set.
  211. *
  212. * This helper deal with the GPIO cases where the control register has 4 bits
  213. * of control per GPIO, generally in the form of:
  214. * 0000 = Input
  215. * 0001 = Output
  216. * others = Special functions (dependent on bank)
  217. *
  218. * Note, since the code to deal with the case where there are two control
  219. * registers instead of one, we do not have a separate set of functions for
  220. * each case.
  221. */
  222. static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
  223. unsigned int off, unsigned int cfg)
  224. {
  225. void __iomem *reg = chip->base;
  226. unsigned int shift = (off & 7) * 4;
  227. u32 con;
  228. if (off < 8 && chip->chip.ngpio > 8)
  229. reg -= 4;
  230. if (samsung_gpio_is_cfg_special(cfg)) {
  231. cfg &= 0xf;
  232. cfg <<= shift;
  233. }
  234. con = __raw_readl(reg);
  235. con &= ~(0xf << shift);
  236. con |= cfg;
  237. __raw_writel(con, reg);
  238. return 0;
  239. }
  240. /*
  241. * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
  242. * @chip: The gpio chip that is being configured.
  243. * @off: The offset for the GPIO being configured.
  244. *
  245. * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
  246. * register setting into a value the software can use, such as could be passed
  247. * to samsung_gpio_setcfg_4bit().
  248. *
  249. * @sa samsung_gpio_getcfg_2bit
  250. */
  251. static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
  252. unsigned int off)
  253. {
  254. void __iomem *reg = chip->base;
  255. unsigned int shift = (off & 7) * 4;
  256. u32 con;
  257. if (off < 8 && chip->chip.ngpio > 8)
  258. reg -= 4;
  259. con = __raw_readl(reg);
  260. con >>= shift;
  261. con &= 0xf;
  262. /* this conversion works for IN and OUT as well as special mode */
  263. return S3C_GPIO_SPECIAL(con);
  264. }
  265. #ifdef CONFIG_PLAT_S3C24XX
  266. /*
  267. * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
  268. * @chip: The gpio chip that is being configured.
  269. * @off: The offset for the GPIO being configured.
  270. * @cfg: The configuration value to set.
  271. *
  272. * This helper deal with the GPIO cases where the control register
  273. * has one bit of configuration for the gpio, where setting the bit
  274. * means the pin is in special function mode and unset means output.
  275. */
  276. static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
  277. unsigned int off, unsigned int cfg)
  278. {
  279. void __iomem *reg = chip->base;
  280. unsigned int shift = off;
  281. u32 con;
  282. if (samsung_gpio_is_cfg_special(cfg)) {
  283. cfg &= 0xf;
  284. /* Map output to 0, and SFN2 to 1 */
  285. cfg -= 1;
  286. if (cfg > 1)
  287. return -EINVAL;
  288. cfg <<= shift;
  289. }
  290. con = __raw_readl(reg);
  291. con &= ~(0x1 << shift);
  292. con |= cfg;
  293. __raw_writel(con, reg);
  294. return 0;
  295. }
  296. /*
  297. * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
  298. * @chip: The gpio chip that is being configured.
  299. * @off: The offset for the GPIO being configured.
  300. *
  301. * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
  302. * GPIO configuration value.
  303. *
  304. * @sa samsung_gpio_getcfg_2bit
  305. * @sa samsung_gpio_getcfg_4bit
  306. */
  307. static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
  308. unsigned int off)
  309. {
  310. u32 con;
  311. con = __raw_readl(chip->base);
  312. con >>= off;
  313. con &= 1;
  314. con++;
  315. return S3C_GPIO_SFN(con);
  316. }
  317. #endif
  318. #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
  319. static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
  320. unsigned int off, unsigned int cfg)
  321. {
  322. void __iomem *reg = chip->base;
  323. unsigned int shift;
  324. u32 con;
  325. switch (off) {
  326. case 0:
  327. case 1:
  328. case 2:
  329. case 3:
  330. case 4:
  331. case 5:
  332. shift = (off & 7) * 4;
  333. reg -= 4;
  334. break;
  335. case 6:
  336. shift = ((off + 1) & 7) * 4;
  337. reg -= 4;
  338. default:
  339. shift = ((off + 1) & 7) * 4;
  340. break;
  341. }
  342. if (samsung_gpio_is_cfg_special(cfg)) {
  343. cfg &= 0xf;
  344. cfg <<= shift;
  345. }
  346. con = __raw_readl(reg);
  347. con &= ~(0xf << shift);
  348. con |= cfg;
  349. __raw_writel(con, reg);
  350. return 0;
  351. }
  352. #endif
  353. static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
  354. int nr_chips)
  355. {
  356. for (; nr_chips > 0; nr_chips--, chipcfg++) {
  357. if (!chipcfg->set_config)
  358. chipcfg->set_config = samsung_gpio_setcfg_4bit;
  359. if (!chipcfg->get_config)
  360. chipcfg->get_config = samsung_gpio_getcfg_4bit;
  361. if (!chipcfg->set_pull)
  362. chipcfg->set_pull = samsung_gpio_setpull_updown;
  363. if (!chipcfg->get_pull)
  364. chipcfg->get_pull = samsung_gpio_getpull_updown;
  365. }
  366. }
  367. struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
  368. .set_config = samsung_gpio_setcfg_2bit,
  369. .get_config = samsung_gpio_getcfg_2bit,
  370. };
  371. #ifdef CONFIG_PLAT_S3C24XX
  372. static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
  373. .set_config = s3c24xx_gpio_setcfg_abank,
  374. .get_config = s3c24xx_gpio_getcfg_abank,
  375. };
  376. #endif
  377. #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
  378. static struct samsung_gpio_cfg exynos_gpio_cfg = {
  379. .set_pull = exynos_gpio_setpull,
  380. .get_pull = exynos_gpio_getpull,
  381. .set_config = samsung_gpio_setcfg_4bit,
  382. .get_config = samsung_gpio_getcfg_4bit,
  383. };
  384. #endif
  385. #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
  386. static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
  387. .cfg_eint = 0x3,
  388. .set_config = s5p64x0_gpio_setcfg_rbank,
  389. .get_config = samsung_gpio_getcfg_4bit,
  390. .set_pull = samsung_gpio_setpull_updown,
  391. .get_pull = samsung_gpio_getpull_updown,
  392. };
  393. #endif
  394. static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
  395. [0] = {
  396. .cfg_eint = 0x0,
  397. },
  398. [1] = {
  399. .cfg_eint = 0x3,
  400. },
  401. [2] = {
  402. .cfg_eint = 0x7,
  403. },
  404. [3] = {
  405. .cfg_eint = 0xF,
  406. },
  407. [4] = {
  408. .cfg_eint = 0x0,
  409. .set_config = samsung_gpio_setcfg_2bit,
  410. .get_config = samsung_gpio_getcfg_2bit,
  411. },
  412. [5] = {
  413. .cfg_eint = 0x2,
  414. .set_config = samsung_gpio_setcfg_2bit,
  415. .get_config = samsung_gpio_getcfg_2bit,
  416. },
  417. [6] = {
  418. .cfg_eint = 0x3,
  419. .set_config = samsung_gpio_setcfg_2bit,
  420. .get_config = samsung_gpio_getcfg_2bit,
  421. },
  422. [7] = {
  423. .set_config = samsung_gpio_setcfg_2bit,
  424. .get_config = samsung_gpio_getcfg_2bit,
  425. },
  426. [8] = {
  427. .set_pull = exynos_gpio_setpull,
  428. .get_pull = exynos_gpio_getpull,
  429. },
  430. [9] = {
  431. .cfg_eint = 0x3,
  432. .set_pull = exynos_gpio_setpull,
  433. .get_pull = exynos_gpio_getpull,
  434. }
  435. };
  436. /*
  437. * Default routines for controlling GPIO, based on the original S3C24XX
  438. * GPIO functions which deal with the case where each gpio bank of the
  439. * chip is as following:
  440. *
  441. * base + 0x00: Control register, 2 bits per gpio
  442. * gpio n: 2 bits starting at (2*n)
  443. * 00 = input, 01 = output, others mean special-function
  444. * base + 0x04: Data register, 1 bit per gpio
  445. * bit n: data bit n
  446. */
  447. static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
  448. {
  449. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  450. void __iomem *base = ourchip->base;
  451. unsigned long flags;
  452. unsigned long con;
  453. samsung_gpio_lock(ourchip, flags);
  454. con = __raw_readl(base + 0x00);
  455. con &= ~(3 << (offset * 2));
  456. __raw_writel(con, base + 0x00);
  457. samsung_gpio_unlock(ourchip, flags);
  458. return 0;
  459. }
  460. static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
  461. unsigned offset, int value)
  462. {
  463. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  464. void __iomem *base = ourchip->base;
  465. unsigned long flags;
  466. unsigned long dat;
  467. unsigned long con;
  468. samsung_gpio_lock(ourchip, flags);
  469. dat = __raw_readl(base + 0x04);
  470. dat &= ~(1 << offset);
  471. if (value)
  472. dat |= 1 << offset;
  473. __raw_writel(dat, base + 0x04);
  474. con = __raw_readl(base + 0x00);
  475. con &= ~(3 << (offset * 2));
  476. con |= 1 << (offset * 2);
  477. __raw_writel(con, base + 0x00);
  478. __raw_writel(dat, base + 0x04);
  479. samsung_gpio_unlock(ourchip, flags);
  480. return 0;
  481. }
  482. /*
  483. * The samsung_gpiolib_4bit routines are to control the gpio banks where
  484. * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
  485. * following example:
  486. *
  487. * base + 0x00: Control register, 4 bits per gpio
  488. * gpio n: 4 bits starting at (4*n)
  489. * 0000 = input, 0001 = output, others mean special-function
  490. * base + 0x04: Data register, 1 bit per gpio
  491. * bit n: data bit n
  492. *
  493. * Note, since the data register is one bit per gpio and is at base + 0x4
  494. * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
  495. * state of the output.
  496. */
  497. static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
  498. unsigned int offset)
  499. {
  500. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  501. void __iomem *base = ourchip->base;
  502. unsigned long con;
  503. con = __raw_readl(base + GPIOCON_OFF);
  504. if (ourchip->bitmap_gpio_int & BIT(offset))
  505. con |= 0xf << con_4bit_shift(offset);
  506. else
  507. con &= ~(0xf << con_4bit_shift(offset));
  508. __raw_writel(con, base + GPIOCON_OFF);
  509. pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
  510. return 0;
  511. }
  512. static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
  513. unsigned int offset, int value)
  514. {
  515. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  516. void __iomem *base = ourchip->base;
  517. unsigned long con;
  518. unsigned long dat;
  519. con = __raw_readl(base + GPIOCON_OFF);
  520. con &= ~(0xf << con_4bit_shift(offset));
  521. con |= 0x1 << con_4bit_shift(offset);
  522. dat = __raw_readl(base + GPIODAT_OFF);
  523. if (value)
  524. dat |= 1 << offset;
  525. else
  526. dat &= ~(1 << offset);
  527. __raw_writel(dat, base + GPIODAT_OFF);
  528. __raw_writel(con, base + GPIOCON_OFF);
  529. __raw_writel(dat, base + GPIODAT_OFF);
  530. pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
  531. return 0;
  532. }
  533. /*
  534. * The next set of routines are for the case where the GPIO configuration
  535. * registers are 4 bits per GPIO but there is more than one register (the
  536. * bank has more than 8 GPIOs.
  537. *
  538. * This case is the similar to the 4 bit case, but the registers are as
  539. * follows:
  540. *
  541. * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
  542. * gpio n: 4 bits starting at (4*n)
  543. * 0000 = input, 0001 = output, others mean special-function
  544. * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
  545. * gpio n: 4 bits starting at (4*n)
  546. * 0000 = input, 0001 = output, others mean special-function
  547. * base + 0x08: Data register, 1 bit per gpio
  548. * bit n: data bit n
  549. *
  550. * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
  551. * routines we store the 'base + 0x4' address so that these routines see
  552. * the data register at ourchip->base + 0x04.
  553. */
  554. static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
  555. unsigned int offset)
  556. {
  557. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  558. void __iomem *base = ourchip->base;
  559. void __iomem *regcon = base;
  560. unsigned long con;
  561. if (offset > 7)
  562. offset -= 8;
  563. else
  564. regcon -= 4;
  565. con = __raw_readl(regcon);
  566. con &= ~(0xf << con_4bit_shift(offset));
  567. __raw_writel(con, regcon);
  568. pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
  569. return 0;
  570. }
  571. static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
  572. unsigned int offset, int value)
  573. {
  574. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  575. void __iomem *base = ourchip->base;
  576. void __iomem *regcon = base;
  577. unsigned long con;
  578. unsigned long dat;
  579. unsigned con_offset = offset;
  580. if (con_offset > 7)
  581. con_offset -= 8;
  582. else
  583. regcon -= 4;
  584. con = __raw_readl(regcon);
  585. con &= ~(0xf << con_4bit_shift(con_offset));
  586. con |= 0x1 << con_4bit_shift(con_offset);
  587. dat = __raw_readl(base + GPIODAT_OFF);
  588. if (value)
  589. dat |= 1 << offset;
  590. else
  591. dat &= ~(1 << offset);
  592. __raw_writel(dat, base + GPIODAT_OFF);
  593. __raw_writel(con, regcon);
  594. __raw_writel(dat, base + GPIODAT_OFF);
  595. pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
  596. return 0;
  597. }
  598. #ifdef CONFIG_PLAT_S3C24XX
  599. /* The next set of routines are for the case of s3c24xx bank a */
  600. static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
  601. {
  602. return -EINVAL;
  603. }
  604. static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
  605. unsigned offset, int value)
  606. {
  607. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  608. void __iomem *base = ourchip->base;
  609. unsigned long flags;
  610. unsigned long dat;
  611. unsigned long con;
  612. local_irq_save(flags);
  613. con = __raw_readl(base + 0x00);
  614. dat = __raw_readl(base + 0x04);
  615. dat &= ~(1 << offset);
  616. if (value)
  617. dat |= 1 << offset;
  618. __raw_writel(dat, base + 0x04);
  619. con &= ~(1 << offset);
  620. __raw_writel(con, base + 0x00);
  621. __raw_writel(dat, base + 0x04);
  622. local_irq_restore(flags);
  623. return 0;
  624. }
  625. #endif
  626. /* The next set of routines are for the case of s5p64x0 bank r */
  627. static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
  628. unsigned int offset)
  629. {
  630. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  631. void __iomem *base = ourchip->base;
  632. void __iomem *regcon = base;
  633. unsigned long con;
  634. unsigned long flags;
  635. switch (offset) {
  636. case 6:
  637. offset += 1;
  638. case 0:
  639. case 1:
  640. case 2:
  641. case 3:
  642. case 4:
  643. case 5:
  644. regcon -= 4;
  645. break;
  646. default:
  647. offset -= 7;
  648. break;
  649. }
  650. samsung_gpio_lock(ourchip, flags);
  651. con = __raw_readl(regcon);
  652. con &= ~(0xf << con_4bit_shift(offset));
  653. __raw_writel(con, regcon);
  654. samsung_gpio_unlock(ourchip, flags);
  655. return 0;
  656. }
  657. static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
  658. unsigned int offset, int value)
  659. {
  660. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  661. void __iomem *base = ourchip->base;
  662. void __iomem *regcon = base;
  663. unsigned long con;
  664. unsigned long dat;
  665. unsigned long flags;
  666. unsigned con_offset = offset;
  667. switch (con_offset) {
  668. case 6:
  669. con_offset += 1;
  670. case 0:
  671. case 1:
  672. case 2:
  673. case 3:
  674. case 4:
  675. case 5:
  676. regcon -= 4;
  677. break;
  678. default:
  679. con_offset -= 7;
  680. break;
  681. }
  682. samsung_gpio_lock(ourchip, flags);
  683. con = __raw_readl(regcon);
  684. con &= ~(0xf << con_4bit_shift(con_offset));
  685. con |= 0x1 << con_4bit_shift(con_offset);
  686. dat = __raw_readl(base + GPIODAT_OFF);
  687. if (value)
  688. dat |= 1 << offset;
  689. else
  690. dat &= ~(1 << offset);
  691. __raw_writel(con, regcon);
  692. __raw_writel(dat, base + GPIODAT_OFF);
  693. samsung_gpio_unlock(ourchip, flags);
  694. return 0;
  695. }
  696. static void samsung_gpiolib_set(struct gpio_chip *chip,
  697. unsigned offset, int value)
  698. {
  699. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  700. void __iomem *base = ourchip->base;
  701. unsigned long flags;
  702. unsigned long dat;
  703. samsung_gpio_lock(ourchip, flags);
  704. dat = __raw_readl(base + 0x04);
  705. dat &= ~(1 << offset);
  706. if (value)
  707. dat |= 1 << offset;
  708. __raw_writel(dat, base + 0x04);
  709. samsung_gpio_unlock(ourchip, flags);
  710. }
  711. static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
  712. {
  713. struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
  714. unsigned long val;
  715. val = __raw_readl(ourchip->base + 0x04);
  716. val >>= offset;
  717. val &= 1;
  718. return val;
  719. }
  720. /*
  721. * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
  722. * for use with the configuration calls, and other parts of the s3c gpiolib
  723. * support code.
  724. *
  725. * Not all s3c support code will need this, as some configurations of cpu
  726. * may only support one or two different configuration options and have an
  727. * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
  728. * the machine support file should provide its own samsung_gpiolib_getchip()
  729. * and any other necessary functions.
  730. */
  731. #ifdef CONFIG_S3C_GPIO_TRACK
  732. struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
  733. static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
  734. {
  735. unsigned int gpn;
  736. int i;
  737. gpn = chip->chip.base;
  738. for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
  739. BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
  740. s3c_gpios[gpn] = chip;
  741. }
  742. }
  743. #endif /* CONFIG_S3C_GPIO_TRACK */
  744. /*
  745. * samsung_gpiolib_add() - add the Samsung gpio_chip.
  746. * @chip: The chip to register
  747. *
  748. * This is a wrapper to gpiochip_add() that takes our specific gpio chip
  749. * information and makes the necessary alterations for the platform and
  750. * notes the information for use with the configuration systems and any
  751. * other parts of the system.
  752. */
  753. static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
  754. {
  755. struct gpio_chip *gc = &chip->chip;
  756. int ret;
  757. BUG_ON(!chip->base);
  758. BUG_ON(!gc->label);
  759. BUG_ON(!gc->ngpio);
  760. spin_lock_init(&chip->lock);
  761. if (!gc->direction_input)
  762. gc->direction_input = samsung_gpiolib_2bit_input;
  763. if (!gc->direction_output)
  764. gc->direction_output = samsung_gpiolib_2bit_output;
  765. if (!gc->set)
  766. gc->set = samsung_gpiolib_set;
  767. if (!gc->get)
  768. gc->get = samsung_gpiolib_get;
  769. #ifdef CONFIG_PM
  770. if (chip->pm != NULL) {
  771. if (!chip->pm->save || !chip->pm->resume)
  772. pr_err("gpio: %s has missing PM functions\n",
  773. gc->label);
  774. } else
  775. pr_err("gpio: %s has no PM function\n", gc->label);
  776. #endif
  777. /* gpiochip_add() prints own failure message on error. */
  778. ret = gpiochip_add(gc);
  779. if (ret >= 0)
  780. s3c_gpiolib_track(chip);
  781. }
  782. #if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
  783. static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
  784. const struct of_phandle_args *gpiospec, u32 *flags)
  785. {
  786. unsigned int pin;
  787. if (WARN_ON(gc->of_gpio_n_cells < 3))
  788. return -EINVAL;
  789. if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
  790. return -EINVAL;
  791. if (gpiospec->args[0] > gc->ngpio)
  792. return -EINVAL;
  793. pin = gc->base + gpiospec->args[0];
  794. if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
  795. pr_warn("gpio_xlate: failed to set pin function\n");
  796. if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
  797. pr_warn("gpio_xlate: failed to set pin pull up/down\n");
  798. if (flags)
  799. *flags = gpiospec->args[2] >> 16;
  800. return gpiospec->args[0];
  801. }
  802. static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
  803. { .compatible = "samsung,s3c24xx-gpio", },
  804. {}
  805. };
  806. static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
  807. u64 base, u64 offset)
  808. {
  809. struct gpio_chip *gc = &chip->chip;
  810. u64 address;
  811. if (!of_have_populated_dt())
  812. return;
  813. address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
  814. gc->of_node = of_find_matching_node_by_address(NULL,
  815. s3c24xx_gpio_dt_match, address);
  816. if (!gc->of_node) {
  817. pr_info("gpio: device tree node not found for gpio controller"
  818. " with base address %08llx\n", address);
  819. return;
  820. }
  821. gc->of_gpio_n_cells = 3;
  822. gc->of_xlate = s3c24xx_gpio_xlate;
  823. }
  824. #else
  825. static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
  826. u64 base, u64 offset)
  827. {
  828. return;
  829. }
  830. #endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
  831. static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
  832. int nr_chips, void __iomem *base)
  833. {
  834. int i;
  835. struct gpio_chip *gc = &chip->chip;
  836. for (i = 0 ; i < nr_chips; i++, chip++) {
  837. /* skip banks not present on SoC */
  838. if (chip->chip.base >= S3C_GPIO_END)
  839. continue;
  840. if (!chip->config)
  841. chip->config = &s3c24xx_gpiocfg_default;
  842. if (!chip->pm)
  843. chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
  844. if ((base != NULL) && (chip->base == NULL))
  845. chip->base = base + ((i) * 0x10);
  846. if (!gc->direction_input)
  847. gc->direction_input = samsung_gpiolib_2bit_input;
  848. if (!gc->direction_output)
  849. gc->direction_output = samsung_gpiolib_2bit_output;
  850. samsung_gpiolib_add(chip);
  851. s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
  852. }
  853. }
  854. static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
  855. int nr_chips, void __iomem *base,
  856. unsigned int offset)
  857. {
  858. int i;
  859. for (i = 0 ; i < nr_chips; i++, chip++) {
  860. chip->chip.direction_input = samsung_gpiolib_2bit_input;
  861. chip->chip.direction_output = samsung_gpiolib_2bit_output;
  862. if (!chip->config)
  863. chip->config = &samsung_gpio_cfgs[7];
  864. if (!chip->pm)
  865. chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
  866. if ((base != NULL) && (chip->base == NULL))
  867. chip->base = base + ((i) * offset);
  868. samsung_gpiolib_add(chip);
  869. }
  870. }
  871. /*
  872. * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
  873. * @chip: The gpio chip that is being configured.
  874. * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
  875. *
  876. * This helper deal with the GPIO cases where the control register has 4 bits
  877. * of control per GPIO, generally in the form of:
  878. * 0000 = Input
  879. * 0001 = Output
  880. * others = Special functions (dependent on bank)
  881. *
  882. * Note, since the code to deal with the case where there are two control
  883. * registers instead of one, we do not have a separate set of function
  884. * (samsung_gpiolib_add_4bit2_chips)for each case.
  885. */
  886. static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
  887. int nr_chips, void __iomem *base)
  888. {
  889. int i;
  890. for (i = 0 ; i < nr_chips; i++, chip++) {
  891. chip->chip.direction_input = samsung_gpiolib_4bit_input;
  892. chip->chip.direction_output = samsung_gpiolib_4bit_output;
  893. if (!chip->config)
  894. chip->config = &samsung_gpio_cfgs[2];
  895. if (!chip->pm)
  896. chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
  897. if ((base != NULL) && (chip->base == NULL))
  898. chip->base = base + ((i) * 0x20);
  899. chip->bitmap_gpio_int = 0;
  900. samsung_gpiolib_add(chip);
  901. }
  902. }
  903. static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
  904. int nr_chips)
  905. {
  906. for (; nr_chips > 0; nr_chips--, chip++) {
  907. chip->chip.direction_input = samsung_gpiolib_4bit2_input;
  908. chip->chip.direction_output = samsung_gpiolib_4bit2_output;
  909. if (!chip->config)
  910. chip->config = &samsung_gpio_cfgs[2];
  911. if (!chip->pm)
  912. chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
  913. samsung_gpiolib_add(chip);
  914. }
  915. }
  916. static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
  917. int nr_chips)
  918. {
  919. for (; nr_chips > 0; nr_chips--, chip++) {
  920. chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
  921. chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
  922. if (!chip->pm)
  923. chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
  924. samsung_gpiolib_add(chip);
  925. }
  926. }
  927. int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
  928. {
  929. struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
  930. return samsung_chip->irq_base + offset;
  931. }
  932. #ifdef CONFIG_PLAT_S3C24XX
  933. static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
  934. {
  935. if (offset < 4)
  936. return IRQ_EINT0 + offset;
  937. if (offset < 8)
  938. return IRQ_EINT4 + offset - 4;
  939. return -EINVAL;
  940. }
  941. #endif
  942. #ifdef CONFIG_PLAT_S3C64XX
  943. static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
  944. {
  945. return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
  946. }
  947. static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
  948. {
  949. return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
  950. }
  951. #endif
  952. struct samsung_gpio_chip s3c24xx_gpios[] = {
  953. #ifdef CONFIG_PLAT_S3C24XX
  954. {
  955. .config = &s3c24xx_gpiocfg_banka,
  956. .chip = {
  957. .base = S3C2410_GPA(0),
  958. .owner = THIS_MODULE,
  959. .label = "GPIOA",
  960. .ngpio = 24,
  961. .direction_input = s3c24xx_gpiolib_banka_input,
  962. .direction_output = s3c24xx_gpiolib_banka_output,
  963. },
  964. }, {
  965. .chip = {
  966. .base = S3C2410_GPB(0),
  967. .owner = THIS_MODULE,
  968. .label = "GPIOB",
  969. .ngpio = 16,
  970. },
  971. }, {
  972. .chip = {
  973. .base = S3C2410_GPC(0),
  974. .owner = THIS_MODULE,
  975. .label = "GPIOC",
  976. .ngpio = 16,
  977. },
  978. }, {
  979. .chip = {
  980. .base = S3C2410_GPD(0),
  981. .owner = THIS_MODULE,
  982. .label = "GPIOD",
  983. .ngpio = 16,
  984. },
  985. }, {
  986. .chip = {
  987. .base = S3C2410_GPE(0),
  988. .label = "GPIOE",
  989. .owner = THIS_MODULE,
  990. .ngpio = 16,
  991. },
  992. }, {
  993. .chip = {
  994. .base = S3C2410_GPF(0),
  995. .owner = THIS_MODULE,
  996. .label = "GPIOF",
  997. .ngpio = 8,
  998. .to_irq = s3c24xx_gpiolib_fbank_to_irq,
  999. },
  1000. }, {
  1001. .irq_base = IRQ_EINT8,
  1002. .chip = {
  1003. .base = S3C2410_GPG(0),
  1004. .owner = THIS_MODULE,
  1005. .label = "GPIOG",
  1006. .ngpio = 16,
  1007. .to_irq = samsung_gpiolib_to_irq,
  1008. },
  1009. }, {
  1010. .chip = {
  1011. .base = S3C2410_GPH(0),
  1012. .owner = THIS_MODULE,
  1013. .label = "GPIOH",
  1014. .ngpio = 11,
  1015. },
  1016. },
  1017. /* GPIOS for the S3C2443 and later devices. */
  1018. {
  1019. .base = S3C2440_GPJCON,
  1020. .chip = {
  1021. .base = S3C2410_GPJ(0),
  1022. .owner = THIS_MODULE,
  1023. .label = "GPIOJ",
  1024. .ngpio = 16,
  1025. },
  1026. }, {
  1027. .base = S3C2443_GPKCON,
  1028. .chip = {
  1029. .base = S3C2410_GPK(0),
  1030. .owner = THIS_MODULE,
  1031. .label = "GPIOK",
  1032. .ngpio = 16,
  1033. },
  1034. }, {
  1035. .base = S3C2443_GPLCON,
  1036. .chip = {
  1037. .base = S3C2410_GPL(0),
  1038. .owner = THIS_MODULE,
  1039. .label = "GPIOL",
  1040. .ngpio = 15,
  1041. },
  1042. }, {
  1043. .base = S3C2443_GPMCON,
  1044. .chip = {
  1045. .base = S3C2410_GPM(0),
  1046. .owner = THIS_MODULE,
  1047. .label = "GPIOM",
  1048. .ngpio = 2,
  1049. },
  1050. },
  1051. #endif
  1052. };
  1053. /*
  1054. * GPIO bank summary:
  1055. *
  1056. * Bank GPIOs Style SlpCon ExtInt Group
  1057. * A 8 4Bit Yes 1
  1058. * B 7 4Bit Yes 1
  1059. * C 8 4Bit Yes 2
  1060. * D 5 4Bit Yes 3
  1061. * E 5 4Bit Yes None
  1062. * F 16 2Bit Yes 4 [1]
  1063. * G 7 4Bit Yes 5
  1064. * H 10 4Bit[2] Yes 6
  1065. * I 16 2Bit Yes None
  1066. * J 12 2Bit Yes None
  1067. * K 16 4Bit[2] No None
  1068. * L 15 4Bit[2] No None
  1069. * M 6 4Bit No IRQ_EINT
  1070. * N 16 2Bit No IRQ_EINT
  1071. * O 16 2Bit Yes 7
  1072. * P 15 2Bit Yes 8
  1073. * Q 9 2Bit Yes 9
  1074. *
  1075. * [1] BANKF pins 14,15 do not form part of the external interrupt sources
  1076. * [2] BANK has two control registers, GPxCON0 and GPxCON1
  1077. */
  1078. static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
  1079. #ifdef CONFIG_PLAT_S3C64XX
  1080. {
  1081. .chip = {
  1082. .base = S3C64XX_GPA(0),
  1083. .ngpio = S3C64XX_GPIO_A_NR,
  1084. .label = "GPA",
  1085. },
  1086. }, {
  1087. .chip = {
  1088. .base = S3C64XX_GPB(0),
  1089. .ngpio = S3C64XX_GPIO_B_NR,
  1090. .label = "GPB",
  1091. },
  1092. }, {
  1093. .chip = {
  1094. .base = S3C64XX_GPC(0),
  1095. .ngpio = S3C64XX_GPIO_C_NR,
  1096. .label = "GPC",
  1097. },
  1098. }, {
  1099. .chip = {
  1100. .base = S3C64XX_GPD(0),
  1101. .ngpio = S3C64XX_GPIO_D_NR,
  1102. .label = "GPD",
  1103. },
  1104. }, {
  1105. .config = &samsung_gpio_cfgs[0],
  1106. .chip = {
  1107. .base = S3C64XX_GPE(0),
  1108. .ngpio = S3C64XX_GPIO_E_NR,
  1109. .label = "GPE",
  1110. },
  1111. }, {
  1112. .base = S3C64XX_GPG_BASE,
  1113. .chip = {
  1114. .base = S3C64XX_GPG(0),
  1115. .ngpio = S3C64XX_GPIO_G_NR,
  1116. .label = "GPG",
  1117. },
  1118. }, {
  1119. .base = S3C64XX_GPM_BASE,
  1120. .config = &samsung_gpio_cfgs[1],
  1121. .chip = {
  1122. .base = S3C64XX_GPM(0),
  1123. .ngpio = S3C64XX_GPIO_M_NR,
  1124. .label = "GPM",
  1125. .to_irq = s3c64xx_gpiolib_mbank_to_irq,
  1126. },
  1127. },
  1128. #endif
  1129. };
  1130. static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
  1131. #ifdef CONFIG_PLAT_S3C64XX
  1132. {
  1133. .base = S3C64XX_GPH_BASE + 0x4,
  1134. .chip = {
  1135. .base = S3C64XX_GPH(0),
  1136. .ngpio = S3C64XX_GPIO_H_NR,
  1137. .label = "GPH",
  1138. },
  1139. }, {
  1140. .base = S3C64XX_GPK_BASE + 0x4,
  1141. .config = &samsung_gpio_cfgs[0],
  1142. .chip = {
  1143. .base = S3C64XX_GPK(0),
  1144. .ngpio = S3C64XX_GPIO_K_NR,
  1145. .label = "GPK",
  1146. },
  1147. }, {
  1148. .base = S3C64XX_GPL_BASE + 0x4,
  1149. .config = &samsung_gpio_cfgs[1],
  1150. .chip = {
  1151. .base = S3C64XX_GPL(0),
  1152. .ngpio = S3C64XX_GPIO_L_NR,
  1153. .label = "GPL",
  1154. .to_irq = s3c64xx_gpiolib_lbank_to_irq,
  1155. },
  1156. },
  1157. #endif
  1158. };
  1159. static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
  1160. #ifdef CONFIG_PLAT_S3C64XX
  1161. {
  1162. .base = S3C64XX_GPF_BASE,
  1163. .config = &samsung_gpio_cfgs[6],
  1164. .chip = {
  1165. .base = S3C64XX_GPF(0),
  1166. .ngpio = S3C64XX_GPIO_F_NR,
  1167. .label = "GPF",
  1168. },
  1169. }, {
  1170. .config = &samsung_gpio_cfgs[7],
  1171. .chip = {
  1172. .base = S3C64XX_GPI(0),
  1173. .ngpio = S3C64XX_GPIO_I_NR,
  1174. .label = "GPI",
  1175. },
  1176. }, {
  1177. .config = &samsung_gpio_cfgs[7],
  1178. .chip = {
  1179. .base = S3C64XX_GPJ(0),
  1180. .ngpio = S3C64XX_GPIO_J_NR,
  1181. .label = "GPJ",
  1182. },
  1183. }, {
  1184. .config = &samsung_gpio_cfgs[6],
  1185. .chip = {
  1186. .base = S3C64XX_GPO(0),
  1187. .ngpio = S3C64XX_GPIO_O_NR,
  1188. .label = "GPO",
  1189. },
  1190. }, {
  1191. .config = &samsung_gpio_cfgs[6],
  1192. .chip = {
  1193. .base = S3C64XX_GPP(0),
  1194. .ngpio = S3C64XX_GPIO_P_NR,
  1195. .label = "GPP",
  1196. },
  1197. }, {
  1198. .config = &samsung_gpio_cfgs[6],
  1199. .chip = {
  1200. .base = S3C64XX_GPQ(0),
  1201. .ngpio = S3C64XX_GPIO_Q_NR,
  1202. .label = "GPQ",
  1203. },
  1204. }, {
  1205. .base = S3C64XX_GPN_BASE,
  1206. .irq_base = IRQ_EINT(0),
  1207. .config = &samsung_gpio_cfgs[5],
  1208. .chip = {
  1209. .base = S3C64XX_GPN(0),
  1210. .ngpio = S3C64XX_GPIO_N_NR,
  1211. .label = "GPN",
  1212. .to_irq = samsung_gpiolib_to_irq,
  1213. },
  1214. },
  1215. #endif
  1216. };
  1217. /*
  1218. * S5P6440 GPIO bank summary:
  1219. *
  1220. * Bank GPIOs Style SlpCon ExtInt Group
  1221. * A 6 4Bit Yes 1
  1222. * B 7 4Bit Yes 1
  1223. * C 8 4Bit Yes 2
  1224. * F 2 2Bit Yes 4 [1]
  1225. * G 7 4Bit Yes 5
  1226. * H 10 4Bit[2] Yes 6
  1227. * I 16 2Bit Yes None
  1228. * J 12 2Bit Yes None
  1229. * N 16 2Bit No IRQ_EINT
  1230. * P 8 2Bit Yes 8
  1231. * R 15 4Bit[2] Yes 8
  1232. */
  1233. static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
  1234. #ifdef CONFIG_CPU_S5P6440
  1235. {
  1236. .chip = {
  1237. .base = S5P6440_GPA(0),
  1238. .ngpio = S5P6440_GPIO_A_NR,
  1239. .label = "GPA",
  1240. },
  1241. }, {
  1242. .chip = {
  1243. .base = S5P6440_GPB(0),
  1244. .ngpio = S5P6440_GPIO_B_NR,
  1245. .label = "GPB",
  1246. },
  1247. }, {
  1248. .chip = {
  1249. .base = S5P6440_GPC(0),
  1250. .ngpio = S5P6440_GPIO_C_NR,
  1251. .label = "GPC",
  1252. },
  1253. }, {
  1254. .base = S5P64X0_GPG_BASE,
  1255. .chip = {
  1256. .base = S5P6440_GPG(0),
  1257. .ngpio = S5P6440_GPIO_G_NR,
  1258. .label = "GPG",
  1259. },
  1260. },
  1261. #endif
  1262. };
  1263. static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
  1264. #ifdef CONFIG_CPU_S5P6440
  1265. {
  1266. .base = S5P64X0_GPH_BASE + 0x4,
  1267. .chip = {
  1268. .base = S5P6440_GPH(0),
  1269. .ngpio = S5P6440_GPIO_H_NR,
  1270. .label = "GPH",
  1271. },
  1272. },
  1273. #endif
  1274. };
  1275. static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
  1276. #ifdef CONFIG_CPU_S5P6440
  1277. {
  1278. .base = S5P64X0_GPR_BASE + 0x4,
  1279. .config = &s5p64x0_gpio_cfg_rbank,
  1280. .chip = {
  1281. .base = S5P6440_GPR(0),
  1282. .ngpio = S5P6440_GPIO_R_NR,
  1283. .label = "GPR",
  1284. },
  1285. },
  1286. #endif
  1287. };
  1288. static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
  1289. #ifdef CONFIG_CPU_S5P6440
  1290. {
  1291. .base = S5P64X0_GPF_BASE,
  1292. .config = &samsung_gpio_cfgs[6],
  1293. .chip = {
  1294. .base = S5P6440_GPF(0),
  1295. .ngpio = S5P6440_GPIO_F_NR,
  1296. .label = "GPF",
  1297. },
  1298. }, {
  1299. .base = S5P64X0_GPI_BASE,
  1300. .config = &samsung_gpio_cfgs[4],
  1301. .chip = {
  1302. .base = S5P6440_GPI(0),
  1303. .ngpio = S5P6440_GPIO_I_NR,
  1304. .label = "GPI",
  1305. },
  1306. }, {
  1307. .base = S5P64X0_GPJ_BASE,
  1308. .config = &samsung_gpio_cfgs[4],
  1309. .chip = {
  1310. .base = S5P6440_GPJ(0),
  1311. .ngpio = S5P6440_GPIO_J_NR,
  1312. .label = "GPJ",
  1313. },
  1314. }, {
  1315. .base = S5P64X0_GPN_BASE,
  1316. .config = &samsung_gpio_cfgs[5],
  1317. .chip = {
  1318. .base = S5P6440_GPN(0),
  1319. .ngpio = S5P6440_GPIO_N_NR,
  1320. .label = "GPN",
  1321. },
  1322. }, {
  1323. .base = S5P64X0_GPP_BASE,
  1324. .config = &samsung_gpio_cfgs[6],
  1325. .chip = {
  1326. .base = S5P6440_GPP(0),
  1327. .ngpio = S5P6440_GPIO_P_NR,
  1328. .label = "GPP",
  1329. },
  1330. },
  1331. #endif
  1332. };
  1333. /*
  1334. * S5P6450 GPIO bank summary:
  1335. *
  1336. * Bank GPIOs Style SlpCon ExtInt Group
  1337. * A 6 4Bit Yes 1
  1338. * B 7 4Bit Yes 1
  1339. * C 8 4Bit Yes 2
  1340. * D 8 4Bit Yes None
  1341. * F 2 2Bit Yes None
  1342. * G 14 4Bit[2] Yes 5
  1343. * H 10 4Bit[2] Yes 6
  1344. * I 16 2Bit Yes None
  1345. * J 12 2Bit Yes None
  1346. * K 5 4Bit Yes None
  1347. * N 16 2Bit No IRQ_EINT
  1348. * P 11 2Bit Yes 8
  1349. * Q 14 2Bit Yes None
  1350. * R 15 4Bit[2] Yes None
  1351. * S 8 2Bit Yes None
  1352. *
  1353. * [1] BANKF pins 14,15 do not form part of the external interrupt sources
  1354. * [2] BANK has two control registers, GPxCON0 and GPxCON1
  1355. */
  1356. static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
  1357. #ifdef CONFIG_CPU_S5P6450
  1358. {
  1359. .chip = {
  1360. .base = S5P6450_GPA(0),
  1361. .ngpio = S5P6450_GPIO_A_NR,
  1362. .label = "GPA",
  1363. },
  1364. }, {
  1365. .chip = {
  1366. .base = S5P6450_GPB(0),
  1367. .ngpio = S5P6450_GPIO_B_NR,
  1368. .label = "GPB",
  1369. },
  1370. }, {
  1371. .chip = {
  1372. .base = S5P6450_GPC(0),
  1373. .ngpio = S5P6450_GPIO_C_NR,
  1374. .label = "GPC",
  1375. },
  1376. }, {
  1377. .chip = {
  1378. .base = S5P6450_GPD(0),
  1379. .ngpio = S5P6450_GPIO_D_NR,
  1380. .label = "GPD",
  1381. },
  1382. }, {
  1383. .base = S5P6450_GPK_BASE,
  1384. .chip = {
  1385. .base = S5P6450_GPK(0),
  1386. .ngpio = S5P6450_GPIO_K_NR,
  1387. .label = "GPK",
  1388. },
  1389. },
  1390. #endif
  1391. };
  1392. static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
  1393. #ifdef CONFIG_CPU_S5P6450
  1394. {
  1395. .base = S5P64X0_GPG_BASE + 0x4,
  1396. .chip = {
  1397. .base = S5P6450_GPG(0),
  1398. .ngpio = S5P6450_GPIO_G_NR,
  1399. .label = "GPG",
  1400. },
  1401. }, {
  1402. .base = S5P64X0_GPH_BASE + 0x4,
  1403. .chip = {
  1404. .base = S5P6450_GPH(0),
  1405. .ngpio = S5P6450_GPIO_H_NR,
  1406. .label = "GPH",
  1407. },
  1408. },
  1409. #endif
  1410. };
  1411. static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
  1412. #ifdef CONFIG_CPU_S5P6450
  1413. {
  1414. .base = S5P64X0_GPR_BASE + 0x4,
  1415. .config = &s5p64x0_gpio_cfg_rbank,
  1416. .chip = {
  1417. .base = S5P6450_GPR(0),
  1418. .ngpio = S5P6450_GPIO_R_NR,
  1419. .label = "GPR",
  1420. },
  1421. },
  1422. #endif
  1423. };
  1424. static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
  1425. #ifdef CONFIG_CPU_S5P6450
  1426. {
  1427. .base = S5P64X0_GPF_BASE,
  1428. .config = &samsung_gpio_cfgs[6],
  1429. .chip = {
  1430. .base = S5P6450_GPF(0),
  1431. .ngpio = S5P6450_GPIO_F_NR,
  1432. .label = "GPF",
  1433. },
  1434. }, {
  1435. .base = S5P64X0_GPI_BASE,
  1436. .config = &samsung_gpio_cfgs[4],
  1437. .chip = {
  1438. .base = S5P6450_GPI(0),
  1439. .ngpio = S5P6450_GPIO_I_NR,
  1440. .label = "GPI",
  1441. },
  1442. }, {
  1443. .base = S5P64X0_GPJ_BASE,
  1444. .config = &samsung_gpio_cfgs[4],
  1445. .chip = {
  1446. .base = S5P6450_GPJ(0),
  1447. .ngpio = S5P6450_GPIO_J_NR,
  1448. .label = "GPJ",
  1449. },
  1450. }, {
  1451. .base = S5P64X0_GPN_BASE,
  1452. .config = &samsung_gpio_cfgs[5],
  1453. .chip = {
  1454. .base = S5P6450_GPN(0),
  1455. .ngpio = S5P6450_GPIO_N_NR,
  1456. .label = "GPN",
  1457. },
  1458. }, {
  1459. .base = S5P64X0_GPP_BASE,
  1460. .config = &samsung_gpio_cfgs[6],
  1461. .chip = {
  1462. .base = S5P6450_GPP(0),
  1463. .ngpio = S5P6450_GPIO_P_NR,
  1464. .label = "GPP",
  1465. },
  1466. }, {
  1467. .base = S5P6450_GPQ_BASE,
  1468. .config = &samsung_gpio_cfgs[5],
  1469. .chip = {
  1470. .base = S5P6450_GPQ(0),
  1471. .ngpio = S5P6450_GPIO_Q_NR,
  1472. .label = "GPQ",
  1473. },
  1474. }, {
  1475. .base = S5P6450_GPS_BASE,
  1476. .config = &samsung_gpio_cfgs[6],
  1477. .chip = {
  1478. .base = S5P6450_GPS(0),
  1479. .ngpio = S5P6450_GPIO_S_NR,
  1480. .label = "GPS",
  1481. },
  1482. },
  1483. #endif
  1484. };
  1485. /*
  1486. * S5PC100 GPIO bank summary:
  1487. *
  1488. * Bank GPIOs Style INT Type
  1489. * A0 8 4Bit GPIO_INT0
  1490. * A1 5 4Bit GPIO_INT1
  1491. * B 8 4Bit GPIO_INT2
  1492. * C 5 4Bit GPIO_INT3
  1493. * D 7 4Bit GPIO_INT4
  1494. * E0 8 4Bit GPIO_INT5
  1495. * E1 6 4Bit GPIO_INT6
  1496. * F0 8 4Bit GPIO_INT7
  1497. * F1 8 4Bit GPIO_INT8
  1498. * F2 8 4Bit GPIO_INT9
  1499. * F3 4 4Bit GPIO_INT10
  1500. * G0 8 4Bit GPIO_INT11
  1501. * G1 3 4Bit GPIO_INT12
  1502. * G2 7 4Bit GPIO_INT13
  1503. * G3 7 4Bit GPIO_INT14
  1504. * H0 8 4Bit WKUP_INT
  1505. * H1 8 4Bit WKUP_INT
  1506. * H2 8 4Bit WKUP_INT
  1507. * H3 8 4Bit WKUP_INT
  1508. * I 8 4Bit GPIO_INT15
  1509. * J0 8 4Bit GPIO_INT16
  1510. * J1 5 4Bit GPIO_INT17
  1511. * J2 8 4Bit GPIO_INT18
  1512. * J3 8 4Bit GPIO_INT19
  1513. * J4 4 4Bit GPIO_INT20
  1514. * K0 8 4Bit None
  1515. * K1 6 4Bit None
  1516. * K2 8 4Bit None
  1517. * K3 8 4Bit None
  1518. * L0 8 4Bit None
  1519. * L1 8 4Bit None
  1520. * L2 8 4Bit None
  1521. * L3 8 4Bit None
  1522. */
  1523. static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
  1524. #ifdef CONFIG_CPU_S5PC100
  1525. {
  1526. .chip = {
  1527. .base = S5PC100_GPA0(0),
  1528. .ngpio = S5PC100_GPIO_A0_NR,
  1529. .label = "GPA0",
  1530. },
  1531. }, {
  1532. .chip = {
  1533. .base = S5PC100_GPA1(0),
  1534. .ngpio = S5PC100_GPIO_A1_NR,
  1535. .label = "GPA1",
  1536. },
  1537. }, {
  1538. .chip = {
  1539. .base = S5PC100_GPB(0),
  1540. .ngpio = S5PC100_GPIO_B_NR,
  1541. .label = "GPB",
  1542. },
  1543. }, {
  1544. .chip = {
  1545. .base = S5PC100_GPC(0),
  1546. .ngpio = S5PC100_GPIO_C_NR,
  1547. .label = "GPC",
  1548. },
  1549. }, {
  1550. .chip = {
  1551. .base = S5PC100_GPD(0),
  1552. .ngpio = S5PC100_GPIO_D_NR,
  1553. .label = "GPD",
  1554. },
  1555. }, {
  1556. .chip = {
  1557. .base = S5PC100_GPE0(0),
  1558. .ngpio = S5PC100_GPIO_E0_NR,
  1559. .label = "GPE0",
  1560. },
  1561. }, {
  1562. .chip = {
  1563. .base = S5PC100_GPE1(0),
  1564. .ngpio = S5PC100_GPIO_E1_NR,
  1565. .label = "GPE1",
  1566. },
  1567. }, {
  1568. .chip = {
  1569. .base = S5PC100_GPF0(0),
  1570. .ngpio = S5PC100_GPIO_F0_NR,
  1571. .label = "GPF0",
  1572. },
  1573. }, {
  1574. .chip = {
  1575. .base = S5PC100_GPF1(0),
  1576. .ngpio = S5PC100_GPIO_F1_NR,
  1577. .label = "GPF1",
  1578. },
  1579. }, {
  1580. .chip = {
  1581. .base = S5PC100_GPF2(0),
  1582. .ngpio = S5PC100_GPIO_F2_NR,
  1583. .label = "GPF2",
  1584. },
  1585. }, {
  1586. .chip = {
  1587. .base = S5PC100_GPF3(0),
  1588. .ngpio = S5PC100_GPIO_F3_NR,
  1589. .label = "GPF3",
  1590. },
  1591. }, {
  1592. .chip = {
  1593. .base = S5PC100_GPG0(0),
  1594. .ngpio = S5PC100_GPIO_G0_NR,
  1595. .label = "GPG0",
  1596. },
  1597. }, {
  1598. .chip = {
  1599. .base = S5PC100_GPG1(0),
  1600. .ngpio = S5PC100_GPIO_G1_NR,
  1601. .label = "GPG1",
  1602. },
  1603. }, {
  1604. .chip = {
  1605. .base = S5PC100_GPG2(0),
  1606. .ngpio = S5PC100_GPIO_G2_NR,
  1607. .label = "GPG2",
  1608. },
  1609. }, {
  1610. .chip = {
  1611. .base = S5PC100_GPG3(0),
  1612. .ngpio = S5PC100_GPIO_G3_NR,
  1613. .label = "GPG3",
  1614. },
  1615. }, {
  1616. .chip = {
  1617. .base = S5PC100_GPI(0),
  1618. .ngpio = S5PC100_GPIO_I_NR,
  1619. .label = "GPI",
  1620. },
  1621. }, {
  1622. .chip = {
  1623. .base = S5PC100_GPJ0(0),
  1624. .ngpio = S5PC100_GPIO_J0_NR,
  1625. .label = "GPJ0",
  1626. },
  1627. }, {
  1628. .chip = {
  1629. .base = S5PC100_GPJ1(0),
  1630. .ngpio = S5PC100_GPIO_J1_NR,
  1631. .label = "GPJ1",
  1632. },
  1633. }, {
  1634. .chip = {
  1635. .base = S5PC100_GPJ2(0),
  1636. .ngpio = S5PC100_GPIO_J2_NR,
  1637. .label = "GPJ2",
  1638. },
  1639. }, {
  1640. .chip = {
  1641. .base = S5PC100_GPJ3(0),
  1642. .ngpio = S5PC100_GPIO_J3_NR,
  1643. .label = "GPJ3",
  1644. },
  1645. }, {
  1646. .chip = {
  1647. .base = S5PC100_GPJ4(0),
  1648. .ngpio = S5PC100_GPIO_J4_NR,
  1649. .label = "GPJ4",
  1650. },
  1651. }, {
  1652. .chip = {
  1653. .base = S5PC100_GPK0(0),
  1654. .ngpio = S5PC100_GPIO_K0_NR,
  1655. .label = "GPK0",
  1656. },
  1657. }, {
  1658. .chip = {
  1659. .base = S5PC100_GPK1(0),
  1660. .ngpio = S5PC100_GPIO_K1_NR,
  1661. .label = "GPK1",
  1662. },
  1663. }, {
  1664. .chip = {
  1665. .base = S5PC100_GPK2(0),
  1666. .ngpio = S5PC100_GPIO_K2_NR,
  1667. .label = "GPK2",
  1668. },
  1669. }, {
  1670. .chip = {
  1671. .base = S5PC100_GPK3(0),
  1672. .ngpio = S5PC100_GPIO_K3_NR,
  1673. .label = "GPK3",
  1674. },
  1675. }, {
  1676. .chip = {
  1677. .base = S5PC100_GPL0(0),
  1678. .ngpio = S5PC100_GPIO_L0_NR,
  1679. .label = "GPL0",
  1680. },
  1681. }, {
  1682. .chip = {
  1683. .base = S5PC100_GPL1(0),
  1684. .ngpio = S5PC100_GPIO_L1_NR,
  1685. .label = "GPL1",
  1686. },
  1687. }, {
  1688. .chip = {
  1689. .base = S5PC100_GPL2(0),
  1690. .ngpio = S5PC100_GPIO_L2_NR,
  1691. .label = "GPL2",
  1692. },
  1693. }, {
  1694. .chip = {
  1695. .base = S5PC100_GPL3(0),
  1696. .ngpio = S5PC100_GPIO_L3_NR,
  1697. .label = "GPL3",
  1698. },
  1699. }, {
  1700. .chip = {
  1701. .base = S5PC100_GPL4(0),
  1702. .ngpio = S5PC100_GPIO_L4_NR,
  1703. .label = "GPL4",
  1704. },
  1705. }, {
  1706. .base = (S5P_VA_GPIO + 0xC00),
  1707. .irq_base = IRQ_EINT(0),
  1708. .chip = {
  1709. .base = S5PC100_GPH0(0),
  1710. .ngpio = S5PC100_GPIO_H0_NR,
  1711. .label = "GPH0",
  1712. .to_irq = samsung_gpiolib_to_irq,
  1713. },
  1714. }, {
  1715. .base = (S5P_VA_GPIO + 0xC20),
  1716. .irq_base = IRQ_EINT(8),
  1717. .chip = {
  1718. .base = S5PC100_GPH1(0),
  1719. .ngpio = S5PC100_GPIO_H1_NR,
  1720. .label = "GPH1",
  1721. .to_irq = samsung_gpiolib_to_irq,
  1722. },
  1723. }, {
  1724. .base = (S5P_VA_GPIO + 0xC40),
  1725. .irq_base = IRQ_EINT(16),
  1726. .chip = {
  1727. .base = S5PC100_GPH2(0),
  1728. .ngpio = S5PC100_GPIO_H2_NR,
  1729. .label = "GPH2",
  1730. .to_irq = samsung_gpiolib_to_irq,
  1731. },
  1732. }, {
  1733. .base = (S5P_VA_GPIO + 0xC60),
  1734. .irq_base = IRQ_EINT(24),
  1735. .chip = {
  1736. .base = S5PC100_GPH3(0),
  1737. .ngpio = S5PC100_GPIO_H3_NR,
  1738. .label = "GPH3",
  1739. .to_irq = samsung_gpiolib_to_irq,
  1740. },
  1741. },
  1742. #endif
  1743. };
  1744. /*
  1745. * Followings are the gpio banks in S5PV210/S5PC110
  1746. *
  1747. * The 'config' member when left to NULL, is initialized to the default
  1748. * structure samsung_gpio_cfgs[3] in the init function below.
  1749. *
  1750. * The 'base' member is also initialized in the init function below.
  1751. * Note: The initialization of 'base' member of samsung_gpio_chip structure
  1752. * uses the above macro and depends on the banks being listed in order here.
  1753. */
  1754. static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
  1755. #ifdef CONFIG_CPU_S5PV210
  1756. {
  1757. .chip = {
  1758. .base = S5PV210_GPA0(0),
  1759. .ngpio = S5PV210_GPIO_A0_NR,
  1760. .label = "GPA0",
  1761. },
  1762. }, {
  1763. .chip = {
  1764. .base = S5PV210_GPA1(0),
  1765. .ngpio = S5PV210_GPIO_A1_NR,
  1766. .label = "GPA1",
  1767. },
  1768. }, {
  1769. .chip = {
  1770. .base = S5PV210_GPB(0),
  1771. .ngpio = S5PV210_GPIO_B_NR,
  1772. .label = "GPB",
  1773. },
  1774. }, {
  1775. .chip = {
  1776. .base = S5PV210_GPC0(0),
  1777. .ngpio = S5PV210_GPIO_C0_NR,
  1778. .label = "GPC0",
  1779. },
  1780. }, {
  1781. .chip = {
  1782. .base = S5PV210_GPC1(0),
  1783. .ngpio = S5PV210_GPIO_C1_NR,
  1784. .label = "GPC1",
  1785. },
  1786. }, {
  1787. .chip = {
  1788. .base = S5PV210_GPD0(0),
  1789. .ngpio = S5PV210_GPIO_D0_NR,
  1790. .label = "GPD0",
  1791. },
  1792. }, {
  1793. .chip = {
  1794. .base = S5PV210_GPD1(0),
  1795. .ngpio = S5PV210_GPIO_D1_NR,
  1796. .label = "GPD1",
  1797. },
  1798. }, {
  1799. .chip = {
  1800. .base = S5PV210_GPE0(0),
  1801. .ngpio = S5PV210_GPIO_E0_NR,
  1802. .label = "GPE0",
  1803. },
  1804. }, {
  1805. .chip = {
  1806. .base = S5PV210_GPE1(0),
  1807. .ngpio = S5PV210_GPIO_E1_NR,
  1808. .label = "GPE1",
  1809. },
  1810. }, {
  1811. .chip = {
  1812. .base = S5PV210_GPF0(0),
  1813. .ngpio = S5PV210_GPIO_F0_NR,
  1814. .label = "GPF0",
  1815. },
  1816. }, {
  1817. .chip = {
  1818. .base = S5PV210_GPF1(0),
  1819. .ngpio = S5PV210_GPIO_F1_NR,
  1820. .label = "GPF1",
  1821. },
  1822. }, {
  1823. .chip = {
  1824. .base = S5PV210_GPF2(0),
  1825. .ngpio = S5PV210_GPIO_F2_NR,
  1826. .label = "GPF2",
  1827. },
  1828. }, {
  1829. .chip = {
  1830. .base = S5PV210_GPF3(0),
  1831. .ngpio = S5PV210_GPIO_F3_NR,
  1832. .label = "GPF3",
  1833. },
  1834. }, {
  1835. .chip = {
  1836. .base = S5PV210_GPG0(0),
  1837. .ngpio = S5PV210_GPIO_G0_NR,
  1838. .label = "GPG0",
  1839. },
  1840. }, {
  1841. .chip = {
  1842. .base = S5PV210_GPG1(0),
  1843. .ngpio = S5PV210_GPIO_G1_NR,
  1844. .label = "GPG1",
  1845. },
  1846. }, {
  1847. .chip = {
  1848. .base = S5PV210_GPG2(0),
  1849. .ngpio = S5PV210_GPIO_G2_NR,
  1850. .label = "GPG2",
  1851. },
  1852. }, {
  1853. .chip = {
  1854. .base = S5PV210_GPG3(0),
  1855. .ngpio = S5PV210_GPIO_G3_NR,
  1856. .label = "GPG3",
  1857. },
  1858. }, {
  1859. .chip = {
  1860. .base = S5PV210_GPI(0),
  1861. .ngpio = S5PV210_GPIO_I_NR,
  1862. .label = "GPI",
  1863. },
  1864. }, {
  1865. .chip = {
  1866. .base = S5PV210_GPJ0(0),
  1867. .ngpio = S5PV210_GPIO_J0_NR,
  1868. .label = "GPJ0",
  1869. },
  1870. }, {
  1871. .chip = {
  1872. .base = S5PV210_GPJ1(0),
  1873. .ngpio = S5PV210_GPIO_J1_NR,
  1874. .label = "GPJ1",
  1875. },
  1876. }, {
  1877. .chip = {
  1878. .base = S5PV210_GPJ2(0),
  1879. .ngpio = S5PV210_GPIO_J2_NR,
  1880. .label = "GPJ2",
  1881. },
  1882. }, {
  1883. .chip = {
  1884. .base = S5PV210_GPJ3(0),
  1885. .ngpio = S5PV210_GPIO_J3_NR,
  1886. .label = "GPJ3",
  1887. },
  1888. }, {
  1889. .chip = {
  1890. .base = S5PV210_GPJ4(0),
  1891. .ngpio = S5PV210_GPIO_J4_NR,
  1892. .label = "GPJ4",
  1893. },
  1894. }, {
  1895. .chip = {
  1896. .base = S5PV210_MP01(0),
  1897. .ngpio = S5PV210_GPIO_MP01_NR,
  1898. .label = "MP01",
  1899. },
  1900. }, {
  1901. .chip = {
  1902. .base = S5PV210_MP02(0),
  1903. .ngpio = S5PV210_GPIO_MP02_NR,
  1904. .label = "MP02",
  1905. },
  1906. }, {
  1907. .chip = {
  1908. .base = S5PV210_MP03(0),
  1909. .ngpio = S5PV210_GPIO_MP03_NR,
  1910. .label = "MP03",
  1911. },
  1912. }, {
  1913. .chip = {
  1914. .base = S5PV210_MP04(0),
  1915. .ngpio = S5PV210_GPIO_MP04_NR,
  1916. .label = "MP04",
  1917. },
  1918. }, {
  1919. .chip = {
  1920. .base = S5PV210_MP05(0),
  1921. .ngpio = S5PV210_GPIO_MP05_NR,
  1922. .label = "MP05",
  1923. },
  1924. }, {
  1925. .base = (S5P_VA_GPIO + 0xC00),
  1926. .irq_base = IRQ_EINT(0),
  1927. .chip = {
  1928. .base = S5PV210_GPH0(0),
  1929. .ngpio = S5PV210_GPIO_H0_NR,
  1930. .label = "GPH0",
  1931. .to_irq = samsung_gpiolib_to_irq,
  1932. },
  1933. }, {
  1934. .base = (S5P_VA_GPIO + 0xC20),
  1935. .irq_base = IRQ_EINT(8),
  1936. .chip = {
  1937. .base = S5PV210_GPH1(0),
  1938. .ngpio = S5PV210_GPIO_H1_NR,
  1939. .label = "GPH1",
  1940. .to_irq = samsung_gpiolib_to_irq,
  1941. },
  1942. }, {
  1943. .base = (S5P_VA_GPIO + 0xC40),
  1944. .irq_base = IRQ_EINT(16),
  1945. .chip = {
  1946. .base = S5PV210_GPH2(0),
  1947. .ngpio = S5PV210_GPIO_H2_NR,
  1948. .label = "GPH2",
  1949. .to_irq = samsung_gpiolib_to_irq,
  1950. },
  1951. }, {
  1952. .base = (S5P_VA_GPIO + 0xC60),
  1953. .irq_base = IRQ_EINT(24),
  1954. .chip = {
  1955. .base = S5PV210_GPH3(0),
  1956. .ngpio = S5PV210_GPIO_H3_NR,
  1957. .label = "GPH3",
  1958. .to_irq = samsung_gpiolib_to_irq,
  1959. },
  1960. },
  1961. #endif
  1962. };
  1963. /*
  1964. * Followings are the gpio banks in EXYNOS SoCs
  1965. *
  1966. * The 'config' member when left to NULL, is initialized to the default
  1967. * structure exynos_gpio_cfg in the init function below.
  1968. *
  1969. * The 'base' member is also initialized in the init function below.
  1970. * Note: The initialization of 'base' member of samsung_gpio_chip structure
  1971. * uses the above macro and depends on the banks being listed in order here.
  1972. */
  1973. #ifdef CONFIG_ARCH_EXYNOS4
  1974. static struct samsung_gpio_chip exynos4_gpios_1[] = {
  1975. {
  1976. .chip = {
  1977. .base = EXYNOS4_GPA0(0),
  1978. .ngpio = EXYNOS4_GPIO_A0_NR,
  1979. .label = "GPA0",
  1980. },
  1981. }, {
  1982. .chip = {
  1983. .base = EXYNOS4_GPA1(0),
  1984. .ngpio = EXYNOS4_GPIO_A1_NR,
  1985. .label = "GPA1",
  1986. },
  1987. }, {
  1988. .chip = {
  1989. .base = EXYNOS4_GPB(0),
  1990. .ngpio = EXYNOS4_GPIO_B_NR,
  1991. .label = "GPB",
  1992. },
  1993. }, {
  1994. .chip = {
  1995. .base = EXYNOS4_GPC0(0),
  1996. .ngpio = EXYNOS4_GPIO_C0_NR,
  1997. .label = "GPC0",
  1998. },
  1999. }, {
  2000. .chip = {
  2001. .base = EXYNOS4_GPC1(0),
  2002. .ngpio = EXYNOS4_GPIO_C1_NR,
  2003. .label = "GPC1",
  2004. },
  2005. }, {
  2006. .chip = {
  2007. .base = EXYNOS4_GPD0(0),
  2008. .ngpio = EXYNOS4_GPIO_D0_NR,
  2009. .label = "GPD0",
  2010. },
  2011. }, {
  2012. .chip = {
  2013. .base = EXYNOS4_GPD1(0),
  2014. .ngpio = EXYNOS4_GPIO_D1_NR,
  2015. .label = "GPD1",
  2016. },
  2017. }, {
  2018. .chip = {
  2019. .base = EXYNOS4_GPE0(0),
  2020. .ngpio = EXYNOS4_GPIO_E0_NR,
  2021. .label = "GPE0",
  2022. },
  2023. }, {
  2024. .chip = {
  2025. .base = EXYNOS4_GPE1(0),
  2026. .ngpio = EXYNOS4_GPIO_E1_NR,
  2027. .label = "GPE1",
  2028. },
  2029. }, {
  2030. .chip = {
  2031. .base = EXYNOS4_GPE2(0),
  2032. .ngpio = EXYNOS4_GPIO_E2_NR,
  2033. .label = "GPE2",
  2034. },
  2035. }, {
  2036. .chip = {
  2037. .base = EXYNOS4_GPE3(0),
  2038. .ngpio = EXYNOS4_GPIO_E3_NR,
  2039. .label = "GPE3",
  2040. },
  2041. }, {
  2042. .chip = {
  2043. .base = EXYNOS4_GPE4(0),
  2044. .ngpio = EXYNOS4_GPIO_E4_NR,
  2045. .label = "GPE4",
  2046. },
  2047. }, {
  2048. .chip = {
  2049. .base = EXYNOS4_GPF0(0),
  2050. .ngpio = EXYNOS4_GPIO_F0_NR,
  2051. .label = "GPF0",
  2052. },
  2053. }, {
  2054. .chip = {
  2055. .base = EXYNOS4_GPF1(0),
  2056. .ngpio = EXYNOS4_GPIO_F1_NR,
  2057. .label = "GPF1",
  2058. },
  2059. }, {
  2060. .chip = {
  2061. .base = EXYNOS4_GPF2(0),
  2062. .ngpio = EXYNOS4_GPIO_F2_NR,
  2063. .label = "GPF2",
  2064. },
  2065. }, {
  2066. .chip = {
  2067. .base = EXYNOS4_GPF3(0),
  2068. .ngpio = EXYNOS4_GPIO_F3_NR,
  2069. .label = "GPF3",
  2070. },
  2071. },
  2072. };
  2073. #endif
  2074. #ifdef CONFIG_ARCH_EXYNOS4
  2075. static struct samsung_gpio_chip exynos4_gpios_2[] = {
  2076. {
  2077. .chip = {
  2078. .base = EXYNOS4_GPJ0(0),
  2079. .ngpio = EXYNOS4_GPIO_J0_NR,
  2080. .label = "GPJ0",
  2081. },
  2082. }, {
  2083. .chip = {
  2084. .base = EXYNOS4_GPJ1(0),
  2085. .ngpio = EXYNOS4_GPIO_J1_NR,
  2086. .label = "GPJ1",
  2087. },
  2088. }, {
  2089. .chip = {
  2090. .base = EXYNOS4_GPK0(0),
  2091. .ngpio = EXYNOS4_GPIO_K0_NR,
  2092. .label = "GPK0",
  2093. },
  2094. }, {
  2095. .chip = {
  2096. .base = EXYNOS4_GPK1(0),
  2097. .ngpio = EXYNOS4_GPIO_K1_NR,
  2098. .label = "GPK1",
  2099. },
  2100. }, {
  2101. .chip = {
  2102. .base = EXYNOS4_GPK2(0),
  2103. .ngpio = EXYNOS4_GPIO_K2_NR,
  2104. .label = "GPK2",
  2105. },
  2106. }, {
  2107. .chip = {
  2108. .base = EXYNOS4_GPK3(0),
  2109. .ngpio = EXYNOS4_GPIO_K3_NR,
  2110. .label = "GPK3",
  2111. },
  2112. }, {
  2113. .chip = {
  2114. .base = EXYNOS4_GPL0(0),
  2115. .ngpio = EXYNOS4_GPIO_L0_NR,
  2116. .label = "GPL0",
  2117. },
  2118. }, {
  2119. .chip = {
  2120. .base = EXYNOS4_GPL1(0),
  2121. .ngpio = EXYNOS4_GPIO_L1_NR,
  2122. .label = "GPL1",
  2123. },
  2124. }, {
  2125. .chip = {
  2126. .base = EXYNOS4_GPL2(0),
  2127. .ngpio = EXYNOS4_GPIO_L2_NR,
  2128. .label = "GPL2",
  2129. },
  2130. }, {
  2131. .config = &samsung_gpio_cfgs[8],
  2132. .chip = {
  2133. .base = EXYNOS4_GPY0(0),
  2134. .ngpio = EXYNOS4_GPIO_Y0_NR,
  2135. .label = "GPY0",
  2136. },
  2137. }, {
  2138. .config = &samsung_gpio_cfgs[8],
  2139. .chip = {
  2140. .base = EXYNOS4_GPY1(0),
  2141. .ngpio = EXYNOS4_GPIO_Y1_NR,
  2142. .label = "GPY1",
  2143. },
  2144. }, {
  2145. .config = &samsung_gpio_cfgs[8],
  2146. .chip = {
  2147. .base = EXYNOS4_GPY2(0),
  2148. .ngpio = EXYNOS4_GPIO_Y2_NR,
  2149. .label = "GPY2",
  2150. },
  2151. }, {
  2152. .config = &samsung_gpio_cfgs[8],
  2153. .chip = {
  2154. .base = EXYNOS4_GPY3(0),
  2155. .ngpio = EXYNOS4_GPIO_Y3_NR,
  2156. .label = "GPY3",
  2157. },
  2158. }, {
  2159. .config = &samsung_gpio_cfgs[8],
  2160. .chip = {
  2161. .base = EXYNOS4_GPY4(0),
  2162. .ngpio = EXYNOS4_GPIO_Y4_NR,
  2163. .label = "GPY4",
  2164. },
  2165. }, {
  2166. .config = &samsung_gpio_cfgs[8],
  2167. .chip = {
  2168. .base = EXYNOS4_GPY5(0),
  2169. .ngpio = EXYNOS4_GPIO_Y5_NR,
  2170. .label = "GPY5",
  2171. },
  2172. }, {
  2173. .config = &samsung_gpio_cfgs[8],
  2174. .chip = {
  2175. .base = EXYNOS4_GPY6(0),
  2176. .ngpio = EXYNOS4_GPIO_Y6_NR,
  2177. .label = "GPY6",
  2178. },
  2179. }, {
  2180. .config = &samsung_gpio_cfgs[9],
  2181. .irq_base = IRQ_EINT(0),
  2182. .chip = {
  2183. .base = EXYNOS4_GPX0(0),
  2184. .ngpio = EXYNOS4_GPIO_X0_NR,
  2185. .label = "GPX0",
  2186. .to_irq = samsung_gpiolib_to_irq,
  2187. },
  2188. }, {
  2189. .config = &samsung_gpio_cfgs[9],
  2190. .irq_base = IRQ_EINT(8),
  2191. .chip = {
  2192. .base = EXYNOS4_GPX1(0),
  2193. .ngpio = EXYNOS4_GPIO_X1_NR,
  2194. .label = "GPX1",
  2195. .to_irq = samsung_gpiolib_to_irq,
  2196. },
  2197. }, {
  2198. .config = &samsung_gpio_cfgs[9],
  2199. .irq_base = IRQ_EINT(16),
  2200. .chip = {
  2201. .base = EXYNOS4_GPX2(0),
  2202. .ngpio = EXYNOS4_GPIO_X2_NR,
  2203. .label = "GPX2",
  2204. .to_irq = samsung_gpiolib_to_irq,
  2205. },
  2206. }, {
  2207. .config = &samsung_gpio_cfgs[9],
  2208. .irq_base = IRQ_EINT(24),
  2209. .chip = {
  2210. .base = EXYNOS4_GPX3(0),
  2211. .ngpio = EXYNOS4_GPIO_X3_NR,
  2212. .label = "GPX3",
  2213. .to_irq = samsung_gpiolib_to_irq,
  2214. },
  2215. },
  2216. };
  2217. #endif
  2218. #ifdef CONFIG_ARCH_EXYNOS4
  2219. static struct samsung_gpio_chip exynos4_gpios_3[] = {
  2220. {
  2221. .chip = {
  2222. .base = EXYNOS4_GPZ(0),
  2223. .ngpio = EXYNOS4_GPIO_Z_NR,
  2224. .label = "GPZ",
  2225. },
  2226. },
  2227. };
  2228. #endif
  2229. #ifdef CONFIG_SOC_EXYNOS5250
  2230. static struct samsung_gpio_chip exynos5_gpios_1[] = {
  2231. {
  2232. .chip = {
  2233. .base = EXYNOS5_GPA0(0),
  2234. .ngpio = EXYNOS5_GPIO_A0_NR,
  2235. .label = "GPA0",
  2236. },
  2237. }, {
  2238. .chip = {
  2239. .base = EXYNOS5_GPA1(0),
  2240. .ngpio = EXYNOS5_GPIO_A1_NR,
  2241. .label = "GPA1",
  2242. },
  2243. }, {
  2244. .chip = {
  2245. .base = EXYNOS5_GPA2(0),
  2246. .ngpio = EXYNOS5_GPIO_A2_NR,
  2247. .label = "GPA2",
  2248. },
  2249. }, {
  2250. .chip = {
  2251. .base = EXYNOS5_GPB0(0),
  2252. .ngpio = EXYNOS5_GPIO_B0_NR,
  2253. .label = "GPB0",
  2254. },
  2255. }, {
  2256. .chip = {
  2257. .base = EXYNOS5_GPB1(0),
  2258. .ngpio = EXYNOS5_GPIO_B1_NR,
  2259. .label = "GPB1",
  2260. },
  2261. }, {
  2262. .chip = {
  2263. .base = EXYNOS5_GPB2(0),
  2264. .ngpio = EXYNOS5_GPIO_B2_NR,
  2265. .label = "GPB2",
  2266. },
  2267. }, {
  2268. .chip = {
  2269. .base = EXYNOS5_GPB3(0),
  2270. .ngpio = EXYNOS5_GPIO_B3_NR,
  2271. .label = "GPB3",
  2272. },
  2273. }, {
  2274. .chip = {
  2275. .base = EXYNOS5_GPC0(0),
  2276. .ngpio = EXYNOS5_GPIO_C0_NR,
  2277. .label = "GPC0",
  2278. },
  2279. }, {
  2280. .chip = {
  2281. .base = EXYNOS5_GPC1(0),
  2282. .ngpio = EXYNOS5_GPIO_C1_NR,
  2283. .label = "GPC1",
  2284. },
  2285. }, {
  2286. .chip = {
  2287. .base = EXYNOS5_GPC2(0),
  2288. .ngpio = EXYNOS5_GPIO_C2_NR,
  2289. .label = "GPC2",
  2290. },
  2291. }, {
  2292. .chip = {
  2293. .base = EXYNOS5_GPC3(0),
  2294. .ngpio = EXYNOS5_GPIO_C3_NR,
  2295. .label = "GPC3",
  2296. },
  2297. }, {
  2298. .chip = {
  2299. .base = EXYNOS5_GPD0(0),
  2300. .ngpio = EXYNOS5_GPIO_D0_NR,
  2301. .label = "GPD0",
  2302. },
  2303. }, {
  2304. .chip = {
  2305. .base = EXYNOS5_GPD1(0),
  2306. .ngpio = EXYNOS5_GPIO_D1_NR,
  2307. .label = "GPD1",
  2308. },
  2309. }, {
  2310. .chip = {
  2311. .base = EXYNOS5_GPY0(0),
  2312. .ngpio = EXYNOS5_GPIO_Y0_NR,
  2313. .label = "GPY0",
  2314. },
  2315. }, {
  2316. .chip = {
  2317. .base = EXYNOS5_GPY1(0),
  2318. .ngpio = EXYNOS5_GPIO_Y1_NR,
  2319. .label = "GPY1",
  2320. },
  2321. }, {
  2322. .chip = {
  2323. .base = EXYNOS5_GPY2(0),
  2324. .ngpio = EXYNOS5_GPIO_Y2_NR,
  2325. .label = "GPY2",
  2326. },
  2327. }, {
  2328. .chip = {
  2329. .base = EXYNOS5_GPY3(0),
  2330. .ngpio = EXYNOS5_GPIO_Y3_NR,
  2331. .label = "GPY3",
  2332. },
  2333. }, {
  2334. .chip = {
  2335. .base = EXYNOS5_GPY4(0),
  2336. .ngpio = EXYNOS5_GPIO_Y4_NR,
  2337. .label = "GPY4",
  2338. },
  2339. }, {
  2340. .chip = {
  2341. .base = EXYNOS5_GPY5(0),
  2342. .ngpio = EXYNOS5_GPIO_Y5_NR,
  2343. .label = "GPY5",
  2344. },
  2345. }, {
  2346. .chip = {
  2347. .base = EXYNOS5_GPY6(0),
  2348. .ngpio = EXYNOS5_GPIO_Y6_NR,
  2349. .label = "GPY6",
  2350. },
  2351. }, {
  2352. .chip = {
  2353. .base = EXYNOS5_GPC4(0),
  2354. .ngpio = EXYNOS5_GPIO_C4_NR,
  2355. .label = "GPC4",
  2356. },
  2357. }, {
  2358. .config = &samsung_gpio_cfgs[9],
  2359. .irq_base = IRQ_EINT(0),
  2360. .chip = {
  2361. .base = EXYNOS5_GPX0(0),
  2362. .ngpio = EXYNOS5_GPIO_X0_NR,
  2363. .label = "GPX0",
  2364. .to_irq = samsung_gpiolib_to_irq,
  2365. },
  2366. }, {
  2367. .config = &samsung_gpio_cfgs[9],
  2368. .irq_base = IRQ_EINT(8),
  2369. .chip = {
  2370. .base = EXYNOS5_GPX1(0),
  2371. .ngpio = EXYNOS5_GPIO_X1_NR,
  2372. .label = "GPX1",
  2373. .to_irq = samsung_gpiolib_to_irq,
  2374. },
  2375. }, {
  2376. .config = &samsung_gpio_cfgs[9],
  2377. .irq_base = IRQ_EINT(16),
  2378. .chip = {
  2379. .base = EXYNOS5_GPX2(0),
  2380. .ngpio = EXYNOS5_GPIO_X2_NR,
  2381. .label = "GPX2",
  2382. .to_irq = samsung_gpiolib_to_irq,
  2383. },
  2384. }, {
  2385. .config = &samsung_gpio_cfgs[9],
  2386. .irq_base = IRQ_EINT(24),
  2387. .chip = {
  2388. .base = EXYNOS5_GPX3(0),
  2389. .ngpio = EXYNOS5_GPIO_X3_NR,
  2390. .label = "GPX3",
  2391. .to_irq = samsung_gpiolib_to_irq,
  2392. },
  2393. },
  2394. };
  2395. #endif
  2396. #ifdef CONFIG_SOC_EXYNOS5250
  2397. static struct samsung_gpio_chip exynos5_gpios_2[] = {
  2398. {
  2399. .chip = {
  2400. .base = EXYNOS5_GPE0(0),
  2401. .ngpio = EXYNOS5_GPIO_E0_NR,
  2402. .label = "GPE0",
  2403. },
  2404. }, {
  2405. .chip = {
  2406. .base = EXYNOS5_GPE1(0),
  2407. .ngpio = EXYNOS5_GPIO_E1_NR,
  2408. .label = "GPE1",
  2409. },
  2410. }, {
  2411. .chip = {
  2412. .base = EXYNOS5_GPF0(0),
  2413. .ngpio = EXYNOS5_GPIO_F0_NR,
  2414. .label = "GPF0",
  2415. },
  2416. }, {
  2417. .chip = {
  2418. .base = EXYNOS5_GPF1(0),
  2419. .ngpio = EXYNOS5_GPIO_F1_NR,
  2420. .label = "GPF1",
  2421. },
  2422. }, {
  2423. .chip = {
  2424. .base = EXYNOS5_GPG0(0),
  2425. .ngpio = EXYNOS5_GPIO_G0_NR,
  2426. .label = "GPG0",
  2427. },
  2428. }, {
  2429. .chip = {
  2430. .base = EXYNOS5_GPG1(0),
  2431. .ngpio = EXYNOS5_GPIO_G1_NR,
  2432. .label = "GPG1",
  2433. },
  2434. }, {
  2435. .chip = {
  2436. .base = EXYNOS5_GPG2(0),
  2437. .ngpio = EXYNOS5_GPIO_G2_NR,
  2438. .label = "GPG2",
  2439. },
  2440. }, {
  2441. .chip = {
  2442. .base = EXYNOS5_GPH0(0),
  2443. .ngpio = EXYNOS5_GPIO_H0_NR,
  2444. .label = "GPH0",
  2445. },
  2446. }, {
  2447. .chip = {
  2448. .base = EXYNOS5_GPH1(0),
  2449. .ngpio = EXYNOS5_GPIO_H1_NR,
  2450. .label = "GPH1",
  2451. },
  2452. },
  2453. };
  2454. #endif
  2455. #ifdef CONFIG_SOC_EXYNOS5250
  2456. static struct samsung_gpio_chip exynos5_gpios_3[] = {
  2457. {
  2458. .chip = {
  2459. .base = EXYNOS5_GPV0(0),
  2460. .ngpio = EXYNOS5_GPIO_V0_NR,
  2461. .label = "GPV0",
  2462. },
  2463. }, {
  2464. .chip = {
  2465. .base = EXYNOS5_GPV1(0),
  2466. .ngpio = EXYNOS5_GPIO_V1_NR,
  2467. .label = "GPV1",
  2468. },
  2469. }, {
  2470. .chip = {
  2471. .base = EXYNOS5_GPV2(0),
  2472. .ngpio = EXYNOS5_GPIO_V2_NR,
  2473. .label = "GPV2",
  2474. },
  2475. }, {
  2476. .chip = {
  2477. .base = EXYNOS5_GPV3(0),
  2478. .ngpio = EXYNOS5_GPIO_V3_NR,
  2479. .label = "GPV3",
  2480. },
  2481. }, {
  2482. .chip = {
  2483. .base = EXYNOS5_GPV4(0),
  2484. .ngpio = EXYNOS5_GPIO_V4_NR,
  2485. .label = "GPV4",
  2486. },
  2487. },
  2488. };
  2489. #endif
  2490. #ifdef CONFIG_SOC_EXYNOS5250
  2491. static struct samsung_gpio_chip exynos5_gpios_4[] = {
  2492. {
  2493. .chip = {
  2494. .base = EXYNOS5_GPZ(0),
  2495. .ngpio = EXYNOS5_GPIO_Z_NR,
  2496. .label = "GPZ",
  2497. },
  2498. },
  2499. };
  2500. #endif
  2501. #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
  2502. static int exynos_gpio_xlate(struct gpio_chip *gc,
  2503. const struct of_phandle_args *gpiospec, u32 *flags)
  2504. {
  2505. unsigned int pin;
  2506. if (WARN_ON(gc->of_gpio_n_cells < 4))
  2507. return -EINVAL;
  2508. if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
  2509. return -EINVAL;
  2510. if (gpiospec->args[0] > gc->ngpio)
  2511. return -EINVAL;
  2512. pin = gc->base + gpiospec->args[0];
  2513. if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
  2514. pr_warn("gpio_xlate: failed to set pin function\n");
  2515. if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
  2516. pr_warn("gpio_xlate: failed to set pin pull up/down\n");
  2517. if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
  2518. pr_warn("gpio_xlate: failed to set pin drive strength\n");
  2519. if (flags)
  2520. *flags = gpiospec->args[2] >> 16;
  2521. return gpiospec->args[0];
  2522. }
  2523. static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
  2524. { .compatible = "samsung,exynos4-gpio", },
  2525. {}
  2526. };
  2527. static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
  2528. u64 base, u64 offset)
  2529. {
  2530. struct gpio_chip *gc = &chip->chip;
  2531. u64 address;
  2532. if (!of_have_populated_dt())
  2533. return;
  2534. address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
  2535. gc->of_node = of_find_matching_node_by_address(NULL,
  2536. exynos_gpio_dt_match, address);
  2537. if (!gc->of_node) {
  2538. pr_info("gpio: device tree node not found for gpio controller"
  2539. " with base address %08llx\n", address);
  2540. return;
  2541. }
  2542. gc->of_gpio_n_cells = 4;
  2543. gc->of_xlate = exynos_gpio_xlate;
  2544. }
  2545. #elif defined(CONFIG_ARCH_EXYNOS)
  2546. static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
  2547. u64 base, u64 offset)
  2548. {
  2549. return;
  2550. }
  2551. #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
  2552. static __init void exynos4_gpiolib_init(void)
  2553. {
  2554. #ifdef CONFIG_CPU_EXYNOS4210
  2555. struct samsung_gpio_chip *chip;
  2556. int i, nr_chips;
  2557. void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
  2558. int group = 0;
  2559. void __iomem *gpx_base;
  2560. /* gpio part1 */
  2561. gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
  2562. if (gpio_base1 == NULL) {
  2563. pr_err("unable to ioremap for gpio_base1\n");
  2564. goto err_ioremap1;
  2565. }
  2566. chip = exynos4_gpios_1;
  2567. nr_chips = ARRAY_SIZE(exynos4_gpios_1);
  2568. for (i = 0; i < nr_chips; i++, chip++) {
  2569. if (!chip->config) {
  2570. chip->config = &exynos_gpio_cfg;
  2571. chip->group = group++;
  2572. }
  2573. exynos_gpiolib_attach_ofnode(chip,
  2574. EXYNOS4_PA_GPIO1, i * 0x20);
  2575. }
  2576. samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
  2577. nr_chips, gpio_base1);
  2578. /* gpio part2 */
  2579. gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
  2580. if (gpio_base2 == NULL) {
  2581. pr_err("unable to ioremap for gpio_base2\n");
  2582. goto err_ioremap2;
  2583. }
  2584. /* need to set base address for gpx */
  2585. chip = &exynos4_gpios_2[16];
  2586. gpx_base = gpio_base2 + 0xC00;
  2587. for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
  2588. chip->base = gpx_base;
  2589. chip = exynos4_gpios_2;
  2590. nr_chips = ARRAY_SIZE(exynos4_gpios_2);
  2591. for (i = 0; i < nr_chips; i++, chip++) {
  2592. if (!chip->config) {
  2593. chip->config = &exynos_gpio_cfg;
  2594. chip->group = group++;
  2595. }
  2596. exynos_gpiolib_attach_ofnode(chip,
  2597. EXYNOS4_PA_GPIO2, i * 0x20);
  2598. }
  2599. samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
  2600. nr_chips, gpio_base2);
  2601. /* gpio part3 */
  2602. gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
  2603. if (gpio_base3 == NULL) {
  2604. pr_err("unable to ioremap for gpio_base3\n");
  2605. goto err_ioremap3;
  2606. }
  2607. chip = exynos4_gpios_3;
  2608. nr_chips = ARRAY_SIZE(exynos4_gpios_3);
  2609. for (i = 0; i < nr_chips; i++, chip++) {
  2610. if (!chip->config) {
  2611. chip->config = &exynos_gpio_cfg;
  2612. chip->group = group++;
  2613. }
  2614. exynos_gpiolib_attach_ofnode(chip,
  2615. EXYNOS4_PA_GPIO3, i * 0x20);
  2616. }
  2617. samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
  2618. nr_chips, gpio_base3);
  2619. #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
  2620. s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
  2621. s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
  2622. #endif
  2623. return;
  2624. err_ioremap3:
  2625. iounmap(gpio_base2);
  2626. err_ioremap2:
  2627. iounmap(gpio_base1);
  2628. err_ioremap1:
  2629. return;
  2630. #endif /* CONFIG_CPU_EXYNOS4210 */
  2631. }
  2632. static __init void exynos5_gpiolib_init(void)
  2633. {
  2634. #ifdef CONFIG_SOC_EXYNOS5250
  2635. struct samsung_gpio_chip *chip;
  2636. int i, nr_chips;
  2637. void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
  2638. int group = 0;
  2639. void __iomem *gpx_base;
  2640. /* gpio part1 */
  2641. gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
  2642. if (gpio_base1 == NULL) {
  2643. pr_err("unable to ioremap for gpio_base1\n");
  2644. goto err_ioremap1;
  2645. }
  2646. /* need to set base address for gpc4 */
  2647. exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
  2648. /* need to set base address for gpx */
  2649. chip = &exynos5_gpios_1[21];
  2650. gpx_base = gpio_base1 + 0xC00;
  2651. for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
  2652. chip->base = gpx_base;
  2653. chip = exynos5_gpios_1;
  2654. nr_chips = ARRAY_SIZE(exynos5_gpios_1);
  2655. for (i = 0; i < nr_chips; i++, chip++) {
  2656. if (!chip->config) {
  2657. chip->config = &exynos_gpio_cfg;
  2658. chip->group = group++;
  2659. }
  2660. exynos_gpiolib_attach_ofnode(chip,
  2661. EXYNOS5_PA_GPIO1, i * 0x20);
  2662. }
  2663. samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
  2664. nr_chips, gpio_base1);
  2665. /* gpio part2 */
  2666. gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
  2667. if (gpio_base2 == NULL) {
  2668. pr_err("unable to ioremap for gpio_base2\n");
  2669. goto err_ioremap2;
  2670. }
  2671. chip = exynos5_gpios_2;
  2672. nr_chips = ARRAY_SIZE(exynos5_gpios_2);
  2673. for (i = 0; i < nr_chips; i++, chip++) {
  2674. if (!chip->config) {
  2675. chip->config = &exynos_gpio_cfg;
  2676. chip->group = group++;
  2677. }
  2678. exynos_gpiolib_attach_ofnode(chip,
  2679. EXYNOS5_PA_GPIO2, i * 0x20);
  2680. }
  2681. samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
  2682. nr_chips, gpio_base2);
  2683. /* gpio part3 */
  2684. gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
  2685. if (gpio_base3 == NULL) {
  2686. pr_err("unable to ioremap for gpio_base3\n");
  2687. goto err_ioremap3;
  2688. }
  2689. /* need to set base address for gpv */
  2690. exynos5_gpios_3[0].base = gpio_base3;
  2691. exynos5_gpios_3[1].base = gpio_base3 + 0x20;
  2692. exynos5_gpios_3[2].base = gpio_base3 + 0x60;
  2693. exynos5_gpios_3[3].base = gpio_base3 + 0x80;
  2694. exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
  2695. chip = exynos5_gpios_3;
  2696. nr_chips = ARRAY_SIZE(exynos5_gpios_3);
  2697. for (i = 0; i < nr_chips; i++, chip++) {
  2698. if (!chip->config) {
  2699. chip->config = &exynos_gpio_cfg;
  2700. chip->group = group++;
  2701. }
  2702. exynos_gpiolib_attach_ofnode(chip,
  2703. EXYNOS5_PA_GPIO3, i * 0x20);
  2704. }
  2705. samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
  2706. nr_chips, gpio_base3);
  2707. /* gpio part4 */
  2708. gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
  2709. if (gpio_base4 == NULL) {
  2710. pr_err("unable to ioremap for gpio_base4\n");
  2711. goto err_ioremap4;
  2712. }
  2713. chip = exynos5_gpios_4;
  2714. nr_chips = ARRAY_SIZE(exynos5_gpios_4);
  2715. for (i = 0; i < nr_chips; i++, chip++) {
  2716. if (!chip->config) {
  2717. chip->config = &exynos_gpio_cfg;
  2718. chip->group = group++;
  2719. }
  2720. exynos_gpiolib_attach_ofnode(chip,
  2721. EXYNOS5_PA_GPIO4, i * 0x20);
  2722. }
  2723. samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
  2724. nr_chips, gpio_base4);
  2725. return;
  2726. err_ioremap4:
  2727. iounmap(gpio_base3);
  2728. err_ioremap3:
  2729. iounmap(gpio_base2);
  2730. err_ioremap2:
  2731. iounmap(gpio_base1);
  2732. err_ioremap1:
  2733. return;
  2734. #endif /* CONFIG_SOC_EXYNOS5250 */
  2735. }
  2736. /* TODO: cleanup soc_is_* */
  2737. static __init int samsung_gpiolib_init(void)
  2738. {
  2739. struct samsung_gpio_chip *chip;
  2740. int i, nr_chips;
  2741. int group = 0;
  2742. #if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
  2743. /*
  2744. * This gpio driver includes support for device tree support and there
  2745. * are platforms using it. In order to maintain compatibility with those
  2746. * platforms, and to allow non-dt Exynos4210 platforms to use this
  2747. * gpiolib support, a check is added to find out if there is a active
  2748. * pin-controller driver support available. If it is available, this
  2749. * gpiolib support is ignored and the gpiolib support available in
  2750. * pin-controller driver is used. This is a temporary check and will go
  2751. * away when all of the Exynos4210 platforms have switched to using
  2752. * device tree and the pin-ctrl driver.
  2753. */
  2754. struct device_node *pctrl_np;
  2755. static const struct of_device_id exynos_pinctrl_ids[] = {
  2756. { .compatible = "samsung,pinctrl-exynos4210", },
  2757. { .compatible = "samsung,pinctrl-exynos4x12", },
  2758. { .compatible = "samsung,pinctrl-exynos5440", },
  2759. };
  2760. for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
  2761. if (pctrl_np && of_device_is_available(pctrl_np))
  2762. return -ENODEV;
  2763. #endif
  2764. samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
  2765. if (soc_is_s3c24xx()) {
  2766. s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
  2767. ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
  2768. } else if (soc_is_s3c64xx()) {
  2769. samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
  2770. ARRAY_SIZE(s3c64xx_gpios_2bit),
  2771. S3C64XX_VA_GPIO + 0xE0, 0x20);
  2772. samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
  2773. ARRAY_SIZE(s3c64xx_gpios_4bit),
  2774. S3C64XX_VA_GPIO);
  2775. samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
  2776. ARRAY_SIZE(s3c64xx_gpios_4bit2));
  2777. } else if (soc_is_s5p6440()) {
  2778. samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
  2779. ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
  2780. samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
  2781. ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
  2782. samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
  2783. ARRAY_SIZE(s5p6440_gpios_4bit2));
  2784. s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
  2785. ARRAY_SIZE(s5p6440_gpios_rbank));
  2786. } else if (soc_is_s5p6450()) {
  2787. samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
  2788. ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
  2789. samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
  2790. ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
  2791. samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
  2792. ARRAY_SIZE(s5p6450_gpios_4bit2));
  2793. s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
  2794. ARRAY_SIZE(s5p6450_gpios_rbank));
  2795. } else if (soc_is_s5pc100()) {
  2796. group = 0;
  2797. chip = s5pc100_gpios_4bit;
  2798. nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
  2799. for (i = 0; i < nr_chips; i++, chip++) {
  2800. if (!chip->config) {
  2801. chip->config = &samsung_gpio_cfgs[3];
  2802. chip->group = group++;
  2803. }
  2804. }
  2805. samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
  2806. #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
  2807. s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
  2808. #endif
  2809. } else if (soc_is_s5pv210()) {
  2810. group = 0;
  2811. chip = s5pv210_gpios_4bit;
  2812. nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
  2813. for (i = 0; i < nr_chips; i++, chip++) {
  2814. if (!chip->config) {
  2815. chip->config = &samsung_gpio_cfgs[3];
  2816. chip->group = group++;
  2817. }
  2818. }
  2819. samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
  2820. #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
  2821. s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
  2822. #endif
  2823. } else if (soc_is_exynos4210()) {
  2824. exynos4_gpiolib_init();
  2825. } else if (soc_is_exynos5250()) {
  2826. exynos5_gpiolib_init();
  2827. } else {
  2828. WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
  2829. return -ENODEV;
  2830. }
  2831. return 0;
  2832. }
  2833. core_initcall(samsung_gpiolib_init);
  2834. int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
  2835. {
  2836. struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
  2837. unsigned long flags;
  2838. int offset;
  2839. int ret;
  2840. if (!chip)
  2841. return -EINVAL;
  2842. offset = pin - chip->chip.base;
  2843. samsung_gpio_lock(chip, flags);
  2844. ret = samsung_gpio_do_setcfg(chip, offset, config);
  2845. samsung_gpio_unlock(chip, flags);
  2846. return ret;
  2847. }
  2848. EXPORT_SYMBOL(s3c_gpio_cfgpin);
  2849. int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
  2850. unsigned int cfg)
  2851. {
  2852. int ret;
  2853. for (; nr > 0; nr--, start++) {
  2854. ret = s3c_gpio_cfgpin(start, cfg);
  2855. if (ret != 0)
  2856. return ret;
  2857. }
  2858. return 0;
  2859. }
  2860. EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
  2861. int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
  2862. unsigned int cfg, samsung_gpio_pull_t pull)
  2863. {
  2864. int ret;
  2865. for (; nr > 0; nr--, start++) {
  2866. s3c_gpio_setpull(start, pull);
  2867. ret = s3c_gpio_cfgpin(start, cfg);
  2868. if (ret != 0)
  2869. return ret;
  2870. }
  2871. return 0;
  2872. }
  2873. EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
  2874. unsigned s3c_gpio_getcfg(unsigned int pin)
  2875. {
  2876. struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
  2877. unsigned long flags;
  2878. unsigned ret = 0;
  2879. int offset;
  2880. if (chip) {
  2881. offset = pin - chip->chip.base;
  2882. samsung_gpio_lock(chip, flags);
  2883. ret = samsung_gpio_do_getcfg(chip, offset);
  2884. samsung_gpio_unlock(chip, flags);
  2885. }
  2886. return ret;
  2887. }
  2888. EXPORT_SYMBOL(s3c_gpio_getcfg);
  2889. int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
  2890. {
  2891. struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
  2892. unsigned long flags;
  2893. int offset, ret;
  2894. if (!chip)
  2895. return -EINVAL;
  2896. offset = pin - chip->chip.base;
  2897. samsung_gpio_lock(chip, flags);
  2898. ret = samsung_gpio_do_setpull(chip, offset, pull);
  2899. samsung_gpio_unlock(chip, flags);
  2900. return ret;
  2901. }
  2902. EXPORT_SYMBOL(s3c_gpio_setpull);
  2903. samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
  2904. {
  2905. struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
  2906. unsigned long flags;
  2907. int offset;
  2908. u32 pup = 0;
  2909. if (chip) {
  2910. offset = pin - chip->chip.base;
  2911. samsung_gpio_lock(chip, flags);
  2912. pup = samsung_gpio_do_getpull(chip, offset);
  2913. samsung_gpio_unlock(chip, flags);
  2914. }
  2915. return (__force samsung_gpio_pull_t)pup;
  2916. }
  2917. EXPORT_SYMBOL(s3c_gpio_getpull);
  2918. #ifdef CONFIG_S5P_GPIO_DRVSTR
  2919. s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
  2920. {
  2921. struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
  2922. unsigned int off;
  2923. void __iomem *reg;
  2924. int shift;
  2925. u32 drvstr;
  2926. if (!chip)
  2927. return -EINVAL;
  2928. off = pin - chip->chip.base;
  2929. shift = off * 2;
  2930. reg = chip->base + 0x0C;
  2931. drvstr = __raw_readl(reg);
  2932. drvstr = drvstr >> shift;
  2933. drvstr &= 0x3;
  2934. return (__force s5p_gpio_drvstr_t)drvstr;
  2935. }
  2936. EXPORT_SYMBOL(s5p_gpio_get_drvstr);
  2937. int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
  2938. {
  2939. struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
  2940. unsigned int off;
  2941. void __iomem *reg;
  2942. int shift;
  2943. u32 tmp;
  2944. if (!chip)
  2945. return -EINVAL;
  2946. off = pin - chip->chip.base;
  2947. shift = off * 2;
  2948. reg = chip->base + 0x0C;
  2949. tmp = __raw_readl(reg);
  2950. tmp &= ~(0x3 << shift);
  2951. tmp |= drvstr << shift;
  2952. __raw_writel(tmp, reg);
  2953. return 0;
  2954. }
  2955. EXPORT_SYMBOL(s5p_gpio_set_drvstr);
  2956. #endif /* CONFIG_S5P_GPIO_DRVSTR */
  2957. #ifdef CONFIG_PLAT_S3C24XX
  2958. unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
  2959. {
  2960. unsigned long flags;
  2961. unsigned long misccr;
  2962. local_irq_save(flags);
  2963. misccr = __raw_readl(S3C24XX_MISCCR);
  2964. misccr &= ~clear;
  2965. misccr ^= change;
  2966. __raw_writel(misccr, S3C24XX_MISCCR);
  2967. local_irq_restore(flags);
  2968. return misccr;
  2969. }
  2970. EXPORT_SYMBOL(s3c2410_modify_misccr);
  2971. #endif