mci.c 21 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 55, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. if (list_empty(&mci->info))
  27. return NULL;
  28. list_for_each_entry(entry, &mci->info, list) {
  29. if (entry->conn_handle == info->conn_handle)
  30. return entry;
  31. }
  32. return NULL;
  33. }
  34. static bool ath_mci_add_profile(struct ath_common *common,
  35. struct ath_mci_profile *mci,
  36. struct ath_mci_profile_info *info)
  37. {
  38. struct ath_mci_profile_info *entry;
  39. u8 voice_priority[] = { 110, 110, 110, 112, 110, 110, 114, 116, 118 };
  40. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  41. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  42. return false;
  43. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  44. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  45. return false;
  46. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  47. if (!entry)
  48. return false;
  49. memcpy(entry, info, 10);
  50. INC_PROF(mci, info);
  51. list_add_tail(&entry->list, &mci->info);
  52. if (info->type == MCI_GPM_COEX_PROFILE_VOICE) {
  53. if (info->voice_type < sizeof(voice_priority))
  54. mci->voice_priority = voice_priority[info->voice_type];
  55. else
  56. mci->voice_priority = 110;
  57. }
  58. return true;
  59. }
  60. static void ath_mci_del_profile(struct ath_common *common,
  61. struct ath_mci_profile *mci,
  62. struct ath_mci_profile_info *entry)
  63. {
  64. if (!entry)
  65. return;
  66. DEC_PROF(mci, entry);
  67. list_del(&entry->list);
  68. kfree(entry);
  69. }
  70. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  71. {
  72. struct ath_mci_profile_info *info, *tinfo;
  73. mci->aggr_limit = 0;
  74. mci->num_mgmt = 0;
  75. if (list_empty(&mci->info))
  76. return;
  77. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  78. list_del(&info->list);
  79. DEC_PROF(mci, info);
  80. kfree(info);
  81. }
  82. }
  83. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  84. {
  85. struct ath_mci_profile *mci = &btcoex->mci;
  86. u32 wlan_airtime = btcoex->btcoex_period *
  87. (100 - btcoex->duty_cycle) / 100;
  88. /*
  89. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  90. * When wlan_airtime is less than 4ms, aggregation limit has to be
  91. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  92. * without collision with BT traffic.
  93. */
  94. if ((wlan_airtime <= 4) &&
  95. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  96. mci->aggr_limit = 2 * wlan_airtime;
  97. }
  98. static void ath_mci_update_scheme(struct ath_softc *sc)
  99. {
  100. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  101. struct ath_btcoex *btcoex = &sc->btcoex;
  102. struct ath_mci_profile *mci = &btcoex->mci;
  103. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  104. struct ath_mci_profile_info *info;
  105. u32 num_profile = NUM_PROF(mci);
  106. if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_TUNING)
  107. goto skip_tuning;
  108. mci->aggr_limit = 0;
  109. btcoex->duty_cycle = ath_mci_duty_cycle[num_profile];
  110. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  111. if (NUM_PROF(mci))
  112. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  113. else
  114. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  115. ATH_BTCOEX_STOMP_LOW;
  116. if (num_profile == 1) {
  117. info = list_first_entry(&mci->info,
  118. struct ath_mci_profile_info,
  119. list);
  120. if (mci->num_sco) {
  121. if (info->T == 12)
  122. mci->aggr_limit = 8;
  123. else if (info->T == 6) {
  124. mci->aggr_limit = 6;
  125. btcoex->duty_cycle = 30;
  126. } else
  127. mci->aggr_limit = 6;
  128. ath_dbg(common, MCI,
  129. "Single SCO, aggregation limit %d 1/4 ms\n",
  130. mci->aggr_limit);
  131. } else if (mci->num_pan || mci->num_other_acl) {
  132. /*
  133. * For single PAN/FTP profile, allocate 35% for BT
  134. * to improve WLAN throughput.
  135. */
  136. btcoex->duty_cycle = AR_SREV_9565(sc->sc_ah) ? 40 : 35;
  137. btcoex->btcoex_period = 53;
  138. ath_dbg(common, MCI,
  139. "Single PAN/FTP bt period %d ms dutycycle %d\n",
  140. btcoex->duty_cycle, btcoex->btcoex_period);
  141. } else if (mci->num_hid) {
  142. btcoex->duty_cycle = 30;
  143. mci->aggr_limit = 6;
  144. ath_dbg(common, MCI,
  145. "Multiple attempt/timeout single HID "
  146. "aggregation limit 1.5 ms dutycycle 30%%\n");
  147. }
  148. } else if (num_profile == 2) {
  149. if (mci->num_hid == 2)
  150. btcoex->duty_cycle = 30;
  151. mci->aggr_limit = 6;
  152. ath_dbg(common, MCI,
  153. "Two BT profiles aggr limit 1.5 ms dutycycle %d%%\n",
  154. btcoex->duty_cycle);
  155. } else if (num_profile >= 3) {
  156. mci->aggr_limit = 4;
  157. ath_dbg(common, MCI,
  158. "Three or more profiles aggregation limit 1 ms\n");
  159. }
  160. skip_tuning:
  161. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  162. if (IS_CHAN_HT(sc->sc_ah->curchan))
  163. ath_mci_adjust_aggr_limit(btcoex);
  164. else
  165. btcoex->btcoex_period >>= 1;
  166. }
  167. ath9k_btcoex_timer_pause(sc);
  168. ath9k_hw_btcoex_disable(sc->sc_ah);
  169. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  170. return;
  171. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_BDR_DUTY_CYCLE : 0);
  172. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  173. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  174. btcoex->btcoex_no_stomp = btcoex->btcoex_period * 1000 *
  175. (100 - btcoex->duty_cycle) / 100;
  176. ath9k_hw_btcoex_enable(sc->sc_ah);
  177. ath9k_btcoex_timer_resume(sc);
  178. }
  179. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  180. {
  181. struct ath_hw *ah = sc->sc_ah;
  182. struct ath_common *common = ath9k_hw_common(ah);
  183. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  184. u32 payload[4] = {0, 0, 0, 0};
  185. switch (opcode) {
  186. case MCI_GPM_BT_CAL_REQ:
  187. if (mci_hw->bt_state == MCI_BT_AWAKE) {
  188. mci_hw->bt_state = MCI_BT_CAL_START;
  189. ath9k_queue_reset(sc, RESET_TYPE_MCI);
  190. }
  191. ath_dbg(common, MCI, "MCI State : %d\n", mci_hw->bt_state);
  192. break;
  193. case MCI_GPM_BT_CAL_GRANT:
  194. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  195. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  196. 16, false, true);
  197. break;
  198. default:
  199. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  200. break;
  201. }
  202. }
  203. static void ath9k_mci_work(struct work_struct *work)
  204. {
  205. struct ath_softc *sc = container_of(work, struct ath_softc, mci_work);
  206. ath_mci_update_scheme(sc);
  207. }
  208. static void ath_mci_update_stomp_txprio(u8 cur_txprio, u8 *stomp_prio)
  209. {
  210. if (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_NONE])
  211. stomp_prio[ATH_BTCOEX_STOMP_NONE] = cur_txprio;
  212. if (cur_txprio > stomp_prio[ATH_BTCOEX_STOMP_ALL])
  213. stomp_prio[ATH_BTCOEX_STOMP_ALL] = cur_txprio;
  214. if ((cur_txprio > ATH_MCI_HI_PRIO) &&
  215. (cur_txprio < stomp_prio[ATH_BTCOEX_STOMP_LOW]))
  216. stomp_prio[ATH_BTCOEX_STOMP_LOW] = cur_txprio;
  217. }
  218. static void ath_mci_set_concur_txprio(struct ath_softc *sc)
  219. {
  220. struct ath_btcoex *btcoex = &sc->btcoex;
  221. struct ath_mci_profile *mci = &btcoex->mci;
  222. u8 stomp_txprio[] = { 0, 0, 0, 0 }; /* all, low, none, low_ftp */
  223. if (mci->num_mgmt) {
  224. stomp_txprio[ATH_BTCOEX_STOMP_ALL] = ATH_MCI_INQUIRY_PRIO;
  225. if (!mci->num_pan && !mci->num_other_acl)
  226. stomp_txprio[ATH_BTCOEX_STOMP_NONE] =
  227. ATH_MCI_INQUIRY_PRIO;
  228. } else {
  229. u8 prof_prio[] = { 50, 90, 94, 52 };/* RFCOMM, A2DP, HID, PAN */
  230. stomp_txprio[ATH_BTCOEX_STOMP_LOW] =
  231. stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0xff;
  232. if (mci->num_sco)
  233. ath_mci_update_stomp_txprio(mci->voice_priority,
  234. stomp_txprio);
  235. if (mci->num_other_acl)
  236. ath_mci_update_stomp_txprio(prof_prio[0], stomp_txprio);
  237. if (mci->num_a2dp)
  238. ath_mci_update_stomp_txprio(prof_prio[1], stomp_txprio);
  239. if (mci->num_hid)
  240. ath_mci_update_stomp_txprio(prof_prio[2], stomp_txprio);
  241. if (mci->num_pan)
  242. ath_mci_update_stomp_txprio(prof_prio[3], stomp_txprio);
  243. if (stomp_txprio[ATH_BTCOEX_STOMP_NONE] == 0xff)
  244. stomp_txprio[ATH_BTCOEX_STOMP_NONE] = 0;
  245. if (stomp_txprio[ATH_BTCOEX_STOMP_LOW] == 0xff)
  246. stomp_txprio[ATH_BTCOEX_STOMP_LOW] = 0;
  247. }
  248. ath9k_hw_btcoex_set_concur_txprio(sc->sc_ah, stomp_txprio);
  249. }
  250. static u8 ath_mci_process_profile(struct ath_softc *sc,
  251. struct ath_mci_profile_info *info)
  252. {
  253. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  254. struct ath_btcoex *btcoex = &sc->btcoex;
  255. struct ath_mci_profile *mci = &btcoex->mci;
  256. struct ath_mci_profile_info *entry = NULL;
  257. entry = ath_mci_find_profile(mci, info);
  258. if (entry) {
  259. /*
  260. * Two MCI interrupts are generated while connecting to
  261. * headset and A2DP profile, but only one MCI interrupt
  262. * is generated with last added profile type while disconnecting
  263. * both profiles.
  264. * So while adding second profile type decrement
  265. * the first one.
  266. */
  267. if (entry->type != info->type) {
  268. DEC_PROF(mci, entry);
  269. INC_PROF(mci, info);
  270. }
  271. memcpy(entry, info, 10);
  272. }
  273. if (info->start) {
  274. if (!entry && !ath_mci_add_profile(common, mci, info))
  275. return 0;
  276. } else
  277. ath_mci_del_profile(common, mci, entry);
  278. ath_mci_set_concur_txprio(sc);
  279. return 1;
  280. }
  281. static u8 ath_mci_process_status(struct ath_softc *sc,
  282. struct ath_mci_profile_status *status)
  283. {
  284. struct ath_btcoex *btcoex = &sc->btcoex;
  285. struct ath_mci_profile *mci = &btcoex->mci;
  286. struct ath_mci_profile_info info;
  287. int i = 0, old_num_mgmt = mci->num_mgmt;
  288. /* Link status type are not handled */
  289. if (status->is_link)
  290. return 0;
  291. info.conn_handle = status->conn_handle;
  292. if (ath_mci_find_profile(mci, &info))
  293. return 0;
  294. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  295. return 0;
  296. if (status->is_critical)
  297. __set_bit(status->conn_handle, mci->status);
  298. else
  299. __clear_bit(status->conn_handle, mci->status);
  300. mci->num_mgmt = 0;
  301. do {
  302. if (test_bit(i, mci->status))
  303. mci->num_mgmt++;
  304. } while (++i < ATH_MCI_MAX_PROFILE);
  305. ath_mci_set_concur_txprio(sc);
  306. if (old_num_mgmt != mci->num_mgmt)
  307. return 1;
  308. return 0;
  309. }
  310. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  311. {
  312. struct ath_hw *ah = sc->sc_ah;
  313. struct ath_mci_profile_info profile_info;
  314. struct ath_mci_profile_status profile_status;
  315. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  316. u8 major, minor, update_scheme = 0;
  317. u32 seq_num;
  318. if (ar9003_mci_state(ah, MCI_STATE_NEED_FLUSH_BT_INFO) &&
  319. ar9003_mci_state(ah, MCI_STATE_ENABLE)) {
  320. ath_dbg(common, MCI, "(MCI) Need to flush BT profiles\n");
  321. ath_mci_flush_profile(&sc->btcoex.mci);
  322. ar9003_mci_state(ah, MCI_STATE_SEND_STATUS_QUERY);
  323. }
  324. switch (opcode) {
  325. case MCI_GPM_COEX_VERSION_QUERY:
  326. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION);
  327. break;
  328. case MCI_GPM_COEX_VERSION_RESPONSE:
  329. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  330. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  331. ar9003_mci_set_bt_version(ah, major, minor);
  332. break;
  333. case MCI_GPM_COEX_STATUS_QUERY:
  334. ar9003_mci_send_wlan_channels(ah);
  335. break;
  336. case MCI_GPM_COEX_BT_PROFILE_INFO:
  337. memcpy(&profile_info,
  338. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  339. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  340. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  341. ath_dbg(common, MCI,
  342. "Illegal profile type = %d, state = %d\n",
  343. profile_info.type,
  344. profile_info.start);
  345. break;
  346. }
  347. update_scheme += ath_mci_process_profile(sc, &profile_info);
  348. break;
  349. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  350. profile_status.is_link = *(rx_payload +
  351. MCI_GPM_COEX_B_STATUS_TYPE);
  352. profile_status.conn_handle = *(rx_payload +
  353. MCI_GPM_COEX_B_STATUS_LINKID);
  354. profile_status.is_critical = *(rx_payload +
  355. MCI_GPM_COEX_B_STATUS_STATE);
  356. seq_num = *((u32 *)(rx_payload + 12));
  357. ath_dbg(common, MCI,
  358. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%u\n",
  359. profile_status.is_link, profile_status.conn_handle,
  360. profile_status.is_critical, seq_num);
  361. update_scheme += ath_mci_process_status(sc, &profile_status);
  362. break;
  363. default:
  364. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  365. break;
  366. }
  367. if (update_scheme)
  368. ieee80211_queue_work(sc->hw, &sc->mci_work);
  369. }
  370. int ath_mci_setup(struct ath_softc *sc)
  371. {
  372. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  373. struct ath_mci_coex *mci = &sc->mci_coex;
  374. struct ath_mci_buf *buf = &mci->sched_buf;
  375. int ret;
  376. buf->bf_addr = dma_alloc_coherent(sc->dev,
  377. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  378. &buf->bf_paddr, GFP_KERNEL);
  379. if (buf->bf_addr == NULL) {
  380. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  381. return -ENOMEM;
  382. }
  383. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  384. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  385. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  386. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  387. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  388. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  389. ret = ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  390. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  391. mci->sched_buf.bf_paddr);
  392. if (ret) {
  393. ath_err(common, "Failed to initialize MCI\n");
  394. return ret;
  395. }
  396. INIT_WORK(&sc->mci_work, ath9k_mci_work);
  397. ath_dbg(common, MCI, "MCI Initialized\n");
  398. return 0;
  399. }
  400. void ath_mci_cleanup(struct ath_softc *sc)
  401. {
  402. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  403. struct ath_hw *ah = sc->sc_ah;
  404. struct ath_mci_coex *mci = &sc->mci_coex;
  405. struct ath_mci_buf *buf = &mci->sched_buf;
  406. if (buf->bf_addr)
  407. dma_free_coherent(sc->dev,
  408. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  409. buf->bf_addr, buf->bf_paddr);
  410. ar9003_mci_cleanup(ah);
  411. ath_dbg(common, MCI, "MCI De-Initialized\n");
  412. }
  413. void ath_mci_intr(struct ath_softc *sc)
  414. {
  415. struct ath_mci_coex *mci = &sc->mci_coex;
  416. struct ath_hw *ah = sc->sc_ah;
  417. struct ath_common *common = ath9k_hw_common(ah);
  418. struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
  419. u32 mci_int, mci_int_rxmsg;
  420. u32 offset, subtype, opcode;
  421. u32 *pgpm;
  422. u32 more_data = MCI_GPM_MORE;
  423. bool skip_gpm = false;
  424. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  425. if (ar9003_mci_state(ah, MCI_STATE_ENABLE) == 0) {
  426. ar9003_mci_get_next_gpm_offset(ah, true, NULL);
  427. return;
  428. }
  429. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  430. u32 payload[4] = { 0xffffffff, 0xffffffff,
  431. 0xffffffff, 0xffffff00};
  432. /*
  433. * The following REMOTE_RESET and SYS_WAKING used to sent
  434. * only when BT wake up. Now they are always sent, as a
  435. * recovery method to reset BT MCI's RX alignment.
  436. */
  437. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  438. payload, 16, true, false);
  439. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  440. NULL, 0, true, false);
  441. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  442. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE);
  443. /*
  444. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  445. */
  446. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  447. }
  448. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  449. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  450. if ((mci_hw->bt_state == MCI_BT_SLEEP) &&
  451. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  452. MCI_BT_SLEEP))
  453. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE);
  454. }
  455. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  456. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  457. if ((mci_hw->bt_state == MCI_BT_AWAKE) &&
  458. (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP) !=
  459. MCI_BT_AWAKE))
  460. mci_hw->bt_state = MCI_BT_SLEEP;
  461. }
  462. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  463. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  464. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX);
  465. skip_gpm = true;
  466. }
  467. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  468. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  469. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET);
  470. }
  471. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  472. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  473. while (more_data == MCI_GPM_MORE) {
  474. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  475. return;
  476. pgpm = mci->gpm_buf.bf_addr;
  477. offset = ar9003_mci_get_next_gpm_offset(ah, false,
  478. &more_data);
  479. if (offset == MCI_GPM_INVALID)
  480. break;
  481. pgpm += (offset >> 2);
  482. /*
  483. * The first dword is timer.
  484. * The real data starts from 2nd dword.
  485. */
  486. subtype = MCI_GPM_TYPE(pgpm);
  487. opcode = MCI_GPM_OPCODE(pgpm);
  488. if (skip_gpm)
  489. goto recycle;
  490. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  491. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  492. } else {
  493. switch (subtype) {
  494. case MCI_GPM_COEX_AGENT:
  495. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  496. break;
  497. default:
  498. break;
  499. }
  500. }
  501. recycle:
  502. MCI_GPM_RECYCLE(pgpm);
  503. }
  504. }
  505. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  506. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  507. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  508. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  509. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  510. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  511. int value_dbm = MS(mci_hw->cont_status,
  512. AR_MCI_CONT_RSSI_POWER);
  513. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  514. ath_dbg(common, MCI,
  515. "MCI CONT_INFO: (%s) pri = %d pwr = %d dBm\n",
  516. MS(mci_hw->cont_status, AR_MCI_CONT_TXRX) ?
  517. "tx" : "rx",
  518. MS(mci_hw->cont_status, AR_MCI_CONT_PRIORITY),
  519. value_dbm);
  520. }
  521. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  522. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  523. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  524. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  525. }
  526. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  527. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  528. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  529. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  530. ath_mci_msg(sc, MCI_GPM_COEX_NOOP, NULL);
  531. }
  532. }
  533. void ath_mci_enable(struct ath_softc *sc)
  534. {
  535. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  536. if (!common->btcoex_enabled)
  537. return;
  538. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)
  539. sc->sc_ah->imask |= ATH9K_INT_MCI;
  540. }
  541. void ath9k_mci_update_wlan_channels(struct ath_softc *sc, bool allow_all)
  542. {
  543. struct ath_hw *ah = sc->sc_ah;
  544. struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
  545. struct ath9k_channel *chan = ah->curchan;
  546. u32 channelmap[] = {0x00000000, 0xffff0000, 0xffffffff, 0x7fffffff};
  547. int i;
  548. s16 chan_start, chan_end;
  549. u16 wlan_chan;
  550. if (!chan || !IS_CHAN_2GHZ(chan))
  551. return;
  552. if (allow_all)
  553. goto send_wlan_chan;
  554. wlan_chan = chan->channel - 2402;
  555. chan_start = wlan_chan - 10;
  556. chan_end = wlan_chan + 10;
  557. if (chan->chanmode == CHANNEL_G_HT40PLUS)
  558. chan_end += 20;
  559. else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  560. chan_start -= 20;
  561. /* adjust side band */
  562. chan_start -= 7;
  563. chan_end += 7;
  564. if (chan_start <= 0)
  565. chan_start = 0;
  566. if (chan_end >= ATH_MCI_NUM_BT_CHANNELS)
  567. chan_end = ATH_MCI_NUM_BT_CHANNELS - 1;
  568. ath_dbg(ath9k_hw_common(ah), MCI,
  569. "WLAN current channel %d mask BT channel %d - %d\n",
  570. wlan_chan, chan_start, chan_end);
  571. for (i = chan_start; i < chan_end; i++)
  572. MCI_GPM_CLR_CHANNEL_BIT(&channelmap, i);
  573. send_wlan_chan:
  574. /* update and send wlan channels info to BT */
  575. for (i = 0; i < 4; i++)
  576. mci->wlan_channels[i] = channelmap[i];
  577. ar9003_mci_send_wlan_channels(ah);
  578. ar9003_mci_state(ah, MCI_STATE_SEND_VERSION_QUERY);
  579. }
  580. void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
  581. bool concur_tx)
  582. {
  583. struct ath_hw *ah = sc->sc_ah;
  584. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  585. bool old_concur_tx = mci_hw->concur_tx;
  586. if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX)) {
  587. mci_hw->concur_tx = false;
  588. return;
  589. }
  590. if (!IS_CHAN_2GHZ(ah->curchan))
  591. return;
  592. if (setchannel) {
  593. struct ath9k_hw_cal_data *caldata = &sc->caldata;
  594. if ((caldata->chanmode == CHANNEL_G_HT40PLUS) &&
  595. (ah->curchan->channel > caldata->channel) &&
  596. (ah->curchan->channel <= caldata->channel + 20))
  597. return;
  598. if ((caldata->chanmode == CHANNEL_G_HT40MINUS) &&
  599. (ah->curchan->channel < caldata->channel) &&
  600. (ah->curchan->channel >= caldata->channel - 20))
  601. return;
  602. mci_hw->concur_tx = false;
  603. } else
  604. mci_hw->concur_tx = concur_tx;
  605. if (old_concur_tx != mci_hw->concur_tx)
  606. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
  607. }
  608. static void ath9k_mci_stomp_audio(struct ath_softc *sc)
  609. {
  610. struct ath_hw *ah = sc->sc_ah;
  611. struct ath_btcoex *btcoex = &sc->btcoex;
  612. struct ath_mci_profile *mci = &btcoex->mci;
  613. if (!mci->num_sco && !mci->num_a2dp)
  614. return;
  615. if (ah->stats.avgbrssi > 25) {
  616. btcoex->stomp_audio = 0;
  617. return;
  618. }
  619. btcoex->stomp_audio++;
  620. }
  621. void ath9k_mci_update_rssi(struct ath_softc *sc)
  622. {
  623. struct ath_hw *ah = sc->sc_ah;
  624. struct ath_btcoex *btcoex = &sc->btcoex;
  625. struct ath9k_hw_mci *mci_hw = &sc->sc_ah->btcoex_hw.mci;
  626. ath9k_mci_stomp_audio(sc);
  627. if (!(mci_hw->config & ATH_MCI_CONFIG_CONCUR_TX))
  628. return;
  629. if (ah->stats.avgbrssi >= 40) {
  630. if (btcoex->rssi_count < 0)
  631. btcoex->rssi_count = 0;
  632. if (++btcoex->rssi_count >= ATH_MCI_CONCUR_TX_SWITCH) {
  633. btcoex->rssi_count = 0;
  634. ath9k_mci_set_txpower(sc, false, true);
  635. }
  636. } else {
  637. if (btcoex->rssi_count > 0)
  638. btcoex->rssi_count = 0;
  639. if (--btcoex->rssi_count <= -ATH_MCI_CONCUR_TX_SWITCH) {
  640. btcoex->rssi_count = 0;
  641. ath9k_mci_set_txpower(sc, false, false);
  642. }
  643. }
  644. }