main.c 58 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408
  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath9k_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  243. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  244. ath9k_mci_set_txpower(sc, true, false);
  245. if (!ath_complete_reset(sc, true))
  246. r = -EIO;
  247. out:
  248. spin_unlock_bh(&sc->sc_pcu_lock);
  249. return r;
  250. }
  251. /*
  252. * Set/change channels. If the channel is really being changed, it's done
  253. * by reseting the chip. To accomplish this we must first cleanup any pending
  254. * DMA, then restart stuff.
  255. */
  256. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  257. struct ath9k_channel *hchan)
  258. {
  259. int r;
  260. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  261. return -EIO;
  262. r = ath_reset_internal(sc, hchan, false);
  263. return r;
  264. }
  265. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  266. struct ieee80211_vif *vif)
  267. {
  268. struct ath_node *an;
  269. u8 density;
  270. an = (struct ath_node *)sta->drv_priv;
  271. an->sta = sta;
  272. an->vif = vif;
  273. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  274. ath_tx_node_init(sc, an);
  275. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  276. sta->ht_cap.ampdu_factor);
  277. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  278. an->mpdudensity = density;
  279. }
  280. }
  281. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  282. {
  283. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  284. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  285. ath_tx_node_cleanup(sc, an);
  286. }
  287. void ath9k_tasklet(unsigned long data)
  288. {
  289. struct ath_softc *sc = (struct ath_softc *)data;
  290. struct ath_hw *ah = sc->sc_ah;
  291. struct ath_common *common = ath9k_hw_common(ah);
  292. enum ath_reset_type type;
  293. unsigned long flags;
  294. u32 status = sc->intrstatus;
  295. u32 rxmask;
  296. ath9k_ps_wakeup(sc);
  297. spin_lock(&sc->sc_pcu_lock);
  298. if ((status & ATH9K_INT_FATAL) ||
  299. (status & ATH9K_INT_BB_WATCHDOG)) {
  300. if (status & ATH9K_INT_FATAL)
  301. type = RESET_TYPE_FATAL_INT;
  302. else
  303. type = RESET_TYPE_BB_WATCHDOG;
  304. ath9k_queue_reset(sc, type);
  305. goto out;
  306. }
  307. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  308. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  309. /*
  310. * TSF sync does not look correct; remain awake to sync with
  311. * the next Beacon.
  312. */
  313. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  314. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  315. }
  316. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  317. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  318. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  319. ATH9K_INT_RXORN);
  320. else
  321. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  322. if (status & rxmask) {
  323. /* Check for high priority Rx first */
  324. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  325. (status & ATH9K_INT_RXHP))
  326. ath_rx_tasklet(sc, 0, true);
  327. ath_rx_tasklet(sc, 0, false);
  328. }
  329. if (status & ATH9K_INT_TX) {
  330. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  331. ath_tx_edma_tasklet(sc);
  332. else
  333. ath_tx_tasklet(sc);
  334. }
  335. ath9k_btcoex_handle_interrupt(sc, status);
  336. out:
  337. /* re-enable hardware interrupt */
  338. ath9k_hw_enable_interrupts(ah);
  339. spin_unlock(&sc->sc_pcu_lock);
  340. ath9k_ps_restore(sc);
  341. }
  342. irqreturn_t ath_isr(int irq, void *dev)
  343. {
  344. #define SCHED_INTR ( \
  345. ATH9K_INT_FATAL | \
  346. ATH9K_INT_BB_WATCHDOG | \
  347. ATH9K_INT_RXORN | \
  348. ATH9K_INT_RXEOL | \
  349. ATH9K_INT_RX | \
  350. ATH9K_INT_RXLP | \
  351. ATH9K_INT_RXHP | \
  352. ATH9K_INT_TX | \
  353. ATH9K_INT_BMISS | \
  354. ATH9K_INT_CST | \
  355. ATH9K_INT_TSFOOR | \
  356. ATH9K_INT_GENTIMER | \
  357. ATH9K_INT_MCI)
  358. struct ath_softc *sc = dev;
  359. struct ath_hw *ah = sc->sc_ah;
  360. struct ath_common *common = ath9k_hw_common(ah);
  361. enum ath9k_int status;
  362. bool sched = false;
  363. /*
  364. * The hardware is not ready/present, don't
  365. * touch anything. Note this can happen early
  366. * on if the IRQ is shared.
  367. */
  368. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  369. return IRQ_NONE;
  370. /* shared irq, not for us */
  371. if (!ath9k_hw_intrpend(ah))
  372. return IRQ_NONE;
  373. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  374. ath9k_hw_kill_interrupts(ah);
  375. return IRQ_HANDLED;
  376. }
  377. /*
  378. * Figure out the reason(s) for the interrupt. Note
  379. * that the hal returns a pseudo-ISR that may include
  380. * bits we haven't explicitly enabled so we mask the
  381. * value to insure we only process bits we requested.
  382. */
  383. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  384. status &= ah->imask; /* discard unasked-for bits */
  385. /*
  386. * If there are no status bits set, then this interrupt was not
  387. * for me (should have been caught above).
  388. */
  389. if (!status)
  390. return IRQ_NONE;
  391. /* Cache the status */
  392. sc->intrstatus = status;
  393. if (status & SCHED_INTR)
  394. sched = true;
  395. /*
  396. * If a FATAL or RXORN interrupt is received, we have to reset the
  397. * chip immediately.
  398. */
  399. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  400. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  401. goto chip_reset;
  402. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  403. (status & ATH9K_INT_BB_WATCHDOG)) {
  404. spin_lock(&common->cc_lock);
  405. ath_hw_cycle_counters_update(common);
  406. ar9003_hw_bb_watchdog_dbg_info(ah);
  407. spin_unlock(&common->cc_lock);
  408. goto chip_reset;
  409. }
  410. #ifdef CONFIG_PM_SLEEP
  411. if (status & ATH9K_INT_BMISS) {
  412. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  413. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  414. atomic_inc(&sc->wow_got_bmiss_intr);
  415. atomic_dec(&sc->wow_sleep_proc_intr);
  416. }
  417. }
  418. #endif
  419. if (status & ATH9K_INT_SWBA)
  420. tasklet_schedule(&sc->bcon_tasklet);
  421. if (status & ATH9K_INT_TXURN)
  422. ath9k_hw_updatetxtriglevel(ah, true);
  423. if (status & ATH9K_INT_RXEOL) {
  424. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  425. ath9k_hw_set_interrupts(ah);
  426. }
  427. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  428. if (status & ATH9K_INT_TIM_TIMER) {
  429. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  430. goto chip_reset;
  431. /* Clear RxAbort bit so that we can
  432. * receive frames */
  433. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  434. spin_lock(&sc->sc_pm_lock);
  435. ath9k_hw_setrxabort(sc->sc_ah, 0);
  436. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  437. spin_unlock(&sc->sc_pm_lock);
  438. }
  439. chip_reset:
  440. ath_debug_stat_interrupt(sc, status);
  441. if (sched) {
  442. /* turn off every interrupt */
  443. ath9k_hw_disable_interrupts(ah);
  444. tasklet_schedule(&sc->intr_tq);
  445. }
  446. return IRQ_HANDLED;
  447. #undef SCHED_INTR
  448. }
  449. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  450. {
  451. int r;
  452. ath9k_ps_wakeup(sc);
  453. r = ath_reset_internal(sc, NULL, retry_tx);
  454. if (retry_tx) {
  455. int i;
  456. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  457. if (ATH_TXQ_SETUP(sc, i)) {
  458. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  459. ath_txq_schedule(sc, &sc->tx.txq[i]);
  460. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  461. }
  462. }
  463. }
  464. ath9k_ps_restore(sc);
  465. return r;
  466. }
  467. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  468. {
  469. #ifdef CONFIG_ATH9K_DEBUGFS
  470. RESET_STAT_INC(sc, type);
  471. #endif
  472. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  473. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  474. }
  475. void ath_reset_work(struct work_struct *work)
  476. {
  477. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  478. ath_reset(sc, true);
  479. }
  480. /**********************/
  481. /* mac80211 callbacks */
  482. /**********************/
  483. static int ath9k_start(struct ieee80211_hw *hw)
  484. {
  485. struct ath_softc *sc = hw->priv;
  486. struct ath_hw *ah = sc->sc_ah;
  487. struct ath_common *common = ath9k_hw_common(ah);
  488. struct ieee80211_channel *curchan = hw->conf.channel;
  489. struct ath9k_channel *init_channel;
  490. int r;
  491. ath_dbg(common, CONFIG,
  492. "Starting driver with initial channel: %d MHz\n",
  493. curchan->center_freq);
  494. ath9k_ps_wakeup(sc);
  495. mutex_lock(&sc->mutex);
  496. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  497. /* Reset SERDES registers */
  498. ath9k_hw_configpcipowersave(ah, false);
  499. /*
  500. * The basic interface to setting the hardware in a good
  501. * state is ``reset''. On return the hardware is known to
  502. * be powered up and with interrupts disabled. This must
  503. * be followed by initialization of the appropriate bits
  504. * and then setup of the interrupt mask.
  505. */
  506. spin_lock_bh(&sc->sc_pcu_lock);
  507. atomic_set(&ah->intr_ref_cnt, -1);
  508. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  509. if (r) {
  510. ath_err(common,
  511. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  512. r, curchan->center_freq);
  513. ah->reset_power_on = false;
  514. }
  515. /* Setup our intr mask. */
  516. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  517. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  518. ATH9K_INT_GLOBAL;
  519. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  520. ah->imask |= ATH9K_INT_RXHP |
  521. ATH9K_INT_RXLP |
  522. ATH9K_INT_BB_WATCHDOG;
  523. else
  524. ah->imask |= ATH9K_INT_RX;
  525. ah->imask |= ATH9K_INT_GTT;
  526. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  527. ah->imask |= ATH9K_INT_CST;
  528. ath_mci_enable(sc);
  529. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  530. sc->sc_ah->is_monitoring = false;
  531. if (!ath_complete_reset(sc, false))
  532. ah->reset_power_on = false;
  533. if (ah->led_pin >= 0) {
  534. ath9k_hw_cfg_output(ah, ah->led_pin,
  535. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  536. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  537. }
  538. /*
  539. * Reset key cache to sane defaults (all entries cleared) instead of
  540. * semi-random values after suspend/resume.
  541. */
  542. ath9k_cmn_init_crypto(sc->sc_ah);
  543. spin_unlock_bh(&sc->sc_pcu_lock);
  544. mutex_unlock(&sc->mutex);
  545. ath9k_ps_restore(sc);
  546. return 0;
  547. }
  548. static void ath9k_tx(struct ieee80211_hw *hw,
  549. struct ieee80211_tx_control *control,
  550. struct sk_buff *skb)
  551. {
  552. struct ath_softc *sc = hw->priv;
  553. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  554. struct ath_tx_control txctl;
  555. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  556. unsigned long flags;
  557. if (sc->ps_enabled) {
  558. /*
  559. * mac80211 does not set PM field for normal data frames, so we
  560. * need to update that based on the current PS mode.
  561. */
  562. if (ieee80211_is_data(hdr->frame_control) &&
  563. !ieee80211_is_nullfunc(hdr->frame_control) &&
  564. !ieee80211_has_pm(hdr->frame_control)) {
  565. ath_dbg(common, PS,
  566. "Add PM=1 for a TX frame while in PS mode\n");
  567. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  568. }
  569. }
  570. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  571. /*
  572. * We are using PS-Poll and mac80211 can request TX while in
  573. * power save mode. Need to wake up hardware for the TX to be
  574. * completed and if needed, also for RX of buffered frames.
  575. */
  576. ath9k_ps_wakeup(sc);
  577. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  578. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  579. ath9k_hw_setrxabort(sc->sc_ah, 0);
  580. if (ieee80211_is_pspoll(hdr->frame_control)) {
  581. ath_dbg(common, PS,
  582. "Sending PS-Poll to pick a buffered frame\n");
  583. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  584. } else {
  585. ath_dbg(common, PS, "Wake up to complete TX\n");
  586. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  587. }
  588. /*
  589. * The actual restore operation will happen only after
  590. * the ps_flags bit is cleared. We are just dropping
  591. * the ps_usecount here.
  592. */
  593. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  594. ath9k_ps_restore(sc);
  595. }
  596. /*
  597. * Cannot tx while the hardware is in full sleep, it first needs a full
  598. * chip reset to recover from that
  599. */
  600. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  601. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  602. goto exit;
  603. }
  604. memset(&txctl, 0, sizeof(struct ath_tx_control));
  605. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  606. txctl.sta = control->sta;
  607. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  608. if (ath_tx_start(hw, skb, &txctl) != 0) {
  609. ath_dbg(common, XMIT, "TX failed\n");
  610. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  611. goto exit;
  612. }
  613. return;
  614. exit:
  615. ieee80211_free_txskb(hw, skb);
  616. }
  617. static void ath9k_stop(struct ieee80211_hw *hw)
  618. {
  619. struct ath_softc *sc = hw->priv;
  620. struct ath_hw *ah = sc->sc_ah;
  621. struct ath_common *common = ath9k_hw_common(ah);
  622. bool prev_idle;
  623. mutex_lock(&sc->mutex);
  624. ath_cancel_work(sc);
  625. del_timer_sync(&sc->rx_poll_timer);
  626. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  627. ath_dbg(common, ANY, "Device not present\n");
  628. mutex_unlock(&sc->mutex);
  629. return;
  630. }
  631. /* Ensure HW is awake when we try to shut it down. */
  632. ath9k_ps_wakeup(sc);
  633. spin_lock_bh(&sc->sc_pcu_lock);
  634. /* prevent tasklets to enable interrupts once we disable them */
  635. ah->imask &= ~ATH9K_INT_GLOBAL;
  636. /* make sure h/w will not generate any interrupt
  637. * before setting the invalid flag. */
  638. ath9k_hw_disable_interrupts(ah);
  639. spin_unlock_bh(&sc->sc_pcu_lock);
  640. /* we can now sync irq and kill any running tasklets, since we already
  641. * disabled interrupts and not holding a spin lock */
  642. synchronize_irq(sc->irq);
  643. tasklet_kill(&sc->intr_tq);
  644. tasklet_kill(&sc->bcon_tasklet);
  645. prev_idle = sc->ps_idle;
  646. sc->ps_idle = true;
  647. spin_lock_bh(&sc->sc_pcu_lock);
  648. if (ah->led_pin >= 0) {
  649. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  650. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  651. }
  652. ath_prepare_reset(sc, false, true);
  653. if (sc->rx.frag) {
  654. dev_kfree_skb_any(sc->rx.frag);
  655. sc->rx.frag = NULL;
  656. }
  657. if (!ah->curchan)
  658. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  659. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  660. ath9k_hw_phy_disable(ah);
  661. ath9k_hw_configpcipowersave(ah, true);
  662. spin_unlock_bh(&sc->sc_pcu_lock);
  663. ath9k_ps_restore(sc);
  664. set_bit(SC_OP_INVALID, &sc->sc_flags);
  665. sc->ps_idle = prev_idle;
  666. mutex_unlock(&sc->mutex);
  667. ath_dbg(common, CONFIG, "Driver halt\n");
  668. }
  669. bool ath9k_uses_beacons(int type)
  670. {
  671. switch (type) {
  672. case NL80211_IFTYPE_AP:
  673. case NL80211_IFTYPE_ADHOC:
  674. case NL80211_IFTYPE_MESH_POINT:
  675. return true;
  676. default:
  677. return false;
  678. }
  679. }
  680. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  681. {
  682. struct ath9k_vif_iter_data *iter_data = data;
  683. int i;
  684. if (iter_data->hw_macaddr)
  685. for (i = 0; i < ETH_ALEN; i++)
  686. iter_data->mask[i] &=
  687. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  688. switch (vif->type) {
  689. case NL80211_IFTYPE_AP:
  690. iter_data->naps++;
  691. break;
  692. case NL80211_IFTYPE_STATION:
  693. iter_data->nstations++;
  694. break;
  695. case NL80211_IFTYPE_ADHOC:
  696. iter_data->nadhocs++;
  697. break;
  698. case NL80211_IFTYPE_MESH_POINT:
  699. iter_data->nmeshes++;
  700. break;
  701. case NL80211_IFTYPE_WDS:
  702. iter_data->nwds++;
  703. break;
  704. default:
  705. break;
  706. }
  707. }
  708. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  709. {
  710. struct ath_softc *sc = data;
  711. struct ath_vif *avp = (void *)vif->drv_priv;
  712. if (vif->type != NL80211_IFTYPE_STATION)
  713. return;
  714. if (avp->primary_sta_vif)
  715. ath9k_set_assoc_state(sc, vif);
  716. }
  717. /* Called with sc->mutex held. */
  718. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  719. struct ieee80211_vif *vif,
  720. struct ath9k_vif_iter_data *iter_data)
  721. {
  722. struct ath_softc *sc = hw->priv;
  723. struct ath_hw *ah = sc->sc_ah;
  724. struct ath_common *common = ath9k_hw_common(ah);
  725. /*
  726. * Use the hardware MAC address as reference, the hardware uses it
  727. * together with the BSSID mask when matching addresses.
  728. */
  729. memset(iter_data, 0, sizeof(*iter_data));
  730. iter_data->hw_macaddr = common->macaddr;
  731. memset(&iter_data->mask, 0xff, ETH_ALEN);
  732. if (vif)
  733. ath9k_vif_iter(iter_data, vif->addr, vif);
  734. /* Get list of all active MAC addresses */
  735. ieee80211_iterate_active_interfaces_atomic(
  736. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  737. ath9k_vif_iter, iter_data);
  738. }
  739. /* Called with sc->mutex held. */
  740. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  741. struct ieee80211_vif *vif)
  742. {
  743. struct ath_softc *sc = hw->priv;
  744. struct ath_hw *ah = sc->sc_ah;
  745. struct ath_common *common = ath9k_hw_common(ah);
  746. struct ath9k_vif_iter_data iter_data;
  747. enum nl80211_iftype old_opmode = ah->opmode;
  748. ath9k_calculate_iter_data(hw, vif, &iter_data);
  749. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  750. ath_hw_setbssidmask(common);
  751. if (iter_data.naps > 0) {
  752. ath9k_hw_set_tsfadjust(ah, true);
  753. ah->opmode = NL80211_IFTYPE_AP;
  754. } else {
  755. ath9k_hw_set_tsfadjust(ah, false);
  756. if (iter_data.nmeshes)
  757. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  758. else if (iter_data.nwds)
  759. ah->opmode = NL80211_IFTYPE_AP;
  760. else if (iter_data.nadhocs)
  761. ah->opmode = NL80211_IFTYPE_ADHOC;
  762. else
  763. ah->opmode = NL80211_IFTYPE_STATION;
  764. }
  765. ath9k_hw_setopmode(ah);
  766. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  767. ah->imask |= ATH9K_INT_TSFOOR;
  768. else
  769. ah->imask &= ~ATH9K_INT_TSFOOR;
  770. ath9k_hw_set_interrupts(ah);
  771. /*
  772. * If we are changing the opmode to STATION,
  773. * a beacon sync needs to be done.
  774. */
  775. if (ah->opmode == NL80211_IFTYPE_STATION &&
  776. old_opmode == NL80211_IFTYPE_AP &&
  777. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  778. ieee80211_iterate_active_interfaces_atomic(
  779. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  780. ath9k_sta_vif_iter, sc);
  781. }
  782. }
  783. static int ath9k_add_interface(struct ieee80211_hw *hw,
  784. struct ieee80211_vif *vif)
  785. {
  786. struct ath_softc *sc = hw->priv;
  787. struct ath_hw *ah = sc->sc_ah;
  788. struct ath_common *common = ath9k_hw_common(ah);
  789. mutex_lock(&sc->mutex);
  790. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  791. sc->nvifs++;
  792. ath9k_ps_wakeup(sc);
  793. ath9k_calculate_summary_state(hw, vif);
  794. ath9k_ps_restore(sc);
  795. if (ath9k_uses_beacons(vif->type))
  796. ath9k_beacon_assign_slot(sc, vif);
  797. mutex_unlock(&sc->mutex);
  798. return 0;
  799. }
  800. static int ath9k_change_interface(struct ieee80211_hw *hw,
  801. struct ieee80211_vif *vif,
  802. enum nl80211_iftype new_type,
  803. bool p2p)
  804. {
  805. struct ath_softc *sc = hw->priv;
  806. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  807. ath_dbg(common, CONFIG, "Change Interface\n");
  808. mutex_lock(&sc->mutex);
  809. if (ath9k_uses_beacons(vif->type))
  810. ath9k_beacon_remove_slot(sc, vif);
  811. vif->type = new_type;
  812. vif->p2p = p2p;
  813. ath9k_ps_wakeup(sc);
  814. ath9k_calculate_summary_state(hw, vif);
  815. ath9k_ps_restore(sc);
  816. if (ath9k_uses_beacons(vif->type))
  817. ath9k_beacon_assign_slot(sc, vif);
  818. mutex_unlock(&sc->mutex);
  819. return 0;
  820. }
  821. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  822. struct ieee80211_vif *vif)
  823. {
  824. struct ath_softc *sc = hw->priv;
  825. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  826. ath_dbg(common, CONFIG, "Detach Interface\n");
  827. mutex_lock(&sc->mutex);
  828. sc->nvifs--;
  829. if (ath9k_uses_beacons(vif->type))
  830. ath9k_beacon_remove_slot(sc, vif);
  831. ath9k_ps_wakeup(sc);
  832. ath9k_calculate_summary_state(hw, NULL);
  833. ath9k_ps_restore(sc);
  834. mutex_unlock(&sc->mutex);
  835. }
  836. static void ath9k_enable_ps(struct ath_softc *sc)
  837. {
  838. struct ath_hw *ah = sc->sc_ah;
  839. struct ath_common *common = ath9k_hw_common(ah);
  840. sc->ps_enabled = true;
  841. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  842. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  843. ah->imask |= ATH9K_INT_TIM_TIMER;
  844. ath9k_hw_set_interrupts(ah);
  845. }
  846. ath9k_hw_setrxabort(ah, 1);
  847. }
  848. ath_dbg(common, PS, "PowerSave enabled\n");
  849. }
  850. static void ath9k_disable_ps(struct ath_softc *sc)
  851. {
  852. struct ath_hw *ah = sc->sc_ah;
  853. struct ath_common *common = ath9k_hw_common(ah);
  854. sc->ps_enabled = false;
  855. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  856. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  857. ath9k_hw_setrxabort(ah, 0);
  858. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  859. PS_WAIT_FOR_CAB |
  860. PS_WAIT_FOR_PSPOLL_DATA |
  861. PS_WAIT_FOR_TX_ACK);
  862. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  863. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  864. ath9k_hw_set_interrupts(ah);
  865. }
  866. }
  867. ath_dbg(common, PS, "PowerSave disabled\n");
  868. }
  869. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  870. {
  871. struct ath_softc *sc = hw->priv;
  872. struct ath_hw *ah = sc->sc_ah;
  873. struct ath_common *common = ath9k_hw_common(ah);
  874. struct ieee80211_conf *conf = &hw->conf;
  875. bool reset_channel = false;
  876. ath9k_ps_wakeup(sc);
  877. mutex_lock(&sc->mutex);
  878. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  879. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  880. if (sc->ps_idle) {
  881. ath_cancel_work(sc);
  882. ath9k_stop_btcoex(sc);
  883. } else {
  884. ath9k_start_btcoex(sc);
  885. /*
  886. * The chip needs a reset to properly wake up from
  887. * full sleep
  888. */
  889. reset_channel = ah->chip_fullsleep;
  890. }
  891. }
  892. /*
  893. * We just prepare to enable PS. We have to wait until our AP has
  894. * ACK'd our null data frame to disable RX otherwise we'll ignore
  895. * those ACKs and end up retransmitting the same null data frames.
  896. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  897. */
  898. if (changed & IEEE80211_CONF_CHANGE_PS) {
  899. unsigned long flags;
  900. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  901. if (conf->flags & IEEE80211_CONF_PS)
  902. ath9k_enable_ps(sc);
  903. else
  904. ath9k_disable_ps(sc);
  905. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  906. }
  907. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  908. if (conf->flags & IEEE80211_CONF_MONITOR) {
  909. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  910. sc->sc_ah->is_monitoring = true;
  911. } else {
  912. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  913. sc->sc_ah->is_monitoring = false;
  914. }
  915. }
  916. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  917. struct ieee80211_channel *curchan = hw->conf.channel;
  918. int pos = curchan->hw_value;
  919. int old_pos = -1;
  920. unsigned long flags;
  921. if (ah->curchan)
  922. old_pos = ah->curchan - &ah->channels[0];
  923. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  924. curchan->center_freq, conf->channel_type);
  925. /* update survey stats for the old channel before switching */
  926. spin_lock_irqsave(&common->cc_lock, flags);
  927. ath_update_survey_stats(sc);
  928. spin_unlock_irqrestore(&common->cc_lock, flags);
  929. /*
  930. * Preserve the current channel values, before updating
  931. * the same channel
  932. */
  933. if (ah->curchan && (old_pos == pos))
  934. ath9k_hw_getnf(ah, ah->curchan);
  935. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  936. curchan, conf->channel_type);
  937. /*
  938. * If the operating channel changes, change the survey in-use flags
  939. * along with it.
  940. * Reset the survey data for the new channel, unless we're switching
  941. * back to the operating channel from an off-channel operation.
  942. */
  943. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  944. sc->cur_survey != &sc->survey[pos]) {
  945. if (sc->cur_survey)
  946. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  947. sc->cur_survey = &sc->survey[pos];
  948. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  949. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  950. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  951. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  952. }
  953. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  954. ath_err(common, "Unable to set channel\n");
  955. mutex_unlock(&sc->mutex);
  956. ath9k_ps_restore(sc);
  957. return -EINVAL;
  958. }
  959. /*
  960. * The most recent snapshot of channel->noisefloor for the old
  961. * channel is only available after the hardware reset. Copy it to
  962. * the survey stats now.
  963. */
  964. if (old_pos >= 0)
  965. ath_update_survey_nf(sc, old_pos);
  966. }
  967. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  968. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  969. sc->config.txpowlimit = 2 * conf->power_level;
  970. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  971. sc->config.txpowlimit, &sc->curtxpow);
  972. }
  973. mutex_unlock(&sc->mutex);
  974. ath9k_ps_restore(sc);
  975. return 0;
  976. }
  977. #define SUPPORTED_FILTERS \
  978. (FIF_PROMISC_IN_BSS | \
  979. FIF_ALLMULTI | \
  980. FIF_CONTROL | \
  981. FIF_PSPOLL | \
  982. FIF_OTHER_BSS | \
  983. FIF_BCN_PRBRESP_PROMISC | \
  984. FIF_PROBE_REQ | \
  985. FIF_FCSFAIL)
  986. /* FIXME: sc->sc_full_reset ? */
  987. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  988. unsigned int changed_flags,
  989. unsigned int *total_flags,
  990. u64 multicast)
  991. {
  992. struct ath_softc *sc = hw->priv;
  993. u32 rfilt;
  994. changed_flags &= SUPPORTED_FILTERS;
  995. *total_flags &= SUPPORTED_FILTERS;
  996. sc->rx.rxfilter = *total_flags;
  997. ath9k_ps_wakeup(sc);
  998. rfilt = ath_calcrxfilter(sc);
  999. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1000. ath9k_ps_restore(sc);
  1001. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1002. rfilt);
  1003. }
  1004. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1005. struct ieee80211_vif *vif,
  1006. struct ieee80211_sta *sta)
  1007. {
  1008. struct ath_softc *sc = hw->priv;
  1009. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1010. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1011. struct ieee80211_key_conf ps_key = { };
  1012. ath_node_attach(sc, sta, vif);
  1013. if (vif->type != NL80211_IFTYPE_AP &&
  1014. vif->type != NL80211_IFTYPE_AP_VLAN)
  1015. return 0;
  1016. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1017. return 0;
  1018. }
  1019. static void ath9k_del_ps_key(struct ath_softc *sc,
  1020. struct ieee80211_vif *vif,
  1021. struct ieee80211_sta *sta)
  1022. {
  1023. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1024. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1025. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1026. if (!an->ps_key)
  1027. return;
  1028. ath_key_delete(common, &ps_key);
  1029. }
  1030. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1031. struct ieee80211_vif *vif,
  1032. struct ieee80211_sta *sta)
  1033. {
  1034. struct ath_softc *sc = hw->priv;
  1035. ath9k_del_ps_key(sc, vif, sta);
  1036. ath_node_detach(sc, sta);
  1037. return 0;
  1038. }
  1039. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1040. struct ieee80211_vif *vif,
  1041. enum sta_notify_cmd cmd,
  1042. struct ieee80211_sta *sta)
  1043. {
  1044. struct ath_softc *sc = hw->priv;
  1045. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1046. if (!sta->ht_cap.ht_supported)
  1047. return;
  1048. switch (cmd) {
  1049. case STA_NOTIFY_SLEEP:
  1050. an->sleeping = true;
  1051. ath_tx_aggr_sleep(sta, sc, an);
  1052. break;
  1053. case STA_NOTIFY_AWAKE:
  1054. an->sleeping = false;
  1055. ath_tx_aggr_wakeup(sc, an);
  1056. break;
  1057. }
  1058. }
  1059. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1060. struct ieee80211_vif *vif, u16 queue,
  1061. const struct ieee80211_tx_queue_params *params)
  1062. {
  1063. struct ath_softc *sc = hw->priv;
  1064. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1065. struct ath_txq *txq;
  1066. struct ath9k_tx_queue_info qi;
  1067. int ret = 0;
  1068. if (queue >= IEEE80211_NUM_ACS)
  1069. return 0;
  1070. txq = sc->tx.txq_map[queue];
  1071. ath9k_ps_wakeup(sc);
  1072. mutex_lock(&sc->mutex);
  1073. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1074. qi.tqi_aifs = params->aifs;
  1075. qi.tqi_cwmin = params->cw_min;
  1076. qi.tqi_cwmax = params->cw_max;
  1077. qi.tqi_burstTime = params->txop * 32;
  1078. ath_dbg(common, CONFIG,
  1079. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1080. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1081. params->cw_max, params->txop);
  1082. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1083. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1084. if (ret)
  1085. ath_err(common, "TXQ Update failed\n");
  1086. mutex_unlock(&sc->mutex);
  1087. ath9k_ps_restore(sc);
  1088. return ret;
  1089. }
  1090. static int ath9k_set_key(struct ieee80211_hw *hw,
  1091. enum set_key_cmd cmd,
  1092. struct ieee80211_vif *vif,
  1093. struct ieee80211_sta *sta,
  1094. struct ieee80211_key_conf *key)
  1095. {
  1096. struct ath_softc *sc = hw->priv;
  1097. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1098. int ret = 0;
  1099. if (ath9k_modparam_nohwcrypt)
  1100. return -ENOSPC;
  1101. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1102. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1103. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1104. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1105. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1106. /*
  1107. * For now, disable hw crypto for the RSN IBSS group keys. This
  1108. * could be optimized in the future to use a modified key cache
  1109. * design to support per-STA RX GTK, but until that gets
  1110. * implemented, use of software crypto for group addressed
  1111. * frames is a acceptable to allow RSN IBSS to be used.
  1112. */
  1113. return -EOPNOTSUPP;
  1114. }
  1115. mutex_lock(&sc->mutex);
  1116. ath9k_ps_wakeup(sc);
  1117. ath_dbg(common, CONFIG, "Set HW Key\n");
  1118. switch (cmd) {
  1119. case SET_KEY:
  1120. if (sta)
  1121. ath9k_del_ps_key(sc, vif, sta);
  1122. ret = ath_key_config(common, vif, sta, key);
  1123. if (ret >= 0) {
  1124. key->hw_key_idx = ret;
  1125. /* push IV and Michael MIC generation to stack */
  1126. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1127. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1128. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1129. if (sc->sc_ah->sw_mgmt_crypto &&
  1130. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1131. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1132. ret = 0;
  1133. }
  1134. break;
  1135. case DISABLE_KEY:
  1136. ath_key_delete(common, key);
  1137. break;
  1138. default:
  1139. ret = -EINVAL;
  1140. }
  1141. ath9k_ps_restore(sc);
  1142. mutex_unlock(&sc->mutex);
  1143. return ret;
  1144. }
  1145. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1146. struct ieee80211_vif *vif)
  1147. {
  1148. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1149. struct ath_vif *avp = (void *)vif->drv_priv;
  1150. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1151. unsigned long flags;
  1152. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1153. avp->primary_sta_vif = true;
  1154. /*
  1155. * Set the AID, BSSID and do beacon-sync only when
  1156. * the HW opmode is STATION.
  1157. *
  1158. * But the primary bit is set above in any case.
  1159. */
  1160. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1161. return;
  1162. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1163. common->curaid = bss_conf->aid;
  1164. ath9k_hw_write_associd(sc->sc_ah);
  1165. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1166. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1167. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1168. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1169. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1170. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1171. ath9k_mci_update_wlan_channels(sc, false);
  1172. ath_dbg(common, CONFIG,
  1173. "Primary Station interface: %pM, BSSID: %pM\n",
  1174. vif->addr, common->curbssid);
  1175. }
  1176. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1177. {
  1178. struct ath_softc *sc = data;
  1179. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1180. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1181. return;
  1182. if (bss_conf->assoc)
  1183. ath9k_set_assoc_state(sc, vif);
  1184. }
  1185. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1186. struct ieee80211_vif *vif,
  1187. struct ieee80211_bss_conf *bss_conf,
  1188. u32 changed)
  1189. {
  1190. #define CHECK_ANI \
  1191. (BSS_CHANGED_ASSOC | \
  1192. BSS_CHANGED_IBSS | \
  1193. BSS_CHANGED_BEACON_ENABLED)
  1194. struct ath_softc *sc = hw->priv;
  1195. struct ath_hw *ah = sc->sc_ah;
  1196. struct ath_common *common = ath9k_hw_common(ah);
  1197. struct ath_vif *avp = (void *)vif->drv_priv;
  1198. int slottime;
  1199. ath9k_ps_wakeup(sc);
  1200. mutex_lock(&sc->mutex);
  1201. if (changed & BSS_CHANGED_ASSOC) {
  1202. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1203. bss_conf->bssid, bss_conf->assoc);
  1204. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1205. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1206. avp->primary_sta_vif = false;
  1207. if (ah->opmode == NL80211_IFTYPE_STATION)
  1208. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1209. }
  1210. ieee80211_iterate_active_interfaces_atomic(
  1211. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1212. ath9k_bss_assoc_iter, sc);
  1213. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1214. ah->opmode == NL80211_IFTYPE_STATION) {
  1215. memset(common->curbssid, 0, ETH_ALEN);
  1216. common->curaid = 0;
  1217. ath9k_hw_write_associd(sc->sc_ah);
  1218. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1219. ath9k_mci_update_wlan_channels(sc, true);
  1220. }
  1221. }
  1222. if (changed & BSS_CHANGED_IBSS) {
  1223. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1224. common->curaid = bss_conf->aid;
  1225. ath9k_hw_write_associd(sc->sc_ah);
  1226. }
  1227. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1228. (changed & BSS_CHANGED_BEACON_INT)) {
  1229. if (ah->opmode == NL80211_IFTYPE_AP &&
  1230. bss_conf->enable_beacon)
  1231. ath9k_set_tsfadjust(sc, vif);
  1232. if (ath9k_allow_beacon_config(sc, vif))
  1233. ath9k_beacon_config(sc, vif, changed);
  1234. }
  1235. if (changed & BSS_CHANGED_ERP_SLOT) {
  1236. if (bss_conf->use_short_slot)
  1237. slottime = 9;
  1238. else
  1239. slottime = 20;
  1240. if (vif->type == NL80211_IFTYPE_AP) {
  1241. /*
  1242. * Defer update, so that connected stations can adjust
  1243. * their settings at the same time.
  1244. * See beacon.c for more details
  1245. */
  1246. sc->beacon.slottime = slottime;
  1247. sc->beacon.updateslot = UPDATE;
  1248. } else {
  1249. ah->slottime = slottime;
  1250. ath9k_hw_init_global_settings(ah);
  1251. }
  1252. }
  1253. if (changed & CHECK_ANI)
  1254. ath_check_ani(sc);
  1255. mutex_unlock(&sc->mutex);
  1256. ath9k_ps_restore(sc);
  1257. #undef CHECK_ANI
  1258. }
  1259. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1260. {
  1261. struct ath_softc *sc = hw->priv;
  1262. u64 tsf;
  1263. mutex_lock(&sc->mutex);
  1264. ath9k_ps_wakeup(sc);
  1265. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1266. ath9k_ps_restore(sc);
  1267. mutex_unlock(&sc->mutex);
  1268. return tsf;
  1269. }
  1270. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1271. struct ieee80211_vif *vif,
  1272. u64 tsf)
  1273. {
  1274. struct ath_softc *sc = hw->priv;
  1275. mutex_lock(&sc->mutex);
  1276. ath9k_ps_wakeup(sc);
  1277. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1278. ath9k_ps_restore(sc);
  1279. mutex_unlock(&sc->mutex);
  1280. }
  1281. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1282. {
  1283. struct ath_softc *sc = hw->priv;
  1284. mutex_lock(&sc->mutex);
  1285. ath9k_ps_wakeup(sc);
  1286. ath9k_hw_reset_tsf(sc->sc_ah);
  1287. ath9k_ps_restore(sc);
  1288. mutex_unlock(&sc->mutex);
  1289. }
  1290. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1291. struct ieee80211_vif *vif,
  1292. enum ieee80211_ampdu_mlme_action action,
  1293. struct ieee80211_sta *sta,
  1294. u16 tid, u16 *ssn, u8 buf_size)
  1295. {
  1296. struct ath_softc *sc = hw->priv;
  1297. int ret = 0;
  1298. local_bh_disable();
  1299. switch (action) {
  1300. case IEEE80211_AMPDU_RX_START:
  1301. break;
  1302. case IEEE80211_AMPDU_RX_STOP:
  1303. break;
  1304. case IEEE80211_AMPDU_TX_START:
  1305. ath9k_ps_wakeup(sc);
  1306. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1307. if (!ret)
  1308. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1309. ath9k_ps_restore(sc);
  1310. break;
  1311. case IEEE80211_AMPDU_TX_STOP:
  1312. ath9k_ps_wakeup(sc);
  1313. ath_tx_aggr_stop(sc, sta, tid);
  1314. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1315. ath9k_ps_restore(sc);
  1316. break;
  1317. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1318. ath9k_ps_wakeup(sc);
  1319. ath_tx_aggr_resume(sc, sta, tid);
  1320. ath9k_ps_restore(sc);
  1321. break;
  1322. default:
  1323. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1324. }
  1325. local_bh_enable();
  1326. return ret;
  1327. }
  1328. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1329. struct survey_info *survey)
  1330. {
  1331. struct ath_softc *sc = hw->priv;
  1332. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1333. struct ieee80211_supported_band *sband;
  1334. struct ieee80211_channel *chan;
  1335. unsigned long flags;
  1336. int pos;
  1337. spin_lock_irqsave(&common->cc_lock, flags);
  1338. if (idx == 0)
  1339. ath_update_survey_stats(sc);
  1340. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1341. if (sband && idx >= sband->n_channels) {
  1342. idx -= sband->n_channels;
  1343. sband = NULL;
  1344. }
  1345. if (!sband)
  1346. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1347. if (!sband || idx >= sband->n_channels) {
  1348. spin_unlock_irqrestore(&common->cc_lock, flags);
  1349. return -ENOENT;
  1350. }
  1351. chan = &sband->channels[idx];
  1352. pos = chan->hw_value;
  1353. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1354. survey->channel = chan;
  1355. spin_unlock_irqrestore(&common->cc_lock, flags);
  1356. return 0;
  1357. }
  1358. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1359. {
  1360. struct ath_softc *sc = hw->priv;
  1361. struct ath_hw *ah = sc->sc_ah;
  1362. mutex_lock(&sc->mutex);
  1363. ah->coverage_class = coverage_class;
  1364. ath9k_ps_wakeup(sc);
  1365. ath9k_hw_init_global_settings(ah);
  1366. ath9k_ps_restore(sc);
  1367. mutex_unlock(&sc->mutex);
  1368. }
  1369. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1370. {
  1371. struct ath_softc *sc = hw->priv;
  1372. struct ath_hw *ah = sc->sc_ah;
  1373. struct ath_common *common = ath9k_hw_common(ah);
  1374. int timeout = 200; /* ms */
  1375. int i, j;
  1376. bool drain_txq;
  1377. mutex_lock(&sc->mutex);
  1378. cancel_delayed_work_sync(&sc->tx_complete_work);
  1379. if (ah->ah_flags & AH_UNPLUGGED) {
  1380. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1381. mutex_unlock(&sc->mutex);
  1382. return;
  1383. }
  1384. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1385. ath_dbg(common, ANY, "Device not present\n");
  1386. mutex_unlock(&sc->mutex);
  1387. return;
  1388. }
  1389. for (j = 0; j < timeout; j++) {
  1390. bool npend = false;
  1391. if (j)
  1392. usleep_range(1000, 2000);
  1393. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1394. if (!ATH_TXQ_SETUP(sc, i))
  1395. continue;
  1396. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1397. if (npend)
  1398. break;
  1399. }
  1400. if (!npend)
  1401. break;
  1402. }
  1403. if (drop) {
  1404. ath9k_ps_wakeup(sc);
  1405. spin_lock_bh(&sc->sc_pcu_lock);
  1406. drain_txq = ath_drain_all_txq(sc, false);
  1407. spin_unlock_bh(&sc->sc_pcu_lock);
  1408. if (!drain_txq)
  1409. ath_reset(sc, false);
  1410. ath9k_ps_restore(sc);
  1411. ieee80211_wake_queues(hw);
  1412. }
  1413. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1414. mutex_unlock(&sc->mutex);
  1415. }
  1416. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1417. {
  1418. struct ath_softc *sc = hw->priv;
  1419. int i;
  1420. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1421. if (!ATH_TXQ_SETUP(sc, i))
  1422. continue;
  1423. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1424. return true;
  1425. }
  1426. return false;
  1427. }
  1428. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1429. {
  1430. struct ath_softc *sc = hw->priv;
  1431. struct ath_hw *ah = sc->sc_ah;
  1432. struct ieee80211_vif *vif;
  1433. struct ath_vif *avp;
  1434. struct ath_buf *bf;
  1435. struct ath_tx_status ts;
  1436. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1437. int status;
  1438. vif = sc->beacon.bslot[0];
  1439. if (!vif)
  1440. return 0;
  1441. if (!vif->bss_conf.enable_beacon)
  1442. return 0;
  1443. avp = (void *)vif->drv_priv;
  1444. if (!sc->beacon.tx_processed && !edma) {
  1445. tasklet_disable(&sc->bcon_tasklet);
  1446. bf = avp->av_bcbuf;
  1447. if (!bf || !bf->bf_mpdu)
  1448. goto skip;
  1449. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1450. if (status == -EINPROGRESS)
  1451. goto skip;
  1452. sc->beacon.tx_processed = true;
  1453. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1454. skip:
  1455. tasklet_enable(&sc->bcon_tasklet);
  1456. }
  1457. return sc->beacon.tx_last;
  1458. }
  1459. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1460. struct ieee80211_low_level_stats *stats)
  1461. {
  1462. struct ath_softc *sc = hw->priv;
  1463. struct ath_hw *ah = sc->sc_ah;
  1464. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1465. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1466. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1467. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1468. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1469. return 0;
  1470. }
  1471. static u32 fill_chainmask(u32 cap, u32 new)
  1472. {
  1473. u32 filled = 0;
  1474. int i;
  1475. for (i = 0; cap && new; i++, cap >>= 1) {
  1476. if (!(cap & BIT(0)))
  1477. continue;
  1478. if (new & BIT(0))
  1479. filled |= BIT(i);
  1480. new >>= 1;
  1481. }
  1482. return filled;
  1483. }
  1484. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1485. {
  1486. switch (val & 0x7) {
  1487. case 0x1:
  1488. case 0x3:
  1489. case 0x7:
  1490. return true;
  1491. case 0x2:
  1492. return (ah->caps.rx_chainmask == 1);
  1493. default:
  1494. return false;
  1495. }
  1496. }
  1497. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1498. {
  1499. struct ath_softc *sc = hw->priv;
  1500. struct ath_hw *ah = sc->sc_ah;
  1501. if (ah->caps.rx_chainmask != 1)
  1502. rx_ant |= tx_ant;
  1503. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1504. return -EINVAL;
  1505. sc->ant_rx = rx_ant;
  1506. sc->ant_tx = tx_ant;
  1507. if (ah->caps.rx_chainmask == 1)
  1508. return 0;
  1509. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1510. if (AR_SREV_9100(ah))
  1511. ah->rxchainmask = 0x7;
  1512. else
  1513. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1514. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1515. ath9k_reload_chainmask_settings(sc);
  1516. return 0;
  1517. }
  1518. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1519. {
  1520. struct ath_softc *sc = hw->priv;
  1521. *tx_ant = sc->ant_tx;
  1522. *rx_ant = sc->ant_rx;
  1523. return 0;
  1524. }
  1525. #ifdef CONFIG_ATH9K_DEBUGFS
  1526. /* Ethtool support for get-stats */
  1527. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1528. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1529. "tx_pkts_nic",
  1530. "tx_bytes_nic",
  1531. "rx_pkts_nic",
  1532. "rx_bytes_nic",
  1533. AMKSTR(d_tx_pkts),
  1534. AMKSTR(d_tx_bytes),
  1535. AMKSTR(d_tx_mpdus_queued),
  1536. AMKSTR(d_tx_mpdus_completed),
  1537. AMKSTR(d_tx_mpdu_xretries),
  1538. AMKSTR(d_tx_aggregates),
  1539. AMKSTR(d_tx_ampdus_queued_hw),
  1540. AMKSTR(d_tx_ampdus_queued_sw),
  1541. AMKSTR(d_tx_ampdus_completed),
  1542. AMKSTR(d_tx_ampdu_retries),
  1543. AMKSTR(d_tx_ampdu_xretries),
  1544. AMKSTR(d_tx_fifo_underrun),
  1545. AMKSTR(d_tx_op_exceeded),
  1546. AMKSTR(d_tx_timer_expiry),
  1547. AMKSTR(d_tx_desc_cfg_err),
  1548. AMKSTR(d_tx_data_underrun),
  1549. AMKSTR(d_tx_delim_underrun),
  1550. "d_rx_decrypt_crc_err",
  1551. "d_rx_phy_err",
  1552. "d_rx_mic_err",
  1553. "d_rx_pre_delim_crc_err",
  1554. "d_rx_post_delim_crc_err",
  1555. "d_rx_decrypt_busy_err",
  1556. "d_rx_phyerr_radar",
  1557. "d_rx_phyerr_ofdm_timing",
  1558. "d_rx_phyerr_cck_timing",
  1559. };
  1560. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1561. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1562. struct ieee80211_vif *vif,
  1563. u32 sset, u8 *data)
  1564. {
  1565. if (sset == ETH_SS_STATS)
  1566. memcpy(data, *ath9k_gstrings_stats,
  1567. sizeof(ath9k_gstrings_stats));
  1568. }
  1569. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1570. struct ieee80211_vif *vif, int sset)
  1571. {
  1572. if (sset == ETH_SS_STATS)
  1573. return ATH9K_SSTATS_LEN;
  1574. return 0;
  1575. }
  1576. #define AWDATA(elem) \
  1577. do { \
  1578. data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BE)].elem; \
  1579. data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BK)].elem; \
  1580. data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VI)].elem; \
  1581. data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VO)].elem; \
  1582. } while (0)
  1583. #define AWDATA_RX(elem) \
  1584. do { \
  1585. data[i++] = sc->debug.stats.rxstats.elem; \
  1586. } while (0)
  1587. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1588. struct ieee80211_vif *vif,
  1589. struct ethtool_stats *stats, u64 *data)
  1590. {
  1591. struct ath_softc *sc = hw->priv;
  1592. int i = 0;
  1593. data[i++] = (sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BE)].tx_pkts_all +
  1594. sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BK)].tx_pkts_all +
  1595. sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VI)].tx_pkts_all +
  1596. sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VO)].tx_pkts_all);
  1597. data[i++] = (sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BE)].tx_bytes_all +
  1598. sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BK)].tx_bytes_all +
  1599. sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VI)].tx_bytes_all +
  1600. sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VO)].tx_bytes_all);
  1601. AWDATA_RX(rx_pkts_all);
  1602. AWDATA_RX(rx_bytes_all);
  1603. AWDATA(tx_pkts_all);
  1604. AWDATA(tx_bytes_all);
  1605. AWDATA(queued);
  1606. AWDATA(completed);
  1607. AWDATA(xretries);
  1608. AWDATA(a_aggr);
  1609. AWDATA(a_queued_hw);
  1610. AWDATA(a_queued_sw);
  1611. AWDATA(a_completed);
  1612. AWDATA(a_retries);
  1613. AWDATA(a_xretries);
  1614. AWDATA(fifo_underrun);
  1615. AWDATA(xtxop);
  1616. AWDATA(timer_exp);
  1617. AWDATA(desc_cfg_err);
  1618. AWDATA(data_underrun);
  1619. AWDATA(delim_underrun);
  1620. AWDATA_RX(decrypt_crc_err);
  1621. AWDATA_RX(phy_err);
  1622. AWDATA_RX(mic_err);
  1623. AWDATA_RX(pre_delim_crc_err);
  1624. AWDATA_RX(post_delim_crc_err);
  1625. AWDATA_RX(decrypt_busy_err);
  1626. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1627. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1628. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1629. WARN_ON(i != ATH9K_SSTATS_LEN);
  1630. }
  1631. /* End of ethtool get-stats functions */
  1632. #endif
  1633. #ifdef CONFIG_PM_SLEEP
  1634. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1635. struct cfg80211_wowlan *wowlan,
  1636. u32 *wow_triggers)
  1637. {
  1638. if (wowlan->disconnect)
  1639. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1640. AH_WOW_BEACON_MISS;
  1641. if (wowlan->magic_pkt)
  1642. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1643. if (wowlan->n_patterns)
  1644. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1645. sc->wow_enabled = *wow_triggers;
  1646. }
  1647. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1648. {
  1649. struct ath_hw *ah = sc->sc_ah;
  1650. struct ath_common *common = ath9k_hw_common(ah);
  1651. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1652. int pattern_count = 0;
  1653. int i, byte_cnt;
  1654. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1655. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1656. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1657. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1658. /*
  1659. * Create Dissassociate / Deauthenticate packet filter
  1660. *
  1661. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1662. * +--------------+----------+---------+--------+--------+----
  1663. * + Frame Control+ Duration + DA + SA + BSSID +
  1664. * +--------------+----------+---------+--------+--------+----
  1665. *
  1666. * The above is the management frame format for disassociate/
  1667. * deauthenticate pattern, from this we need to match the first byte
  1668. * of 'Frame Control' and DA, SA, and BSSID fields
  1669. * (skipping 2nd byte of FC and Duration feild.
  1670. *
  1671. * Disassociate pattern
  1672. * --------------------
  1673. * Frame control = 00 00 1010
  1674. * DA, SA, BSSID = x:x:x:x:x:x
  1675. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1676. * | x:x:x:x:x:x -- 22 bytes
  1677. *
  1678. * Deauthenticate pattern
  1679. * ----------------------
  1680. * Frame control = 00 00 1100
  1681. * DA, SA, BSSID = x:x:x:x:x:x
  1682. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1683. * | x:x:x:x:x:x -- 22 bytes
  1684. */
  1685. /* Create Disassociate Pattern first */
  1686. byte_cnt = 0;
  1687. /* Fill out the mask with all FF's */
  1688. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1689. dis_deauth_mask[i] = 0xff;
  1690. /* copy the first byte of frame control field */
  1691. dis_deauth_pattern[byte_cnt] = 0xa0;
  1692. byte_cnt++;
  1693. /* skip 2nd byte of frame control and Duration field */
  1694. byte_cnt += 3;
  1695. /*
  1696. * need not match the destination mac address, it can be a broadcast
  1697. * mac address or an unicast to this station
  1698. */
  1699. byte_cnt += 6;
  1700. /* copy the source mac address */
  1701. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1702. byte_cnt += 6;
  1703. /* copy the bssid, its same as the source mac address */
  1704. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1705. /* Create Disassociate pattern mask */
  1706. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1707. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1708. /*
  1709. * for AR9280, because of hardware limitation, the
  1710. * first 4 bytes have to be matched for all patterns.
  1711. * the mask for disassociation and de-auth pattern
  1712. * matching need to enable the first 4 bytes.
  1713. * also the duration field needs to be filled.
  1714. */
  1715. dis_deauth_mask[0] = 0xf0;
  1716. /*
  1717. * fill in duration field
  1718. FIXME: what is the exact value ?
  1719. */
  1720. dis_deauth_pattern[2] = 0xff;
  1721. dis_deauth_pattern[3] = 0xff;
  1722. } else {
  1723. dis_deauth_mask[0] = 0xfe;
  1724. }
  1725. dis_deauth_mask[1] = 0x03;
  1726. dis_deauth_mask[2] = 0xc0;
  1727. } else {
  1728. dis_deauth_mask[0] = 0xef;
  1729. dis_deauth_mask[1] = 0x3f;
  1730. dis_deauth_mask[2] = 0x00;
  1731. dis_deauth_mask[3] = 0xfc;
  1732. }
  1733. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1734. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1735. pattern_count, byte_cnt);
  1736. pattern_count++;
  1737. /*
  1738. * for de-authenticate pattern, only the first byte of the frame
  1739. * control field gets changed from 0xA0 to 0xC0
  1740. */
  1741. dis_deauth_pattern[0] = 0xC0;
  1742. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1743. pattern_count, byte_cnt);
  1744. }
  1745. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1746. struct cfg80211_wowlan *wowlan)
  1747. {
  1748. struct ath_hw *ah = sc->sc_ah;
  1749. struct ath9k_wow_pattern *wow_pattern = NULL;
  1750. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1751. int mask_len;
  1752. s8 i = 0;
  1753. if (!wowlan->n_patterns)
  1754. return;
  1755. /*
  1756. * Add the new user configured patterns
  1757. */
  1758. for (i = 0; i < wowlan->n_patterns; i++) {
  1759. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1760. if (!wow_pattern)
  1761. return;
  1762. /*
  1763. * TODO: convert the generic user space pattern to
  1764. * appropriate chip specific/802.11 pattern.
  1765. */
  1766. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1767. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1768. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1769. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1770. patterns[i].pattern_len);
  1771. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1772. wow_pattern->pattern_len = patterns[i].pattern_len;
  1773. /*
  1774. * just need to take care of deauth and disssoc pattern,
  1775. * make sure we don't overwrite them.
  1776. */
  1777. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1778. wow_pattern->mask_bytes,
  1779. i + 2,
  1780. wow_pattern->pattern_len);
  1781. kfree(wow_pattern);
  1782. }
  1783. }
  1784. static int ath9k_suspend(struct ieee80211_hw *hw,
  1785. struct cfg80211_wowlan *wowlan)
  1786. {
  1787. struct ath_softc *sc = hw->priv;
  1788. struct ath_hw *ah = sc->sc_ah;
  1789. struct ath_common *common = ath9k_hw_common(ah);
  1790. u32 wow_triggers_enabled = 0;
  1791. int ret = 0;
  1792. mutex_lock(&sc->mutex);
  1793. ath_cancel_work(sc);
  1794. ath_stop_ani(sc);
  1795. del_timer_sync(&sc->rx_poll_timer);
  1796. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1797. ath_dbg(common, ANY, "Device not present\n");
  1798. ret = -EINVAL;
  1799. goto fail_wow;
  1800. }
  1801. if (WARN_ON(!wowlan)) {
  1802. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1803. ret = -EINVAL;
  1804. goto fail_wow;
  1805. }
  1806. if (!device_can_wakeup(sc->dev)) {
  1807. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1808. ret = 1;
  1809. goto fail_wow;
  1810. }
  1811. /*
  1812. * none of the sta vifs are associated
  1813. * and we are not currently handling multivif
  1814. * cases, for instance we have to seperately
  1815. * configure 'keep alive frame' for each
  1816. * STA.
  1817. */
  1818. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1819. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1820. ret = 1;
  1821. goto fail_wow;
  1822. }
  1823. if (sc->nvifs > 1) {
  1824. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1825. ret = 1;
  1826. goto fail_wow;
  1827. }
  1828. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1829. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1830. wow_triggers_enabled);
  1831. ath9k_ps_wakeup(sc);
  1832. ath9k_stop_btcoex(sc);
  1833. /*
  1834. * Enable wake up on recieving disassoc/deauth
  1835. * frame by default.
  1836. */
  1837. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1838. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1839. ath9k_wow_add_pattern(sc, wowlan);
  1840. spin_lock_bh(&sc->sc_pcu_lock);
  1841. /*
  1842. * To avoid false wake, we enable beacon miss interrupt only
  1843. * when we go to sleep. We save the current interrupt mask
  1844. * so we can restore it after the system wakes up
  1845. */
  1846. sc->wow_intr_before_sleep = ah->imask;
  1847. ah->imask &= ~ATH9K_INT_GLOBAL;
  1848. ath9k_hw_disable_interrupts(ah);
  1849. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1850. ath9k_hw_set_interrupts(ah);
  1851. ath9k_hw_enable_interrupts(ah);
  1852. spin_unlock_bh(&sc->sc_pcu_lock);
  1853. /*
  1854. * we can now sync irq and kill any running tasklets, since we already
  1855. * disabled interrupts and not holding a spin lock
  1856. */
  1857. synchronize_irq(sc->irq);
  1858. tasklet_kill(&sc->intr_tq);
  1859. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1860. ath9k_ps_restore(sc);
  1861. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1862. atomic_inc(&sc->wow_sleep_proc_intr);
  1863. fail_wow:
  1864. mutex_unlock(&sc->mutex);
  1865. return ret;
  1866. }
  1867. static int ath9k_resume(struct ieee80211_hw *hw)
  1868. {
  1869. struct ath_softc *sc = hw->priv;
  1870. struct ath_hw *ah = sc->sc_ah;
  1871. struct ath_common *common = ath9k_hw_common(ah);
  1872. u32 wow_status;
  1873. mutex_lock(&sc->mutex);
  1874. ath9k_ps_wakeup(sc);
  1875. spin_lock_bh(&sc->sc_pcu_lock);
  1876. ath9k_hw_disable_interrupts(ah);
  1877. ah->imask = sc->wow_intr_before_sleep;
  1878. ath9k_hw_set_interrupts(ah);
  1879. ath9k_hw_enable_interrupts(ah);
  1880. spin_unlock_bh(&sc->sc_pcu_lock);
  1881. wow_status = ath9k_hw_wow_wakeup(ah);
  1882. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1883. /*
  1884. * some devices may not pick beacon miss
  1885. * as the reason they woke up so we add
  1886. * that here for that shortcoming.
  1887. */
  1888. wow_status |= AH_WOW_BEACON_MISS;
  1889. atomic_dec(&sc->wow_got_bmiss_intr);
  1890. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1891. }
  1892. atomic_dec(&sc->wow_sleep_proc_intr);
  1893. if (wow_status) {
  1894. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1895. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1896. }
  1897. ath_restart_work(sc);
  1898. ath9k_start_btcoex(sc);
  1899. ath9k_ps_restore(sc);
  1900. mutex_unlock(&sc->mutex);
  1901. return 0;
  1902. }
  1903. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1904. {
  1905. struct ath_softc *sc = hw->priv;
  1906. mutex_lock(&sc->mutex);
  1907. device_init_wakeup(sc->dev, 1);
  1908. device_set_wakeup_enable(sc->dev, enabled);
  1909. mutex_unlock(&sc->mutex);
  1910. }
  1911. #endif
  1912. struct ieee80211_ops ath9k_ops = {
  1913. .tx = ath9k_tx,
  1914. .start = ath9k_start,
  1915. .stop = ath9k_stop,
  1916. .add_interface = ath9k_add_interface,
  1917. .change_interface = ath9k_change_interface,
  1918. .remove_interface = ath9k_remove_interface,
  1919. .config = ath9k_config,
  1920. .configure_filter = ath9k_configure_filter,
  1921. .sta_add = ath9k_sta_add,
  1922. .sta_remove = ath9k_sta_remove,
  1923. .sta_notify = ath9k_sta_notify,
  1924. .conf_tx = ath9k_conf_tx,
  1925. .bss_info_changed = ath9k_bss_info_changed,
  1926. .set_key = ath9k_set_key,
  1927. .get_tsf = ath9k_get_tsf,
  1928. .set_tsf = ath9k_set_tsf,
  1929. .reset_tsf = ath9k_reset_tsf,
  1930. .ampdu_action = ath9k_ampdu_action,
  1931. .get_survey = ath9k_get_survey,
  1932. .rfkill_poll = ath9k_rfkill_poll_state,
  1933. .set_coverage_class = ath9k_set_coverage_class,
  1934. .flush = ath9k_flush,
  1935. .tx_frames_pending = ath9k_tx_frames_pending,
  1936. .tx_last_beacon = ath9k_tx_last_beacon,
  1937. .get_stats = ath9k_get_stats,
  1938. .set_antenna = ath9k_set_antenna,
  1939. .get_antenna = ath9k_get_antenna,
  1940. #ifdef CONFIG_PM_SLEEP
  1941. .suspend = ath9k_suspend,
  1942. .resume = ath9k_resume,
  1943. .set_wakeup = ath9k_set_wakeup,
  1944. #endif
  1945. #ifdef CONFIG_ATH9K_DEBUGFS
  1946. .get_et_sset_count = ath9k_get_et_sset_count,
  1947. .get_et_stats = ath9k_get_et_stats,
  1948. .get_et_strings = ath9k_get_et_strings,
  1949. #endif
  1950. };