davinci_spi.c 28 KB

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  1. /*
  2. * Copyright (C) 2009 Texas Instruments.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. */
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/gpio.h>
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/err.h>
  25. #include <linux/clk.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/spi/spi.h>
  28. #include <linux/spi/spi_bitbang.h>
  29. #include <linux/slab.h>
  30. #include <mach/spi.h>
  31. #include <mach/edma.h>
  32. #define SPI_NO_RESOURCE ((resource_size_t)-1)
  33. #define SPI_MAX_CHIPSELECT 2
  34. #define CS_DEFAULT 0xFF
  35. #define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
  36. #define SPIFMT_PHASE_MASK BIT(16)
  37. #define SPIFMT_POLARITY_MASK BIT(17)
  38. #define SPIFMT_DISTIMER_MASK BIT(18)
  39. #define SPIFMT_SHIFTDIR_MASK BIT(20)
  40. #define SPIFMT_WAITENA_MASK BIT(21)
  41. #define SPIFMT_PARITYENA_MASK BIT(22)
  42. #define SPIFMT_ODD_PARITY_MASK BIT(23)
  43. #define SPIFMT_WDELAY_MASK 0x3f000000u
  44. #define SPIFMT_WDELAY_SHIFT 24
  45. #define SPIFMT_PRESCALE_SHIFT 8
  46. /* SPIPC0 */
  47. #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
  48. #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
  49. #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
  50. #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
  51. #define SPIINT_MASKALL 0x0101035F
  52. /* SPIDAT1 (upper 16 bit defines) */
  53. #define SPIDAT1_CSHOLD_MASK BIT(12)
  54. /* SPIGCR1 */
  55. #define SPIGCR1_CLKMOD_MASK BIT(1)
  56. #define SPIGCR1_MASTER_MASK BIT(0)
  57. #define SPIGCR1_LOOPBACK_MASK BIT(16)
  58. #define SPIGCR1_SPIENA_MASK BIT(24)
  59. /* SPIBUF */
  60. #define SPIBUF_TXFULL_MASK BIT(29)
  61. #define SPIBUF_RXEMPTY_MASK BIT(31)
  62. /* SPIDELAY */
  63. #define SPIDELAY_C2TDELAY_SHIFT 24
  64. #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
  65. #define SPIDELAY_T2CDELAY_SHIFT 16
  66. #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
  67. #define SPIDELAY_T2EDELAY_SHIFT 8
  68. #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
  69. #define SPIDELAY_C2EDELAY_SHIFT 0
  70. #define SPIDELAY_C2EDELAY_MASK 0xFF
  71. /* Error Masks */
  72. #define SPIFLG_DLEN_ERR_MASK BIT(0)
  73. #define SPIFLG_TIMEOUT_MASK BIT(1)
  74. #define SPIFLG_PARERR_MASK BIT(2)
  75. #define SPIFLG_DESYNC_MASK BIT(3)
  76. #define SPIFLG_BITERR_MASK BIT(4)
  77. #define SPIFLG_OVRRUN_MASK BIT(6)
  78. #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
  79. #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
  80. | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
  81. | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
  82. | SPIFLG_OVRRUN_MASK)
  83. #define SPIINT_DMA_REQ_EN BIT(16)
  84. /* SPI Controller registers */
  85. #define SPIGCR0 0x00
  86. #define SPIGCR1 0x04
  87. #define SPIINT 0x08
  88. #define SPILVL 0x0c
  89. #define SPIFLG 0x10
  90. #define SPIPC0 0x14
  91. #define SPIDAT1 0x3c
  92. #define SPIBUF 0x40
  93. #define SPIDELAY 0x48
  94. #define SPIDEF 0x4c
  95. #define SPIFMT0 0x50
  96. /* We have 2 DMA channels per CS, one for RX and one for TX */
  97. struct davinci_spi_dma {
  98. int dma_tx_channel;
  99. int dma_rx_channel;
  100. int dma_tx_sync_dev;
  101. int dma_rx_sync_dev;
  102. enum dma_event_q eventq;
  103. struct completion dma_tx_completion;
  104. struct completion dma_rx_completion;
  105. };
  106. /* SPI Controller driver's private data. */
  107. struct davinci_spi {
  108. struct spi_bitbang bitbang;
  109. struct clk *clk;
  110. u8 version;
  111. resource_size_t pbase;
  112. void __iomem *base;
  113. size_t region_size;
  114. const void *tx;
  115. void *rx;
  116. u8 *tmp_buf;
  117. struct davinci_spi_dma *dma_channels;
  118. struct davinci_spi_platform_data *pdata;
  119. void (*get_rx)(u32 rx_data, struct davinci_spi *);
  120. u32 (*get_tx)(struct davinci_spi *);
  121. u8 bytes_per_word[SPI_MAX_CHIPSELECT];
  122. };
  123. static struct davinci_spi_config davinci_spi_default_cfg;
  124. static unsigned use_dma;
  125. static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
  126. {
  127. if (davinci_spi->rx) {
  128. u8 *rx = davinci_spi->rx;
  129. *rx++ = (u8)data;
  130. davinci_spi->rx = rx;
  131. }
  132. }
  133. static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
  134. {
  135. if (davinci_spi->rx) {
  136. u16 *rx = davinci_spi->rx;
  137. *rx++ = (u16)data;
  138. davinci_spi->rx = rx;
  139. }
  140. }
  141. static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
  142. {
  143. u32 data = 0;
  144. if (davinci_spi->tx) {
  145. const u8 *tx = davinci_spi->tx;
  146. data = *tx++;
  147. davinci_spi->tx = tx;
  148. }
  149. return data;
  150. }
  151. static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
  152. {
  153. u32 data = 0;
  154. if (davinci_spi->tx) {
  155. const u16 *tx = davinci_spi->tx;
  156. data = *tx++;
  157. davinci_spi->tx = tx;
  158. }
  159. return data;
  160. }
  161. static inline void set_io_bits(void __iomem *addr, u32 bits)
  162. {
  163. u32 v = ioread32(addr);
  164. v |= bits;
  165. iowrite32(v, addr);
  166. }
  167. static inline void clear_io_bits(void __iomem *addr, u32 bits)
  168. {
  169. u32 v = ioread32(addr);
  170. v &= ~bits;
  171. iowrite32(v, addr);
  172. }
  173. static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
  174. {
  175. struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
  176. if (enable)
  177. set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
  178. else
  179. clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
  180. }
  181. /*
  182. * Interface to control the chip select signal
  183. */
  184. static void davinci_spi_chipselect(struct spi_device *spi, int value)
  185. {
  186. struct davinci_spi *davinci_spi;
  187. struct davinci_spi_platform_data *pdata;
  188. u8 chip_sel = spi->chip_select;
  189. u16 spidat1_cfg = CS_DEFAULT;
  190. bool gpio_chipsel = false;
  191. davinci_spi = spi_master_get_devdata(spi->master);
  192. pdata = davinci_spi->pdata;
  193. if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
  194. pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
  195. gpio_chipsel = true;
  196. /*
  197. * Board specific chip select logic decides the polarity and cs
  198. * line for the controller
  199. */
  200. if (gpio_chipsel) {
  201. if (value == BITBANG_CS_ACTIVE)
  202. gpio_set_value(pdata->chip_sel[chip_sel], 0);
  203. else
  204. gpio_set_value(pdata->chip_sel[chip_sel], 1);
  205. } else {
  206. if (value == BITBANG_CS_ACTIVE) {
  207. spidat1_cfg |= SPIDAT1_CSHOLD_MASK;
  208. spidat1_cfg &= ~(0x1 << chip_sel);
  209. }
  210. iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2);
  211. }
  212. }
  213. /**
  214. * davinci_spi_get_prescale - Calculates the correct prescale value
  215. * @maxspeed_hz: the maximum rate the SPI clock can run at
  216. *
  217. * This function calculates the prescale value that generates a clock rate
  218. * less than or equal to the specified maximum.
  219. *
  220. * Returns: calculated prescale - 1 for easy programming into SPI registers
  221. * or negative error number if valid prescalar cannot be updated.
  222. */
  223. static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi,
  224. u32 max_speed_hz)
  225. {
  226. int ret;
  227. ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz);
  228. if (ret < 3 || ret > 256)
  229. return -EINVAL;
  230. return ret - 1;
  231. }
  232. /**
  233. * davinci_spi_setup_transfer - This functions will determine transfer method
  234. * @spi: spi device on which data transfer to be done
  235. * @t: spi transfer in which transfer info is filled
  236. *
  237. * This function determines data transfer method (8/16/32 bit transfer).
  238. * It will also set the SPI Clock Control register according to
  239. * SPI slave device freq.
  240. */
  241. static int davinci_spi_setup_transfer(struct spi_device *spi,
  242. struct spi_transfer *t)
  243. {
  244. struct davinci_spi *davinci_spi;
  245. struct davinci_spi_config *spicfg;
  246. u8 bits_per_word = 0;
  247. u32 hz = 0, spifmt = 0, prescale = 0;
  248. davinci_spi = spi_master_get_devdata(spi->master);
  249. spicfg = (struct davinci_spi_config *)spi->controller_data;
  250. if (!spicfg)
  251. spicfg = &davinci_spi_default_cfg;
  252. if (t) {
  253. bits_per_word = t->bits_per_word;
  254. hz = t->speed_hz;
  255. }
  256. /* if bits_per_word is not set then set it default */
  257. if (!bits_per_word)
  258. bits_per_word = spi->bits_per_word;
  259. /*
  260. * Assign function pointer to appropriate transfer method
  261. * 8bit, 16bit or 32bit transfer
  262. */
  263. if (bits_per_word <= 8 && bits_per_word >= 2) {
  264. davinci_spi->get_rx = davinci_spi_rx_buf_u8;
  265. davinci_spi->get_tx = davinci_spi_tx_buf_u8;
  266. davinci_spi->bytes_per_word[spi->chip_select] = 1;
  267. } else if (bits_per_word <= 16 && bits_per_word >= 2) {
  268. davinci_spi->get_rx = davinci_spi_rx_buf_u16;
  269. davinci_spi->get_tx = davinci_spi_tx_buf_u16;
  270. davinci_spi->bytes_per_word[spi->chip_select] = 2;
  271. } else
  272. return -EINVAL;
  273. if (!hz)
  274. hz = spi->max_speed_hz;
  275. /* Set up SPIFMTn register, unique to this chipselect. */
  276. prescale = davinci_spi_get_prescale(davinci_spi, hz);
  277. if (prescale < 0)
  278. return prescale;
  279. spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
  280. if (spi->mode & SPI_LSB_FIRST)
  281. spifmt |= SPIFMT_SHIFTDIR_MASK;
  282. if (spi->mode & SPI_CPOL)
  283. spifmt |= SPIFMT_POLARITY_MASK;
  284. if (!(spi->mode & SPI_CPHA))
  285. spifmt |= SPIFMT_PHASE_MASK;
  286. /*
  287. * Version 1 hardware supports two basic SPI modes:
  288. * - Standard SPI mode uses 4 pins, with chipselect
  289. * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
  290. * (distinct from SPI_3WIRE, with just one data wire;
  291. * or similar variants without MOSI or without MISO)
  292. *
  293. * Version 2 hardware supports an optional handshaking signal,
  294. * so it can support two more modes:
  295. * - 5 pin SPI variant is standard SPI plus SPI_READY
  296. * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
  297. */
  298. if (davinci_spi->version == SPI_VERSION_2) {
  299. u32 delay = 0;
  300. spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
  301. & SPIFMT_WDELAY_MASK);
  302. if (spicfg->odd_parity)
  303. spifmt |= SPIFMT_ODD_PARITY_MASK;
  304. if (spicfg->parity_enable)
  305. spifmt |= SPIFMT_PARITYENA_MASK;
  306. if (spicfg->timer_disable) {
  307. spifmt |= SPIFMT_DISTIMER_MASK;
  308. } else {
  309. delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
  310. & SPIDELAY_C2TDELAY_MASK;
  311. delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
  312. & SPIDELAY_T2CDELAY_MASK;
  313. }
  314. if (spi->mode & SPI_READY) {
  315. spifmt |= SPIFMT_WAITENA_MASK;
  316. delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
  317. & SPIDELAY_T2EDELAY_MASK;
  318. delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
  319. & SPIDELAY_C2EDELAY_MASK;
  320. }
  321. iowrite32(delay, davinci_spi->base + SPIDELAY);
  322. }
  323. iowrite32(spifmt, davinci_spi->base + SPIFMT0);
  324. return 0;
  325. }
  326. static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
  327. {
  328. struct spi_device *spi = (struct spi_device *)data;
  329. struct davinci_spi *davinci_spi;
  330. struct davinci_spi_dma *davinci_spi_dma;
  331. davinci_spi = spi_master_get_devdata(spi->master);
  332. davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
  333. if (ch_status == DMA_COMPLETE)
  334. edma_stop(davinci_spi_dma->dma_rx_channel);
  335. else
  336. edma_clean_channel(davinci_spi_dma->dma_rx_channel);
  337. complete(&davinci_spi_dma->dma_rx_completion);
  338. /* We must disable the DMA RX request */
  339. davinci_spi_set_dma_req(spi, 0);
  340. }
  341. static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
  342. {
  343. struct spi_device *spi = (struct spi_device *)data;
  344. struct davinci_spi *davinci_spi;
  345. struct davinci_spi_dma *davinci_spi_dma;
  346. davinci_spi = spi_master_get_devdata(spi->master);
  347. davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
  348. if (ch_status == DMA_COMPLETE)
  349. edma_stop(davinci_spi_dma->dma_tx_channel);
  350. else
  351. edma_clean_channel(davinci_spi_dma->dma_tx_channel);
  352. complete(&davinci_spi_dma->dma_tx_completion);
  353. /* We must disable the DMA TX request */
  354. davinci_spi_set_dma_req(spi, 0);
  355. }
  356. static int davinci_spi_request_dma(struct spi_device *spi)
  357. {
  358. struct davinci_spi *davinci_spi;
  359. struct davinci_spi_dma *davinci_spi_dma;
  360. struct device *sdev;
  361. int r;
  362. davinci_spi = spi_master_get_devdata(spi->master);
  363. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  364. sdev = davinci_spi->bitbang.master->dev.parent;
  365. r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
  366. davinci_spi_dma_rx_callback, spi,
  367. davinci_spi_dma->eventq);
  368. if (r < 0) {
  369. dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
  370. return -EAGAIN;
  371. }
  372. davinci_spi_dma->dma_rx_channel = r;
  373. r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
  374. davinci_spi_dma_tx_callback, spi,
  375. davinci_spi_dma->eventq);
  376. if (r < 0) {
  377. edma_free_channel(davinci_spi_dma->dma_rx_channel);
  378. davinci_spi_dma->dma_rx_channel = -1;
  379. dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
  380. return -EAGAIN;
  381. }
  382. davinci_spi_dma->dma_tx_channel = r;
  383. return 0;
  384. }
  385. /**
  386. * davinci_spi_setup - This functions will set default transfer method
  387. * @spi: spi device on which data transfer to be done
  388. *
  389. * This functions sets the default transfer method.
  390. */
  391. static int davinci_spi_setup(struct spi_device *spi)
  392. {
  393. int retval;
  394. struct davinci_spi *davinci_spi;
  395. struct davinci_spi_dma *davinci_spi_dma;
  396. davinci_spi = spi_master_get_devdata(spi->master);
  397. /* if bits per word length is zero then set it default 8 */
  398. if (!spi->bits_per_word)
  399. spi->bits_per_word = 8;
  400. if (use_dma && davinci_spi->dma_channels) {
  401. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  402. if ((davinci_spi_dma->dma_rx_channel == -1)
  403. || (davinci_spi_dma->dma_tx_channel == -1)) {
  404. retval = davinci_spi_request_dma(spi);
  405. if (retval < 0)
  406. return retval;
  407. }
  408. }
  409. retval = davinci_spi_setup_transfer(spi, NULL);
  410. return retval;
  411. }
  412. static void davinci_spi_cleanup(struct spi_device *spi)
  413. {
  414. struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
  415. struct davinci_spi_dma *davinci_spi_dma;
  416. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  417. if (use_dma && davinci_spi->dma_channels) {
  418. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  419. if ((davinci_spi_dma->dma_rx_channel != -1)
  420. && (davinci_spi_dma->dma_tx_channel != -1)) {
  421. edma_free_channel(davinci_spi_dma->dma_tx_channel);
  422. edma_free_channel(davinci_spi_dma->dma_rx_channel);
  423. }
  424. }
  425. }
  426. static int davinci_spi_bufs_prep(struct spi_device *spi,
  427. struct davinci_spi *davinci_spi)
  428. {
  429. struct davinci_spi_platform_data *pdata;
  430. int op_mode = 0;
  431. /*
  432. * REVISIT unless devices disagree about SPI_LOOP or
  433. * SPI_READY (SPI_NO_CS only allows one device!), this
  434. * should not need to be done before each message...
  435. * optimize for both flags staying cleared.
  436. */
  437. op_mode = SPIPC0_DIFUN_MASK
  438. | SPIPC0_DOFUN_MASK
  439. | SPIPC0_CLKFUN_MASK;
  440. if (!(spi->mode & SPI_NO_CS)) {
  441. pdata = davinci_spi->pdata;
  442. if (!pdata->chip_sel ||
  443. pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)
  444. op_mode |= 1 << spi->chip_select;
  445. }
  446. if (spi->mode & SPI_READY)
  447. op_mode |= SPIPC0_SPIENA_MASK;
  448. iowrite32(op_mode, davinci_spi->base + SPIPC0);
  449. if (spi->mode & SPI_LOOP)
  450. set_io_bits(davinci_spi->base + SPIGCR1,
  451. SPIGCR1_LOOPBACK_MASK);
  452. else
  453. clear_io_bits(davinci_spi->base + SPIGCR1,
  454. SPIGCR1_LOOPBACK_MASK);
  455. return 0;
  456. }
  457. static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
  458. int int_status)
  459. {
  460. struct device *sdev = davinci_spi->bitbang.master->dev.parent;
  461. if (int_status & SPIFLG_TIMEOUT_MASK) {
  462. dev_dbg(sdev, "SPI Time-out Error\n");
  463. return -ETIMEDOUT;
  464. }
  465. if (int_status & SPIFLG_DESYNC_MASK) {
  466. dev_dbg(sdev, "SPI Desynchronization Error\n");
  467. return -EIO;
  468. }
  469. if (int_status & SPIFLG_BITERR_MASK) {
  470. dev_dbg(sdev, "SPI Bit error\n");
  471. return -EIO;
  472. }
  473. if (davinci_spi->version == SPI_VERSION_2) {
  474. if (int_status & SPIFLG_DLEN_ERR_MASK) {
  475. dev_dbg(sdev, "SPI Data Length Error\n");
  476. return -EIO;
  477. }
  478. if (int_status & SPIFLG_PARERR_MASK) {
  479. dev_dbg(sdev, "SPI Parity Error\n");
  480. return -EIO;
  481. }
  482. if (int_status & SPIFLG_OVRRUN_MASK) {
  483. dev_dbg(sdev, "SPI Data Overrun error\n");
  484. return -EIO;
  485. }
  486. if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
  487. dev_dbg(sdev, "SPI Buffer Init Active\n");
  488. return -EBUSY;
  489. }
  490. }
  491. return 0;
  492. }
  493. /**
  494. * davinci_spi_bufs - functions which will handle transfer data
  495. * @spi: spi device on which data transfer to be done
  496. * @t: spi transfer in which transfer info is filled
  497. *
  498. * This function will put data to be transferred into data register
  499. * of SPI controller and then wait until the completion will be marked
  500. * by the IRQ Handler.
  501. */
  502. static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
  503. {
  504. struct davinci_spi *davinci_spi;
  505. int ret;
  506. int rcount, wcount;
  507. u32 tx_data, data1_reg_val;
  508. u32 errors = 0;
  509. struct davinci_spi_platform_data *pdata;
  510. davinci_spi = spi_master_get_devdata(spi->master);
  511. pdata = davinci_spi->pdata;
  512. davinci_spi->tx = t->tx_buf;
  513. davinci_spi->rx = t->rx_buf;
  514. wcount = t->len / davinci_spi->bytes_per_word[spi->chip_select];
  515. rcount = wcount;
  516. ret = davinci_spi_bufs_prep(spi, davinci_spi);
  517. if (ret)
  518. return ret;
  519. data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
  520. /* Enable SPI */
  521. set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  522. clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
  523. /* start the transfer */
  524. wcount--;
  525. tx_data = davinci_spi->get_tx(davinci_spi);
  526. data1_reg_val &= 0xFFFF0000;
  527. data1_reg_val |= tx_data & 0xFFFF;
  528. iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
  529. while (rcount > 0 || wcount > 0) {
  530. u32 buf, status;
  531. buf = ioread32(davinci_spi->base + SPIBUF);
  532. if (!(buf & SPIBUF_RXEMPTY_MASK)) {
  533. davinci_spi->get_rx(buf & 0xFFFF, davinci_spi);
  534. rcount--;
  535. }
  536. status = ioread32(davinci_spi->base + SPIFLG);
  537. if (unlikely(status & SPIFLG_ERROR_MASK)) {
  538. errors = status & SPIFLG_ERROR_MASK;
  539. break;
  540. }
  541. if (wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
  542. wcount--;
  543. tx_data = davinci_spi->get_tx(davinci_spi);
  544. data1_reg_val &= ~0xFFFF;
  545. data1_reg_val |= 0xFFFF & tx_data;
  546. iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
  547. }
  548. }
  549. /*
  550. * Check for bit error, desync error,parity error,timeout error and
  551. * receive overflow errors
  552. */
  553. if (errors) {
  554. ret = davinci_spi_check_error(davinci_spi, errors);
  555. WARN(!ret, "%s: error reported but no error found!\n",
  556. dev_name(&spi->dev));
  557. return ret;
  558. }
  559. return t->len;
  560. }
  561. static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
  562. {
  563. struct davinci_spi *davinci_spi;
  564. int int_status = 0;
  565. int count, temp_count;
  566. u32 data1_reg_val;
  567. struct davinci_spi_dma *davinci_spi_dma;
  568. int data_type, ret;
  569. unsigned long tx_reg, rx_reg;
  570. struct device *sdev;
  571. davinci_spi = spi_master_get_devdata(spi->master);
  572. sdev = davinci_spi->bitbang.master->dev.parent;
  573. davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
  574. tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
  575. rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
  576. davinci_spi->tx = t->tx_buf;
  577. davinci_spi->rx = t->rx_buf;
  578. /* convert len to words based on bits_per_word */
  579. data_type = davinci_spi->bytes_per_word[spi->chip_select];
  580. data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
  581. init_completion(&davinci_spi_dma->dma_rx_completion);
  582. init_completion(&davinci_spi_dma->dma_tx_completion);
  583. ret = davinci_spi_bufs_prep(spi, davinci_spi);
  584. if (ret)
  585. return ret;
  586. count = t->len / data_type; /* the number of elements */
  587. /* disable all interrupts for dma transfers */
  588. clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
  589. /* Enable SPI */
  590. set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
  591. if (t->tx_buf) {
  592. t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
  593. DMA_TO_DEVICE);
  594. if (dma_mapping_error(&spi->dev, t->tx_dma)) {
  595. dev_dbg(sdev, "Unable to DMA map a %d bytes"
  596. " TX buffer\n", count);
  597. return -ENOMEM;
  598. }
  599. temp_count = count;
  600. } else {
  601. /* We need TX clocking for RX transaction */
  602. t->tx_dma = dma_map_single(&spi->dev,
  603. (void *)davinci_spi->tmp_buf, count + 1,
  604. DMA_TO_DEVICE);
  605. if (dma_mapping_error(&spi->dev, t->tx_dma)) {
  606. dev_dbg(sdev, "Unable to DMA map a %d bytes"
  607. " TX tmp buffer\n", count);
  608. return -ENOMEM;
  609. }
  610. temp_count = count + 1;
  611. }
  612. edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
  613. data_type, temp_count, 1, 0, ASYNC);
  614. edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
  615. edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
  616. edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
  617. edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
  618. if (t->rx_buf) {
  619. /* initiate transaction */
  620. iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
  621. t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
  622. DMA_FROM_DEVICE);
  623. if (dma_mapping_error(&spi->dev, t->rx_dma)) {
  624. dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
  625. count);
  626. if (t->tx_buf != NULL)
  627. dma_unmap_single(NULL, t->tx_dma,
  628. count, DMA_TO_DEVICE);
  629. return -ENOMEM;
  630. }
  631. edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
  632. data_type, count, 1, 0, ASYNC);
  633. edma_set_src(davinci_spi_dma->dma_rx_channel,
  634. rx_reg, INCR, W8BIT);
  635. edma_set_dest(davinci_spi_dma->dma_rx_channel,
  636. t->rx_dma, INCR, W8BIT);
  637. edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
  638. edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
  639. data_type, 0);
  640. }
  641. if ((t->tx_buf) || (t->rx_buf))
  642. edma_start(davinci_spi_dma->dma_tx_channel);
  643. if (t->rx_buf)
  644. edma_start(davinci_spi_dma->dma_rx_channel);
  645. if ((t->rx_buf) || (t->tx_buf))
  646. davinci_spi_set_dma_req(spi, 1);
  647. if (t->tx_buf)
  648. wait_for_completion_interruptible(
  649. &davinci_spi_dma->dma_tx_completion);
  650. if (t->rx_buf)
  651. wait_for_completion_interruptible(
  652. &davinci_spi_dma->dma_rx_completion);
  653. dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
  654. if (t->rx_buf)
  655. dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
  656. /*
  657. * Check for bit error, desync error,parity error,timeout error and
  658. * receive overflow errors
  659. */
  660. int_status = ioread32(davinci_spi->base + SPIFLG);
  661. ret = davinci_spi_check_error(davinci_spi, int_status);
  662. if (ret != 0)
  663. return ret;
  664. return t->len;
  665. }
  666. /**
  667. * davinci_spi_probe - probe function for SPI Master Controller
  668. * @pdev: platform_device structure which contains plateform specific data
  669. */
  670. static int davinci_spi_probe(struct platform_device *pdev)
  671. {
  672. struct spi_master *master;
  673. struct davinci_spi *davinci_spi;
  674. struct davinci_spi_platform_data *pdata;
  675. struct resource *r, *mem;
  676. resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
  677. resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
  678. resource_size_t dma_eventq = SPI_NO_RESOURCE;
  679. int i = 0, ret = 0;
  680. pdata = pdev->dev.platform_data;
  681. if (pdata == NULL) {
  682. ret = -ENODEV;
  683. goto err;
  684. }
  685. master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
  686. if (master == NULL) {
  687. ret = -ENOMEM;
  688. goto err;
  689. }
  690. dev_set_drvdata(&pdev->dev, master);
  691. davinci_spi = spi_master_get_devdata(master);
  692. if (davinci_spi == NULL) {
  693. ret = -ENOENT;
  694. goto free_master;
  695. }
  696. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  697. if (r == NULL) {
  698. ret = -ENOENT;
  699. goto free_master;
  700. }
  701. davinci_spi->pbase = r->start;
  702. davinci_spi->region_size = resource_size(r);
  703. davinci_spi->pdata = pdata;
  704. mem = request_mem_region(r->start, davinci_spi->region_size,
  705. pdev->name);
  706. if (mem == NULL) {
  707. ret = -EBUSY;
  708. goto free_master;
  709. }
  710. davinci_spi->base = ioremap(r->start, davinci_spi->region_size);
  711. if (davinci_spi->base == NULL) {
  712. ret = -ENOMEM;
  713. goto release_region;
  714. }
  715. /* Allocate tmp_buf for tx_buf */
  716. davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
  717. if (davinci_spi->tmp_buf == NULL) {
  718. ret = -ENOMEM;
  719. goto unmap_io;
  720. }
  721. davinci_spi->bitbang.master = spi_master_get(master);
  722. if (davinci_spi->bitbang.master == NULL) {
  723. ret = -ENODEV;
  724. goto free_tmp_buf;
  725. }
  726. davinci_spi->clk = clk_get(&pdev->dev, NULL);
  727. if (IS_ERR(davinci_spi->clk)) {
  728. ret = -ENODEV;
  729. goto put_master;
  730. }
  731. clk_enable(davinci_spi->clk);
  732. master->bus_num = pdev->id;
  733. master->num_chipselect = pdata->num_chipselect;
  734. master->setup = davinci_spi_setup;
  735. master->cleanup = davinci_spi_cleanup;
  736. davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
  737. davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
  738. davinci_spi->version = pdata->version;
  739. use_dma = pdata->use_dma;
  740. davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
  741. if (davinci_spi->version == SPI_VERSION_2)
  742. davinci_spi->bitbang.flags |= SPI_READY;
  743. if (use_dma) {
  744. r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  745. if (r)
  746. dma_rx_chan = r->start;
  747. r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  748. if (r)
  749. dma_tx_chan = r->start;
  750. r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
  751. if (r)
  752. dma_eventq = r->start;
  753. }
  754. if (!use_dma ||
  755. dma_rx_chan == SPI_NO_RESOURCE ||
  756. dma_tx_chan == SPI_NO_RESOURCE ||
  757. dma_eventq == SPI_NO_RESOURCE) {
  758. davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
  759. use_dma = 0;
  760. } else {
  761. davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
  762. davinci_spi->dma_channels = kzalloc(master->num_chipselect
  763. * sizeof(struct davinci_spi_dma), GFP_KERNEL);
  764. if (davinci_spi->dma_channels == NULL) {
  765. ret = -ENOMEM;
  766. goto free_clk;
  767. }
  768. for (i = 0; i < master->num_chipselect; i++) {
  769. davinci_spi->dma_channels[i].dma_rx_channel = -1;
  770. davinci_spi->dma_channels[i].dma_rx_sync_dev =
  771. dma_rx_chan;
  772. davinci_spi->dma_channels[i].dma_tx_channel = -1;
  773. davinci_spi->dma_channels[i].dma_tx_sync_dev =
  774. dma_tx_chan;
  775. davinci_spi->dma_channels[i].eventq = dma_eventq;
  776. }
  777. dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
  778. "Using RX channel = %d , TX channel = %d and "
  779. "event queue = %d", dma_rx_chan, dma_tx_chan,
  780. dma_eventq);
  781. }
  782. davinci_spi->get_rx = davinci_spi_rx_buf_u8;
  783. davinci_spi->get_tx = davinci_spi_tx_buf_u8;
  784. /* Reset In/OUT SPI module */
  785. iowrite32(0, davinci_spi->base + SPIGCR0);
  786. udelay(100);
  787. iowrite32(1, davinci_spi->base + SPIGCR0);
  788. /* initialize chip selects */
  789. if (pdata->chip_sel) {
  790. for (i = 0; i < pdata->num_chipselect; i++) {
  791. if (pdata->chip_sel[i] != SPI_INTERN_CS)
  792. gpio_direction_output(pdata->chip_sel[i], 1);
  793. }
  794. }
  795. /* Clock internal */
  796. if (davinci_spi->pdata->clk_internal)
  797. set_io_bits(davinci_spi->base + SPIGCR1,
  798. SPIGCR1_CLKMOD_MASK);
  799. else
  800. clear_io_bits(davinci_spi->base + SPIGCR1,
  801. SPIGCR1_CLKMOD_MASK);
  802. iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
  803. /* master mode default */
  804. set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
  805. ret = spi_bitbang_start(&davinci_spi->bitbang);
  806. if (ret)
  807. goto free_clk;
  808. dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base);
  809. return ret;
  810. free_clk:
  811. clk_disable(davinci_spi->clk);
  812. clk_put(davinci_spi->clk);
  813. put_master:
  814. spi_master_put(master);
  815. free_tmp_buf:
  816. kfree(davinci_spi->tmp_buf);
  817. unmap_io:
  818. iounmap(davinci_spi->base);
  819. release_region:
  820. release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
  821. free_master:
  822. kfree(master);
  823. err:
  824. return ret;
  825. }
  826. /**
  827. * davinci_spi_remove - remove function for SPI Master Controller
  828. * @pdev: platform_device structure which contains plateform specific data
  829. *
  830. * This function will do the reverse action of davinci_spi_probe function
  831. * It will free the IRQ and SPI controller's memory region.
  832. * It will also call spi_bitbang_stop to destroy the work queue which was
  833. * created by spi_bitbang_start.
  834. */
  835. static int __exit davinci_spi_remove(struct platform_device *pdev)
  836. {
  837. struct davinci_spi *davinci_spi;
  838. struct spi_master *master;
  839. master = dev_get_drvdata(&pdev->dev);
  840. davinci_spi = spi_master_get_devdata(master);
  841. spi_bitbang_stop(&davinci_spi->bitbang);
  842. clk_disable(davinci_spi->clk);
  843. clk_put(davinci_spi->clk);
  844. spi_master_put(master);
  845. kfree(davinci_spi->tmp_buf);
  846. iounmap(davinci_spi->base);
  847. release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
  848. return 0;
  849. }
  850. static struct platform_driver davinci_spi_driver = {
  851. .driver.name = "spi_davinci",
  852. .remove = __exit_p(davinci_spi_remove),
  853. };
  854. static int __init davinci_spi_init(void)
  855. {
  856. return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
  857. }
  858. module_init(davinci_spi_init);
  859. static void __exit davinci_spi_exit(void)
  860. {
  861. platform_driver_unregister(&davinci_spi_driver);
  862. }
  863. module_exit(davinci_spi_exit);
  864. MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
  865. MODULE_LICENSE("GPL");