mach-imx6q.c 4.9 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clkdev.h>
  14. #include <linux/cpuidle.h>
  15. #include <linux/delay.h>
  16. #include <linux/export.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/pinctrl/machine.h>
  26. #include <linux/phy.h>
  27. #include <linux/micrel_phy.h>
  28. #include <asm/cpuidle.h>
  29. #include <asm/smp_twd.h>
  30. #include <asm/hardware/cache-l2x0.h>
  31. #include <asm/hardware/gic.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/time.h>
  34. #include <asm/system_misc.h>
  35. #include <mach/common.h>
  36. #include <mach/cpuidle.h>
  37. #include <mach/hardware.h>
  38. void imx6q_restart(char mode, const char *cmd)
  39. {
  40. struct device_node *np;
  41. void __iomem *wdog_base;
  42. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  43. wdog_base = of_iomap(np, 0);
  44. if (!wdog_base)
  45. goto soft;
  46. imx_src_prepare_restart();
  47. /* enable wdog */
  48. writew_relaxed(1 << 2, wdog_base);
  49. /* write twice to ensure the request will not get ignored */
  50. writew_relaxed(1 << 2, wdog_base);
  51. /* wait for reset to assert ... */
  52. mdelay(500);
  53. pr_err("Watchdog reset failed to assert reset\n");
  54. /* delay to allow the serial port to show the message */
  55. mdelay(50);
  56. soft:
  57. /* we'll take a jump through zero as a poor second */
  58. soft_restart(0);
  59. }
  60. /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
  61. static int ksz9021rn_phy_fixup(struct phy_device *phydev)
  62. {
  63. if (IS_ENABLED(CONFIG_PHYLIB)) {
  64. /* min rx data delay */
  65. phy_write(phydev, 0x0b, 0x8105);
  66. phy_write(phydev, 0x0c, 0x0000);
  67. /* max rx/tx clock delay, min rx/tx control delay */
  68. phy_write(phydev, 0x0b, 0x8104);
  69. phy_write(phydev, 0x0c, 0xf0f0);
  70. phy_write(phydev, 0x0b, 0x104);
  71. }
  72. return 0;
  73. }
  74. static void __init imx6q_sabrelite_cko1_setup(void)
  75. {
  76. struct clk *cko1_sel, *ahb, *cko1;
  77. unsigned long rate;
  78. cko1_sel = clk_get_sys(NULL, "cko1_sel");
  79. ahb = clk_get_sys(NULL, "ahb");
  80. cko1 = clk_get_sys(NULL, "cko1");
  81. if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
  82. pr_err("cko1 setup failed!\n");
  83. goto put_clk;
  84. }
  85. clk_set_parent(cko1_sel, ahb);
  86. rate = clk_round_rate(cko1, 16000000);
  87. clk_set_rate(cko1, rate);
  88. clk_register_clkdev(cko1, NULL, "0-000a");
  89. put_clk:
  90. if (!IS_ERR(cko1_sel))
  91. clk_put(cko1_sel);
  92. if (!IS_ERR(ahb))
  93. clk_put(ahb);
  94. if (!IS_ERR(cko1))
  95. clk_put(cko1);
  96. }
  97. static void __init imx6q_sabrelite_init(void)
  98. {
  99. if (IS_ENABLED(CONFIG_PHYLIB))
  100. phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
  101. ksz9021rn_phy_fixup);
  102. imx6q_sabrelite_cko1_setup();
  103. }
  104. static void __init imx6q_init_machine(void)
  105. {
  106. /*
  107. * This should be removed when all imx6q boards have pinctrl
  108. * states for devices defined in device tree.
  109. */
  110. pinctrl_provide_dummies();
  111. if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
  112. imx6q_sabrelite_init();
  113. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  114. imx6q_pm_init();
  115. }
  116. static struct cpuidle_driver imx6q_cpuidle_driver = {
  117. .name = "imx6q_cpuidle",
  118. .owner = THIS_MODULE,
  119. .en_core_tk_irqen = 1,
  120. .states[0] = ARM_CPUIDLE_WFI_STATE,
  121. .state_count = 1,
  122. };
  123. static void __init imx6q_init_late(void)
  124. {
  125. imx_cpuidle_init(&imx6q_cpuidle_driver);
  126. }
  127. static void __init imx6q_map_io(void)
  128. {
  129. imx_lluart_map_io();
  130. imx_scu_map_io();
  131. imx6q_clock_map_io();
  132. }
  133. static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
  134. struct device_node *interrupt_parent)
  135. {
  136. static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
  137. gpio_irq_base -= 32;
  138. irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
  139. NULL);
  140. return 0;
  141. }
  142. static const struct of_device_id imx6q_irq_match[] __initconst = {
  143. { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
  144. { .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
  145. { /* sentinel */ }
  146. };
  147. static void __init imx6q_init_irq(void)
  148. {
  149. l2x0_of_init(0, ~0UL);
  150. imx_src_init();
  151. imx_gpc_init();
  152. of_irq_init(imx6q_irq_match);
  153. }
  154. static void __init imx6q_timer_init(void)
  155. {
  156. mx6q_clocks_init();
  157. twd_local_timer_of_register();
  158. }
  159. static struct sys_timer imx6q_timer = {
  160. .init = imx6q_timer_init,
  161. };
  162. static const char *imx6q_dt_compat[] __initdata = {
  163. "fsl,imx6q-arm2",
  164. "fsl,imx6q-sabrelite",
  165. "fsl,imx6q-sabresd",
  166. "fsl,imx6q",
  167. NULL,
  168. };
  169. DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
  170. .map_io = imx6q_map_io,
  171. .init_irq = imx6q_init_irq,
  172. .handle_irq = imx6q_handle_irq,
  173. .timer = &imx6q_timer,
  174. .init_machine = imx6q_init_machine,
  175. .init_late = imx6q_init_late,
  176. .dt_compat = imx6q_dt_compat,
  177. .restart = imx6q_restart,
  178. MACHINE_END