dmatest.c 21 KB

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  1. /*
  2. * DMA Engine test module
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/freezer.h>
  14. #include <linux/init.h>
  15. #include <linux/kthread.h>
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/random.h>
  19. #include <linux/slab.h>
  20. #include <linux/wait.h>
  21. static unsigned int test_buf_size = 16384;
  22. module_param(test_buf_size, uint, S_IRUGO);
  23. MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  24. static char test_channel[20];
  25. module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
  26. MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
  27. static char test_device[20];
  28. module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
  29. MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  30. static unsigned int threads_per_chan = 1;
  31. module_param(threads_per_chan, uint, S_IRUGO);
  32. MODULE_PARM_DESC(threads_per_chan,
  33. "Number of threads to start per channel (default: 1)");
  34. static unsigned int max_channels;
  35. module_param(max_channels, uint, S_IRUGO);
  36. MODULE_PARM_DESC(max_channels,
  37. "Maximum number of channels to use (default: all)");
  38. static unsigned int iterations;
  39. module_param(iterations, uint, S_IRUGO);
  40. MODULE_PARM_DESC(iterations,
  41. "Iterations before stopping test (default: infinite)");
  42. static unsigned int xor_sources = 3;
  43. module_param(xor_sources, uint, S_IRUGO);
  44. MODULE_PARM_DESC(xor_sources,
  45. "Number of xor source buffers (default: 3)");
  46. static unsigned int pq_sources = 3;
  47. module_param(pq_sources, uint, S_IRUGO);
  48. MODULE_PARM_DESC(pq_sources,
  49. "Number of p+q source buffers (default: 3)");
  50. static int timeout = 3000;
  51. module_param(timeout, uint, S_IRUGO);
  52. MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  53. "Pass -1 for infinite timeout");
  54. /*
  55. * Initialization patterns. All bytes in the source buffer has bit 7
  56. * set, all bytes in the destination buffer has bit 7 cleared.
  57. *
  58. * Bit 6 is set for all bytes which are to be copied by the DMA
  59. * engine. Bit 5 is set for all bytes which are to be overwritten by
  60. * the DMA engine.
  61. *
  62. * The remaining bits are the inverse of a counter which increments by
  63. * one for each byte address.
  64. */
  65. #define PATTERN_SRC 0x80
  66. #define PATTERN_DST 0x00
  67. #define PATTERN_COPY 0x40
  68. #define PATTERN_OVERWRITE 0x20
  69. #define PATTERN_COUNT_MASK 0x1f
  70. struct dmatest_info;
  71. struct dmatest_thread {
  72. struct list_head node;
  73. struct dmatest_info *info;
  74. struct task_struct *task;
  75. struct dma_chan *chan;
  76. u8 **srcs;
  77. u8 **dsts;
  78. enum dma_transaction_type type;
  79. };
  80. struct dmatest_chan {
  81. struct list_head node;
  82. struct dma_chan *chan;
  83. struct list_head threads;
  84. };
  85. /**
  86. * struct dmatest_info - test information.
  87. * @buf_size: size of the memcpy test buffer
  88. * @channel: bus ID of the channel to test
  89. * @device: bus ID of the DMA Engine to test
  90. * @threads_per_chan: number of threads to start per channel
  91. * @max_channels: maximum number of channels to use
  92. * @iterations: iterations before stopping test
  93. * @xor_sources: number of xor source buffers
  94. * @pq_sources: number of p+q source buffers
  95. * @timeout: transfer timeout in msec, -1 for infinite timeout
  96. */
  97. struct dmatest_info {
  98. /* Test parameters */
  99. unsigned int buf_size;
  100. char channel[20];
  101. char device[20];
  102. unsigned int threads_per_chan;
  103. unsigned int max_channels;
  104. unsigned int iterations;
  105. unsigned int xor_sources;
  106. unsigned int pq_sources;
  107. int timeout;
  108. /* Internal state */
  109. struct list_head channels;
  110. unsigned int nr_channels;
  111. };
  112. static struct dmatest_info test_info;
  113. static bool dmatest_match_channel(struct dmatest_info *info,
  114. struct dma_chan *chan)
  115. {
  116. if (info->channel[0] == '\0')
  117. return true;
  118. return strcmp(dma_chan_name(chan), info->channel) == 0;
  119. }
  120. static bool dmatest_match_device(struct dmatest_info *info,
  121. struct dma_device *device)
  122. {
  123. if (info->device[0] == '\0')
  124. return true;
  125. return strcmp(dev_name(device->dev), info->device) == 0;
  126. }
  127. static unsigned long dmatest_random(void)
  128. {
  129. unsigned long buf;
  130. get_random_bytes(&buf, sizeof(buf));
  131. return buf;
  132. }
  133. static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
  134. unsigned int buf_size)
  135. {
  136. unsigned int i;
  137. u8 *buf;
  138. for (; (buf = *bufs); bufs++) {
  139. for (i = 0; i < start; i++)
  140. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  141. for ( ; i < start + len; i++)
  142. buf[i] = PATTERN_SRC | PATTERN_COPY
  143. | (~i & PATTERN_COUNT_MASK);
  144. for ( ; i < buf_size; i++)
  145. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  146. buf++;
  147. }
  148. }
  149. static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
  150. unsigned int buf_size)
  151. {
  152. unsigned int i;
  153. u8 *buf;
  154. for (; (buf = *bufs); bufs++) {
  155. for (i = 0; i < start; i++)
  156. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  157. for ( ; i < start + len; i++)
  158. buf[i] = PATTERN_DST | PATTERN_OVERWRITE
  159. | (~i & PATTERN_COUNT_MASK);
  160. for ( ; i < buf_size; i++)
  161. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  162. }
  163. }
  164. static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
  165. unsigned int counter, bool is_srcbuf)
  166. {
  167. u8 diff = actual ^ pattern;
  168. u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
  169. const char *thread_name = current->comm;
  170. if (is_srcbuf)
  171. pr_warning("%s: srcbuf[0x%x] overwritten!"
  172. " Expected %02x, got %02x\n",
  173. thread_name, index, expected, actual);
  174. else if ((pattern & PATTERN_COPY)
  175. && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
  176. pr_warning("%s: dstbuf[0x%x] not copied!"
  177. " Expected %02x, got %02x\n",
  178. thread_name, index, expected, actual);
  179. else if (diff & PATTERN_SRC)
  180. pr_warning("%s: dstbuf[0x%x] was copied!"
  181. " Expected %02x, got %02x\n",
  182. thread_name, index, expected, actual);
  183. else
  184. pr_warning("%s: dstbuf[0x%x] mismatch!"
  185. " Expected %02x, got %02x\n",
  186. thread_name, index, expected, actual);
  187. }
  188. static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
  189. unsigned int end, unsigned int counter, u8 pattern,
  190. bool is_srcbuf)
  191. {
  192. unsigned int i;
  193. unsigned int error_count = 0;
  194. u8 actual;
  195. u8 expected;
  196. u8 *buf;
  197. unsigned int counter_orig = counter;
  198. for (; (buf = *bufs); bufs++) {
  199. counter = counter_orig;
  200. for (i = start; i < end; i++) {
  201. actual = buf[i];
  202. expected = pattern | (~counter & PATTERN_COUNT_MASK);
  203. if (actual != expected) {
  204. if (error_count < 32)
  205. dmatest_mismatch(actual, pattern, i,
  206. counter, is_srcbuf);
  207. error_count++;
  208. }
  209. counter++;
  210. }
  211. }
  212. if (error_count > 32)
  213. pr_warning("%s: %u errors suppressed\n",
  214. current->comm, error_count - 32);
  215. return error_count;
  216. }
  217. /* poor man's completion - we want to use wait_event_freezable() on it */
  218. struct dmatest_done {
  219. bool done;
  220. wait_queue_head_t *wait;
  221. };
  222. static void dmatest_callback(void *arg)
  223. {
  224. struct dmatest_done *done = arg;
  225. done->done = true;
  226. wake_up_all(done->wait);
  227. }
  228. static inline void unmap_src(struct device *dev, dma_addr_t *addr, size_t len,
  229. unsigned int count)
  230. {
  231. while (count--)
  232. dma_unmap_single(dev, addr[count], len, DMA_TO_DEVICE);
  233. }
  234. static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
  235. unsigned int count)
  236. {
  237. while (count--)
  238. dma_unmap_single(dev, addr[count], len, DMA_BIDIRECTIONAL);
  239. }
  240. static unsigned int min_odd(unsigned int x, unsigned int y)
  241. {
  242. unsigned int val = min(x, y);
  243. return val % 2 ? val : val - 1;
  244. }
  245. /*
  246. * This function repeatedly tests DMA transfers of various lengths and
  247. * offsets for a given operation type until it is told to exit by
  248. * kthread_stop(). There may be multiple threads running this function
  249. * in parallel for a single channel, and there may be multiple channels
  250. * being tested in parallel.
  251. *
  252. * Before each test, the source and destination buffer is initialized
  253. * with a known pattern. This pattern is different depending on
  254. * whether it's in an area which is supposed to be copied or
  255. * overwritten, and different in the source and destination buffers.
  256. * So if the DMA engine doesn't copy exactly what we tell it to copy,
  257. * we'll notice.
  258. */
  259. static int dmatest_func(void *data)
  260. {
  261. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
  262. struct dmatest_thread *thread = data;
  263. struct dmatest_done done = { .wait = &done_wait };
  264. struct dmatest_info *info;
  265. struct dma_chan *chan;
  266. struct dma_device *dev;
  267. const char *thread_name;
  268. unsigned int src_off, dst_off, len;
  269. unsigned int error_count;
  270. unsigned int failed_tests = 0;
  271. unsigned int total_tests = 0;
  272. dma_cookie_t cookie;
  273. enum dma_status status;
  274. enum dma_ctrl_flags flags;
  275. u8 *pq_coefs = NULL;
  276. int ret;
  277. int src_cnt;
  278. int dst_cnt;
  279. int i;
  280. thread_name = current->comm;
  281. set_freezable();
  282. ret = -ENOMEM;
  283. smp_rmb();
  284. info = thread->info;
  285. chan = thread->chan;
  286. dev = chan->device;
  287. if (thread->type == DMA_MEMCPY)
  288. src_cnt = dst_cnt = 1;
  289. else if (thread->type == DMA_XOR) {
  290. /* force odd to ensure dst = src */
  291. src_cnt = min_odd(info->xor_sources | 1, dev->max_xor);
  292. dst_cnt = 1;
  293. } else if (thread->type == DMA_PQ) {
  294. /* force odd to ensure dst = src */
  295. src_cnt = min_odd(info->pq_sources | 1, dma_maxpq(dev, 0));
  296. dst_cnt = 2;
  297. pq_coefs = kmalloc(info->pq_sources+1, GFP_KERNEL);
  298. if (!pq_coefs)
  299. goto err_thread_type;
  300. for (i = 0; i < src_cnt; i++)
  301. pq_coefs[i] = 1;
  302. } else
  303. goto err_thread_type;
  304. thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
  305. if (!thread->srcs)
  306. goto err_srcs;
  307. for (i = 0; i < src_cnt; i++) {
  308. thread->srcs[i] = kmalloc(info->buf_size, GFP_KERNEL);
  309. if (!thread->srcs[i])
  310. goto err_srcbuf;
  311. }
  312. thread->srcs[i] = NULL;
  313. thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
  314. if (!thread->dsts)
  315. goto err_dsts;
  316. for (i = 0; i < dst_cnt; i++) {
  317. thread->dsts[i] = kmalloc(info->buf_size, GFP_KERNEL);
  318. if (!thread->dsts[i])
  319. goto err_dstbuf;
  320. }
  321. thread->dsts[i] = NULL;
  322. set_user_nice(current, 10);
  323. /*
  324. * src buffers are freed by the DMAEngine code with dma_unmap_single()
  325. * dst buffers are freed by ourselves below
  326. */
  327. flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
  328. | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
  329. while (!kthread_should_stop()
  330. && !(info->iterations && total_tests >= info->iterations)) {
  331. struct dma_async_tx_descriptor *tx = NULL;
  332. dma_addr_t dma_srcs[src_cnt];
  333. dma_addr_t dma_dsts[dst_cnt];
  334. u8 align = 0;
  335. total_tests++;
  336. /* honor alignment restrictions */
  337. if (thread->type == DMA_MEMCPY)
  338. align = dev->copy_align;
  339. else if (thread->type == DMA_XOR)
  340. align = dev->xor_align;
  341. else if (thread->type == DMA_PQ)
  342. align = dev->pq_align;
  343. if (1 << align > info->buf_size) {
  344. pr_err("%u-byte buffer too small for %d-byte alignment\n",
  345. info->buf_size, 1 << align);
  346. break;
  347. }
  348. len = dmatest_random() % info->buf_size + 1;
  349. len = (len >> align) << align;
  350. if (!len)
  351. len = 1 << align;
  352. src_off = dmatest_random() % (info->buf_size - len + 1);
  353. dst_off = dmatest_random() % (info->buf_size - len + 1);
  354. src_off = (src_off >> align) << align;
  355. dst_off = (dst_off >> align) << align;
  356. dmatest_init_srcs(thread->srcs, src_off, len, info->buf_size);
  357. dmatest_init_dsts(thread->dsts, dst_off, len, info->buf_size);
  358. for (i = 0; i < src_cnt; i++) {
  359. u8 *buf = thread->srcs[i] + src_off;
  360. dma_srcs[i] = dma_map_single(dev->dev, buf, len,
  361. DMA_TO_DEVICE);
  362. ret = dma_mapping_error(dev->dev, dma_srcs[i]);
  363. if (ret) {
  364. unmap_src(dev->dev, dma_srcs, len, i);
  365. pr_warn("%s: #%u: mapping error %d with "
  366. "src_off=0x%x len=0x%x\n",
  367. thread_name, total_tests - 1, ret,
  368. src_off, len);
  369. failed_tests++;
  370. continue;
  371. }
  372. }
  373. /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
  374. for (i = 0; i < dst_cnt; i++) {
  375. dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
  376. info->buf_size,
  377. DMA_BIDIRECTIONAL);
  378. ret = dma_mapping_error(dev->dev, dma_dsts[i]);
  379. if (ret) {
  380. unmap_src(dev->dev, dma_srcs, len, src_cnt);
  381. unmap_dst(dev->dev, dma_dsts, info->buf_size, i);
  382. pr_warn("%s: #%u: mapping error %d with "
  383. "dst_off=0x%x len=0x%x\n",
  384. thread_name, total_tests - 1, ret,
  385. dst_off, info->buf_size);
  386. failed_tests++;
  387. continue;
  388. }
  389. }
  390. if (thread->type == DMA_MEMCPY)
  391. tx = dev->device_prep_dma_memcpy(chan,
  392. dma_dsts[0] + dst_off,
  393. dma_srcs[0], len,
  394. flags);
  395. else if (thread->type == DMA_XOR)
  396. tx = dev->device_prep_dma_xor(chan,
  397. dma_dsts[0] + dst_off,
  398. dma_srcs, src_cnt,
  399. len, flags);
  400. else if (thread->type == DMA_PQ) {
  401. dma_addr_t dma_pq[dst_cnt];
  402. for (i = 0; i < dst_cnt; i++)
  403. dma_pq[i] = dma_dsts[i] + dst_off;
  404. tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
  405. src_cnt, pq_coefs,
  406. len, flags);
  407. }
  408. if (!tx) {
  409. unmap_src(dev->dev, dma_srcs, len, src_cnt);
  410. unmap_dst(dev->dev, dma_dsts, info->buf_size, dst_cnt);
  411. pr_warning("%s: #%u: prep error with src_off=0x%x "
  412. "dst_off=0x%x len=0x%x\n",
  413. thread_name, total_tests - 1,
  414. src_off, dst_off, len);
  415. msleep(100);
  416. failed_tests++;
  417. continue;
  418. }
  419. done.done = false;
  420. tx->callback = dmatest_callback;
  421. tx->callback_param = &done;
  422. cookie = tx->tx_submit(tx);
  423. if (dma_submit_error(cookie)) {
  424. pr_warning("%s: #%u: submit error %d with src_off=0x%x "
  425. "dst_off=0x%x len=0x%x\n",
  426. thread_name, total_tests - 1, cookie,
  427. src_off, dst_off, len);
  428. msleep(100);
  429. failed_tests++;
  430. continue;
  431. }
  432. dma_async_issue_pending(chan);
  433. wait_event_freezable_timeout(done_wait,
  434. done.done || kthread_should_stop(),
  435. msecs_to_jiffies(info->timeout));
  436. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  437. if (!done.done) {
  438. /*
  439. * We're leaving the timed out dma operation with
  440. * dangling pointer to done_wait. To make this
  441. * correct, we'll need to allocate wait_done for
  442. * each test iteration and perform "who's gonna
  443. * free it this time?" dancing. For now, just
  444. * leave it dangling.
  445. */
  446. pr_warning("%s: #%u: test timed out\n",
  447. thread_name, total_tests - 1);
  448. failed_tests++;
  449. continue;
  450. } else if (status != DMA_SUCCESS) {
  451. pr_warning("%s: #%u: got completion callback,"
  452. " but status is \'%s\'\n",
  453. thread_name, total_tests - 1,
  454. status == DMA_ERROR ? "error" : "in progress");
  455. failed_tests++;
  456. continue;
  457. }
  458. /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
  459. unmap_dst(dev->dev, dma_dsts, info->buf_size, dst_cnt);
  460. error_count = 0;
  461. pr_debug("%s: verifying source buffer...\n", thread_name);
  462. error_count += dmatest_verify(thread->srcs, 0, src_off,
  463. 0, PATTERN_SRC, true);
  464. error_count += dmatest_verify(thread->srcs, src_off,
  465. src_off + len, src_off,
  466. PATTERN_SRC | PATTERN_COPY, true);
  467. error_count += dmatest_verify(thread->srcs, src_off + len,
  468. info->buf_size, src_off + len,
  469. PATTERN_SRC, true);
  470. pr_debug("%s: verifying dest buffer...\n",
  471. thread->task->comm);
  472. error_count += dmatest_verify(thread->dsts, 0, dst_off,
  473. 0, PATTERN_DST, false);
  474. error_count += dmatest_verify(thread->dsts, dst_off,
  475. dst_off + len, src_off,
  476. PATTERN_SRC | PATTERN_COPY, false);
  477. error_count += dmatest_verify(thread->dsts, dst_off + len,
  478. info->buf_size, dst_off + len,
  479. PATTERN_DST, false);
  480. if (error_count) {
  481. pr_warning("%s: #%u: %u errors with "
  482. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  483. thread_name, total_tests - 1, error_count,
  484. src_off, dst_off, len);
  485. failed_tests++;
  486. } else {
  487. pr_debug("%s: #%u: No errors with "
  488. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  489. thread_name, total_tests - 1,
  490. src_off, dst_off, len);
  491. }
  492. }
  493. ret = 0;
  494. for (i = 0; thread->dsts[i]; i++)
  495. kfree(thread->dsts[i]);
  496. err_dstbuf:
  497. kfree(thread->dsts);
  498. err_dsts:
  499. for (i = 0; thread->srcs[i]; i++)
  500. kfree(thread->srcs[i]);
  501. err_srcbuf:
  502. kfree(thread->srcs);
  503. err_srcs:
  504. kfree(pq_coefs);
  505. err_thread_type:
  506. pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
  507. thread_name, total_tests, failed_tests, ret);
  508. /* terminate all transfers on specified channels */
  509. if (ret)
  510. dmaengine_terminate_all(chan);
  511. if (info->iterations > 0)
  512. while (!kthread_should_stop()) {
  513. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
  514. interruptible_sleep_on(&wait_dmatest_exit);
  515. }
  516. return ret;
  517. }
  518. static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
  519. {
  520. struct dmatest_thread *thread;
  521. struct dmatest_thread *_thread;
  522. int ret;
  523. list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
  524. ret = kthread_stop(thread->task);
  525. pr_debug("dmatest: thread %s exited with status %d\n",
  526. thread->task->comm, ret);
  527. list_del(&thread->node);
  528. kfree(thread);
  529. }
  530. /* terminate all transfers on specified channels */
  531. dmaengine_terminate_all(dtc->chan);
  532. kfree(dtc);
  533. }
  534. static int dmatest_add_threads(struct dmatest_info *info,
  535. struct dmatest_chan *dtc, enum dma_transaction_type type)
  536. {
  537. struct dmatest_thread *thread;
  538. struct dma_chan *chan = dtc->chan;
  539. char *op;
  540. unsigned int i;
  541. if (type == DMA_MEMCPY)
  542. op = "copy";
  543. else if (type == DMA_XOR)
  544. op = "xor";
  545. else if (type == DMA_PQ)
  546. op = "pq";
  547. else
  548. return -EINVAL;
  549. for (i = 0; i < info->threads_per_chan; i++) {
  550. thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
  551. if (!thread) {
  552. pr_warning("dmatest: No memory for %s-%s%u\n",
  553. dma_chan_name(chan), op, i);
  554. break;
  555. }
  556. thread->info = info;
  557. thread->chan = dtc->chan;
  558. thread->type = type;
  559. smp_wmb();
  560. thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
  561. dma_chan_name(chan), op, i);
  562. if (IS_ERR(thread->task)) {
  563. pr_warning("dmatest: Failed to run thread %s-%s%u\n",
  564. dma_chan_name(chan), op, i);
  565. kfree(thread);
  566. break;
  567. }
  568. /* srcbuf and dstbuf are allocated by the thread itself */
  569. list_add_tail(&thread->node, &dtc->threads);
  570. }
  571. return i;
  572. }
  573. static int dmatest_add_channel(struct dmatest_info *info,
  574. struct dma_chan *chan)
  575. {
  576. struct dmatest_chan *dtc;
  577. struct dma_device *dma_dev = chan->device;
  578. unsigned int thread_count = 0;
  579. int cnt;
  580. dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
  581. if (!dtc) {
  582. pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
  583. return -ENOMEM;
  584. }
  585. dtc->chan = chan;
  586. INIT_LIST_HEAD(&dtc->threads);
  587. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  588. cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
  589. thread_count += cnt > 0 ? cnt : 0;
  590. }
  591. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  592. cnt = dmatest_add_threads(info, dtc, DMA_XOR);
  593. thread_count += cnt > 0 ? cnt : 0;
  594. }
  595. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  596. cnt = dmatest_add_threads(info, dtc, DMA_PQ);
  597. thread_count += cnt > 0 ? cnt : 0;
  598. }
  599. pr_info("dmatest: Started %u threads using %s\n",
  600. thread_count, dma_chan_name(chan));
  601. list_add_tail(&dtc->node, &info->channels);
  602. info->nr_channels++;
  603. return 0;
  604. }
  605. static bool filter(struct dma_chan *chan, void *param)
  606. {
  607. struct dmatest_info *info = param;
  608. if (!dmatest_match_channel(info, chan) ||
  609. !dmatest_match_device(info, chan->device))
  610. return false;
  611. else
  612. return true;
  613. }
  614. static int run_threaded_test(struct dmatest_info *info)
  615. {
  616. dma_cap_mask_t mask;
  617. struct dma_chan *chan;
  618. int err = 0;
  619. dma_cap_zero(mask);
  620. dma_cap_set(DMA_MEMCPY, mask);
  621. for (;;) {
  622. chan = dma_request_channel(mask, filter, info);
  623. if (chan) {
  624. err = dmatest_add_channel(info, chan);
  625. if (err) {
  626. dma_release_channel(chan);
  627. break; /* add_channel failed, punt */
  628. }
  629. } else
  630. break; /* no more channels available */
  631. if (info->max_channels &&
  632. info->nr_channels >= info->max_channels)
  633. break; /* we have all we need */
  634. }
  635. return err;
  636. }
  637. static void stop_threaded_test(struct dmatest_info *info)
  638. {
  639. struct dmatest_chan *dtc, *_dtc;
  640. struct dma_chan *chan;
  641. list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
  642. list_del(&dtc->node);
  643. chan = dtc->chan;
  644. dmatest_cleanup_channel(dtc);
  645. pr_debug("dmatest: dropped channel %s\n", dma_chan_name(chan));
  646. dma_release_channel(chan);
  647. }
  648. info->nr_channels = 0;
  649. }
  650. static int __init dmatest_init(void)
  651. {
  652. struct dmatest_info *info = &test_info;
  653. memset(info, 0, sizeof(*info));
  654. INIT_LIST_HEAD(&info->channels);
  655. /* Set default parameters */
  656. info->buf_size = test_buf_size;
  657. strlcpy(info->channel, test_channel, sizeof(info->channel));
  658. strlcpy(info->device, test_device, sizeof(info->device));
  659. info->threads_per_chan = threads_per_chan;
  660. info->max_channels = max_channels;
  661. info->iterations = iterations;
  662. info->xor_sources = xor_sources;
  663. info->pq_sources = pq_sources;
  664. info->timeout = timeout;
  665. return run_threaded_test(info);
  666. }
  667. /* when compiled-in wait for drivers to load first */
  668. late_initcall(dmatest_init);
  669. static void __exit dmatest_exit(void)
  670. {
  671. struct dmatest_info *info = &test_info;
  672. stop_threaded_test(info);
  673. }
  674. module_exit(dmatest_exit);
  675. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  676. MODULE_LICENSE("GPL v2");