Kconfig 29 KB

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  1. config SYMBOL_PREFIX
  2. string
  3. default "_"
  4. config MMU
  5. def_bool n
  6. config FPU
  7. def_bool n
  8. config RWSEM_GENERIC_SPINLOCK
  9. def_bool y
  10. config RWSEM_XCHGADD_ALGORITHM
  11. def_bool n
  12. config BLACKFIN
  13. def_bool y
  14. select HAVE_ARCH_KGDB
  15. select HAVE_ARCH_TRACEHOOK
  16. select HAVE_FUNCTION_GRAPH_TRACER
  17. select HAVE_FUNCTION_TRACER
  18. select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  19. select HAVE_IDE
  20. select HAVE_KERNEL_GZIP if RAMKERNEL
  21. select HAVE_KERNEL_BZIP2 if RAMKERNEL
  22. select HAVE_KERNEL_LZMA if RAMKERNEL
  23. select HAVE_OPROFILE
  24. select ARCH_WANT_OPTIONAL_GPIOLIB
  25. config GENERIC_CSUM
  26. def_bool y
  27. config GENERIC_BUG
  28. def_bool y
  29. depends on BUG
  30. config ZONE_DMA
  31. def_bool y
  32. config GENERIC_FIND_NEXT_BIT
  33. def_bool y
  34. config GENERIC_HARDIRQS
  35. def_bool y
  36. config GENERIC_IRQ_PROBE
  37. def_bool y
  38. config GENERIC_HARDIRQS_NO__DO_IRQ
  39. def_bool y
  40. config GENERIC_GPIO
  41. def_bool y
  42. config FORCE_MAX_ZONEORDER
  43. int
  44. default "14"
  45. config GENERIC_CALIBRATE_DELAY
  46. def_bool y
  47. config LOCKDEP_SUPPORT
  48. def_bool y
  49. config STACKTRACE_SUPPORT
  50. def_bool y
  51. config TRACE_IRQFLAGS_SUPPORT
  52. def_bool y
  53. source "init/Kconfig"
  54. source "kernel/Kconfig.preempt"
  55. source "kernel/Kconfig.freezer"
  56. menu "Blackfin Processor Options"
  57. comment "Processor and Board Settings"
  58. choice
  59. prompt "CPU"
  60. default BF533
  61. config BF512
  62. bool "BF512"
  63. help
  64. BF512 Processor Support.
  65. config BF514
  66. bool "BF514"
  67. help
  68. BF514 Processor Support.
  69. config BF516
  70. bool "BF516"
  71. help
  72. BF516 Processor Support.
  73. config BF518
  74. bool "BF518"
  75. help
  76. BF518 Processor Support.
  77. config BF522
  78. bool "BF522"
  79. help
  80. BF522 Processor Support.
  81. config BF523
  82. bool "BF523"
  83. help
  84. BF523 Processor Support.
  85. config BF524
  86. bool "BF524"
  87. help
  88. BF524 Processor Support.
  89. config BF525
  90. bool "BF525"
  91. help
  92. BF525 Processor Support.
  93. config BF526
  94. bool "BF526"
  95. help
  96. BF526 Processor Support.
  97. config BF527
  98. bool "BF527"
  99. help
  100. BF527 Processor Support.
  101. config BF531
  102. bool "BF531"
  103. help
  104. BF531 Processor Support.
  105. config BF532
  106. bool "BF532"
  107. help
  108. BF532 Processor Support.
  109. config BF533
  110. bool "BF533"
  111. help
  112. BF533 Processor Support.
  113. config BF534
  114. bool "BF534"
  115. help
  116. BF534 Processor Support.
  117. config BF536
  118. bool "BF536"
  119. help
  120. BF536 Processor Support.
  121. config BF537
  122. bool "BF537"
  123. help
  124. BF537 Processor Support.
  125. config BF538
  126. bool "BF538"
  127. help
  128. BF538 Processor Support.
  129. config BF539
  130. bool "BF539"
  131. help
  132. BF539 Processor Support.
  133. config BF542_std
  134. bool "BF542"
  135. help
  136. BF542 Processor Support.
  137. config BF542M
  138. bool "BF542m"
  139. help
  140. BF542 Processor Support.
  141. config BF544_std
  142. bool "BF544"
  143. help
  144. BF544 Processor Support.
  145. config BF544M
  146. bool "BF544m"
  147. help
  148. BF544 Processor Support.
  149. config BF547_std
  150. bool "BF547"
  151. help
  152. BF547 Processor Support.
  153. config BF547M
  154. bool "BF547m"
  155. help
  156. BF547 Processor Support.
  157. config BF548_std
  158. bool "BF548"
  159. help
  160. BF548 Processor Support.
  161. config BF548M
  162. bool "BF548m"
  163. help
  164. BF548 Processor Support.
  165. config BF549_std
  166. bool "BF549"
  167. help
  168. BF549 Processor Support.
  169. config BF549M
  170. bool "BF549m"
  171. help
  172. BF549 Processor Support.
  173. config BF561
  174. bool "BF561"
  175. help
  176. BF561 Processor Support.
  177. endchoice
  178. config SMP
  179. depends on BF561
  180. select TICKSOURCE_CORETMR
  181. bool "Symmetric multi-processing support"
  182. ---help---
  183. This enables support for systems with more than one CPU,
  184. like the dual core BF561. If you have a system with only one
  185. CPU, say N. If you have a system with more than one CPU, say Y.
  186. If you don't know what to do here, say N.
  187. config NR_CPUS
  188. int
  189. depends on SMP
  190. default 2 if BF561
  191. config HOTPLUG_CPU
  192. bool "Support for hot-pluggable CPUs"
  193. depends on SMP && HOTPLUG
  194. default y
  195. config IRQ_PER_CPU
  196. bool
  197. depends on SMP
  198. default y
  199. config HAVE_LEGACY_PER_CPU_AREA
  200. def_bool y
  201. depends on SMP
  202. config BF_REV_MIN
  203. int
  204. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  205. default 2 if (BF537 || BF536 || BF534)
  206. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  207. default 4 if (BF538 || BF539)
  208. config BF_REV_MAX
  209. int
  210. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  211. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  212. default 5 if (BF561 || BF538 || BF539)
  213. default 6 if (BF533 || BF532 || BF531)
  214. choice
  215. prompt "Silicon Rev"
  216. default BF_REV_0_0 if (BF51x || BF52x)
  217. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  218. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  219. config BF_REV_0_0
  220. bool "0.0"
  221. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  222. config BF_REV_0_1
  223. bool "0.1"
  224. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  225. config BF_REV_0_2
  226. bool "0.2"
  227. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  228. config BF_REV_0_3
  229. bool "0.3"
  230. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  231. config BF_REV_0_4
  232. bool "0.4"
  233. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  234. config BF_REV_0_5
  235. bool "0.5"
  236. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  237. config BF_REV_0_6
  238. bool "0.6"
  239. depends on (BF533 || BF532 || BF531)
  240. config BF_REV_ANY
  241. bool "any"
  242. config BF_REV_NONE
  243. bool "none"
  244. endchoice
  245. config BF53x
  246. bool
  247. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  248. default y
  249. config MEM_GENERIC_BOARD
  250. bool
  251. depends on GENERIC_BOARD
  252. default y
  253. config MEM_MT48LC64M4A2FB_7E
  254. bool
  255. depends on (BFIN533_STAMP)
  256. default y
  257. config MEM_MT48LC16M16A2TG_75
  258. bool
  259. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  260. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
  261. || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
  262. || BFIN527_BLUETECHNIX_CM)
  263. default y
  264. config MEM_MT48LC32M8A2_75
  265. bool
  266. depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  267. default y
  268. config MEM_MT48LC8M32B2B5_7
  269. bool
  270. depends on (BFIN561_BLUETECHNIX_CM)
  271. default y
  272. config MEM_MT48LC32M16A2TG_75
  273. bool
  274. depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
  275. default y
  276. config MEM_MT48H32M16LFCJ_75
  277. bool
  278. depends on (BFIN526_EZBRD)
  279. default y
  280. source "arch/blackfin/mach-bf518/Kconfig"
  281. source "arch/blackfin/mach-bf527/Kconfig"
  282. source "arch/blackfin/mach-bf533/Kconfig"
  283. source "arch/blackfin/mach-bf561/Kconfig"
  284. source "arch/blackfin/mach-bf537/Kconfig"
  285. source "arch/blackfin/mach-bf538/Kconfig"
  286. source "arch/blackfin/mach-bf548/Kconfig"
  287. menu "Board customizations"
  288. config CMDLINE_BOOL
  289. bool "Default bootloader kernel arguments"
  290. config CMDLINE
  291. string "Initial kernel command string"
  292. depends on CMDLINE_BOOL
  293. default "console=ttyBF0,57600"
  294. help
  295. If you don't have a boot loader capable of passing a command line string
  296. to the kernel, you may specify one here. As a minimum, you should specify
  297. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  298. config BOOT_LOAD
  299. hex "Kernel load address for booting"
  300. default "0x1000"
  301. range 0x1000 0x20000000
  302. help
  303. This option allows you to set the load address of the kernel.
  304. This can be useful if you are on a board which has a small amount
  305. of memory or you wish to reserve some memory at the beginning of
  306. the address space.
  307. Note that you need to keep this value above 4k (0x1000) as this
  308. memory region is used to capture NULL pointer references as well
  309. as some core kernel functions.
  310. config ROM_BASE
  311. hex "Kernel ROM Base"
  312. depends on ROMKERNEL
  313. default "0x20040040"
  314. range 0x20000000 0x20400000 if !(BF54x || BF561)
  315. range 0x20000000 0x30000000 if (BF54x || BF561)
  316. help
  317. Make sure your ROM base does not include any file-header
  318. information that is prepended to the kernel.
  319. For example, the bootable U-Boot format (created with
  320. mkimage) has a 64 byte header (0x40). So while the image
  321. you write to flash might start at say 0x20080000, you have
  322. to add 0x40 to get the kernel's ROM base as it will come
  323. after the header.
  324. comment "Clock/PLL Setup"
  325. config CLKIN_HZ
  326. int "Frequency of the crystal on the board in Hz"
  327. default "10000000" if BFIN532_IP0X
  328. default "11059200" if BFIN533_STAMP
  329. default "24576000" if PNAV10
  330. default "25000000" # most people use this
  331. default "27000000" if BFIN533_EZKIT
  332. default "30000000" if BFIN561_EZKIT
  333. help
  334. The frequency of CLKIN crystal oscillator on the board in Hz.
  335. Warning: This value should match the crystal on the board. Otherwise,
  336. peripherals won't work properly.
  337. config BFIN_KERNEL_CLOCK
  338. bool "Re-program Clocks while Kernel boots?"
  339. default n
  340. help
  341. This option decides if kernel clocks are re-programed from the
  342. bootloader settings. If the clocks are not set, the SDRAM settings
  343. are also not changed, and the Bootloader does 100% of the hardware
  344. configuration.
  345. config PLL_BYPASS
  346. bool "Bypass PLL"
  347. depends on BFIN_KERNEL_CLOCK
  348. default n
  349. config CLKIN_HALF
  350. bool "Half Clock In"
  351. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  352. default n
  353. help
  354. If this is set the clock will be divided by 2, before it goes to the PLL.
  355. config VCO_MULT
  356. int "VCO Multiplier"
  357. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  358. range 1 64
  359. default "22" if BFIN533_EZKIT
  360. default "45" if BFIN533_STAMP
  361. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  362. default "22" if BFIN533_BLUETECHNIX_CM
  363. default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  364. default "20" if BFIN561_EZKIT
  365. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  366. help
  367. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  368. PLL Frequency = (Crystal Frequency) * (this setting)
  369. choice
  370. prompt "Core Clock Divider"
  371. depends on BFIN_KERNEL_CLOCK
  372. default CCLK_DIV_1
  373. help
  374. This sets the frequency of the core. It can be 1, 2, 4 or 8
  375. Core Frequency = (PLL frequency) / (this setting)
  376. config CCLK_DIV_1
  377. bool "1"
  378. config CCLK_DIV_2
  379. bool "2"
  380. config CCLK_DIV_4
  381. bool "4"
  382. config CCLK_DIV_8
  383. bool "8"
  384. endchoice
  385. config SCLK_DIV
  386. int "System Clock Divider"
  387. depends on BFIN_KERNEL_CLOCK
  388. range 1 15
  389. default 5
  390. help
  391. This sets the frequency of the system clock (including SDRAM or DDR).
  392. This can be between 1 and 15
  393. System Clock = (PLL frequency) / (this setting)
  394. choice
  395. prompt "DDR SDRAM Chip Type"
  396. depends on BFIN_KERNEL_CLOCK
  397. depends on BF54x
  398. default MEM_MT46V32M16_5B
  399. config MEM_MT46V32M16_6T
  400. bool "MT46V32M16_6T"
  401. config MEM_MT46V32M16_5B
  402. bool "MT46V32M16_5B"
  403. endchoice
  404. choice
  405. prompt "DDR/SDRAM Timing"
  406. depends on BFIN_KERNEL_CLOCK
  407. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  408. help
  409. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  410. The calculated SDRAM timing parameters may not be 100%
  411. accurate - This option is therefore marked experimental.
  412. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  413. bool "Calculate Timings (EXPERIMENTAL)"
  414. depends on EXPERIMENTAL
  415. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  416. bool "Provide accurate Timings based on target SCLK"
  417. help
  418. Please consult the Blackfin Hardware Reference Manuals as well
  419. as the memory device datasheet.
  420. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  421. endchoice
  422. menu "Memory Init Control"
  423. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  424. config MEM_DDRCTL0
  425. depends on BF54x
  426. hex "DDRCTL0"
  427. default 0x0
  428. config MEM_DDRCTL1
  429. depends on BF54x
  430. hex "DDRCTL1"
  431. default 0x0
  432. config MEM_DDRCTL2
  433. depends on BF54x
  434. hex "DDRCTL2"
  435. default 0x0
  436. config MEM_EBIU_DDRQUE
  437. depends on BF54x
  438. hex "DDRQUE"
  439. default 0x0
  440. config MEM_SDRRC
  441. depends on !BF54x
  442. hex "SDRRC"
  443. default 0x0
  444. config MEM_SDGCTL
  445. depends on !BF54x
  446. hex "SDGCTL"
  447. default 0x0
  448. endmenu
  449. #
  450. # Max & Min Speeds for various Chips
  451. #
  452. config MAX_VCO_HZ
  453. int
  454. default 400000000 if BF512
  455. default 400000000 if BF514
  456. default 400000000 if BF516
  457. default 400000000 if BF518
  458. default 400000000 if BF522
  459. default 600000000 if BF523
  460. default 400000000 if BF524
  461. default 600000000 if BF525
  462. default 400000000 if BF526
  463. default 600000000 if BF527
  464. default 400000000 if BF531
  465. default 400000000 if BF532
  466. default 750000000 if BF533
  467. default 500000000 if BF534
  468. default 400000000 if BF536
  469. default 600000000 if BF537
  470. default 533333333 if BF538
  471. default 533333333 if BF539
  472. default 600000000 if BF542
  473. default 533333333 if BF544
  474. default 600000000 if BF547
  475. default 600000000 if BF548
  476. default 533333333 if BF549
  477. default 600000000 if BF561
  478. config MIN_VCO_HZ
  479. int
  480. default 50000000
  481. config MAX_SCLK_HZ
  482. int
  483. default 133333333
  484. config MIN_SCLK_HZ
  485. int
  486. default 27000000
  487. comment "Kernel Timer/Scheduler"
  488. source kernel/Kconfig.hz
  489. config GENERIC_TIME
  490. def_bool y
  491. config GENERIC_CLOCKEVENTS
  492. bool "Generic clock events"
  493. default y
  494. menu "Clock event device"
  495. depends on GENERIC_CLOCKEVENTS
  496. config TICKSOURCE_GPTMR0
  497. bool "GPTimer0"
  498. depends on !SMP
  499. select BFIN_GPTIMERS
  500. config TICKSOURCE_CORETMR
  501. bool "Core timer"
  502. default y
  503. endmenu
  504. menu "Clock souce"
  505. depends on GENERIC_CLOCKEVENTS
  506. config CYCLES_CLOCKSOURCE
  507. bool "CYCLES"
  508. default y
  509. depends on !BFIN_SCRATCH_REG_CYCLES
  510. depends on !SMP
  511. help
  512. If you say Y here, you will enable support for using the 'cycles'
  513. registers as a clock source. Doing so means you will be unable to
  514. safely write to the 'cycles' register during runtime. You will
  515. still be able to read it (such as for performance monitoring), but
  516. writing the registers will most likely crash the kernel.
  517. config GPTMR0_CLOCKSOURCE
  518. bool "GPTimer0"
  519. select BFIN_GPTIMERS
  520. depends on !TICKSOURCE_GPTMR0
  521. endmenu
  522. config ARCH_USES_GETTIMEOFFSET
  523. depends on !GENERIC_CLOCKEVENTS
  524. def_bool y
  525. source kernel/time/Kconfig
  526. comment "Misc"
  527. choice
  528. prompt "Blackfin Exception Scratch Register"
  529. default BFIN_SCRATCH_REG_RETN
  530. help
  531. Select the resource to reserve for the Exception handler:
  532. - RETN: Non-Maskable Interrupt (NMI)
  533. - RETE: Exception Return (JTAG/ICE)
  534. - CYCLES: Performance counter
  535. If you are unsure, please select "RETN".
  536. config BFIN_SCRATCH_REG_RETN
  537. bool "RETN"
  538. help
  539. Use the RETN register in the Blackfin exception handler
  540. as a stack scratch register. This means you cannot
  541. safely use NMI on the Blackfin while running Linux, but
  542. you can debug the system with a JTAG ICE and use the
  543. CYCLES performance registers.
  544. If you are unsure, please select "RETN".
  545. config BFIN_SCRATCH_REG_RETE
  546. bool "RETE"
  547. help
  548. Use the RETE register in the Blackfin exception handler
  549. as a stack scratch register. This means you cannot
  550. safely use a JTAG ICE while debugging a Blackfin board,
  551. but you can safely use the CYCLES performance registers
  552. and the NMI.
  553. If you are unsure, please select "RETN".
  554. config BFIN_SCRATCH_REG_CYCLES
  555. bool "CYCLES"
  556. help
  557. Use the CYCLES register in the Blackfin exception handler
  558. as a stack scratch register. This means you cannot
  559. safely use the CYCLES performance registers on a Blackfin
  560. board at anytime, but you can debug the system with a JTAG
  561. ICE and use the NMI.
  562. If you are unsure, please select "RETN".
  563. endchoice
  564. endmenu
  565. menu "Blackfin Kernel Optimizations"
  566. depends on !SMP
  567. comment "Memory Optimizations"
  568. config I_ENTRY_L1
  569. bool "Locate interrupt entry code in L1 Memory"
  570. default y
  571. help
  572. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  573. into L1 instruction memory. (less latency)
  574. config EXCPT_IRQ_SYSC_L1
  575. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  576. default y
  577. help
  578. If enabled, the entire ASM lowlevel exception and interrupt entry code
  579. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  580. (less latency)
  581. config DO_IRQ_L1
  582. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  583. default y
  584. help
  585. If enabled, the frequently called do_irq dispatcher function is linked
  586. into L1 instruction memory. (less latency)
  587. config CORE_TIMER_IRQ_L1
  588. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  589. default y
  590. help
  591. If enabled, the frequently called timer_interrupt() function is linked
  592. into L1 instruction memory. (less latency)
  593. config IDLE_L1
  594. bool "Locate frequently idle function in L1 Memory"
  595. default y
  596. help
  597. If enabled, the frequently called idle function is linked
  598. into L1 instruction memory. (less latency)
  599. config SCHEDULE_L1
  600. bool "Locate kernel schedule function in L1 Memory"
  601. default y
  602. help
  603. If enabled, the frequently called kernel schedule is linked
  604. into L1 instruction memory. (less latency)
  605. config ARITHMETIC_OPS_L1
  606. bool "Locate kernel owned arithmetic functions in L1 Memory"
  607. default y
  608. help
  609. If enabled, arithmetic functions are linked
  610. into L1 instruction memory. (less latency)
  611. config ACCESS_OK_L1
  612. bool "Locate access_ok function in L1 Memory"
  613. default y
  614. help
  615. If enabled, the access_ok function is linked
  616. into L1 instruction memory. (less latency)
  617. config MEMSET_L1
  618. bool "Locate memset function in L1 Memory"
  619. default y
  620. help
  621. If enabled, the memset function is linked
  622. into L1 instruction memory. (less latency)
  623. config MEMCPY_L1
  624. bool "Locate memcpy function in L1 Memory"
  625. default y
  626. help
  627. If enabled, the memcpy function is linked
  628. into L1 instruction memory. (less latency)
  629. config STRCMP_L1
  630. bool "locate strcmp function in L1 Memory"
  631. default y
  632. help
  633. If enabled, the strcmp function is linked
  634. into L1 instruction memory (less latency).
  635. config STRNCMP_L1
  636. bool "locate strncmp function in L1 Memory"
  637. default y
  638. help
  639. If enabled, the strncmp function is linked
  640. into L1 instruction memory (less latency).
  641. config STRCPY_L1
  642. bool "locate strcpy function in L1 Memory"
  643. default y
  644. help
  645. If enabled, the strcpy function is linked
  646. into L1 instruction memory (less latency).
  647. config STRNCPY_L1
  648. bool "locate strncpy function in L1 Memory"
  649. default y
  650. help
  651. If enabled, the strncpy function is linked
  652. into L1 instruction memory (less latency).
  653. config SYS_BFIN_SPINLOCK_L1
  654. bool "Locate sys_bfin_spinlock function in L1 Memory"
  655. default y
  656. help
  657. If enabled, sys_bfin_spinlock function is linked
  658. into L1 instruction memory. (less latency)
  659. config IP_CHECKSUM_L1
  660. bool "Locate IP Checksum function in L1 Memory"
  661. default n
  662. help
  663. If enabled, the IP Checksum function is linked
  664. into L1 instruction memory. (less latency)
  665. config CACHELINE_ALIGNED_L1
  666. bool "Locate cacheline_aligned data to L1 Data Memory"
  667. default y if !BF54x
  668. default n if BF54x
  669. depends on !BF531
  670. help
  671. If enabled, cacheline_aligned data is linked
  672. into L1 data memory. (less latency)
  673. config SYSCALL_TAB_L1
  674. bool "Locate Syscall Table L1 Data Memory"
  675. default n
  676. depends on !BF531
  677. help
  678. If enabled, the Syscall LUT is linked
  679. into L1 data memory. (less latency)
  680. config CPLB_SWITCH_TAB_L1
  681. bool "Locate CPLB Switch Tables L1 Data Memory"
  682. default n
  683. depends on !BF531
  684. help
  685. If enabled, the CPLB Switch Tables are linked
  686. into L1 data memory. (less latency)
  687. config APP_STACK_L1
  688. bool "Support locating application stack in L1 Scratch Memory"
  689. default y
  690. help
  691. If enabled the application stack can be located in L1
  692. scratch memory (less latency).
  693. Currently only works with FLAT binaries.
  694. config EXCEPTION_L1_SCRATCH
  695. bool "Locate exception stack in L1 Scratch Memory"
  696. default n
  697. depends on !APP_STACK_L1
  698. help
  699. Whenever an exception occurs, use the L1 Scratch memory for
  700. stack storage. You cannot place the stacks of FLAT binaries
  701. in L1 when using this option.
  702. If you don't use L1 Scratch, then you should say Y here.
  703. comment "Speed Optimizations"
  704. config BFIN_INS_LOWOVERHEAD
  705. bool "ins[bwl] low overhead, higher interrupt latency"
  706. default y
  707. help
  708. Reads on the Blackfin are speculative. In Blackfin terms, this means
  709. they can be interrupted at any time (even after they have been issued
  710. on to the external bus), and re-issued after the interrupt occurs.
  711. For memory - this is not a big deal, since memory does not change if
  712. it sees a read.
  713. If a FIFO is sitting on the end of the read, it will see two reads,
  714. when the core only sees one since the FIFO receives both the read
  715. which is cancelled (and not delivered to the core) and the one which
  716. is re-issued (which is delivered to the core).
  717. To solve this, interrupts are turned off before reads occur to
  718. I/O space. This option controls which the overhead/latency of
  719. controlling interrupts during this time
  720. "n" turns interrupts off every read
  721. (higher overhead, but lower interrupt latency)
  722. "y" turns interrupts off every loop
  723. (low overhead, but longer interrupt latency)
  724. default behavior is to leave this set to on (type "Y"). If you are experiencing
  725. interrupt latency issues, it is safe and OK to turn this off.
  726. endmenu
  727. choice
  728. prompt "Kernel executes from"
  729. help
  730. Choose the memory type that the kernel will be running in.
  731. config RAMKERNEL
  732. bool "RAM"
  733. help
  734. The kernel will be resident in RAM when running.
  735. config ROMKERNEL
  736. bool "ROM"
  737. help
  738. The kernel will be resident in FLASH/ROM when running.
  739. endchoice
  740. source "mm/Kconfig"
  741. config BFIN_GPTIMERS
  742. tristate "Enable Blackfin General Purpose Timers API"
  743. default n
  744. help
  745. Enable support for the General Purpose Timers API. If you
  746. are unsure, say N.
  747. To compile this driver as a module, choose M here: the module
  748. will be called gptimers.
  749. choice
  750. prompt "Uncached DMA region"
  751. default DMA_UNCACHED_1M
  752. config DMA_UNCACHED_4M
  753. bool "Enable 4M DMA region"
  754. config DMA_UNCACHED_2M
  755. bool "Enable 2M DMA region"
  756. config DMA_UNCACHED_1M
  757. bool "Enable 1M DMA region"
  758. config DMA_UNCACHED_512K
  759. bool "Enable 512K DMA region"
  760. config DMA_UNCACHED_256K
  761. bool "Enable 256K DMA region"
  762. config DMA_UNCACHED_128K
  763. bool "Enable 128K DMA region"
  764. config DMA_UNCACHED_NONE
  765. bool "Disable DMA region"
  766. endchoice
  767. comment "Cache Support"
  768. config BFIN_ICACHE
  769. bool "Enable ICACHE"
  770. default y
  771. config BFIN_EXTMEM_ICACHEABLE
  772. bool "Enable ICACHE for external memory"
  773. depends on BFIN_ICACHE
  774. default y
  775. config BFIN_L2_ICACHEABLE
  776. bool "Enable ICACHE for L2 SRAM"
  777. depends on BFIN_ICACHE
  778. depends on BF54x || BF561
  779. default n
  780. config BFIN_DCACHE
  781. bool "Enable DCACHE"
  782. default y
  783. config BFIN_DCACHE_BANKA
  784. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  785. depends on BFIN_DCACHE && !BF531
  786. default n
  787. config BFIN_EXTMEM_DCACHEABLE
  788. bool "Enable DCACHE for external memory"
  789. depends on BFIN_DCACHE
  790. default y
  791. choice
  792. prompt "External memory DCACHE policy"
  793. depends on BFIN_EXTMEM_DCACHEABLE
  794. default BFIN_EXTMEM_WRITEBACK if !SMP
  795. default BFIN_EXTMEM_WRITETHROUGH if SMP
  796. config BFIN_EXTMEM_WRITEBACK
  797. bool "Write back"
  798. depends on !SMP
  799. help
  800. Write Back Policy:
  801. Cached data will be written back to SDRAM only when needed.
  802. This can give a nice increase in performance, but beware of
  803. broken drivers that do not properly invalidate/flush their
  804. cache.
  805. Write Through Policy:
  806. Cached data will always be written back to SDRAM when the
  807. cache is updated. This is a completely safe setting, but
  808. performance is worse than Write Back.
  809. If you are unsure of the options and you want to be safe,
  810. then go with Write Through.
  811. config BFIN_EXTMEM_WRITETHROUGH
  812. bool "Write through"
  813. help
  814. Write Back Policy:
  815. Cached data will be written back to SDRAM only when needed.
  816. This can give a nice increase in performance, but beware of
  817. broken drivers that do not properly invalidate/flush their
  818. cache.
  819. Write Through Policy:
  820. Cached data will always be written back to SDRAM when the
  821. cache is updated. This is a completely safe setting, but
  822. performance is worse than Write Back.
  823. If you are unsure of the options and you want to be safe,
  824. then go with Write Through.
  825. endchoice
  826. config BFIN_L2_DCACHEABLE
  827. bool "Enable DCACHE for L2 SRAM"
  828. depends on BFIN_DCACHE
  829. depends on (BF54x || BF561) && !SMP
  830. default n
  831. choice
  832. prompt "L2 SRAM DCACHE policy"
  833. depends on BFIN_L2_DCACHEABLE
  834. default BFIN_L2_WRITEBACK
  835. config BFIN_L2_WRITEBACK
  836. bool "Write back"
  837. config BFIN_L2_WRITETHROUGH
  838. bool "Write through"
  839. endchoice
  840. comment "Memory Protection Unit"
  841. config MPU
  842. bool "Enable the memory protection unit (EXPERIMENTAL)"
  843. default n
  844. help
  845. Use the processor's MPU to protect applications from accessing
  846. memory they do not own. This comes at a performance penalty
  847. and is recommended only for debugging.
  848. comment "Asynchronous Memory Configuration"
  849. menu "EBIU_AMGCTL Global Control"
  850. config C_AMCKEN
  851. bool "Enable CLKOUT"
  852. default y
  853. config C_CDPRIO
  854. bool "DMA has priority over core for ext. accesses"
  855. default n
  856. config C_B0PEN
  857. depends on BF561
  858. bool "Bank 0 16 bit packing enable"
  859. default y
  860. config C_B1PEN
  861. depends on BF561
  862. bool "Bank 1 16 bit packing enable"
  863. default y
  864. config C_B2PEN
  865. depends on BF561
  866. bool "Bank 2 16 bit packing enable"
  867. default y
  868. config C_B3PEN
  869. depends on BF561
  870. bool "Bank 3 16 bit packing enable"
  871. default n
  872. choice
  873. prompt "Enable Asynchronous Memory Banks"
  874. default C_AMBEN_ALL
  875. config C_AMBEN
  876. bool "Disable All Banks"
  877. config C_AMBEN_B0
  878. bool "Enable Bank 0"
  879. config C_AMBEN_B0_B1
  880. bool "Enable Bank 0 & 1"
  881. config C_AMBEN_B0_B1_B2
  882. bool "Enable Bank 0 & 1 & 2"
  883. config C_AMBEN_ALL
  884. bool "Enable All Banks"
  885. endchoice
  886. endmenu
  887. menu "EBIU_AMBCTL Control"
  888. config BANK_0
  889. hex "Bank 0 (AMBCTL0.L)"
  890. default 0x7BB0
  891. help
  892. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  893. used to control the Asynchronous Memory Bank 0 settings.
  894. config BANK_1
  895. hex "Bank 1 (AMBCTL0.H)"
  896. default 0x7BB0
  897. default 0x5558 if BF54x
  898. help
  899. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  900. used to control the Asynchronous Memory Bank 1 settings.
  901. config BANK_2
  902. hex "Bank 2 (AMBCTL1.L)"
  903. default 0x7BB0
  904. help
  905. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  906. used to control the Asynchronous Memory Bank 2 settings.
  907. config BANK_3
  908. hex "Bank 3 (AMBCTL1.H)"
  909. default 0x99B3
  910. help
  911. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  912. used to control the Asynchronous Memory Bank 3 settings.
  913. endmenu
  914. config EBIU_MBSCTLVAL
  915. hex "EBIU Bank Select Control Register"
  916. depends on BF54x
  917. default 0
  918. config EBIU_MODEVAL
  919. hex "Flash Memory Mode Control Register"
  920. depends on BF54x
  921. default 1
  922. config EBIU_FCTLVAL
  923. hex "Flash Memory Bank Control Register"
  924. depends on BF54x
  925. default 6
  926. endmenu
  927. #############################################################################
  928. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  929. config PCI
  930. bool "PCI support"
  931. depends on BROKEN
  932. help
  933. Support for PCI bus.
  934. source "drivers/pci/Kconfig"
  935. source "drivers/pcmcia/Kconfig"
  936. source "drivers/pci/hotplug/Kconfig"
  937. endmenu
  938. menu "Executable file formats"
  939. source "fs/Kconfig.binfmt"
  940. endmenu
  941. menu "Power management options"
  942. source "kernel/power/Kconfig"
  943. config ARCH_SUSPEND_POSSIBLE
  944. def_bool y
  945. choice
  946. prompt "Standby Power Saving Mode"
  947. depends on PM
  948. default PM_BFIN_SLEEP_DEEPER
  949. config PM_BFIN_SLEEP_DEEPER
  950. bool "Sleep Deeper"
  951. help
  952. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  953. power dissipation by disabling the clock to the processor core (CCLK).
  954. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  955. to 0.85 V to provide the greatest power savings, while preserving the
  956. processor state.
  957. The PLL and system clock (SCLK) continue to operate at a very low
  958. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  959. the SDRAM is put into Self Refresh Mode. Typically an external event
  960. such as GPIO interrupt or RTC activity wakes up the processor.
  961. Various Peripherals such as UART, SPORT, PPI may not function as
  962. normal during Sleep Deeper, due to the reduced SCLK frequency.
  963. When in the sleep mode, system DMA access to L1 memory is not supported.
  964. If unsure, select "Sleep Deeper".
  965. config PM_BFIN_SLEEP
  966. bool "Sleep"
  967. help
  968. Sleep Mode (High Power Savings) - The sleep mode reduces power
  969. dissipation by disabling the clock to the processor core (CCLK).
  970. The PLL and system clock (SCLK), however, continue to operate in
  971. this mode. Typically an external event or RTC activity will wake
  972. up the processor. When in the sleep mode, system DMA access to L1
  973. memory is not supported.
  974. If unsure, select "Sleep Deeper".
  975. endchoice
  976. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  977. depends on PM
  978. config PM_BFIN_WAKE_PH6
  979. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  980. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  981. default n
  982. help
  983. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  984. config PM_BFIN_WAKE_GP
  985. bool "Allow Wake-Up from GPIOs"
  986. depends on PM && BF54x
  987. default n
  988. help
  989. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  990. (all processors, except ADSP-BF549). This option sets
  991. the general-purpose wake-up enable (GPWE) control bit to enable
  992. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  993. On ADSP-BF549 this option enables the the same functionality on the
  994. /MRXON pin also PH7.
  995. endmenu
  996. menu "CPU Frequency scaling"
  997. source "drivers/cpufreq/Kconfig"
  998. config BFIN_CPU_FREQ
  999. bool
  1000. depends on CPU_FREQ
  1001. select CPU_FREQ_TABLE
  1002. default y
  1003. config CPU_VOLTAGE
  1004. bool "CPU Voltage scaling"
  1005. depends on EXPERIMENTAL
  1006. depends on CPU_FREQ
  1007. default n
  1008. help
  1009. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1010. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1011. manuals. There is a theoretical risk that during VDDINT transitions
  1012. the PLL may unlock.
  1013. endmenu
  1014. source "net/Kconfig"
  1015. source "drivers/Kconfig"
  1016. source "drivers/firmware/Kconfig"
  1017. source "fs/Kconfig"
  1018. source "arch/blackfin/Kconfig.debug"
  1019. source "security/Kconfig"
  1020. source "crypto/Kconfig"
  1021. source "lib/Kconfig"