imx28.dtsi 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. saif0 = &saif0;
  21. saif1 = &saif1;
  22. serial0 = &auart0;
  23. serial1 = &auart1;
  24. serial2 = &auart2;
  25. serial3 = &auart3;
  26. serial4 = &auart4;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. apb@80000000 {
  34. compatible = "simple-bus";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. reg = <0x80000000 0x80000>;
  38. ranges;
  39. apbh@80000000 {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. reg = <0x80000000 0x3c900>;
  44. ranges;
  45. icoll: interrupt-controller@80000000 {
  46. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  47. interrupt-controller;
  48. #interrupt-cells = <1>;
  49. reg = <0x80000000 0x2000>;
  50. };
  51. hsadc@80002000 {
  52. reg = <0x80002000 2000>;
  53. interrupts = <13 87>;
  54. status = "disabled";
  55. };
  56. dma-apbh@80004000 {
  57. compatible = "fsl,imx28-dma-apbh";
  58. reg = <0x80004000 2000>;
  59. };
  60. perfmon@80006000 {
  61. reg = <0x80006000 800>;
  62. interrupts = <27>;
  63. status = "disabled";
  64. };
  65. gpmi-nand@8000c000 {
  66. compatible = "fsl,imx28-gpmi-nand";
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. reg = <0x8000c000 2000>, <0x8000a000 2000>;
  70. reg-names = "gpmi-nand", "bch";
  71. interrupts = <88>, <41>;
  72. interrupt-names = "gpmi-dma", "bch";
  73. fsl,gpmi-dma-channel = <4>;
  74. status = "disabled";
  75. };
  76. ssp0: ssp@80010000 {
  77. reg = <0x80010000 2000>;
  78. interrupts = <96 82>;
  79. fsl,ssp-dma-channel = <0>;
  80. status = "disabled";
  81. };
  82. ssp1: ssp@80012000 {
  83. reg = <0x80012000 2000>;
  84. interrupts = <97 83>;
  85. fsl,ssp-dma-channel = <1>;
  86. status = "disabled";
  87. };
  88. ssp2: ssp@80014000 {
  89. reg = <0x80014000 2000>;
  90. interrupts = <98 84>;
  91. fsl,ssp-dma-channel = <2>;
  92. status = "disabled";
  93. };
  94. ssp3: ssp@80016000 {
  95. reg = <0x80016000 2000>;
  96. interrupts = <99 85>;
  97. fsl,ssp-dma-channel = <3>;
  98. status = "disabled";
  99. };
  100. pinctrl@80018000 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. compatible = "fsl,imx28-pinctrl", "simple-bus";
  104. reg = <0x80018000 2000>;
  105. gpio0: gpio@0 {
  106. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  107. interrupts = <127>;
  108. gpio-controller;
  109. #gpio-cells = <2>;
  110. interrupt-controller;
  111. #interrupt-cells = <2>;
  112. };
  113. gpio1: gpio@1 {
  114. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  115. interrupts = <126>;
  116. gpio-controller;
  117. #gpio-cells = <2>;
  118. interrupt-controller;
  119. #interrupt-cells = <2>;
  120. };
  121. gpio2: gpio@2 {
  122. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  123. interrupts = <125>;
  124. gpio-controller;
  125. #gpio-cells = <2>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. };
  129. gpio3: gpio@3 {
  130. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  131. interrupts = <124>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. interrupt-controller;
  135. #interrupt-cells = <2>;
  136. };
  137. gpio4: gpio@4 {
  138. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  139. interrupts = <123>;
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. interrupt-controller;
  143. #interrupt-cells = <2>;
  144. };
  145. duart_pins_a: duart@0 {
  146. reg = <0>;
  147. fsl,pinmux-ids = <0x3102 0x3112>;
  148. fsl,drive-strength = <0>;
  149. fsl,voltage = <1>;
  150. fsl,pull-up = <0>;
  151. };
  152. duart_pins_b: duart@1 {
  153. reg = <1>;
  154. fsl,pinmux-ids = <0x3022 0x3032>;
  155. fsl,drive-strength = <0>;
  156. fsl,voltage = <1>;
  157. fsl,pull-up = <0>;
  158. };
  159. gpmi_pins_a: gpmi-nand@0 {
  160. reg = <0>;
  161. fsl,pinmux-ids = <0x0000 0x0010 0x0020
  162. 0x0030 0x0040 0x0050 0x0060
  163. 0x0070 0x0100 0x0110 0x0140
  164. 0x0150 0x0180 0x0190 0x01a0
  165. 0x01b0 0x01c0>;
  166. fsl,drive-strength = <0>;
  167. fsl,voltage = <1>;
  168. fsl,pull-up = <0>;
  169. };
  170. gpmi_status_cfg: gpmi-status-cfg {
  171. fsl,pinmux-ids = <0x0180 0x0190 0x01c0>;
  172. fsl,drive-strength = <2>;
  173. };
  174. auart0_pins_a: auart0@0 {
  175. reg = <0>;
  176. fsl,pinmux-ids = <0x3000 0x3010 0x3020 0x3030>;
  177. fsl,drive-strength = <0>;
  178. fsl,voltage = <1>;
  179. fsl,pull-up = <0>;
  180. };
  181. auart3_pins_a: auart3@0 {
  182. reg = <0>;
  183. fsl,pinmux-ids = <0x30c0 0x30d0 0x30e0 0x30f0>;
  184. fsl,drive-strength = <0>;
  185. fsl,voltage = <1>;
  186. fsl,pull-up = <0>;
  187. };
  188. mac0_pins_a: mac0@0 {
  189. reg = <0>;
  190. fsl,pinmux-ids = <0x4000 0x4010 0x4020
  191. 0x4030 0x4040 0x4060 0x4070
  192. 0x4080 0x4100>;
  193. fsl,drive-strength = <1>;
  194. fsl,voltage = <1>;
  195. fsl,pull-up = <1>;
  196. };
  197. mac1_pins_a: mac1@0 {
  198. reg = <0>;
  199. fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
  200. 0x40e1 0x40b1 0x40c1>;
  201. fsl,drive-strength = <1>;
  202. fsl,voltage = <1>;
  203. fsl,pull-up = <1>;
  204. };
  205. mmc0_8bit_pins_a: mmc0-8bit@0 {
  206. reg = <0>;
  207. fsl,pinmux-ids = <0x2000 0x2010 0x2020
  208. 0x2030 0x2040 0x2050 0x2060
  209. 0x2070 0x2080 0x2090 0x20a0>;
  210. fsl,drive-strength = <1>;
  211. fsl,voltage = <1>;
  212. fsl,pull-up = <1>;
  213. };
  214. mmc0_4bit_pins_a: mmc0-4bit@0 {
  215. reg = <0>;
  216. fsl,pinmux-ids = <0x2000 0x2010 0x2020
  217. 0x2030 0x2080 0x2090 0x20a0>;
  218. fsl,drive-strength = <1>;
  219. fsl,voltage = <1>;
  220. fsl,pull-up = <1>;
  221. };
  222. mmc0_cd_cfg: mmc0-cd-cfg {
  223. fsl,pinmux-ids = <0x2090>;
  224. fsl,pull-up = <0>;
  225. };
  226. mmc0_sck_cfg: mmc0-sck-cfg {
  227. fsl,pinmux-ids = <0x20a0>;
  228. fsl,drive-strength = <2>;
  229. fsl,pull-up = <0>;
  230. };
  231. i2c0_pins_a: i2c0@0 {
  232. reg = <0>;
  233. fsl,pinmux-ids = <0x3180 0x3190>;
  234. fsl,drive-strength = <1>;
  235. fsl,voltage = <1>;
  236. fsl,pull-up = <1>;
  237. };
  238. saif0_pins_a: saif0@0 {
  239. reg = <0>;
  240. fsl,pinmux-ids =
  241. <0x3140 0x3150 0x3160 0x3170>;
  242. fsl,drive-strength = <2>;
  243. fsl,voltage = <1>;
  244. fsl,pull-up = <1>;
  245. };
  246. saif1_pins_a: saif1@0 {
  247. reg = <0>;
  248. fsl,pinmux-ids = <0x31a0>;
  249. fsl,drive-strength = <2>;
  250. fsl,voltage = <1>;
  251. fsl,pull-up = <1>;
  252. };
  253. };
  254. digctl@8001c000 {
  255. reg = <0x8001c000 2000>;
  256. interrupts = <89>;
  257. status = "disabled";
  258. };
  259. etm@80022000 {
  260. reg = <0x80022000 2000>;
  261. status = "disabled";
  262. };
  263. dma-apbx@80024000 {
  264. compatible = "fsl,imx28-dma-apbx";
  265. reg = <0x80024000 2000>;
  266. };
  267. dcp@80028000 {
  268. reg = <0x80028000 2000>;
  269. interrupts = <52 53 54>;
  270. status = "disabled";
  271. };
  272. pxp@8002a000 {
  273. reg = <0x8002a000 2000>;
  274. interrupts = <39>;
  275. status = "disabled";
  276. };
  277. ocotp@8002c000 {
  278. reg = <0x8002c000 2000>;
  279. status = "disabled";
  280. };
  281. axi-ahb@8002e000 {
  282. reg = <0x8002e000 2000>;
  283. status = "disabled";
  284. };
  285. lcdif@80030000 {
  286. reg = <0x80030000 2000>;
  287. interrupts = <38 86>;
  288. status = "disabled";
  289. };
  290. can0: can@80032000 {
  291. reg = <0x80032000 2000>;
  292. interrupts = <8>;
  293. status = "disabled";
  294. };
  295. can1: can@80034000 {
  296. reg = <0x80034000 2000>;
  297. interrupts = <9>;
  298. status = "disabled";
  299. };
  300. simdbg@8003c000 {
  301. reg = <0x8003c000 200>;
  302. status = "disabled";
  303. };
  304. simgpmisel@8003c200 {
  305. reg = <0x8003c200 100>;
  306. status = "disabled";
  307. };
  308. simsspsel@8003c300 {
  309. reg = <0x8003c300 100>;
  310. status = "disabled";
  311. };
  312. simmemsel@8003c400 {
  313. reg = <0x8003c400 100>;
  314. status = "disabled";
  315. };
  316. gpiomon@8003c500 {
  317. reg = <0x8003c500 100>;
  318. status = "disabled";
  319. };
  320. simenet@8003c700 {
  321. reg = <0x8003c700 100>;
  322. status = "disabled";
  323. };
  324. armjtag@8003c800 {
  325. reg = <0x8003c800 100>;
  326. status = "disabled";
  327. };
  328. };
  329. apbx@80040000 {
  330. compatible = "simple-bus";
  331. #address-cells = <1>;
  332. #size-cells = <1>;
  333. reg = <0x80040000 0x40000>;
  334. ranges;
  335. clkctl@80040000 {
  336. reg = <0x80040000 2000>;
  337. status = "disabled";
  338. };
  339. saif0: saif@80042000 {
  340. compatible = "fsl,imx28-saif";
  341. reg = <0x80042000 2000>;
  342. interrupts = <59 80>;
  343. fsl,saif-dma-channel = <4>;
  344. status = "disabled";
  345. };
  346. power@80044000 {
  347. reg = <0x80044000 2000>;
  348. status = "disabled";
  349. };
  350. saif1: saif@80046000 {
  351. compatible = "fsl,imx28-saif";
  352. reg = <0x80046000 2000>;
  353. interrupts = <58 81>;
  354. fsl,saif-dma-channel = <5>;
  355. status = "disabled";
  356. };
  357. lradc@80050000 {
  358. reg = <0x80050000 2000>;
  359. status = "disabled";
  360. };
  361. spdif@80054000 {
  362. reg = <0x80054000 2000>;
  363. interrupts = <45 66>;
  364. status = "disabled";
  365. };
  366. rtc@80056000 {
  367. reg = <0x80056000 2000>;
  368. interrupts = <28 29>;
  369. status = "disabled";
  370. };
  371. i2c0: i2c@80058000 {
  372. #address-cells = <1>;
  373. #size-cells = <0>;
  374. compatible = "fsl,imx28-i2c";
  375. reg = <0x80058000 2000>;
  376. interrupts = <111 68>;
  377. status = "disabled";
  378. };
  379. i2c1: i2c@8005a000 {
  380. #address-cells = <1>;
  381. #size-cells = <0>;
  382. compatible = "fsl,imx28-i2c";
  383. reg = <0x8005a000 2000>;
  384. interrupts = <110 69>;
  385. status = "disabled";
  386. };
  387. pwm@80064000 {
  388. reg = <0x80064000 2000>;
  389. status = "disabled";
  390. };
  391. timrot@80068000 {
  392. reg = <0x80068000 2000>;
  393. status = "disabled";
  394. };
  395. auart0: serial@8006a000 {
  396. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  397. reg = <0x8006a000 0x2000>;
  398. interrupts = <112 70 71>;
  399. status = "disabled";
  400. };
  401. auart1: serial@8006c000 {
  402. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  403. reg = <0x8006c000 0x2000>;
  404. interrupts = <113 72 73>;
  405. status = "disabled";
  406. };
  407. auart2: serial@8006e000 {
  408. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  409. reg = <0x8006e000 0x2000>;
  410. interrupts = <114 74 75>;
  411. status = "disabled";
  412. };
  413. auart3: serial@80070000 {
  414. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  415. reg = <0x80070000 0x2000>;
  416. interrupts = <115 76 77>;
  417. status = "disabled";
  418. };
  419. auart4: serial@80072000 {
  420. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  421. reg = <0x80072000 0x2000>;
  422. interrupts = <116 78 79>;
  423. status = "disabled";
  424. };
  425. duart: serial@80074000 {
  426. compatible = "arm,pl011", "arm,primecell";
  427. reg = <0x80074000 0x1000>;
  428. interrupts = <47>;
  429. status = "disabled";
  430. };
  431. usbphy0: usbphy@8007c000 {
  432. reg = <0x8007c000 0x2000>;
  433. status = "disabled";
  434. };
  435. usbphy1: usbphy@8007e000 {
  436. reg = <0x8007e000 0x2000>;
  437. status = "disabled";
  438. };
  439. };
  440. };
  441. ahb@80080000 {
  442. compatible = "simple-bus";
  443. #address-cells = <1>;
  444. #size-cells = <1>;
  445. reg = <0x80080000 0x80000>;
  446. ranges;
  447. usbctrl0: usbctrl@80080000 {
  448. reg = <0x80080000 0x10000>;
  449. status = "disabled";
  450. };
  451. usbctrl1: usbctrl@80090000 {
  452. reg = <0x80090000 0x10000>;
  453. status = "disabled";
  454. };
  455. dflpt@800c0000 {
  456. reg = <0x800c0000 0x10000>;
  457. status = "disabled";
  458. };
  459. mac0: ethernet@800f0000 {
  460. compatible = "fsl,imx28-fec";
  461. reg = <0x800f0000 0x4000>;
  462. interrupts = <101>;
  463. status = "disabled";
  464. };
  465. mac1: ethernet@800f4000 {
  466. compatible = "fsl,imx28-fec";
  467. reg = <0x800f4000 0x4000>;
  468. interrupts = <102>;
  469. status = "disabled";
  470. };
  471. switch@800f8000 {
  472. reg = <0x800f8000 0x8000>;
  473. status = "disabled";
  474. };
  475. };
  476. };