be_main.c 138 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. struct device_attribute *beiscsi_attrs[] = {
  145. &dev_attr_beiscsi_log_enable,
  146. &dev_attr_beiscsi_drvr_ver,
  147. NULL,
  148. };
  149. static char const *cqe_desc[] = {
  150. "RESERVED_DESC",
  151. "SOL_CMD_COMPLETE",
  152. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  153. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  154. "CXN_KILLED_BURST_LEN_MISMATCH",
  155. "CXN_KILLED_AHS_RCVD",
  156. "CXN_KILLED_HDR_DIGEST_ERR",
  157. "CXN_KILLED_UNKNOWN_HDR",
  158. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  159. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  160. "CXN_KILLED_RST_RCVD",
  161. "CXN_KILLED_TIMED_OUT",
  162. "CXN_KILLED_RST_SENT",
  163. "CXN_KILLED_FIN_RCVD",
  164. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  165. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  166. "CXN_KILLED_OVER_RUN_RESIDUAL",
  167. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  168. "CMD_KILLED_INVALID_STATSN_RCVD",
  169. "CMD_KILLED_INVALID_R2T_RCVD",
  170. "CMD_CXN_KILLED_LUN_INVALID",
  171. "CMD_CXN_KILLED_ICD_INVALID",
  172. "CMD_CXN_KILLED_ITT_INVALID",
  173. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  174. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  175. "CXN_INVALIDATE_NOTIFY",
  176. "CXN_INVALIDATE_INDEX_NOTIFY",
  177. "CMD_INVALIDATED_NOTIFY",
  178. "UNSOL_HDR_NOTIFY",
  179. "UNSOL_DATA_NOTIFY",
  180. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  181. "DRIVERMSG_NOTIFY",
  182. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  183. "SOL_CMD_KILLED_DIF_ERR",
  184. "CXN_KILLED_SYN_RCVD",
  185. "CXN_KILLED_IMM_DATA_RCVD"
  186. };
  187. static int beiscsi_slave_configure(struct scsi_device *sdev)
  188. {
  189. blk_queue_max_segment_size(sdev->request_queue, 65536);
  190. return 0;
  191. }
  192. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  193. {
  194. struct iscsi_cls_session *cls_session;
  195. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  196. struct beiscsi_io_task *aborted_io_task;
  197. struct iscsi_conn *conn;
  198. struct beiscsi_conn *beiscsi_conn;
  199. struct beiscsi_hba *phba;
  200. struct iscsi_session *session;
  201. struct invalidate_command_table *inv_tbl;
  202. struct be_dma_mem nonemb_cmd;
  203. unsigned int cid, tag, num_invalidate;
  204. cls_session = starget_to_session(scsi_target(sc->device));
  205. session = cls_session->dd_data;
  206. spin_lock_bh(&session->lock);
  207. if (!aborted_task || !aborted_task->sc) {
  208. /* we raced */
  209. spin_unlock_bh(&session->lock);
  210. return SUCCESS;
  211. }
  212. aborted_io_task = aborted_task->dd_data;
  213. if (!aborted_io_task->scsi_cmnd) {
  214. /* raced or invalid command */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. spin_unlock_bh(&session->lock);
  219. conn = aborted_task->conn;
  220. beiscsi_conn = conn->dd_data;
  221. phba = beiscsi_conn->phba;
  222. /* invalidate iocb */
  223. cid = beiscsi_conn->beiscsi_conn_cid;
  224. inv_tbl = phba->inv_tbl;
  225. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  226. inv_tbl->cid = cid;
  227. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  228. num_invalidate = 1;
  229. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  230. sizeof(struct invalidate_commands_params_in),
  231. &nonemb_cmd.dma);
  232. if (nonemb_cmd.va == NULL) {
  233. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  234. "BM_%d : Failed to allocate memory for"
  235. "mgmt_invalidate_icds\n");
  236. return FAILED;
  237. }
  238. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  239. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  240. cid, &nonemb_cmd);
  241. if (!tag) {
  242. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  243. "BM_%d : mgmt_invalidate_icds could not be"
  244. "submitted\n");
  245. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  246. nonemb_cmd.va, nonemb_cmd.dma);
  247. return FAILED;
  248. } else {
  249. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  250. phba->ctrl.mcc_numtag[tag]);
  251. free_mcc_tag(&phba->ctrl, tag);
  252. }
  253. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  254. nonemb_cmd.va, nonemb_cmd.dma);
  255. return iscsi_eh_abort(sc);
  256. }
  257. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  258. {
  259. struct iscsi_task *abrt_task;
  260. struct beiscsi_io_task *abrt_io_task;
  261. struct iscsi_conn *conn;
  262. struct beiscsi_conn *beiscsi_conn;
  263. struct beiscsi_hba *phba;
  264. struct iscsi_session *session;
  265. struct iscsi_cls_session *cls_session;
  266. struct invalidate_command_table *inv_tbl;
  267. struct be_dma_mem nonemb_cmd;
  268. unsigned int cid, tag, i, num_invalidate;
  269. /* invalidate iocbs */
  270. cls_session = starget_to_session(scsi_target(sc->device));
  271. session = cls_session->dd_data;
  272. spin_lock_bh(&session->lock);
  273. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  274. spin_unlock_bh(&session->lock);
  275. return FAILED;
  276. }
  277. conn = session->leadconn;
  278. beiscsi_conn = conn->dd_data;
  279. phba = beiscsi_conn->phba;
  280. cid = beiscsi_conn->beiscsi_conn_cid;
  281. inv_tbl = phba->inv_tbl;
  282. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  283. num_invalidate = 0;
  284. for (i = 0; i < conn->session->cmds_max; i++) {
  285. abrt_task = conn->session->cmds[i];
  286. abrt_io_task = abrt_task->dd_data;
  287. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  288. continue;
  289. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  290. continue;
  291. inv_tbl->cid = cid;
  292. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  293. num_invalidate++;
  294. inv_tbl++;
  295. }
  296. spin_unlock_bh(&session->lock);
  297. inv_tbl = phba->inv_tbl;
  298. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  299. sizeof(struct invalidate_commands_params_in),
  300. &nonemb_cmd.dma);
  301. if (nonemb_cmd.va == NULL) {
  302. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  303. "BM_%d : Failed to allocate memory for"
  304. "mgmt_invalidate_icds\n");
  305. return FAILED;
  306. }
  307. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  308. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  309. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  310. cid, &nonemb_cmd);
  311. if (!tag) {
  312. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  313. "BM_%d : mgmt_invalidate_icds could not be"
  314. " submitted\n");
  315. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  316. nonemb_cmd.va, nonemb_cmd.dma);
  317. return FAILED;
  318. } else {
  319. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  320. phba->ctrl.mcc_numtag[tag]);
  321. free_mcc_tag(&phba->ctrl, tag);
  322. }
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { 0 }
  484. };
  485. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  486. static struct scsi_host_template beiscsi_sht = {
  487. .module = THIS_MODULE,
  488. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  489. .proc_name = DRV_NAME,
  490. .queuecommand = iscsi_queuecommand,
  491. .change_queue_depth = iscsi_change_queue_depth,
  492. .slave_configure = beiscsi_slave_configure,
  493. .target_alloc = iscsi_target_alloc,
  494. .eh_abort_handler = beiscsi_eh_abort,
  495. .eh_device_reset_handler = beiscsi_eh_device_reset,
  496. .eh_target_reset_handler = iscsi_eh_session_reset,
  497. .shost_attrs = beiscsi_attrs,
  498. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  499. .can_queue = BE2_IO_DEPTH,
  500. .this_id = -1,
  501. .max_sectors = BEISCSI_MAX_SECTORS,
  502. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  503. .use_clustering = ENABLE_CLUSTERING,
  504. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  505. };
  506. static struct scsi_transport_template *beiscsi_scsi_transport;
  507. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  508. {
  509. struct beiscsi_hba *phba;
  510. struct Scsi_Host *shost;
  511. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  512. if (!shost) {
  513. dev_err(&pcidev->dev,
  514. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  515. return NULL;
  516. }
  517. shost->dma_boundary = pcidev->dma_mask;
  518. shost->max_id = BE2_MAX_SESSIONS;
  519. shost->max_channel = 0;
  520. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  521. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  522. shost->transportt = beiscsi_scsi_transport;
  523. phba = iscsi_host_priv(shost);
  524. memset(phba, 0, sizeof(*phba));
  525. phba->shost = shost;
  526. phba->pcidev = pci_dev_get(pcidev);
  527. pci_set_drvdata(pcidev, phba);
  528. phba->interface_handle = 0xFFFFFFFF;
  529. if (iscsi_host_add(shost, &phba->pcidev->dev))
  530. goto free_devices;
  531. return phba;
  532. free_devices:
  533. pci_dev_put(phba->pcidev);
  534. iscsi_host_free(phba->shost);
  535. return NULL;
  536. }
  537. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  538. {
  539. if (phba->csr_va) {
  540. iounmap(phba->csr_va);
  541. phba->csr_va = NULL;
  542. }
  543. if (phba->db_va) {
  544. iounmap(phba->db_va);
  545. phba->db_va = NULL;
  546. }
  547. if (phba->pci_va) {
  548. iounmap(phba->pci_va);
  549. phba->pci_va = NULL;
  550. }
  551. }
  552. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  553. struct pci_dev *pcidev)
  554. {
  555. u8 __iomem *addr;
  556. int pcicfg_reg;
  557. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  558. pci_resource_len(pcidev, 2));
  559. if (addr == NULL)
  560. return -ENOMEM;
  561. phba->ctrl.csr = addr;
  562. phba->csr_va = addr;
  563. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  564. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  565. if (addr == NULL)
  566. goto pci_map_err;
  567. phba->ctrl.db = addr;
  568. phba->db_va = addr;
  569. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  570. if (phba->generation == BE_GEN2)
  571. pcicfg_reg = 1;
  572. else
  573. pcicfg_reg = 0;
  574. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  575. pci_resource_len(pcidev, pcicfg_reg));
  576. if (addr == NULL)
  577. goto pci_map_err;
  578. phba->ctrl.pcicfg = addr;
  579. phba->pci_va = addr;
  580. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  581. return 0;
  582. pci_map_err:
  583. beiscsi_unmap_pci_function(phba);
  584. return -ENOMEM;
  585. }
  586. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  587. {
  588. int ret;
  589. ret = pci_enable_device(pcidev);
  590. if (ret) {
  591. dev_err(&pcidev->dev,
  592. "beiscsi_enable_pci - enable device failed\n");
  593. return ret;
  594. }
  595. pci_set_master(pcidev);
  596. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  597. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  598. if (ret) {
  599. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  600. pci_disable_device(pcidev);
  601. return ret;
  602. }
  603. }
  604. return 0;
  605. }
  606. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  607. {
  608. struct be_ctrl_info *ctrl = &phba->ctrl;
  609. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  610. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  611. int status = 0;
  612. ctrl->pdev = pdev;
  613. status = beiscsi_map_pci_bars(phba, pdev);
  614. if (status)
  615. return status;
  616. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  617. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  618. mbox_mem_alloc->size,
  619. &mbox_mem_alloc->dma);
  620. if (!mbox_mem_alloc->va) {
  621. beiscsi_unmap_pci_function(phba);
  622. return -ENOMEM;
  623. }
  624. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  625. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  626. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  627. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  628. spin_lock_init(&ctrl->mbox_lock);
  629. spin_lock_init(&phba->ctrl.mcc_lock);
  630. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  631. return status;
  632. }
  633. static void beiscsi_get_params(struct beiscsi_hba *phba)
  634. {
  635. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  636. - (phba->fw_config.iscsi_cid_count
  637. + BE2_TMFS
  638. + BE2_NOPOUT_REQ));
  639. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  640. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  641. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  642. phba->params.num_sge_per_io = BE2_SGE;
  643. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  644. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  645. phba->params.eq_timer = 64;
  646. phba->params.num_eq_entries =
  647. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  648. + BE2_TMFS) / 512) + 1) * 512;
  649. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  650. ? 1024 : phba->params.num_eq_entries;
  651. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  652. "BM_%d : phba->params.num_eq_entries=%d\n",
  653. phba->params.num_eq_entries);
  654. phba->params.num_cq_entries =
  655. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  656. + BE2_TMFS) / 512) + 1) * 512;
  657. phba->params.wrbs_per_cxn = 256;
  658. }
  659. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  660. unsigned int id, unsigned int clr_interrupt,
  661. unsigned int num_processed,
  662. unsigned char rearm, unsigned char event)
  663. {
  664. u32 val = 0;
  665. val |= id & DB_EQ_RING_ID_MASK;
  666. if (rearm)
  667. val |= 1 << DB_EQ_REARM_SHIFT;
  668. if (clr_interrupt)
  669. val |= 1 << DB_EQ_CLR_SHIFT;
  670. if (event)
  671. val |= 1 << DB_EQ_EVNT_SHIFT;
  672. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  673. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  674. }
  675. /**
  676. * be_isr_mcc - The isr routine of the driver.
  677. * @irq: Not used
  678. * @dev_id: Pointer to host adapter structure
  679. */
  680. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  681. {
  682. struct beiscsi_hba *phba;
  683. struct be_eq_entry *eqe = NULL;
  684. struct be_queue_info *eq;
  685. struct be_queue_info *mcc;
  686. unsigned int num_eq_processed;
  687. struct be_eq_obj *pbe_eq;
  688. unsigned long flags;
  689. pbe_eq = dev_id;
  690. eq = &pbe_eq->q;
  691. phba = pbe_eq->phba;
  692. mcc = &phba->ctrl.mcc_obj.cq;
  693. eqe = queue_tail_node(eq);
  694. num_eq_processed = 0;
  695. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  696. & EQE_VALID_MASK) {
  697. if (((eqe->dw[offsetof(struct amap_eq_entry,
  698. resource_id) / 32] &
  699. EQE_RESID_MASK) >> 16) == mcc->id) {
  700. spin_lock_irqsave(&phba->isr_lock, flags);
  701. pbe_eq->todo_mcc_cq = true;
  702. spin_unlock_irqrestore(&phba->isr_lock, flags);
  703. }
  704. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  705. queue_tail_inc(eq);
  706. eqe = queue_tail_node(eq);
  707. num_eq_processed++;
  708. }
  709. if (pbe_eq->todo_mcc_cq)
  710. queue_work(phba->wq, &pbe_eq->work_cqs);
  711. if (num_eq_processed)
  712. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  713. return IRQ_HANDLED;
  714. }
  715. /**
  716. * be_isr_msix - The isr routine of the driver.
  717. * @irq: Not used
  718. * @dev_id: Pointer to host adapter structure
  719. */
  720. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  721. {
  722. struct beiscsi_hba *phba;
  723. struct be_eq_entry *eqe = NULL;
  724. struct be_queue_info *eq;
  725. struct be_queue_info *cq;
  726. unsigned int num_eq_processed;
  727. struct be_eq_obj *pbe_eq;
  728. unsigned long flags;
  729. pbe_eq = dev_id;
  730. eq = &pbe_eq->q;
  731. cq = pbe_eq->cq;
  732. eqe = queue_tail_node(eq);
  733. phba = pbe_eq->phba;
  734. num_eq_processed = 0;
  735. if (blk_iopoll_enabled) {
  736. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  737. & EQE_VALID_MASK) {
  738. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  739. blk_iopoll_sched(&pbe_eq->iopoll);
  740. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  741. queue_tail_inc(eq);
  742. eqe = queue_tail_node(eq);
  743. num_eq_processed++;
  744. }
  745. } else {
  746. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  747. & EQE_VALID_MASK) {
  748. spin_lock_irqsave(&phba->isr_lock, flags);
  749. pbe_eq->todo_cq = true;
  750. spin_unlock_irqrestore(&phba->isr_lock, flags);
  751. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  752. queue_tail_inc(eq);
  753. eqe = queue_tail_node(eq);
  754. num_eq_processed++;
  755. }
  756. if (pbe_eq->todo_cq)
  757. queue_work(phba->wq, &pbe_eq->work_cqs);
  758. }
  759. if (num_eq_processed)
  760. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  761. return IRQ_HANDLED;
  762. }
  763. /**
  764. * be_isr - The isr routine of the driver.
  765. * @irq: Not used
  766. * @dev_id: Pointer to host adapter structure
  767. */
  768. static irqreturn_t be_isr(int irq, void *dev_id)
  769. {
  770. struct beiscsi_hba *phba;
  771. struct hwi_controller *phwi_ctrlr;
  772. struct hwi_context_memory *phwi_context;
  773. struct be_eq_entry *eqe = NULL;
  774. struct be_queue_info *eq;
  775. struct be_queue_info *cq;
  776. struct be_queue_info *mcc;
  777. unsigned long flags, index;
  778. unsigned int num_mcceq_processed, num_ioeq_processed;
  779. struct be_ctrl_info *ctrl;
  780. struct be_eq_obj *pbe_eq;
  781. int isr;
  782. phba = dev_id;
  783. ctrl = &phba->ctrl;
  784. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  785. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  786. if (!isr)
  787. return IRQ_NONE;
  788. phwi_ctrlr = phba->phwi_ctrlr;
  789. phwi_context = phwi_ctrlr->phwi_ctxt;
  790. pbe_eq = &phwi_context->be_eq[0];
  791. eq = &phwi_context->be_eq[0].q;
  792. mcc = &phba->ctrl.mcc_obj.cq;
  793. index = 0;
  794. eqe = queue_tail_node(eq);
  795. num_ioeq_processed = 0;
  796. num_mcceq_processed = 0;
  797. if (blk_iopoll_enabled) {
  798. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  799. & EQE_VALID_MASK) {
  800. if (((eqe->dw[offsetof(struct amap_eq_entry,
  801. resource_id) / 32] &
  802. EQE_RESID_MASK) >> 16) == mcc->id) {
  803. spin_lock_irqsave(&phba->isr_lock, flags);
  804. pbe_eq->todo_mcc_cq = true;
  805. spin_unlock_irqrestore(&phba->isr_lock, flags);
  806. num_mcceq_processed++;
  807. } else {
  808. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  809. blk_iopoll_sched(&pbe_eq->iopoll);
  810. num_ioeq_processed++;
  811. }
  812. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  813. queue_tail_inc(eq);
  814. eqe = queue_tail_node(eq);
  815. }
  816. if (num_ioeq_processed || num_mcceq_processed) {
  817. if (pbe_eq->todo_mcc_cq)
  818. queue_work(phba->wq, &pbe_eq->work_cqs);
  819. if ((num_mcceq_processed) && (!num_ioeq_processed))
  820. hwi_ring_eq_db(phba, eq->id, 0,
  821. (num_ioeq_processed +
  822. num_mcceq_processed) , 1, 1);
  823. else
  824. hwi_ring_eq_db(phba, eq->id, 0,
  825. (num_ioeq_processed +
  826. num_mcceq_processed), 0, 1);
  827. return IRQ_HANDLED;
  828. } else
  829. return IRQ_NONE;
  830. } else {
  831. cq = &phwi_context->be_cq[0];
  832. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  833. & EQE_VALID_MASK) {
  834. if (((eqe->dw[offsetof(struct amap_eq_entry,
  835. resource_id) / 32] &
  836. EQE_RESID_MASK) >> 16) != cq->id) {
  837. spin_lock_irqsave(&phba->isr_lock, flags);
  838. pbe_eq->todo_mcc_cq = true;
  839. spin_unlock_irqrestore(&phba->isr_lock, flags);
  840. } else {
  841. spin_lock_irqsave(&phba->isr_lock, flags);
  842. pbe_eq->todo_cq = true;
  843. spin_unlock_irqrestore(&phba->isr_lock, flags);
  844. }
  845. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  846. queue_tail_inc(eq);
  847. eqe = queue_tail_node(eq);
  848. num_ioeq_processed++;
  849. }
  850. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  851. queue_work(phba->wq, &pbe_eq->work_cqs);
  852. if (num_ioeq_processed) {
  853. hwi_ring_eq_db(phba, eq->id, 0,
  854. num_ioeq_processed, 1, 1);
  855. return IRQ_HANDLED;
  856. } else
  857. return IRQ_NONE;
  858. }
  859. }
  860. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  861. {
  862. struct pci_dev *pcidev = phba->pcidev;
  863. struct hwi_controller *phwi_ctrlr;
  864. struct hwi_context_memory *phwi_context;
  865. int ret, msix_vec, i, j;
  866. phwi_ctrlr = phba->phwi_ctrlr;
  867. phwi_context = phwi_ctrlr->phwi_ctxt;
  868. if (phba->msix_enabled) {
  869. for (i = 0; i < phba->num_cpus; i++) {
  870. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  871. GFP_KERNEL);
  872. if (!phba->msi_name[i]) {
  873. ret = -ENOMEM;
  874. goto free_msix_irqs;
  875. }
  876. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  877. phba->shost->host_no, i);
  878. msix_vec = phba->msix_entries[i].vector;
  879. ret = request_irq(msix_vec, be_isr_msix, 0,
  880. phba->msi_name[i],
  881. &phwi_context->be_eq[i]);
  882. if (ret) {
  883. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  884. "BM_%d : beiscsi_init_irqs-Failed to"
  885. "register msix for i = %d\n",
  886. i);
  887. kfree(phba->msi_name[i]);
  888. goto free_msix_irqs;
  889. }
  890. }
  891. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  892. if (!phba->msi_name[i]) {
  893. ret = -ENOMEM;
  894. goto free_msix_irqs;
  895. }
  896. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  897. phba->shost->host_no);
  898. msix_vec = phba->msix_entries[i].vector;
  899. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  900. &phwi_context->be_eq[i]);
  901. if (ret) {
  902. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  903. "BM_%d : beiscsi_init_irqs-"
  904. "Failed to register beiscsi_msix_mcc\n");
  905. kfree(phba->msi_name[i]);
  906. goto free_msix_irqs;
  907. }
  908. } else {
  909. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  910. "beiscsi", phba);
  911. if (ret) {
  912. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  913. "BM_%d : beiscsi_init_irqs-"
  914. "Failed to register irq\\n");
  915. return ret;
  916. }
  917. }
  918. return 0;
  919. free_msix_irqs:
  920. for (j = i - 1; j >= 0; j--) {
  921. kfree(phba->msi_name[j]);
  922. msix_vec = phba->msix_entries[j].vector;
  923. free_irq(msix_vec, &phwi_context->be_eq[j]);
  924. }
  925. return ret;
  926. }
  927. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  928. unsigned int id, unsigned int num_processed,
  929. unsigned char rearm, unsigned char event)
  930. {
  931. u32 val = 0;
  932. val |= id & DB_CQ_RING_ID_MASK;
  933. if (rearm)
  934. val |= 1 << DB_CQ_REARM_SHIFT;
  935. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  936. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  937. }
  938. static unsigned int
  939. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  940. struct beiscsi_hba *phba,
  941. unsigned short cid,
  942. struct pdu_base *ppdu,
  943. unsigned long pdu_len,
  944. void *pbuffer, unsigned long buf_len)
  945. {
  946. struct iscsi_conn *conn = beiscsi_conn->conn;
  947. struct iscsi_session *session = conn->session;
  948. struct iscsi_task *task;
  949. struct beiscsi_io_task *io_task;
  950. struct iscsi_hdr *login_hdr;
  951. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  952. PDUBASE_OPCODE_MASK) {
  953. case ISCSI_OP_NOOP_IN:
  954. pbuffer = NULL;
  955. buf_len = 0;
  956. break;
  957. case ISCSI_OP_ASYNC_EVENT:
  958. break;
  959. case ISCSI_OP_REJECT:
  960. WARN_ON(!pbuffer);
  961. WARN_ON(!(buf_len == 48));
  962. beiscsi_log(phba, KERN_ERR,
  963. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  964. "BM_%d : In ISCSI_OP_REJECT\n");
  965. break;
  966. case ISCSI_OP_LOGIN_RSP:
  967. case ISCSI_OP_TEXT_RSP:
  968. task = conn->login_task;
  969. io_task = task->dd_data;
  970. login_hdr = (struct iscsi_hdr *)ppdu;
  971. login_hdr->itt = io_task->libiscsi_itt;
  972. break;
  973. default:
  974. beiscsi_log(phba, KERN_WARNING,
  975. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  976. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  977. (ppdu->
  978. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  979. & PDUBASE_OPCODE_MASK));
  980. return 1;
  981. }
  982. spin_lock_bh(&session->lock);
  983. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  984. spin_unlock_bh(&session->lock);
  985. return 0;
  986. }
  987. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  988. {
  989. struct sgl_handle *psgl_handle;
  990. if (phba->io_sgl_hndl_avbl) {
  991. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  992. "BM_%d : In alloc_io_sgl_handle,"
  993. " io_sgl_alloc_index=%d\n",
  994. phba->io_sgl_alloc_index);
  995. psgl_handle = phba->io_sgl_hndl_base[phba->
  996. io_sgl_alloc_index];
  997. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  998. phba->io_sgl_hndl_avbl--;
  999. if (phba->io_sgl_alloc_index == (phba->params.
  1000. ios_per_ctrl - 1))
  1001. phba->io_sgl_alloc_index = 0;
  1002. else
  1003. phba->io_sgl_alloc_index++;
  1004. } else
  1005. psgl_handle = NULL;
  1006. return psgl_handle;
  1007. }
  1008. static void
  1009. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1010. {
  1011. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1012. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1013. phba->io_sgl_free_index);
  1014. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1015. /*
  1016. * this can happen if clean_task is called on a task that
  1017. * failed in xmit_task or alloc_pdu.
  1018. */
  1019. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1020. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1021. "value there=%p\n", phba->io_sgl_free_index,
  1022. phba->io_sgl_hndl_base
  1023. [phba->io_sgl_free_index]);
  1024. return;
  1025. }
  1026. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1027. phba->io_sgl_hndl_avbl++;
  1028. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1029. phba->io_sgl_free_index = 0;
  1030. else
  1031. phba->io_sgl_free_index++;
  1032. }
  1033. /**
  1034. * alloc_wrb_handle - To allocate a wrb handle
  1035. * @phba: The hba pointer
  1036. * @cid: The cid to use for allocation
  1037. *
  1038. * This happens under session_lock until submission to chip
  1039. */
  1040. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1041. {
  1042. struct hwi_wrb_context *pwrb_context;
  1043. struct hwi_controller *phwi_ctrlr;
  1044. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1045. phwi_ctrlr = phba->phwi_ctrlr;
  1046. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1047. if (pwrb_context->wrb_handles_available >= 2) {
  1048. pwrb_handle = pwrb_context->pwrb_handle_base[
  1049. pwrb_context->alloc_index];
  1050. pwrb_context->wrb_handles_available--;
  1051. if (pwrb_context->alloc_index ==
  1052. (phba->params.wrbs_per_cxn - 1))
  1053. pwrb_context->alloc_index = 0;
  1054. else
  1055. pwrb_context->alloc_index++;
  1056. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1057. pwrb_context->alloc_index];
  1058. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1059. } else
  1060. pwrb_handle = NULL;
  1061. return pwrb_handle;
  1062. }
  1063. /**
  1064. * free_wrb_handle - To free the wrb handle back to pool
  1065. * @phba: The hba pointer
  1066. * @pwrb_context: The context to free from
  1067. * @pwrb_handle: The wrb_handle to free
  1068. *
  1069. * This happens under session_lock until submission to chip
  1070. */
  1071. static void
  1072. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1073. struct wrb_handle *pwrb_handle)
  1074. {
  1075. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1076. pwrb_context->wrb_handles_available++;
  1077. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1078. pwrb_context->free_index = 0;
  1079. else
  1080. pwrb_context->free_index++;
  1081. beiscsi_log(phba, KERN_INFO,
  1082. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1083. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1084. "wrb_handles_available=%d\n",
  1085. pwrb_handle, pwrb_context->free_index,
  1086. pwrb_context->wrb_handles_available);
  1087. }
  1088. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1089. {
  1090. struct sgl_handle *psgl_handle;
  1091. if (phba->eh_sgl_hndl_avbl) {
  1092. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1093. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1094. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1095. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1096. phba->eh_sgl_alloc_index,
  1097. phba->eh_sgl_alloc_index);
  1098. phba->eh_sgl_hndl_avbl--;
  1099. if (phba->eh_sgl_alloc_index ==
  1100. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1101. 1))
  1102. phba->eh_sgl_alloc_index = 0;
  1103. else
  1104. phba->eh_sgl_alloc_index++;
  1105. } else
  1106. psgl_handle = NULL;
  1107. return psgl_handle;
  1108. }
  1109. void
  1110. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1111. {
  1112. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1113. "BM_%d : In free_mgmt_sgl_handle,"
  1114. "eh_sgl_free_index=%d\n",
  1115. phba->eh_sgl_free_index);
  1116. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1117. /*
  1118. * this can happen if clean_task is called on a task that
  1119. * failed in xmit_task or alloc_pdu.
  1120. */
  1121. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1122. "BM_%d : Double Free in eh SGL ,"
  1123. "eh_sgl_free_index=%d\n",
  1124. phba->eh_sgl_free_index);
  1125. return;
  1126. }
  1127. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1128. phba->eh_sgl_hndl_avbl++;
  1129. if (phba->eh_sgl_free_index ==
  1130. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1131. phba->eh_sgl_free_index = 0;
  1132. else
  1133. phba->eh_sgl_free_index++;
  1134. }
  1135. static void
  1136. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1137. struct iscsi_task *task, struct sol_cqe *psol)
  1138. {
  1139. struct beiscsi_io_task *io_task = task->dd_data;
  1140. struct be_status_bhs *sts_bhs =
  1141. (struct be_status_bhs *)io_task->cmd_bhs;
  1142. struct iscsi_conn *conn = beiscsi_conn->conn;
  1143. unsigned char *sense;
  1144. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1145. u8 rsp, status, flags;
  1146. exp_cmdsn = (psol->
  1147. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1148. & SOL_EXP_CMD_SN_MASK);
  1149. max_cmdsn = ((psol->
  1150. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1151. & SOL_EXP_CMD_SN_MASK) +
  1152. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1153. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1154. rsp = ((psol->dw[offsetof(struct amap_sol_cqe, i_resp) / 32]
  1155. & SOL_RESP_MASK) >> 16);
  1156. status = ((psol->dw[offsetof(struct amap_sol_cqe, i_sts) / 32]
  1157. & SOL_STS_MASK) >> 8);
  1158. flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1159. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1160. if (!task->sc) {
  1161. if (io_task->scsi_cmnd)
  1162. scsi_dma_unmap(io_task->scsi_cmnd);
  1163. return;
  1164. }
  1165. task->sc->result = (DID_OK << 16) | status;
  1166. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1167. task->sc->result = DID_ERROR << 16;
  1168. goto unmap;
  1169. }
  1170. /* bidi not initially supported */
  1171. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1172. resid = (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) /
  1173. 32] & SOL_RES_CNT_MASK);
  1174. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1175. task->sc->result = DID_ERROR << 16;
  1176. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1177. scsi_set_resid(task->sc, resid);
  1178. if (!status && (scsi_bufflen(task->sc) - resid <
  1179. task->sc->underflow))
  1180. task->sc->result = DID_ERROR << 16;
  1181. }
  1182. }
  1183. if (status == SAM_STAT_CHECK_CONDITION) {
  1184. u16 sense_len;
  1185. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1186. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1187. sense_len = be16_to_cpu(*slen);
  1188. memcpy(task->sc->sense_buffer, sense,
  1189. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1190. }
  1191. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) {
  1192. if (psol->dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1193. & SOL_RES_CNT_MASK)
  1194. conn->rxdata_octets += (psol->
  1195. dw[offsetof(struct amap_sol_cqe, i_res_cnt) / 32]
  1196. & SOL_RES_CNT_MASK);
  1197. }
  1198. unmap:
  1199. scsi_dma_unmap(io_task->scsi_cmnd);
  1200. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1201. }
  1202. static void
  1203. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1204. struct iscsi_task *task, struct sol_cqe *psol)
  1205. {
  1206. struct iscsi_logout_rsp *hdr;
  1207. struct beiscsi_io_task *io_task = task->dd_data;
  1208. struct iscsi_conn *conn = beiscsi_conn->conn;
  1209. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1210. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1211. hdr->t2wait = 5;
  1212. hdr->t2retain = 0;
  1213. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1214. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1215. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1216. 32] & SOL_RESP_MASK);
  1217. hdr->exp_cmdsn = cpu_to_be32(psol->
  1218. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1219. & SOL_EXP_CMD_SN_MASK);
  1220. hdr->max_cmdsn = be32_to_cpu((psol->
  1221. dw[offsetof(struct amap_sol_cqe, i_exp_cmd_sn) / 32]
  1222. & SOL_EXP_CMD_SN_MASK) +
  1223. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1224. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1225. hdr->dlength[0] = 0;
  1226. hdr->dlength[1] = 0;
  1227. hdr->dlength[2] = 0;
  1228. hdr->hlength = 0;
  1229. hdr->itt = io_task->libiscsi_itt;
  1230. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1231. }
  1232. static void
  1233. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1234. struct iscsi_task *task, struct sol_cqe *psol)
  1235. {
  1236. struct iscsi_tm_rsp *hdr;
  1237. struct iscsi_conn *conn = beiscsi_conn->conn;
  1238. struct beiscsi_io_task *io_task = task->dd_data;
  1239. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1240. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1241. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1242. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1243. hdr->response = (psol->dw[offsetof(struct amap_sol_cqe, i_resp) /
  1244. 32] & SOL_RESP_MASK);
  1245. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1246. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1247. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1248. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1249. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1250. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1251. hdr->itt = io_task->libiscsi_itt;
  1252. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1253. }
  1254. static void
  1255. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1256. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1257. {
  1258. struct hwi_wrb_context *pwrb_context;
  1259. struct wrb_handle *pwrb_handle = NULL;
  1260. struct hwi_controller *phwi_ctrlr;
  1261. struct iscsi_task *task;
  1262. struct beiscsi_io_task *io_task;
  1263. struct iscsi_conn *conn = beiscsi_conn->conn;
  1264. struct iscsi_session *session = conn->session;
  1265. phwi_ctrlr = phba->phwi_ctrlr;
  1266. pwrb_context = &phwi_ctrlr->wrb_context[((psol->
  1267. dw[offsetof(struct amap_sol_cqe, cid) / 32] &
  1268. SOL_CID_MASK) >> 6) -
  1269. phba->fw_config.iscsi_cid_start];
  1270. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1271. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1272. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1273. task = pwrb_handle->pio_handle;
  1274. io_task = task->dd_data;
  1275. spin_lock_bh(&phba->mgmt_sgl_lock);
  1276. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1277. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1278. spin_lock_bh(&session->lock);
  1279. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1280. spin_unlock_bh(&session->lock);
  1281. }
  1282. static void
  1283. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1284. struct iscsi_task *task, struct sol_cqe *psol)
  1285. {
  1286. struct iscsi_nopin *hdr;
  1287. struct iscsi_conn *conn = beiscsi_conn->conn;
  1288. struct beiscsi_io_task *io_task = task->dd_data;
  1289. hdr = (struct iscsi_nopin *)task->hdr;
  1290. hdr->flags = ((psol->dw[offsetof(struct amap_sol_cqe, i_flags) / 32]
  1291. & SOL_FLAGS_MASK) >> 24) | 0x80;
  1292. hdr->exp_cmdsn = cpu_to_be32(psol->dw[offsetof(struct amap_sol_cqe,
  1293. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK);
  1294. hdr->max_cmdsn = be32_to_cpu((psol->dw[offsetof(struct amap_sol_cqe,
  1295. i_exp_cmd_sn) / 32] & SOL_EXP_CMD_SN_MASK) +
  1296. ((psol->dw[offsetof(struct amap_sol_cqe, i_cmd_wnd)
  1297. / 32] & SOL_CMD_WND_MASK) >> 24) - 1);
  1298. hdr->opcode = ISCSI_OP_NOOP_IN;
  1299. hdr->itt = io_task->libiscsi_itt;
  1300. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1301. }
  1302. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1303. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1304. {
  1305. struct hwi_wrb_context *pwrb_context;
  1306. struct wrb_handle *pwrb_handle;
  1307. struct iscsi_wrb *pwrb = NULL;
  1308. struct hwi_controller *phwi_ctrlr;
  1309. struct iscsi_task *task;
  1310. unsigned int type;
  1311. struct iscsi_conn *conn = beiscsi_conn->conn;
  1312. struct iscsi_session *session = conn->session;
  1313. phwi_ctrlr = phba->phwi_ctrlr;
  1314. pwrb_context = &phwi_ctrlr->wrb_context[((psol->dw[offsetof
  1315. (struct amap_sol_cqe, cid) / 32]
  1316. & SOL_CID_MASK) >> 6) -
  1317. phba->fw_config.iscsi_cid_start];
  1318. pwrb_handle = pwrb_context->pwrb_handle_basestd[((psol->
  1319. dw[offsetof(struct amap_sol_cqe, wrb_index) /
  1320. 32] & SOL_WRB_INDEX_MASK) >> 16)];
  1321. task = pwrb_handle->pio_handle;
  1322. pwrb = pwrb_handle->pwrb;
  1323. type = (pwrb->dw[offsetof(struct amap_iscsi_wrb, type) / 32] &
  1324. WRB_TYPE_MASK) >> 28;
  1325. spin_lock_bh(&session->lock);
  1326. switch (type) {
  1327. case HWH_TYPE_IO:
  1328. case HWH_TYPE_IO_RD:
  1329. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1330. ISCSI_OP_NOOP_OUT)
  1331. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1332. else
  1333. be_complete_io(beiscsi_conn, task, psol);
  1334. break;
  1335. case HWH_TYPE_LOGOUT:
  1336. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1337. be_complete_logout(beiscsi_conn, task, psol);
  1338. else
  1339. be_complete_tmf(beiscsi_conn, task, psol);
  1340. break;
  1341. case HWH_TYPE_LOGIN:
  1342. beiscsi_log(phba, KERN_ERR,
  1343. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1344. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1345. " hwi_complete_cmd- Solicited path\n");
  1346. break;
  1347. case HWH_TYPE_NOP:
  1348. be_complete_nopin_resp(beiscsi_conn, task, psol);
  1349. break;
  1350. default:
  1351. beiscsi_log(phba, KERN_WARNING,
  1352. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1353. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1354. "wrb_index 0x%x CID 0x%x\n", type,
  1355. ((psol->dw[offsetof(struct amap_iscsi_wrb,
  1356. type) / 32] & SOL_WRB_INDEX_MASK) >> 16),
  1357. ((psol->dw[offsetof(struct amap_sol_cqe,
  1358. cid) / 32] & SOL_CID_MASK) >> 6));
  1359. break;
  1360. }
  1361. spin_unlock_bh(&session->lock);
  1362. }
  1363. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1364. *pasync_ctx, unsigned int is_header,
  1365. unsigned int host_write_ptr)
  1366. {
  1367. if (is_header)
  1368. return &pasync_ctx->async_entry[host_write_ptr].
  1369. header_busy_list;
  1370. else
  1371. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1372. }
  1373. static struct async_pdu_handle *
  1374. hwi_get_async_handle(struct beiscsi_hba *phba,
  1375. struct beiscsi_conn *beiscsi_conn,
  1376. struct hwi_async_pdu_context *pasync_ctx,
  1377. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1378. {
  1379. struct be_bus_address phys_addr;
  1380. struct list_head *pbusy_list;
  1381. struct async_pdu_handle *pasync_handle = NULL;
  1382. unsigned char is_header = 0;
  1383. phys_addr.u.a32.address_lo =
  1384. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_lo) / 32] -
  1385. ((pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1386. & PDUCQE_DPL_MASK) >> 16);
  1387. phys_addr.u.a32.address_hi =
  1388. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, db_addr_hi) / 32];
  1389. phys_addr.u.a64.address =
  1390. *((unsigned long long *)(&phys_addr.u.a64.address));
  1391. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1392. & PDUCQE_CODE_MASK) {
  1393. case UNSOL_HDR_NOTIFY:
  1394. is_header = 1;
  1395. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 1,
  1396. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1397. index) / 32] & PDUCQE_INDEX_MASK));
  1398. break;
  1399. case UNSOL_DATA_NOTIFY:
  1400. pbusy_list = hwi_get_async_busy_list(pasync_ctx, 0, (pdpdu_cqe->
  1401. dw[offsetof(struct amap_i_t_dpdu_cqe,
  1402. index) / 32] & PDUCQE_INDEX_MASK));
  1403. break;
  1404. default:
  1405. pbusy_list = NULL;
  1406. beiscsi_log(phba, KERN_WARNING,
  1407. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1408. "BM_%d : Unexpected code=%d\n",
  1409. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1410. code) / 32] & PDUCQE_CODE_MASK);
  1411. return NULL;
  1412. }
  1413. WARN_ON(list_empty(pbusy_list));
  1414. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1415. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1416. break;
  1417. }
  1418. WARN_ON(!pasync_handle);
  1419. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1420. phba->fw_config.iscsi_cid_start;
  1421. pasync_handle->is_header = is_header;
  1422. pasync_handle->buffer_len = ((pdpdu_cqe->
  1423. dw[offsetof(struct amap_i_t_dpdu_cqe, dpl) / 32]
  1424. & PDUCQE_DPL_MASK) >> 16);
  1425. *pcq_index = (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1426. index) / 32] & PDUCQE_INDEX_MASK);
  1427. return pasync_handle;
  1428. }
  1429. static unsigned int
  1430. hwi_update_async_writables(struct beiscsi_hba *phba,
  1431. struct hwi_async_pdu_context *pasync_ctx,
  1432. unsigned int is_header, unsigned int cq_index)
  1433. {
  1434. struct list_head *pbusy_list;
  1435. struct async_pdu_handle *pasync_handle;
  1436. unsigned int num_entries, writables = 0;
  1437. unsigned int *pep_read_ptr, *pwritables;
  1438. num_entries = pasync_ctx->num_entries;
  1439. if (is_header) {
  1440. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1441. pwritables = &pasync_ctx->async_header.writables;
  1442. } else {
  1443. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1444. pwritables = &pasync_ctx->async_data.writables;
  1445. }
  1446. while ((*pep_read_ptr) != cq_index) {
  1447. (*pep_read_ptr)++;
  1448. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1449. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1450. *pep_read_ptr);
  1451. if (writables == 0)
  1452. WARN_ON(list_empty(pbusy_list));
  1453. if (!list_empty(pbusy_list)) {
  1454. pasync_handle = list_entry(pbusy_list->next,
  1455. struct async_pdu_handle,
  1456. link);
  1457. WARN_ON(!pasync_handle);
  1458. pasync_handle->consumed = 1;
  1459. }
  1460. writables++;
  1461. }
  1462. if (!writables) {
  1463. beiscsi_log(phba, KERN_ERR,
  1464. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1465. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1466. cq_index);
  1467. WARN_ON(1);
  1468. }
  1469. *pwritables = *pwritables + writables;
  1470. return 0;
  1471. }
  1472. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1473. unsigned int cri)
  1474. {
  1475. struct hwi_controller *phwi_ctrlr;
  1476. struct hwi_async_pdu_context *pasync_ctx;
  1477. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1478. struct list_head *plist;
  1479. phwi_ctrlr = phba->phwi_ctrlr;
  1480. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1481. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1482. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1483. list_del(&pasync_handle->link);
  1484. if (pasync_handle->is_header) {
  1485. list_add_tail(&pasync_handle->link,
  1486. &pasync_ctx->async_header.free_list);
  1487. pasync_ctx->async_header.free_entries++;
  1488. } else {
  1489. list_add_tail(&pasync_handle->link,
  1490. &pasync_ctx->async_data.free_list);
  1491. pasync_ctx->async_data.free_entries++;
  1492. }
  1493. }
  1494. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1495. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1496. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1497. }
  1498. static struct phys_addr *
  1499. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1500. unsigned int is_header, unsigned int host_write_ptr)
  1501. {
  1502. struct phys_addr *pasync_sge = NULL;
  1503. if (is_header)
  1504. pasync_sge = pasync_ctx->async_header.ring_base;
  1505. else
  1506. pasync_sge = pasync_ctx->async_data.ring_base;
  1507. return pasync_sge + host_write_ptr;
  1508. }
  1509. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1510. unsigned int is_header)
  1511. {
  1512. struct hwi_controller *phwi_ctrlr;
  1513. struct hwi_async_pdu_context *pasync_ctx;
  1514. struct async_pdu_handle *pasync_handle;
  1515. struct list_head *pfree_link, *pbusy_list;
  1516. struct phys_addr *pasync_sge;
  1517. unsigned int ring_id, num_entries;
  1518. unsigned int host_write_num;
  1519. unsigned int writables;
  1520. unsigned int i = 0;
  1521. u32 doorbell = 0;
  1522. phwi_ctrlr = phba->phwi_ctrlr;
  1523. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1524. num_entries = pasync_ctx->num_entries;
  1525. if (is_header) {
  1526. writables = min(pasync_ctx->async_header.writables,
  1527. pasync_ctx->async_header.free_entries);
  1528. pfree_link = pasync_ctx->async_header.free_list.next;
  1529. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1530. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1531. } else {
  1532. writables = min(pasync_ctx->async_data.writables,
  1533. pasync_ctx->async_data.free_entries);
  1534. pfree_link = pasync_ctx->async_data.free_list.next;
  1535. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1536. ring_id = phwi_ctrlr->default_pdu_data.id;
  1537. }
  1538. writables = (writables / 8) * 8;
  1539. if (writables) {
  1540. for (i = 0; i < writables; i++) {
  1541. pbusy_list =
  1542. hwi_get_async_busy_list(pasync_ctx, is_header,
  1543. host_write_num);
  1544. pasync_handle =
  1545. list_entry(pfree_link, struct async_pdu_handle,
  1546. link);
  1547. WARN_ON(!pasync_handle);
  1548. pasync_handle->consumed = 0;
  1549. pfree_link = pfree_link->next;
  1550. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1551. is_header, host_write_num);
  1552. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1553. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1554. list_move(&pasync_handle->link, pbusy_list);
  1555. host_write_num++;
  1556. host_write_num = host_write_num % num_entries;
  1557. }
  1558. if (is_header) {
  1559. pasync_ctx->async_header.host_write_ptr =
  1560. host_write_num;
  1561. pasync_ctx->async_header.free_entries -= writables;
  1562. pasync_ctx->async_header.writables -= writables;
  1563. pasync_ctx->async_header.busy_entries += writables;
  1564. } else {
  1565. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1566. pasync_ctx->async_data.free_entries -= writables;
  1567. pasync_ctx->async_data.writables -= writables;
  1568. pasync_ctx->async_data.busy_entries += writables;
  1569. }
  1570. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1571. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1572. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1573. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1574. << DB_DEF_PDU_CQPROC_SHIFT;
  1575. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1576. }
  1577. }
  1578. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1579. struct beiscsi_conn *beiscsi_conn,
  1580. struct i_t_dpdu_cqe *pdpdu_cqe)
  1581. {
  1582. struct hwi_controller *phwi_ctrlr;
  1583. struct hwi_async_pdu_context *pasync_ctx;
  1584. struct async_pdu_handle *pasync_handle = NULL;
  1585. unsigned int cq_index = -1;
  1586. phwi_ctrlr = phba->phwi_ctrlr;
  1587. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1588. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1589. pdpdu_cqe, &cq_index);
  1590. BUG_ON(pasync_handle->is_header != 0);
  1591. if (pasync_handle->consumed == 0)
  1592. hwi_update_async_writables(phba, pasync_ctx,
  1593. pasync_handle->is_header, cq_index);
  1594. hwi_free_async_msg(phba, pasync_handle->cri);
  1595. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1596. }
  1597. static unsigned int
  1598. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1599. struct beiscsi_hba *phba,
  1600. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1601. {
  1602. struct list_head *plist;
  1603. struct async_pdu_handle *pasync_handle;
  1604. void *phdr = NULL;
  1605. unsigned int hdr_len = 0, buf_len = 0;
  1606. unsigned int status, index = 0, offset = 0;
  1607. void *pfirst_buffer = NULL;
  1608. unsigned int num_buf = 0;
  1609. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1610. list_for_each_entry(pasync_handle, plist, link) {
  1611. if (index == 0) {
  1612. phdr = pasync_handle->pbuffer;
  1613. hdr_len = pasync_handle->buffer_len;
  1614. } else {
  1615. buf_len = pasync_handle->buffer_len;
  1616. if (!num_buf) {
  1617. pfirst_buffer = pasync_handle->pbuffer;
  1618. num_buf++;
  1619. }
  1620. memcpy(pfirst_buffer + offset,
  1621. pasync_handle->pbuffer, buf_len);
  1622. offset += buf_len;
  1623. }
  1624. index++;
  1625. }
  1626. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1627. (beiscsi_conn->beiscsi_conn_cid -
  1628. phba->fw_config.iscsi_cid_start),
  1629. phdr, hdr_len, pfirst_buffer,
  1630. offset);
  1631. hwi_free_async_msg(phba, cri);
  1632. return 0;
  1633. }
  1634. static unsigned int
  1635. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1636. struct beiscsi_hba *phba,
  1637. struct async_pdu_handle *pasync_handle)
  1638. {
  1639. struct hwi_async_pdu_context *pasync_ctx;
  1640. struct hwi_controller *phwi_ctrlr;
  1641. unsigned int bytes_needed = 0, status = 0;
  1642. unsigned short cri = pasync_handle->cri;
  1643. struct pdu_base *ppdu;
  1644. phwi_ctrlr = phba->phwi_ctrlr;
  1645. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1646. list_del(&pasync_handle->link);
  1647. if (pasync_handle->is_header) {
  1648. pasync_ctx->async_header.busy_entries--;
  1649. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1650. hwi_free_async_msg(phba, cri);
  1651. BUG();
  1652. }
  1653. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1654. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1655. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1656. (unsigned short)pasync_handle->buffer_len;
  1657. list_add_tail(&pasync_handle->link,
  1658. &pasync_ctx->async_entry[cri].wait_queue.list);
  1659. ppdu = pasync_handle->pbuffer;
  1660. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1661. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1662. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1663. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1664. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1665. if (status == 0) {
  1666. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1667. bytes_needed;
  1668. if (bytes_needed == 0)
  1669. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1670. pasync_ctx, cri);
  1671. }
  1672. } else {
  1673. pasync_ctx->async_data.busy_entries--;
  1674. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1675. list_add_tail(&pasync_handle->link,
  1676. &pasync_ctx->async_entry[cri].wait_queue.
  1677. list);
  1678. pasync_ctx->async_entry[cri].wait_queue.
  1679. bytes_received +=
  1680. (unsigned short)pasync_handle->buffer_len;
  1681. if (pasync_ctx->async_entry[cri].wait_queue.
  1682. bytes_received >=
  1683. pasync_ctx->async_entry[cri].wait_queue.
  1684. bytes_needed)
  1685. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1686. pasync_ctx, cri);
  1687. }
  1688. }
  1689. return status;
  1690. }
  1691. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1692. struct beiscsi_hba *phba,
  1693. struct i_t_dpdu_cqe *pdpdu_cqe)
  1694. {
  1695. struct hwi_controller *phwi_ctrlr;
  1696. struct hwi_async_pdu_context *pasync_ctx;
  1697. struct async_pdu_handle *pasync_handle = NULL;
  1698. unsigned int cq_index = -1;
  1699. phwi_ctrlr = phba->phwi_ctrlr;
  1700. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1701. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1702. pdpdu_cqe, &cq_index);
  1703. if (pasync_handle->consumed == 0)
  1704. hwi_update_async_writables(phba, pasync_ctx,
  1705. pasync_handle->is_header, cq_index);
  1706. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1707. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1708. }
  1709. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1710. {
  1711. struct be_queue_info *mcc_cq;
  1712. struct be_mcc_compl *mcc_compl;
  1713. unsigned int num_processed = 0;
  1714. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1715. mcc_compl = queue_tail_node(mcc_cq);
  1716. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1717. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1718. if (num_processed >= 32) {
  1719. hwi_ring_cq_db(phba, mcc_cq->id,
  1720. num_processed, 0, 0);
  1721. num_processed = 0;
  1722. }
  1723. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1724. /* Interpret flags as an async trailer */
  1725. if (is_link_state_evt(mcc_compl->flags))
  1726. /* Interpret compl as a async link evt */
  1727. beiscsi_async_link_state_process(phba,
  1728. (struct be_async_event_link_state *) mcc_compl);
  1729. else
  1730. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1731. "BM_%d : Unsupported Async Event, flags"
  1732. " = 0x%08x\n",
  1733. mcc_compl->flags);
  1734. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1735. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1736. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1737. }
  1738. mcc_compl->flags = 0;
  1739. queue_tail_inc(mcc_cq);
  1740. mcc_compl = queue_tail_node(mcc_cq);
  1741. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1742. num_processed++;
  1743. }
  1744. if (num_processed > 0)
  1745. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1746. }
  1747. /**
  1748. * beiscsi_process_cq()- Process the Completion Queue
  1749. * @pbe_eq: Event Q on which the Completion has come
  1750. *
  1751. * return
  1752. * Number of Completion Entries processed.
  1753. **/
  1754. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1755. {
  1756. struct be_queue_info *cq;
  1757. struct sol_cqe *sol;
  1758. struct dmsg_cqe *dmsg;
  1759. unsigned int num_processed = 0;
  1760. unsigned int tot_nump = 0;
  1761. unsigned short code = 0, cid = 0;
  1762. struct beiscsi_conn *beiscsi_conn;
  1763. struct beiscsi_endpoint *beiscsi_ep;
  1764. struct iscsi_endpoint *ep;
  1765. struct beiscsi_hba *phba;
  1766. cq = pbe_eq->cq;
  1767. sol = queue_tail_node(cq);
  1768. phba = pbe_eq->phba;
  1769. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1770. CQE_VALID_MASK) {
  1771. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1772. cid = ((sol->dw[offsetof(struct amap_sol_cqe, cid)/32] &
  1773. CQE_CID_MASK) >> 6);
  1774. code = (sol->dw[offsetof(struct amap_sol_cqe, code)/32] &
  1775. CQE_CODE_MASK);
  1776. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1777. beiscsi_ep = ep->dd_data;
  1778. beiscsi_conn = beiscsi_ep->conn;
  1779. if (num_processed >= 32) {
  1780. hwi_ring_cq_db(phba, cq->id,
  1781. num_processed, 0, 0);
  1782. tot_nump += num_processed;
  1783. num_processed = 0;
  1784. }
  1785. switch (code) {
  1786. case SOL_CMD_COMPLETE:
  1787. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1788. break;
  1789. case DRIVERMSG_NOTIFY:
  1790. beiscsi_log(phba, KERN_INFO,
  1791. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1792. "BM_%d : Received %s[%d] on CID : %d\n",
  1793. cqe_desc[code], code, cid);
  1794. dmsg = (struct dmsg_cqe *)sol;
  1795. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1796. break;
  1797. case UNSOL_HDR_NOTIFY:
  1798. beiscsi_log(phba, KERN_INFO,
  1799. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1800. "BM_%d : Received %s[%d] on CID : %d\n",
  1801. cqe_desc[code], code, cid);
  1802. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1803. (struct i_t_dpdu_cqe *)sol);
  1804. break;
  1805. case UNSOL_DATA_NOTIFY:
  1806. beiscsi_log(phba, KERN_INFO,
  1807. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1808. "BM_%d : Received %s[%d] on CID : %d\n",
  1809. cqe_desc[code], code, cid);
  1810. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1811. (struct i_t_dpdu_cqe *)sol);
  1812. break;
  1813. case CXN_INVALIDATE_INDEX_NOTIFY:
  1814. case CMD_INVALIDATED_NOTIFY:
  1815. case CXN_INVALIDATE_NOTIFY:
  1816. beiscsi_log(phba, KERN_ERR,
  1817. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1818. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1819. cqe_desc[code], code, cid);
  1820. break;
  1821. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1822. case CMD_KILLED_INVALID_STATSN_RCVD:
  1823. case CMD_KILLED_INVALID_R2T_RCVD:
  1824. case CMD_CXN_KILLED_LUN_INVALID:
  1825. case CMD_CXN_KILLED_ICD_INVALID:
  1826. case CMD_CXN_KILLED_ITT_INVALID:
  1827. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1828. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1829. beiscsi_log(phba, KERN_ERR,
  1830. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1831. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1832. cqe_desc[code], code, cid);
  1833. break;
  1834. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1835. beiscsi_log(phba, KERN_ERR,
  1836. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1837. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1838. cqe_desc[code], code, cid);
  1839. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1840. (struct i_t_dpdu_cqe *) sol);
  1841. break;
  1842. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1843. case CXN_KILLED_BURST_LEN_MISMATCH:
  1844. case CXN_KILLED_AHS_RCVD:
  1845. case CXN_KILLED_HDR_DIGEST_ERR:
  1846. case CXN_KILLED_UNKNOWN_HDR:
  1847. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1848. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1849. case CXN_KILLED_TIMED_OUT:
  1850. case CXN_KILLED_FIN_RCVD:
  1851. case CXN_KILLED_RST_SENT:
  1852. case CXN_KILLED_RST_RCVD:
  1853. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1854. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1855. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1856. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1857. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1858. beiscsi_log(phba, KERN_ERR,
  1859. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1860. "BM_%d : Event %s[%d] received on CID : %d\n",
  1861. cqe_desc[code], code, cid);
  1862. if (beiscsi_conn)
  1863. iscsi_conn_failure(beiscsi_conn->conn,
  1864. ISCSI_ERR_CONN_FAILED);
  1865. break;
  1866. default:
  1867. beiscsi_log(phba, KERN_ERR,
  1868. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1869. "BM_%d : Invalid CQE Event Received Code : %d"
  1870. "CID 0x%x...\n",
  1871. code, cid);
  1872. break;
  1873. }
  1874. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1875. queue_tail_inc(cq);
  1876. sol = queue_tail_node(cq);
  1877. num_processed++;
  1878. }
  1879. if (num_processed > 0) {
  1880. tot_nump += num_processed;
  1881. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1882. }
  1883. return tot_nump;
  1884. }
  1885. void beiscsi_process_all_cqs(struct work_struct *work)
  1886. {
  1887. unsigned long flags;
  1888. struct hwi_controller *phwi_ctrlr;
  1889. struct hwi_context_memory *phwi_context;
  1890. struct beiscsi_hba *phba;
  1891. struct be_eq_obj *pbe_eq =
  1892. container_of(work, struct be_eq_obj, work_cqs);
  1893. phba = pbe_eq->phba;
  1894. phwi_ctrlr = phba->phwi_ctrlr;
  1895. phwi_context = phwi_ctrlr->phwi_ctxt;
  1896. if (pbe_eq->todo_mcc_cq) {
  1897. spin_lock_irqsave(&phba->isr_lock, flags);
  1898. pbe_eq->todo_mcc_cq = false;
  1899. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1900. beiscsi_process_mcc_isr(phba);
  1901. }
  1902. if (pbe_eq->todo_cq) {
  1903. spin_lock_irqsave(&phba->isr_lock, flags);
  1904. pbe_eq->todo_cq = false;
  1905. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1906. beiscsi_process_cq(pbe_eq);
  1907. }
  1908. /* rearm EQ for further interrupts */
  1909. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1910. }
  1911. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1912. {
  1913. static unsigned int ret;
  1914. struct beiscsi_hba *phba;
  1915. struct be_eq_obj *pbe_eq;
  1916. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1917. ret = beiscsi_process_cq(pbe_eq);
  1918. if (ret < budget) {
  1919. phba = pbe_eq->phba;
  1920. blk_iopoll_complete(iop);
  1921. beiscsi_log(phba, KERN_INFO,
  1922. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1923. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1924. pbe_eq->q.id);
  1925. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1926. }
  1927. return ret;
  1928. }
  1929. static void
  1930. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1931. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1932. {
  1933. struct iscsi_sge *psgl;
  1934. unsigned int sg_len, index;
  1935. unsigned int sge_len = 0;
  1936. unsigned long long addr;
  1937. struct scatterlist *l_sg;
  1938. unsigned int offset;
  1939. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  1940. io_task->bhs_pa.u.a32.address_lo);
  1941. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  1942. io_task->bhs_pa.u.a32.address_hi);
  1943. l_sg = sg;
  1944. for (index = 0; (index < num_sg) && (index < 2); index++,
  1945. sg = sg_next(sg)) {
  1946. if (index == 0) {
  1947. sg_len = sg_dma_len(sg);
  1948. addr = (u64) sg_dma_address(sg);
  1949. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  1950. ((u32)(addr & 0xFFFFFFFF)));
  1951. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  1952. ((u32)(addr >> 32)));
  1953. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  1954. sg_len);
  1955. sge_len = sg_len;
  1956. } else {
  1957. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  1958. pwrb, sge_len);
  1959. sg_len = sg_dma_len(sg);
  1960. addr = (u64) sg_dma_address(sg);
  1961. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  1962. ((u32)(addr & 0xFFFFFFFF)));
  1963. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  1964. ((u32)(addr >> 32)));
  1965. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  1966. sg_len);
  1967. }
  1968. }
  1969. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  1970. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  1971. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  1972. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  1973. io_task->bhs_pa.u.a32.address_hi);
  1974. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  1975. io_task->bhs_pa.u.a32.address_lo);
  1976. if (num_sg == 1) {
  1977. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1978. 1);
  1979. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1980. 0);
  1981. } else if (num_sg == 2) {
  1982. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1983. 0);
  1984. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1985. 1);
  1986. } else {
  1987. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  1988. 0);
  1989. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  1990. 0);
  1991. }
  1992. sg = l_sg;
  1993. psgl++;
  1994. psgl++;
  1995. offset = 0;
  1996. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  1997. sg_len = sg_dma_len(sg);
  1998. addr = (u64) sg_dma_address(sg);
  1999. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2000. (addr & 0xFFFFFFFF));
  2001. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2002. (addr >> 32));
  2003. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2004. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2005. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2006. offset += sg_len;
  2007. }
  2008. psgl--;
  2009. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2010. }
  2011. /**
  2012. * hwi_write_buffer()- Populate the WRB with task info
  2013. * @pwrb: ptr to the WRB entry
  2014. * @task: iscsi task which is to be executed
  2015. **/
  2016. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2017. {
  2018. struct iscsi_sge *psgl;
  2019. struct beiscsi_io_task *io_task = task->dd_data;
  2020. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2021. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2022. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2023. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2024. io_task->bhs_pa.u.a32.address_lo);
  2025. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2026. io_task->bhs_pa.u.a32.address_hi);
  2027. if (task->data) {
  2028. if (task->data_count) {
  2029. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  2030. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2031. task->data,
  2032. task->data_count,
  2033. PCI_DMA_TODEVICE);
  2034. io_task->mtask_data_count = task->data_count;
  2035. } else {
  2036. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2037. io_task->mtask_addr = 0;
  2038. }
  2039. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2040. lower_32_bits(io_task->mtask_addr));
  2041. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2042. upper_32_bits(io_task->mtask_addr));
  2043. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2044. task->data_count);
  2045. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2046. } else {
  2047. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2048. io_task->mtask_addr = 0;
  2049. }
  2050. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2051. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2052. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2053. io_task->bhs_pa.u.a32.address_hi);
  2054. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2055. io_task->bhs_pa.u.a32.address_lo);
  2056. if (task->data) {
  2057. psgl++;
  2058. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2059. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2060. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2061. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2062. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2063. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2064. psgl++;
  2065. if (task->data) {
  2066. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2067. lower_32_bits(io_task->mtask_addr));
  2068. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2069. upper_32_bits(io_task->mtask_addr));
  2070. }
  2071. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2072. }
  2073. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2074. }
  2075. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2076. {
  2077. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2078. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2079. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2080. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2081. sizeof(struct sol_cqe));
  2082. num_async_pdu_buf_pages =
  2083. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2084. phba->params.defpdu_hdr_sz);
  2085. num_async_pdu_buf_sgl_pages =
  2086. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2087. sizeof(struct phys_addr));
  2088. num_async_pdu_data_pages =
  2089. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2090. phba->params.defpdu_data_sz);
  2091. num_async_pdu_data_sgl_pages =
  2092. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2093. sizeof(struct phys_addr));
  2094. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2095. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2096. BE_ISCSI_PDU_HEADER_SIZE;
  2097. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2098. sizeof(struct hwi_context_memory);
  2099. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2100. * (phba->params.wrbs_per_cxn)
  2101. * phba->params.cxns_per_ctrl;
  2102. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2103. (phba->params.wrbs_per_cxn);
  2104. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2105. phba->params.cxns_per_ctrl);
  2106. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2107. phba->params.icds_per_ctrl;
  2108. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2109. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2110. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2111. num_async_pdu_buf_pages * PAGE_SIZE;
  2112. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2113. num_async_pdu_data_pages * PAGE_SIZE;
  2114. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2115. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2116. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2117. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2118. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2119. phba->params.asyncpdus_per_ctrl *
  2120. sizeof(struct async_pdu_handle);
  2121. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2122. phba->params.asyncpdus_per_ctrl *
  2123. sizeof(struct async_pdu_handle);
  2124. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2125. sizeof(struct hwi_async_pdu_context) +
  2126. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2127. }
  2128. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2129. {
  2130. struct be_mem_descriptor *mem_descr;
  2131. dma_addr_t bus_add;
  2132. struct mem_array *mem_arr, *mem_arr_orig;
  2133. unsigned int i, j, alloc_size, curr_alloc_size;
  2134. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2135. if (!phba->phwi_ctrlr)
  2136. return -ENOMEM;
  2137. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2138. GFP_KERNEL);
  2139. if (!phba->init_mem) {
  2140. kfree(phba->phwi_ctrlr);
  2141. return -ENOMEM;
  2142. }
  2143. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2144. GFP_KERNEL);
  2145. if (!mem_arr_orig) {
  2146. kfree(phba->init_mem);
  2147. kfree(phba->phwi_ctrlr);
  2148. return -ENOMEM;
  2149. }
  2150. mem_descr = phba->init_mem;
  2151. for (i = 0; i < SE_MEM_MAX; i++) {
  2152. j = 0;
  2153. mem_arr = mem_arr_orig;
  2154. alloc_size = phba->mem_req[i];
  2155. memset(mem_arr, 0, sizeof(struct mem_array) *
  2156. BEISCSI_MAX_FRAGS_INIT);
  2157. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2158. do {
  2159. mem_arr->virtual_address = pci_alloc_consistent(
  2160. phba->pcidev,
  2161. curr_alloc_size,
  2162. &bus_add);
  2163. if (!mem_arr->virtual_address) {
  2164. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2165. goto free_mem;
  2166. if (curr_alloc_size -
  2167. rounddown_pow_of_two(curr_alloc_size))
  2168. curr_alloc_size = rounddown_pow_of_two
  2169. (curr_alloc_size);
  2170. else
  2171. curr_alloc_size = curr_alloc_size / 2;
  2172. } else {
  2173. mem_arr->bus_address.u.
  2174. a64.address = (__u64) bus_add;
  2175. mem_arr->size = curr_alloc_size;
  2176. alloc_size -= curr_alloc_size;
  2177. curr_alloc_size = min(be_max_phys_size *
  2178. 1024, alloc_size);
  2179. j++;
  2180. mem_arr++;
  2181. }
  2182. } while (alloc_size);
  2183. mem_descr->num_elements = j;
  2184. mem_descr->size_in_bytes = phba->mem_req[i];
  2185. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2186. GFP_KERNEL);
  2187. if (!mem_descr->mem_array)
  2188. goto free_mem;
  2189. memcpy(mem_descr->mem_array, mem_arr_orig,
  2190. sizeof(struct mem_array) * j);
  2191. mem_descr++;
  2192. }
  2193. kfree(mem_arr_orig);
  2194. return 0;
  2195. free_mem:
  2196. mem_descr->num_elements = j;
  2197. while ((i) || (j)) {
  2198. for (j = mem_descr->num_elements; j > 0; j--) {
  2199. pci_free_consistent(phba->pcidev,
  2200. mem_descr->mem_array[j - 1].size,
  2201. mem_descr->mem_array[j - 1].
  2202. virtual_address,
  2203. (unsigned long)mem_descr->
  2204. mem_array[j - 1].
  2205. bus_address.u.a64.address);
  2206. }
  2207. if (i) {
  2208. i--;
  2209. kfree(mem_descr->mem_array);
  2210. mem_descr--;
  2211. }
  2212. }
  2213. kfree(mem_arr_orig);
  2214. kfree(phba->init_mem);
  2215. kfree(phba->phwi_ctrlr);
  2216. return -ENOMEM;
  2217. }
  2218. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2219. {
  2220. beiscsi_find_mem_req(phba);
  2221. return beiscsi_alloc_mem(phba);
  2222. }
  2223. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2224. {
  2225. struct pdu_data_out *pdata_out;
  2226. struct pdu_nop_out *pnop_out;
  2227. struct be_mem_descriptor *mem_descr;
  2228. mem_descr = phba->init_mem;
  2229. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2230. pdata_out =
  2231. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2232. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2233. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2234. IIOC_SCSI_DATA);
  2235. pnop_out =
  2236. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2237. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2238. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2239. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2240. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2241. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2242. }
  2243. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2244. {
  2245. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2246. struct wrb_handle *pwrb_handle = NULL;
  2247. struct hwi_controller *phwi_ctrlr;
  2248. struct hwi_wrb_context *pwrb_context;
  2249. struct iscsi_wrb *pwrb = NULL;
  2250. unsigned int num_cxn_wrbh = 0;
  2251. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2252. mem_descr_wrbh = phba->init_mem;
  2253. mem_descr_wrbh += HWI_MEM_WRBH;
  2254. mem_descr_wrb = phba->init_mem;
  2255. mem_descr_wrb += HWI_MEM_WRB;
  2256. phwi_ctrlr = phba->phwi_ctrlr;
  2257. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2258. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2259. pwrb_context->pwrb_handle_base =
  2260. kzalloc(sizeof(struct wrb_handle *) *
  2261. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2262. if (!pwrb_context->pwrb_handle_base) {
  2263. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2264. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2265. goto init_wrb_hndl_failed;
  2266. }
  2267. pwrb_context->pwrb_handle_basestd =
  2268. kzalloc(sizeof(struct wrb_handle *) *
  2269. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2270. if (!pwrb_context->pwrb_handle_basestd) {
  2271. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2272. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2273. goto init_wrb_hndl_failed;
  2274. }
  2275. if (!num_cxn_wrbh) {
  2276. pwrb_handle =
  2277. mem_descr_wrbh->mem_array[idx].virtual_address;
  2278. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2279. ((sizeof(struct wrb_handle)) *
  2280. phba->params.wrbs_per_cxn));
  2281. idx++;
  2282. }
  2283. pwrb_context->alloc_index = 0;
  2284. pwrb_context->wrb_handles_available = 0;
  2285. pwrb_context->free_index = 0;
  2286. if (num_cxn_wrbh) {
  2287. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2288. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2289. pwrb_context->pwrb_handle_basestd[j] =
  2290. pwrb_handle;
  2291. pwrb_context->wrb_handles_available++;
  2292. pwrb_handle->wrb_index = j;
  2293. pwrb_handle++;
  2294. }
  2295. num_cxn_wrbh--;
  2296. }
  2297. }
  2298. idx = 0;
  2299. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2300. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2301. if (!num_cxn_wrb) {
  2302. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2303. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2304. ((sizeof(struct iscsi_wrb) *
  2305. phba->params.wrbs_per_cxn));
  2306. idx++;
  2307. }
  2308. if (num_cxn_wrb) {
  2309. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2310. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2311. pwrb_handle->pwrb = pwrb;
  2312. pwrb++;
  2313. }
  2314. num_cxn_wrb--;
  2315. }
  2316. }
  2317. return 0;
  2318. init_wrb_hndl_failed:
  2319. for (j = index; j > 0; j--) {
  2320. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2321. kfree(pwrb_context->pwrb_handle_base);
  2322. kfree(pwrb_context->pwrb_handle_basestd);
  2323. }
  2324. return -ENOMEM;
  2325. }
  2326. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2327. {
  2328. struct hwi_controller *phwi_ctrlr;
  2329. struct hba_parameters *p = &phba->params;
  2330. struct hwi_async_pdu_context *pasync_ctx;
  2331. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2332. unsigned int index, idx, num_per_mem, num_async_data;
  2333. struct be_mem_descriptor *mem_descr;
  2334. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2335. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2336. phwi_ctrlr = phba->phwi_ctrlr;
  2337. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2338. mem_descr->mem_array[0].virtual_address;
  2339. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2340. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2341. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2342. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2343. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2344. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2345. if (mem_descr->mem_array[0].virtual_address) {
  2346. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2347. "BM_%d : hwi_init_async_pdu_ctx"
  2348. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2349. mem_descr->mem_array[0].virtual_address);
  2350. } else
  2351. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2352. "BM_%d : No Virtual address\n");
  2353. pasync_ctx->async_header.va_base =
  2354. mem_descr->mem_array[0].virtual_address;
  2355. pasync_ctx->async_header.pa_base.u.a64.address =
  2356. mem_descr->mem_array[0].bus_address.u.a64.address;
  2357. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2358. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2359. if (mem_descr->mem_array[0].virtual_address) {
  2360. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2361. "BM_%d : hwi_init_async_pdu_ctx"
  2362. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2363. mem_descr->mem_array[0].virtual_address);
  2364. } else
  2365. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2366. "BM_%d : No Virtual address\n");
  2367. pasync_ctx->async_header.ring_base =
  2368. mem_descr->mem_array[0].virtual_address;
  2369. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2370. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2371. if (mem_descr->mem_array[0].virtual_address) {
  2372. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2373. "BM_%d : hwi_init_async_pdu_ctx"
  2374. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2375. mem_descr->mem_array[0].virtual_address);
  2376. } else
  2377. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2378. "BM_%d : No Virtual address\n");
  2379. pasync_ctx->async_header.handle_base =
  2380. mem_descr->mem_array[0].virtual_address;
  2381. pasync_ctx->async_header.writables = 0;
  2382. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2383. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2384. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2385. if (mem_descr->mem_array[0].virtual_address) {
  2386. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2387. "BM_%d : hwi_init_async_pdu_ctx"
  2388. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2389. mem_descr->mem_array[0].virtual_address);
  2390. } else
  2391. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2392. "BM_%d : No Virtual address\n");
  2393. pasync_ctx->async_data.ring_base =
  2394. mem_descr->mem_array[0].virtual_address;
  2395. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2396. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2397. if (!mem_descr->mem_array[0].virtual_address)
  2398. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2399. "BM_%d : No Virtual address\n");
  2400. pasync_ctx->async_data.handle_base =
  2401. mem_descr->mem_array[0].virtual_address;
  2402. pasync_ctx->async_data.writables = 0;
  2403. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2404. pasync_header_h =
  2405. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2406. pasync_data_h =
  2407. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2408. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2409. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2410. if (mem_descr->mem_array[0].virtual_address) {
  2411. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2412. "BM_%d : hwi_init_async_pdu_ctx"
  2413. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2414. mem_descr->mem_array[0].virtual_address);
  2415. } else
  2416. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2417. "BM_%d : No Virtual address\n");
  2418. idx = 0;
  2419. pasync_ctx->async_data.va_base =
  2420. mem_descr->mem_array[idx].virtual_address;
  2421. pasync_ctx->async_data.pa_base.u.a64.address =
  2422. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2423. num_async_data = ((mem_descr->mem_array[idx].size) /
  2424. phba->params.defpdu_data_sz);
  2425. num_per_mem = 0;
  2426. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2427. pasync_header_h->cri = -1;
  2428. pasync_header_h->index = (char)index;
  2429. INIT_LIST_HEAD(&pasync_header_h->link);
  2430. pasync_header_h->pbuffer =
  2431. (void *)((unsigned long)
  2432. (pasync_ctx->async_header.va_base) +
  2433. (p->defpdu_hdr_sz * index));
  2434. pasync_header_h->pa.u.a64.address =
  2435. pasync_ctx->async_header.pa_base.u.a64.address +
  2436. (p->defpdu_hdr_sz * index);
  2437. list_add_tail(&pasync_header_h->link,
  2438. &pasync_ctx->async_header.free_list);
  2439. pasync_header_h++;
  2440. pasync_ctx->async_header.free_entries++;
  2441. pasync_ctx->async_header.writables++;
  2442. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2443. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2444. header_busy_list);
  2445. pasync_data_h->cri = -1;
  2446. pasync_data_h->index = (char)index;
  2447. INIT_LIST_HEAD(&pasync_data_h->link);
  2448. if (!num_async_data) {
  2449. num_per_mem = 0;
  2450. idx++;
  2451. pasync_ctx->async_data.va_base =
  2452. mem_descr->mem_array[idx].virtual_address;
  2453. pasync_ctx->async_data.pa_base.u.a64.address =
  2454. mem_descr->mem_array[idx].
  2455. bus_address.u.a64.address;
  2456. num_async_data = ((mem_descr->mem_array[idx].size) /
  2457. phba->params.defpdu_data_sz);
  2458. }
  2459. pasync_data_h->pbuffer =
  2460. (void *)((unsigned long)
  2461. (pasync_ctx->async_data.va_base) +
  2462. (p->defpdu_data_sz * num_per_mem));
  2463. pasync_data_h->pa.u.a64.address =
  2464. pasync_ctx->async_data.pa_base.u.a64.address +
  2465. (p->defpdu_data_sz * num_per_mem);
  2466. num_per_mem++;
  2467. num_async_data--;
  2468. list_add_tail(&pasync_data_h->link,
  2469. &pasync_ctx->async_data.free_list);
  2470. pasync_data_h++;
  2471. pasync_ctx->async_data.free_entries++;
  2472. pasync_ctx->async_data.writables++;
  2473. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2474. }
  2475. pasync_ctx->async_header.host_write_ptr = 0;
  2476. pasync_ctx->async_header.ep_read_ptr = -1;
  2477. pasync_ctx->async_data.host_write_ptr = 0;
  2478. pasync_ctx->async_data.ep_read_ptr = -1;
  2479. }
  2480. static int
  2481. be_sgl_create_contiguous(void *virtual_address,
  2482. u64 physical_address, u32 length,
  2483. struct be_dma_mem *sgl)
  2484. {
  2485. WARN_ON(!virtual_address);
  2486. WARN_ON(!physical_address);
  2487. WARN_ON(!length > 0);
  2488. WARN_ON(!sgl);
  2489. sgl->va = virtual_address;
  2490. sgl->dma = (unsigned long)physical_address;
  2491. sgl->size = length;
  2492. return 0;
  2493. }
  2494. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2495. {
  2496. memset(sgl, 0, sizeof(*sgl));
  2497. }
  2498. static void
  2499. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2500. struct mem_array *pmem, struct be_dma_mem *sgl)
  2501. {
  2502. if (sgl->va)
  2503. be_sgl_destroy_contiguous(sgl);
  2504. be_sgl_create_contiguous(pmem->virtual_address,
  2505. pmem->bus_address.u.a64.address,
  2506. pmem->size, sgl);
  2507. }
  2508. static void
  2509. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2510. struct mem_array *pmem, struct be_dma_mem *sgl)
  2511. {
  2512. if (sgl->va)
  2513. be_sgl_destroy_contiguous(sgl);
  2514. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2515. pmem->bus_address.u.a64.address,
  2516. pmem->size, sgl);
  2517. }
  2518. static int be_fill_queue(struct be_queue_info *q,
  2519. u16 len, u16 entry_size, void *vaddress)
  2520. {
  2521. struct be_dma_mem *mem = &q->dma_mem;
  2522. memset(q, 0, sizeof(*q));
  2523. q->len = len;
  2524. q->entry_size = entry_size;
  2525. mem->size = len * entry_size;
  2526. mem->va = vaddress;
  2527. if (!mem->va)
  2528. return -ENOMEM;
  2529. memset(mem->va, 0, mem->size);
  2530. return 0;
  2531. }
  2532. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2533. struct hwi_context_memory *phwi_context)
  2534. {
  2535. unsigned int i, num_eq_pages;
  2536. int ret = 0, eq_for_mcc;
  2537. struct be_queue_info *eq;
  2538. struct be_dma_mem *mem;
  2539. void *eq_vaddress;
  2540. dma_addr_t paddr;
  2541. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2542. sizeof(struct be_eq_entry));
  2543. if (phba->msix_enabled)
  2544. eq_for_mcc = 1;
  2545. else
  2546. eq_for_mcc = 0;
  2547. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2548. eq = &phwi_context->be_eq[i].q;
  2549. mem = &eq->dma_mem;
  2550. phwi_context->be_eq[i].phba = phba;
  2551. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2552. num_eq_pages * PAGE_SIZE,
  2553. &paddr);
  2554. if (!eq_vaddress)
  2555. goto create_eq_error;
  2556. mem->va = eq_vaddress;
  2557. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2558. sizeof(struct be_eq_entry), eq_vaddress);
  2559. if (ret) {
  2560. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2561. "BM_%d : be_fill_queue Failed for EQ\n");
  2562. goto create_eq_error;
  2563. }
  2564. mem->dma = paddr;
  2565. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2566. phwi_context->cur_eqd);
  2567. if (ret) {
  2568. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2569. "BM_%d : beiscsi_cmd_eq_create"
  2570. "Failed for EQ\n");
  2571. goto create_eq_error;
  2572. }
  2573. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2574. "BM_%d : eqid = %d\n",
  2575. phwi_context->be_eq[i].q.id);
  2576. }
  2577. return 0;
  2578. create_eq_error:
  2579. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2580. eq = &phwi_context->be_eq[i].q;
  2581. mem = &eq->dma_mem;
  2582. if (mem->va)
  2583. pci_free_consistent(phba->pcidev, num_eq_pages
  2584. * PAGE_SIZE,
  2585. mem->va, mem->dma);
  2586. }
  2587. return ret;
  2588. }
  2589. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2590. struct hwi_context_memory *phwi_context)
  2591. {
  2592. unsigned int i, num_cq_pages;
  2593. int ret = 0;
  2594. struct be_queue_info *cq, *eq;
  2595. struct be_dma_mem *mem;
  2596. struct be_eq_obj *pbe_eq;
  2597. void *cq_vaddress;
  2598. dma_addr_t paddr;
  2599. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2600. sizeof(struct sol_cqe));
  2601. for (i = 0; i < phba->num_cpus; i++) {
  2602. cq = &phwi_context->be_cq[i];
  2603. eq = &phwi_context->be_eq[i].q;
  2604. pbe_eq = &phwi_context->be_eq[i];
  2605. pbe_eq->cq = cq;
  2606. pbe_eq->phba = phba;
  2607. mem = &cq->dma_mem;
  2608. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2609. num_cq_pages * PAGE_SIZE,
  2610. &paddr);
  2611. if (!cq_vaddress)
  2612. goto create_cq_error;
  2613. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2614. sizeof(struct sol_cqe), cq_vaddress);
  2615. if (ret) {
  2616. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2617. "BM_%d : be_fill_queue Failed "
  2618. "for ISCSI CQ\n");
  2619. goto create_cq_error;
  2620. }
  2621. mem->dma = paddr;
  2622. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2623. false, 0);
  2624. if (ret) {
  2625. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2626. "BM_%d : beiscsi_cmd_eq_create"
  2627. "Failed for ISCSI CQ\n");
  2628. goto create_cq_error;
  2629. }
  2630. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2631. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2632. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2633. }
  2634. return 0;
  2635. create_cq_error:
  2636. for (i = 0; i < phba->num_cpus; i++) {
  2637. cq = &phwi_context->be_cq[i];
  2638. mem = &cq->dma_mem;
  2639. if (mem->va)
  2640. pci_free_consistent(phba->pcidev, num_cq_pages
  2641. * PAGE_SIZE,
  2642. mem->va, mem->dma);
  2643. }
  2644. return ret;
  2645. }
  2646. static int
  2647. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2648. struct hwi_context_memory *phwi_context,
  2649. struct hwi_controller *phwi_ctrlr,
  2650. unsigned int def_pdu_ring_sz)
  2651. {
  2652. unsigned int idx;
  2653. int ret;
  2654. struct be_queue_info *dq, *cq;
  2655. struct be_dma_mem *mem;
  2656. struct be_mem_descriptor *mem_descr;
  2657. void *dq_vaddress;
  2658. idx = 0;
  2659. dq = &phwi_context->be_def_hdrq;
  2660. cq = &phwi_context->be_cq[0];
  2661. mem = &dq->dma_mem;
  2662. mem_descr = phba->init_mem;
  2663. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2664. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2665. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2666. sizeof(struct phys_addr),
  2667. sizeof(struct phys_addr), dq_vaddress);
  2668. if (ret) {
  2669. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2670. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2671. return ret;
  2672. }
  2673. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2674. bus_address.u.a64.address;
  2675. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2676. def_pdu_ring_sz,
  2677. phba->params.defpdu_hdr_sz);
  2678. if (ret) {
  2679. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2680. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2681. return ret;
  2682. }
  2683. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2684. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2685. "BM_%d : iscsi def pdu id is %d\n",
  2686. phwi_context->be_def_hdrq.id);
  2687. hwi_post_async_buffers(phba, 1);
  2688. return 0;
  2689. }
  2690. static int
  2691. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2692. struct hwi_context_memory *phwi_context,
  2693. struct hwi_controller *phwi_ctrlr,
  2694. unsigned int def_pdu_ring_sz)
  2695. {
  2696. unsigned int idx;
  2697. int ret;
  2698. struct be_queue_info *dataq, *cq;
  2699. struct be_dma_mem *mem;
  2700. struct be_mem_descriptor *mem_descr;
  2701. void *dq_vaddress;
  2702. idx = 0;
  2703. dataq = &phwi_context->be_def_dataq;
  2704. cq = &phwi_context->be_cq[0];
  2705. mem = &dataq->dma_mem;
  2706. mem_descr = phba->init_mem;
  2707. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2708. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2709. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2710. sizeof(struct phys_addr),
  2711. sizeof(struct phys_addr), dq_vaddress);
  2712. if (ret) {
  2713. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2714. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2715. return ret;
  2716. }
  2717. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2718. bus_address.u.a64.address;
  2719. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2720. def_pdu_ring_sz,
  2721. phba->params.defpdu_data_sz);
  2722. if (ret) {
  2723. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2724. "BM_%d be_cmd_create_default_pdu_queue"
  2725. " Failed for DEF PDU DATA\n");
  2726. return ret;
  2727. }
  2728. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2729. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2730. "BM_%d : iscsi def data id is %d\n",
  2731. phwi_context->be_def_dataq.id);
  2732. hwi_post_async_buffers(phba, 0);
  2733. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2734. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2735. return 0;
  2736. }
  2737. static int
  2738. beiscsi_post_pages(struct beiscsi_hba *phba)
  2739. {
  2740. struct be_mem_descriptor *mem_descr;
  2741. struct mem_array *pm_arr;
  2742. unsigned int page_offset, i;
  2743. struct be_dma_mem sgl;
  2744. int status;
  2745. mem_descr = phba->init_mem;
  2746. mem_descr += HWI_MEM_SGE;
  2747. pm_arr = mem_descr->mem_array;
  2748. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2749. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2750. for (i = 0; i < mem_descr->num_elements; i++) {
  2751. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2752. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2753. page_offset,
  2754. (pm_arr->size / PAGE_SIZE));
  2755. page_offset += pm_arr->size / PAGE_SIZE;
  2756. if (status != 0) {
  2757. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2758. "BM_%d : post sgl failed.\n");
  2759. return status;
  2760. }
  2761. pm_arr++;
  2762. }
  2763. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2764. "BM_%d : POSTED PAGES\n");
  2765. return 0;
  2766. }
  2767. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2768. {
  2769. struct be_dma_mem *mem = &q->dma_mem;
  2770. if (mem->va) {
  2771. pci_free_consistent(phba->pcidev, mem->size,
  2772. mem->va, mem->dma);
  2773. mem->va = NULL;
  2774. }
  2775. }
  2776. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2777. u16 len, u16 entry_size)
  2778. {
  2779. struct be_dma_mem *mem = &q->dma_mem;
  2780. memset(q, 0, sizeof(*q));
  2781. q->len = len;
  2782. q->entry_size = entry_size;
  2783. mem->size = len * entry_size;
  2784. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2785. if (!mem->va)
  2786. return -ENOMEM;
  2787. memset(mem->va, 0, mem->size);
  2788. return 0;
  2789. }
  2790. static int
  2791. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2792. struct hwi_context_memory *phwi_context,
  2793. struct hwi_controller *phwi_ctrlr)
  2794. {
  2795. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2796. u64 pa_addr_lo;
  2797. unsigned int idx, num, i;
  2798. struct mem_array *pwrb_arr;
  2799. void *wrb_vaddr;
  2800. struct be_dma_mem sgl;
  2801. struct be_mem_descriptor *mem_descr;
  2802. int status;
  2803. idx = 0;
  2804. mem_descr = phba->init_mem;
  2805. mem_descr += HWI_MEM_WRB;
  2806. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2807. GFP_KERNEL);
  2808. if (!pwrb_arr) {
  2809. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2810. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2811. return -ENOMEM;
  2812. }
  2813. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2814. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2815. num_wrb_rings = mem_descr->mem_array[idx].size /
  2816. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2817. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2818. if (num_wrb_rings) {
  2819. pwrb_arr[num].virtual_address = wrb_vaddr;
  2820. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2821. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2822. sizeof(struct iscsi_wrb);
  2823. wrb_vaddr += pwrb_arr[num].size;
  2824. pa_addr_lo += pwrb_arr[num].size;
  2825. num_wrb_rings--;
  2826. } else {
  2827. idx++;
  2828. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2829. pa_addr_lo = mem_descr->mem_array[idx].\
  2830. bus_address.u.a64.address;
  2831. num_wrb_rings = mem_descr->mem_array[idx].size /
  2832. (phba->params.wrbs_per_cxn *
  2833. sizeof(struct iscsi_wrb));
  2834. pwrb_arr[num].virtual_address = wrb_vaddr;
  2835. pwrb_arr[num].bus_address.u.a64.address\
  2836. = pa_addr_lo;
  2837. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2838. sizeof(struct iscsi_wrb);
  2839. wrb_vaddr += pwrb_arr[num].size;
  2840. pa_addr_lo += pwrb_arr[num].size;
  2841. num_wrb_rings--;
  2842. }
  2843. }
  2844. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2845. wrb_mem_index = 0;
  2846. offset = 0;
  2847. size = 0;
  2848. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2849. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2850. &phwi_context->be_wrbq[i]);
  2851. if (status != 0) {
  2852. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2853. "BM_%d : wrbq create failed.");
  2854. kfree(pwrb_arr);
  2855. return status;
  2856. }
  2857. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  2858. id;
  2859. }
  2860. kfree(pwrb_arr);
  2861. return 0;
  2862. }
  2863. static void free_wrb_handles(struct beiscsi_hba *phba)
  2864. {
  2865. unsigned int index;
  2866. struct hwi_controller *phwi_ctrlr;
  2867. struct hwi_wrb_context *pwrb_context;
  2868. phwi_ctrlr = phba->phwi_ctrlr;
  2869. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2870. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2871. kfree(pwrb_context->pwrb_handle_base);
  2872. kfree(pwrb_context->pwrb_handle_basestd);
  2873. }
  2874. }
  2875. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  2876. {
  2877. struct be_queue_info *q;
  2878. struct be_ctrl_info *ctrl = &phba->ctrl;
  2879. q = &phba->ctrl.mcc_obj.q;
  2880. if (q->created)
  2881. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  2882. be_queue_free(phba, q);
  2883. q = &phba->ctrl.mcc_obj.cq;
  2884. if (q->created)
  2885. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2886. be_queue_free(phba, q);
  2887. }
  2888. static void hwi_cleanup(struct beiscsi_hba *phba)
  2889. {
  2890. struct be_queue_info *q;
  2891. struct be_ctrl_info *ctrl = &phba->ctrl;
  2892. struct hwi_controller *phwi_ctrlr;
  2893. struct hwi_context_memory *phwi_context;
  2894. int i, eq_num;
  2895. phwi_ctrlr = phba->phwi_ctrlr;
  2896. phwi_context = phwi_ctrlr->phwi_ctxt;
  2897. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2898. q = &phwi_context->be_wrbq[i];
  2899. if (q->created)
  2900. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  2901. }
  2902. free_wrb_handles(phba);
  2903. q = &phwi_context->be_def_hdrq;
  2904. if (q->created)
  2905. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2906. q = &phwi_context->be_def_dataq;
  2907. if (q->created)
  2908. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  2909. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  2910. for (i = 0; i < (phba->num_cpus); i++) {
  2911. q = &phwi_context->be_cq[i];
  2912. if (q->created)
  2913. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  2914. }
  2915. if (phba->msix_enabled)
  2916. eq_num = 1;
  2917. else
  2918. eq_num = 0;
  2919. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  2920. q = &phwi_context->be_eq[i].q;
  2921. if (q->created)
  2922. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  2923. }
  2924. be_mcc_queues_destroy(phba);
  2925. }
  2926. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  2927. struct hwi_context_memory *phwi_context)
  2928. {
  2929. struct be_queue_info *q, *cq;
  2930. struct be_ctrl_info *ctrl = &phba->ctrl;
  2931. /* Alloc MCC compl queue */
  2932. cq = &phba->ctrl.mcc_obj.cq;
  2933. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  2934. sizeof(struct be_mcc_compl)))
  2935. goto err;
  2936. /* Ask BE to create MCC compl queue; */
  2937. if (phba->msix_enabled) {
  2938. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  2939. [phba->num_cpus].q, false, true, 0))
  2940. goto mcc_cq_free;
  2941. } else {
  2942. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  2943. false, true, 0))
  2944. goto mcc_cq_free;
  2945. }
  2946. /* Alloc MCC queue */
  2947. q = &phba->ctrl.mcc_obj.q;
  2948. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  2949. goto mcc_cq_destroy;
  2950. /* Ask BE to create MCC queue */
  2951. if (beiscsi_cmd_mccq_create(phba, q, cq))
  2952. goto mcc_q_free;
  2953. return 0;
  2954. mcc_q_free:
  2955. be_queue_free(phba, q);
  2956. mcc_cq_destroy:
  2957. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  2958. mcc_cq_free:
  2959. be_queue_free(phba, cq);
  2960. err:
  2961. return -ENOMEM;
  2962. }
  2963. /**
  2964. * find_num_cpus()- Get the CPU online count
  2965. * @phba: ptr to priv structure
  2966. *
  2967. * CPU count is used for creating EQ.
  2968. **/
  2969. static void find_num_cpus(struct beiscsi_hba *phba)
  2970. {
  2971. int num_cpus = 0;
  2972. num_cpus = num_online_cpus();
  2973. phba->num_cpus = (num_cpus >= BEISCSI_MAX_NUM_CPU) ?
  2974. (BEISCSI_MAX_NUM_CPU - 1) : num_cpus;
  2975. }
  2976. static int hwi_init_port(struct beiscsi_hba *phba)
  2977. {
  2978. struct hwi_controller *phwi_ctrlr;
  2979. struct hwi_context_memory *phwi_context;
  2980. unsigned int def_pdu_ring_sz;
  2981. struct be_ctrl_info *ctrl = &phba->ctrl;
  2982. int status;
  2983. def_pdu_ring_sz =
  2984. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  2985. phwi_ctrlr = phba->phwi_ctrlr;
  2986. phwi_context = phwi_ctrlr->phwi_ctxt;
  2987. phwi_context->max_eqd = 0;
  2988. phwi_context->min_eqd = 0;
  2989. phwi_context->cur_eqd = 64;
  2990. be_cmd_fw_initialize(&phba->ctrl);
  2991. status = beiscsi_create_eqs(phba, phwi_context);
  2992. if (status != 0) {
  2993. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2994. "BM_%d : EQ not created\n");
  2995. goto error;
  2996. }
  2997. status = be_mcc_queues_create(phba, phwi_context);
  2998. if (status != 0)
  2999. goto error;
  3000. status = mgmt_check_supported_fw(ctrl, phba);
  3001. if (status != 0) {
  3002. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3003. "BM_%d : Unsupported fw version\n");
  3004. goto error;
  3005. }
  3006. status = beiscsi_create_cqs(phba, phwi_context);
  3007. if (status != 0) {
  3008. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3009. "BM_%d : CQ not created\n");
  3010. goto error;
  3011. }
  3012. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3013. def_pdu_ring_sz);
  3014. if (status != 0) {
  3015. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3016. "BM_%d : Default Header not created\n");
  3017. goto error;
  3018. }
  3019. status = beiscsi_create_def_data(phba, phwi_context,
  3020. phwi_ctrlr, def_pdu_ring_sz);
  3021. if (status != 0) {
  3022. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3023. "BM_%d : Default Data not created\n");
  3024. goto error;
  3025. }
  3026. status = beiscsi_post_pages(phba);
  3027. if (status != 0) {
  3028. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3029. "BM_%d : Post SGL Pages Failed\n");
  3030. goto error;
  3031. }
  3032. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3033. if (status != 0) {
  3034. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3035. "BM_%d : WRB Rings not created\n");
  3036. goto error;
  3037. }
  3038. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3039. "BM_%d : hwi_init_port success\n");
  3040. return 0;
  3041. error:
  3042. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3043. "BM_%d : hwi_init_port failed");
  3044. hwi_cleanup(phba);
  3045. return status;
  3046. }
  3047. static int hwi_init_controller(struct beiscsi_hba *phba)
  3048. {
  3049. struct hwi_controller *phwi_ctrlr;
  3050. phwi_ctrlr = phba->phwi_ctrlr;
  3051. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3052. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3053. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3054. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3055. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3056. phwi_ctrlr->phwi_ctxt);
  3057. } else {
  3058. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3059. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3060. "than one element.Failing to load\n");
  3061. return -ENOMEM;
  3062. }
  3063. iscsi_init_global_templates(phba);
  3064. if (beiscsi_init_wrb_handle(phba))
  3065. return -ENOMEM;
  3066. hwi_init_async_pdu_ctx(phba);
  3067. if (hwi_init_port(phba) != 0) {
  3068. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3069. "BM_%d : hwi_init_controller failed\n");
  3070. return -ENOMEM;
  3071. }
  3072. return 0;
  3073. }
  3074. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3075. {
  3076. struct be_mem_descriptor *mem_descr;
  3077. int i, j;
  3078. mem_descr = phba->init_mem;
  3079. i = 0;
  3080. j = 0;
  3081. for (i = 0; i < SE_MEM_MAX; i++) {
  3082. for (j = mem_descr->num_elements; j > 0; j--) {
  3083. pci_free_consistent(phba->pcidev,
  3084. mem_descr->mem_array[j - 1].size,
  3085. mem_descr->mem_array[j - 1].virtual_address,
  3086. (unsigned long)mem_descr->mem_array[j - 1].
  3087. bus_address.u.a64.address);
  3088. }
  3089. kfree(mem_descr->mem_array);
  3090. mem_descr++;
  3091. }
  3092. kfree(phba->init_mem);
  3093. kfree(phba->phwi_ctrlr);
  3094. }
  3095. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3096. {
  3097. int ret = -ENOMEM;
  3098. ret = beiscsi_get_memory(phba);
  3099. if (ret < 0) {
  3100. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3101. "BM_%d : beiscsi_dev_probe -"
  3102. "Failed in beiscsi_alloc_memory\n");
  3103. return ret;
  3104. }
  3105. ret = hwi_init_controller(phba);
  3106. if (ret)
  3107. goto free_init;
  3108. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3109. "BM_%d : Return success from beiscsi_init_controller");
  3110. return 0;
  3111. free_init:
  3112. beiscsi_free_mem(phba);
  3113. return ret;
  3114. }
  3115. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3116. {
  3117. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3118. struct sgl_handle *psgl_handle;
  3119. struct iscsi_sge *pfrag;
  3120. unsigned int arr_index, i, idx;
  3121. phba->io_sgl_hndl_avbl = 0;
  3122. phba->eh_sgl_hndl_avbl = 0;
  3123. mem_descr_sglh = phba->init_mem;
  3124. mem_descr_sglh += HWI_MEM_SGLH;
  3125. if (1 == mem_descr_sglh->num_elements) {
  3126. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3127. phba->params.ios_per_ctrl,
  3128. GFP_KERNEL);
  3129. if (!phba->io_sgl_hndl_base) {
  3130. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3131. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3132. return -ENOMEM;
  3133. }
  3134. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3135. (phba->params.icds_per_ctrl -
  3136. phba->params.ios_per_ctrl),
  3137. GFP_KERNEL);
  3138. if (!phba->eh_sgl_hndl_base) {
  3139. kfree(phba->io_sgl_hndl_base);
  3140. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3141. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3142. return -ENOMEM;
  3143. }
  3144. } else {
  3145. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3146. "BM_%d : HWI_MEM_SGLH is more than one element."
  3147. "Failing to load\n");
  3148. return -ENOMEM;
  3149. }
  3150. arr_index = 0;
  3151. idx = 0;
  3152. while (idx < mem_descr_sglh->num_elements) {
  3153. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3154. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3155. sizeof(struct sgl_handle)); i++) {
  3156. if (arr_index < phba->params.ios_per_ctrl) {
  3157. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3158. phba->io_sgl_hndl_avbl++;
  3159. arr_index++;
  3160. } else {
  3161. phba->eh_sgl_hndl_base[arr_index -
  3162. phba->params.ios_per_ctrl] =
  3163. psgl_handle;
  3164. arr_index++;
  3165. phba->eh_sgl_hndl_avbl++;
  3166. }
  3167. psgl_handle++;
  3168. }
  3169. idx++;
  3170. }
  3171. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3172. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3173. "phba->eh_sgl_hndl_avbl=%d\n",
  3174. phba->io_sgl_hndl_avbl,
  3175. phba->eh_sgl_hndl_avbl);
  3176. mem_descr_sg = phba->init_mem;
  3177. mem_descr_sg += HWI_MEM_SGE;
  3178. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3179. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3180. mem_descr_sg->num_elements);
  3181. arr_index = 0;
  3182. idx = 0;
  3183. while (idx < mem_descr_sg->num_elements) {
  3184. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3185. for (i = 0;
  3186. i < (mem_descr_sg->mem_array[idx].size) /
  3187. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3188. i++) {
  3189. if (arr_index < phba->params.ios_per_ctrl)
  3190. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3191. else
  3192. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3193. phba->params.ios_per_ctrl];
  3194. psgl_handle->pfrag = pfrag;
  3195. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3196. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3197. pfrag += phba->params.num_sge_per_io;
  3198. psgl_handle->sgl_index =
  3199. phba->fw_config.iscsi_icd_start + arr_index++;
  3200. }
  3201. idx++;
  3202. }
  3203. phba->io_sgl_free_index = 0;
  3204. phba->io_sgl_alloc_index = 0;
  3205. phba->eh_sgl_free_index = 0;
  3206. phba->eh_sgl_alloc_index = 0;
  3207. return 0;
  3208. }
  3209. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3210. {
  3211. int i, new_cid;
  3212. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3213. GFP_KERNEL);
  3214. if (!phba->cid_array) {
  3215. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3216. "BM_%d : Failed to allocate memory in "
  3217. "hba_setup_cid_tbls\n");
  3218. return -ENOMEM;
  3219. }
  3220. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3221. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3222. if (!phba->ep_array) {
  3223. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3224. "BM_%d : Failed to allocate memory in "
  3225. "hba_setup_cid_tbls\n");
  3226. kfree(phba->cid_array);
  3227. return -ENOMEM;
  3228. }
  3229. new_cid = phba->fw_config.iscsi_cid_start;
  3230. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3231. phba->cid_array[i] = new_cid;
  3232. new_cid += 2;
  3233. }
  3234. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3235. return 0;
  3236. }
  3237. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3238. {
  3239. struct be_ctrl_info *ctrl = &phba->ctrl;
  3240. struct hwi_controller *phwi_ctrlr;
  3241. struct hwi_context_memory *phwi_context;
  3242. struct be_queue_info *eq;
  3243. u8 __iomem *addr;
  3244. u32 reg, i;
  3245. u32 enabled;
  3246. phwi_ctrlr = phba->phwi_ctrlr;
  3247. phwi_context = phwi_ctrlr->phwi_ctxt;
  3248. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3249. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3250. reg = ioread32(addr);
  3251. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3252. if (!enabled) {
  3253. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3254. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3255. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3256. iowrite32(reg, addr);
  3257. }
  3258. if (!phba->msix_enabled) {
  3259. eq = &phwi_context->be_eq[0].q;
  3260. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3261. "BM_%d : eq->id=%d\n", eq->id);
  3262. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3263. } else {
  3264. for (i = 0; i <= phba->num_cpus; i++) {
  3265. eq = &phwi_context->be_eq[i].q;
  3266. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3267. "BM_%d : eq->id=%d\n", eq->id);
  3268. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3269. }
  3270. }
  3271. }
  3272. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3273. {
  3274. struct be_ctrl_info *ctrl = &phba->ctrl;
  3275. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3276. u32 reg = ioread32(addr);
  3277. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3278. if (enabled) {
  3279. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3280. iowrite32(reg, addr);
  3281. } else
  3282. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3283. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3284. }
  3285. /**
  3286. * beiscsi_get_boot_info()- Get the boot session info
  3287. * @phba: The device priv structure instance
  3288. *
  3289. * Get the boot target info and store in driver priv structure
  3290. *
  3291. * return values
  3292. * Success: 0
  3293. * Failure: Non-Zero Value
  3294. **/
  3295. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3296. {
  3297. struct be_cmd_get_session_resp *session_resp;
  3298. struct be_mcc_wrb *wrb;
  3299. struct be_dma_mem nonemb_cmd;
  3300. unsigned int tag, wrb_num;
  3301. unsigned short status, extd_status;
  3302. unsigned int s_handle;
  3303. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3304. int ret = -ENOMEM;
  3305. /* Get the session handle of the boot target */
  3306. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3307. if (ret) {
  3308. beiscsi_log(phba, KERN_ERR,
  3309. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3310. "BM_%d : No boot session\n");
  3311. return ret;
  3312. }
  3313. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3314. sizeof(*session_resp),
  3315. &nonemb_cmd.dma);
  3316. if (nonemb_cmd.va == NULL) {
  3317. beiscsi_log(phba, KERN_ERR,
  3318. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3319. "BM_%d : Failed to allocate memory for"
  3320. "beiscsi_get_session_info\n");
  3321. return -ENOMEM;
  3322. }
  3323. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3324. tag = mgmt_get_session_info(phba, s_handle,
  3325. &nonemb_cmd);
  3326. if (!tag) {
  3327. beiscsi_log(phba, KERN_ERR,
  3328. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3329. "BM_%d : beiscsi_get_session_info"
  3330. " Failed\n");
  3331. goto boot_freemem;
  3332. } else
  3333. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3334. phba->ctrl.mcc_numtag[tag]);
  3335. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3336. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3337. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3338. if (status || extd_status) {
  3339. beiscsi_log(phba, KERN_ERR,
  3340. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3341. "BM_%d : beiscsi_get_session_info Failed"
  3342. " status = %d extd_status = %d\n",
  3343. status, extd_status);
  3344. free_mcc_tag(&phba->ctrl, tag);
  3345. goto boot_freemem;
  3346. }
  3347. wrb = queue_get_wrb(mccq, wrb_num);
  3348. free_mcc_tag(&phba->ctrl, tag);
  3349. session_resp = nonemb_cmd.va ;
  3350. memcpy(&phba->boot_sess, &session_resp->session_info,
  3351. sizeof(struct mgmt_session_info));
  3352. ret = 0;
  3353. boot_freemem:
  3354. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3355. nonemb_cmd.va, nonemb_cmd.dma);
  3356. return ret;
  3357. }
  3358. static void beiscsi_boot_release(void *data)
  3359. {
  3360. struct beiscsi_hba *phba = data;
  3361. scsi_host_put(phba->shost);
  3362. }
  3363. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3364. {
  3365. struct iscsi_boot_kobj *boot_kobj;
  3366. /* get boot info using mgmt cmd */
  3367. if (beiscsi_get_boot_info(phba))
  3368. /* Try to see if we can carry on without this */
  3369. return 0;
  3370. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3371. if (!phba->boot_kset)
  3372. return -ENOMEM;
  3373. /* get a ref because the show function will ref the phba */
  3374. if (!scsi_host_get(phba->shost))
  3375. goto free_kset;
  3376. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3377. beiscsi_show_boot_tgt_info,
  3378. beiscsi_tgt_get_attr_visibility,
  3379. beiscsi_boot_release);
  3380. if (!boot_kobj)
  3381. goto put_shost;
  3382. if (!scsi_host_get(phba->shost))
  3383. goto free_kset;
  3384. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3385. beiscsi_show_boot_ini_info,
  3386. beiscsi_ini_get_attr_visibility,
  3387. beiscsi_boot_release);
  3388. if (!boot_kobj)
  3389. goto put_shost;
  3390. if (!scsi_host_get(phba->shost))
  3391. goto free_kset;
  3392. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3393. beiscsi_show_boot_eth_info,
  3394. beiscsi_eth_get_attr_visibility,
  3395. beiscsi_boot_release);
  3396. if (!boot_kobj)
  3397. goto put_shost;
  3398. return 0;
  3399. put_shost:
  3400. scsi_host_put(phba->shost);
  3401. free_kset:
  3402. iscsi_boot_destroy_kset(phba->boot_kset);
  3403. return -ENOMEM;
  3404. }
  3405. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3406. {
  3407. int ret;
  3408. ret = beiscsi_init_controller(phba);
  3409. if (ret < 0) {
  3410. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3411. "BM_%d : beiscsi_dev_probe - Failed in"
  3412. "beiscsi_init_controller\n");
  3413. return ret;
  3414. }
  3415. ret = beiscsi_init_sgl_handle(phba);
  3416. if (ret < 0) {
  3417. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3418. "BM_%d : beiscsi_dev_probe - Failed in"
  3419. "beiscsi_init_sgl_handle\n");
  3420. goto do_cleanup_ctrlr;
  3421. }
  3422. if (hba_setup_cid_tbls(phba)) {
  3423. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3424. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3425. kfree(phba->io_sgl_hndl_base);
  3426. kfree(phba->eh_sgl_hndl_base);
  3427. goto do_cleanup_ctrlr;
  3428. }
  3429. return ret;
  3430. do_cleanup_ctrlr:
  3431. hwi_cleanup(phba);
  3432. return ret;
  3433. }
  3434. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3435. {
  3436. struct hwi_controller *phwi_ctrlr;
  3437. struct hwi_context_memory *phwi_context;
  3438. struct be_queue_info *eq;
  3439. struct be_eq_entry *eqe = NULL;
  3440. int i, eq_msix;
  3441. unsigned int num_processed;
  3442. phwi_ctrlr = phba->phwi_ctrlr;
  3443. phwi_context = phwi_ctrlr->phwi_ctxt;
  3444. if (phba->msix_enabled)
  3445. eq_msix = 1;
  3446. else
  3447. eq_msix = 0;
  3448. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3449. eq = &phwi_context->be_eq[i].q;
  3450. eqe = queue_tail_node(eq);
  3451. num_processed = 0;
  3452. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3453. & EQE_VALID_MASK) {
  3454. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3455. queue_tail_inc(eq);
  3456. eqe = queue_tail_node(eq);
  3457. num_processed++;
  3458. }
  3459. if (num_processed)
  3460. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3461. }
  3462. }
  3463. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3464. {
  3465. int mgmt_status;
  3466. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3467. if (mgmt_status)
  3468. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3469. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3470. hwi_purge_eq(phba);
  3471. hwi_cleanup(phba);
  3472. kfree(phba->io_sgl_hndl_base);
  3473. kfree(phba->eh_sgl_hndl_base);
  3474. kfree(phba->cid_array);
  3475. kfree(phba->ep_array);
  3476. }
  3477. /**
  3478. * beiscsi_cleanup_task()- Free driver resources of the task
  3479. * @task: ptr to the iscsi task
  3480. *
  3481. **/
  3482. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3483. {
  3484. struct beiscsi_io_task *io_task = task->dd_data;
  3485. struct iscsi_conn *conn = task->conn;
  3486. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3487. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3488. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3489. struct hwi_wrb_context *pwrb_context;
  3490. struct hwi_controller *phwi_ctrlr;
  3491. phwi_ctrlr = phba->phwi_ctrlr;
  3492. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3493. - phba->fw_config.iscsi_cid_start];
  3494. if (io_task->cmd_bhs) {
  3495. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3496. io_task->bhs_pa.u.a64.address);
  3497. io_task->cmd_bhs = NULL;
  3498. }
  3499. if (task->sc) {
  3500. if (io_task->pwrb_handle) {
  3501. free_wrb_handle(phba, pwrb_context,
  3502. io_task->pwrb_handle);
  3503. io_task->pwrb_handle = NULL;
  3504. }
  3505. if (io_task->psgl_handle) {
  3506. spin_lock(&phba->io_sgl_lock);
  3507. free_io_sgl_handle(phba, io_task->psgl_handle);
  3508. spin_unlock(&phba->io_sgl_lock);
  3509. io_task->psgl_handle = NULL;
  3510. }
  3511. } else {
  3512. if (!beiscsi_conn->login_in_progress) {
  3513. if (io_task->pwrb_handle) {
  3514. free_wrb_handle(phba, pwrb_context,
  3515. io_task->pwrb_handle);
  3516. io_task->pwrb_handle = NULL;
  3517. }
  3518. if (io_task->psgl_handle) {
  3519. spin_lock(&phba->mgmt_sgl_lock);
  3520. free_mgmt_sgl_handle(phba,
  3521. io_task->psgl_handle);
  3522. spin_unlock(&phba->mgmt_sgl_lock);
  3523. io_task->psgl_handle = NULL;
  3524. }
  3525. if (io_task->mtask_addr) {
  3526. pci_unmap_single(phba->pcidev,
  3527. io_task->mtask_addr,
  3528. io_task->mtask_data_count,
  3529. PCI_DMA_TODEVICE);
  3530. io_task->mtask_addr = 0;
  3531. }
  3532. }
  3533. }
  3534. }
  3535. void
  3536. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3537. struct beiscsi_offload_params *params)
  3538. {
  3539. struct wrb_handle *pwrb_handle;
  3540. struct iscsi_target_context_update_wrb *pwrb = NULL;
  3541. struct be_mem_descriptor *mem_descr;
  3542. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3543. struct iscsi_task *task = beiscsi_conn->task;
  3544. struct iscsi_session *session = task->conn->session;
  3545. u32 doorbell = 0;
  3546. /*
  3547. * We can always use 0 here because it is reserved by libiscsi for
  3548. * login/startup related tasks.
  3549. */
  3550. beiscsi_conn->login_in_progress = 0;
  3551. spin_lock_bh(&session->lock);
  3552. beiscsi_cleanup_task(task);
  3553. spin_unlock_bh(&session->lock);
  3554. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3555. phba->fw_config.iscsi_cid_start));
  3556. pwrb = (struct iscsi_target_context_update_wrb *)pwrb_handle->pwrb;
  3557. memset(pwrb, 0, sizeof(*pwrb));
  3558. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3559. max_burst_length, pwrb, params->dw[offsetof
  3560. (struct amap_beiscsi_offload_params,
  3561. max_burst_length) / 32]);
  3562. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3563. max_send_data_segment_length, pwrb,
  3564. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3565. max_send_data_segment_length) / 32]);
  3566. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3567. first_burst_length,
  3568. pwrb,
  3569. params->dw[offsetof(struct amap_beiscsi_offload_params,
  3570. first_burst_length) / 32]);
  3571. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, erl, pwrb,
  3572. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3573. erl) / 32] & OFFLD_PARAMS_ERL));
  3574. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, dde, pwrb,
  3575. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3576. dde) / 32] & OFFLD_PARAMS_DDE) >> 2);
  3577. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, hde, pwrb,
  3578. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3579. hde) / 32] & OFFLD_PARAMS_HDE) >> 3);
  3580. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ir2t, pwrb,
  3581. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3582. ir2t) / 32] & OFFLD_PARAMS_IR2T) >> 4);
  3583. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, imd, pwrb,
  3584. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3585. imd) / 32] & OFFLD_PARAMS_IMD) >> 5);
  3586. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, stat_sn,
  3587. pwrb,
  3588. (params->dw[offsetof(struct amap_beiscsi_offload_params,
  3589. exp_statsn) / 32] + 1));
  3590. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, type, pwrb,
  3591. 0x7);
  3592. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, wrb_idx,
  3593. pwrb, pwrb_handle->wrb_index);
  3594. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, ptr2nextwrb,
  3595. pwrb, pwrb_handle->nxt_wrb_index);
  3596. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3597. session_state, pwrb, 0);
  3598. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, compltonack,
  3599. pwrb, 1);
  3600. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, notpredblq,
  3601. pwrb, 0);
  3602. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb, mode, pwrb,
  3603. 0);
  3604. mem_descr = phba->init_mem;
  3605. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  3606. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3607. pad_buffer_addr_hi, pwrb,
  3608. mem_descr->mem_array[0].bus_address.u.a32.address_hi);
  3609. AMAP_SET_BITS(struct amap_iscsi_target_context_update_wrb,
  3610. pad_buffer_addr_lo, pwrb,
  3611. mem_descr->mem_array[0].bus_address.u.a32.address_lo);
  3612. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_target_context_update_wrb));
  3613. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3614. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3615. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3616. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3617. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3618. }
  3619. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3620. int *index, int *age)
  3621. {
  3622. *index = (int)itt;
  3623. if (age)
  3624. *age = conn->session->age;
  3625. }
  3626. /**
  3627. * beiscsi_alloc_pdu - allocates pdu and related resources
  3628. * @task: libiscsi task
  3629. * @opcode: opcode of pdu for task
  3630. *
  3631. * This is called with the session lock held. It will allocate
  3632. * the wrb and sgl if needed for the command. And it will prep
  3633. * the pdu's itt. beiscsi_parse_pdu will later translate
  3634. * the pdu itt to the libiscsi task itt.
  3635. */
  3636. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3637. {
  3638. struct beiscsi_io_task *io_task = task->dd_data;
  3639. struct iscsi_conn *conn = task->conn;
  3640. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3641. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3642. struct hwi_wrb_context *pwrb_context;
  3643. struct hwi_controller *phwi_ctrlr;
  3644. itt_t itt;
  3645. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3646. dma_addr_t paddr;
  3647. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3648. GFP_ATOMIC, &paddr);
  3649. if (!io_task->cmd_bhs)
  3650. return -ENOMEM;
  3651. io_task->bhs_pa.u.a64.address = paddr;
  3652. io_task->libiscsi_itt = (itt_t)task->itt;
  3653. io_task->conn = beiscsi_conn;
  3654. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3655. task->hdr_max = sizeof(struct be_cmd_bhs);
  3656. io_task->psgl_handle = NULL;
  3657. io_task->pwrb_handle = NULL;
  3658. if (task->sc) {
  3659. spin_lock(&phba->io_sgl_lock);
  3660. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3661. spin_unlock(&phba->io_sgl_lock);
  3662. if (!io_task->psgl_handle) {
  3663. beiscsi_log(phba, KERN_ERR,
  3664. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3665. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3666. "for the CID : %d\n",
  3667. beiscsi_conn->beiscsi_conn_cid);
  3668. goto free_hndls;
  3669. }
  3670. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3671. beiscsi_conn->beiscsi_conn_cid -
  3672. phba->fw_config.iscsi_cid_start);
  3673. if (!io_task->pwrb_handle) {
  3674. beiscsi_log(phba, KERN_ERR,
  3675. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3676. "BM_%d : Alloc of WRB_HANDLE Failed"
  3677. "for the CID : %d\n",
  3678. beiscsi_conn->beiscsi_conn_cid);
  3679. goto free_io_hndls;
  3680. }
  3681. } else {
  3682. io_task->scsi_cmnd = NULL;
  3683. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3684. if (!beiscsi_conn->login_in_progress) {
  3685. spin_lock(&phba->mgmt_sgl_lock);
  3686. io_task->psgl_handle = (struct sgl_handle *)
  3687. alloc_mgmt_sgl_handle(phba);
  3688. spin_unlock(&phba->mgmt_sgl_lock);
  3689. if (!io_task->psgl_handle) {
  3690. beiscsi_log(phba, KERN_ERR,
  3691. BEISCSI_LOG_IO |
  3692. BEISCSI_LOG_CONFIG,
  3693. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3694. "for the CID : %d\n",
  3695. beiscsi_conn->
  3696. beiscsi_conn_cid);
  3697. goto free_hndls;
  3698. }
  3699. beiscsi_conn->login_in_progress = 1;
  3700. beiscsi_conn->plogin_sgl_handle =
  3701. io_task->psgl_handle;
  3702. io_task->pwrb_handle =
  3703. alloc_wrb_handle(phba,
  3704. beiscsi_conn->beiscsi_conn_cid -
  3705. phba->fw_config.iscsi_cid_start);
  3706. if (!io_task->pwrb_handle) {
  3707. beiscsi_log(phba, KERN_ERR,
  3708. BEISCSI_LOG_IO |
  3709. BEISCSI_LOG_CONFIG,
  3710. "BM_%d : Alloc of WRB_HANDLE Failed"
  3711. "for the CID : %d\n",
  3712. beiscsi_conn->
  3713. beiscsi_conn_cid);
  3714. goto free_mgmt_hndls;
  3715. }
  3716. beiscsi_conn->plogin_wrb_handle =
  3717. io_task->pwrb_handle;
  3718. } else {
  3719. io_task->psgl_handle =
  3720. beiscsi_conn->plogin_sgl_handle;
  3721. io_task->pwrb_handle =
  3722. beiscsi_conn->plogin_wrb_handle;
  3723. }
  3724. beiscsi_conn->task = task;
  3725. } else {
  3726. spin_lock(&phba->mgmt_sgl_lock);
  3727. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3728. spin_unlock(&phba->mgmt_sgl_lock);
  3729. if (!io_task->psgl_handle) {
  3730. beiscsi_log(phba, KERN_ERR,
  3731. BEISCSI_LOG_IO |
  3732. BEISCSI_LOG_CONFIG,
  3733. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3734. "for the CID : %d\n",
  3735. beiscsi_conn->
  3736. beiscsi_conn_cid);
  3737. goto free_hndls;
  3738. }
  3739. io_task->pwrb_handle =
  3740. alloc_wrb_handle(phba,
  3741. beiscsi_conn->beiscsi_conn_cid -
  3742. phba->fw_config.iscsi_cid_start);
  3743. if (!io_task->pwrb_handle) {
  3744. beiscsi_log(phba, KERN_ERR,
  3745. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3746. "BM_%d : Alloc of WRB_HANDLE Failed"
  3747. "for the CID : %d\n",
  3748. beiscsi_conn->beiscsi_conn_cid);
  3749. goto free_mgmt_hndls;
  3750. }
  3751. }
  3752. }
  3753. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3754. wrb_index << 16) | (unsigned int)
  3755. (io_task->psgl_handle->sgl_index));
  3756. io_task->pwrb_handle->pio_handle = task;
  3757. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3758. return 0;
  3759. free_io_hndls:
  3760. spin_lock(&phba->io_sgl_lock);
  3761. free_io_sgl_handle(phba, io_task->psgl_handle);
  3762. spin_unlock(&phba->io_sgl_lock);
  3763. goto free_hndls;
  3764. free_mgmt_hndls:
  3765. spin_lock(&phba->mgmt_sgl_lock);
  3766. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3767. spin_unlock(&phba->mgmt_sgl_lock);
  3768. free_hndls:
  3769. phwi_ctrlr = phba->phwi_ctrlr;
  3770. pwrb_context = &phwi_ctrlr->wrb_context[
  3771. beiscsi_conn->beiscsi_conn_cid -
  3772. phba->fw_config.iscsi_cid_start];
  3773. if (io_task->pwrb_handle)
  3774. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3775. io_task->pwrb_handle = NULL;
  3776. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3777. io_task->bhs_pa.u.a64.address);
  3778. io_task->cmd_bhs = NULL;
  3779. return -ENOMEM;
  3780. }
  3781. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3782. unsigned int num_sg, unsigned int xferlen,
  3783. unsigned int writedir)
  3784. {
  3785. struct beiscsi_io_task *io_task = task->dd_data;
  3786. struct iscsi_conn *conn = task->conn;
  3787. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3788. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3789. struct iscsi_wrb *pwrb = NULL;
  3790. unsigned int doorbell = 0;
  3791. pwrb = io_task->pwrb_handle->pwrb;
  3792. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3793. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3794. if (writedir) {
  3795. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3796. INI_WR_CMD);
  3797. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3798. } else {
  3799. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3800. INI_RD_CMD);
  3801. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3802. }
  3803. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3804. cpu_to_be16(*(unsigned short *)
  3805. &io_task->cmd_bhs->iscsi_hdr.lun));
  3806. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3807. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3808. io_task->pwrb_handle->wrb_index);
  3809. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3810. be32_to_cpu(task->cmdsn));
  3811. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3812. io_task->psgl_handle->sgl_index);
  3813. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3814. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3815. io_task->pwrb_handle->nxt_wrb_index);
  3816. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3817. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3818. doorbell |= (io_task->pwrb_handle->wrb_index &
  3819. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3820. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3821. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3822. return 0;
  3823. }
  3824. static int beiscsi_mtask(struct iscsi_task *task)
  3825. {
  3826. struct beiscsi_io_task *io_task = task->dd_data;
  3827. struct iscsi_conn *conn = task->conn;
  3828. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3829. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3830. struct iscsi_wrb *pwrb = NULL;
  3831. unsigned int doorbell = 0;
  3832. unsigned int cid;
  3833. cid = beiscsi_conn->beiscsi_conn_cid;
  3834. pwrb = io_task->pwrb_handle->pwrb;
  3835. memset(pwrb, 0, sizeof(*pwrb));
  3836. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3837. be32_to_cpu(task->cmdsn));
  3838. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3839. io_task->pwrb_handle->wrb_index);
  3840. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3841. io_task->psgl_handle->sgl_index);
  3842. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  3843. case ISCSI_OP_LOGIN:
  3844. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3845. TGT_DM_CMD);
  3846. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3847. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  3848. hwi_write_buffer(pwrb, task);
  3849. break;
  3850. case ISCSI_OP_NOOP_OUT:
  3851. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  3852. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3853. TGT_DM_CMD);
  3854. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt,
  3855. pwrb, 0);
  3856. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 1);
  3857. } else {
  3858. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3859. INI_RD_CMD);
  3860. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3861. }
  3862. hwi_write_buffer(pwrb, task);
  3863. break;
  3864. case ISCSI_OP_TEXT:
  3865. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3866. TGT_DM_CMD);
  3867. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3868. hwi_write_buffer(pwrb, task);
  3869. break;
  3870. case ISCSI_OP_SCSI_TMFUNC:
  3871. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3872. INI_TMF_CMD);
  3873. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3874. hwi_write_buffer(pwrb, task);
  3875. break;
  3876. case ISCSI_OP_LOGOUT:
  3877. AMAP_SET_BITS(struct amap_iscsi_wrb, dmsg, pwrb, 0);
  3878. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3879. HWH_TYPE_LOGOUT);
  3880. hwi_write_buffer(pwrb, task);
  3881. break;
  3882. default:
  3883. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3884. "BM_%d : opcode =%d Not supported\n",
  3885. task->hdr->opcode & ISCSI_OPCODE_MASK);
  3886. return -EINVAL;
  3887. }
  3888. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  3889. task->data_count);
  3890. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3891. io_task->pwrb_handle->nxt_wrb_index);
  3892. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3893. doorbell |= cid & DB_WRB_POST_CID_MASK;
  3894. doorbell |= (io_task->pwrb_handle->wrb_index &
  3895. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3896. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3897. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3898. return 0;
  3899. }
  3900. static int beiscsi_task_xmit(struct iscsi_task *task)
  3901. {
  3902. struct beiscsi_io_task *io_task = task->dd_data;
  3903. struct scsi_cmnd *sc = task->sc;
  3904. struct scatterlist *sg;
  3905. int num_sg;
  3906. unsigned int writedir = 0, xferlen = 0;
  3907. if (!sc)
  3908. return beiscsi_mtask(task);
  3909. io_task->scsi_cmnd = sc;
  3910. num_sg = scsi_dma_map(sc);
  3911. if (num_sg < 0) {
  3912. struct iscsi_conn *conn = task->conn;
  3913. struct beiscsi_hba *phba = NULL;
  3914. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  3915. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  3916. "BM_%d : scsi_dma_map Failed\n");
  3917. return num_sg;
  3918. }
  3919. xferlen = scsi_bufflen(sc);
  3920. sg = scsi_sglist(sc);
  3921. if (sc->sc_data_direction == DMA_TO_DEVICE)
  3922. writedir = 1;
  3923. else
  3924. writedir = 0;
  3925. return beiscsi_iotask(task, sg, num_sg, xferlen, writedir);
  3926. }
  3927. /**
  3928. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  3929. * @job: job to handle
  3930. */
  3931. static int beiscsi_bsg_request(struct bsg_job *job)
  3932. {
  3933. struct Scsi_Host *shost;
  3934. struct beiscsi_hba *phba;
  3935. struct iscsi_bsg_request *bsg_req = job->request;
  3936. int rc = -EINVAL;
  3937. unsigned int tag;
  3938. struct be_dma_mem nonemb_cmd;
  3939. struct be_cmd_resp_hdr *resp;
  3940. struct iscsi_bsg_reply *bsg_reply = job->reply;
  3941. unsigned short status, extd_status;
  3942. shost = iscsi_job_to_shost(job);
  3943. phba = iscsi_host_priv(shost);
  3944. switch (bsg_req->msgcode) {
  3945. case ISCSI_BSG_HST_VENDOR:
  3946. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3947. job->request_payload.payload_len,
  3948. &nonemb_cmd.dma);
  3949. if (nonemb_cmd.va == NULL) {
  3950. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3951. "BM_%d : Failed to allocate memory for "
  3952. "beiscsi_bsg_request\n");
  3953. return -ENOMEM;
  3954. }
  3955. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  3956. &nonemb_cmd);
  3957. if (!tag) {
  3958. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3959. "BM_%d : MBX Tag Allocation Failed\n");
  3960. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3961. nonemb_cmd.va, nonemb_cmd.dma);
  3962. return -EAGAIN;
  3963. } else
  3964. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3965. phba->ctrl.mcc_numtag[tag]);
  3966. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3967. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3968. free_mcc_tag(&phba->ctrl, tag);
  3969. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  3970. sg_copy_from_buffer(job->reply_payload.sg_list,
  3971. job->reply_payload.sg_cnt,
  3972. nonemb_cmd.va, (resp->response_length
  3973. + sizeof(*resp)));
  3974. bsg_reply->reply_payload_rcv_len = resp->response_length;
  3975. bsg_reply->result = status;
  3976. bsg_job_done(job, bsg_reply->result,
  3977. bsg_reply->reply_payload_rcv_len);
  3978. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3979. nonemb_cmd.va, nonemb_cmd.dma);
  3980. if (status || extd_status) {
  3981. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3982. "BM_%d : MBX Cmd Failed"
  3983. " status = %d extd_status = %d\n",
  3984. status, extd_status);
  3985. return -EIO;
  3986. } else {
  3987. rc = 0;
  3988. }
  3989. break;
  3990. default:
  3991. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  3992. "BM_%d : Unsupported bsg command: 0x%x\n",
  3993. bsg_req->msgcode);
  3994. break;
  3995. }
  3996. return rc;
  3997. }
  3998. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  3999. {
  4000. /* Set the logging parameter */
  4001. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4002. }
  4003. /*
  4004. * beiscsi_quiesce()- Cleanup Driver resources
  4005. * @phba: Instance Priv structure
  4006. *
  4007. * Free the OS and HW resources held by the driver
  4008. **/
  4009. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4010. {
  4011. struct hwi_controller *phwi_ctrlr;
  4012. struct hwi_context_memory *phwi_context;
  4013. struct be_eq_obj *pbe_eq;
  4014. unsigned int i, msix_vec;
  4015. phwi_ctrlr = phba->phwi_ctrlr;
  4016. phwi_context = phwi_ctrlr->phwi_ctxt;
  4017. hwi_disable_intr(phba);
  4018. if (phba->msix_enabled) {
  4019. for (i = 0; i <= phba->num_cpus; i++) {
  4020. msix_vec = phba->msix_entries[i].vector;
  4021. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4022. kfree(phba->msi_name[i]);
  4023. }
  4024. } else
  4025. if (phba->pcidev->irq)
  4026. free_irq(phba->pcidev->irq, phba);
  4027. pci_disable_msix(phba->pcidev);
  4028. destroy_workqueue(phba->wq);
  4029. if (blk_iopoll_enabled)
  4030. for (i = 0; i < phba->num_cpus; i++) {
  4031. pbe_eq = &phwi_context->be_eq[i];
  4032. blk_iopoll_disable(&pbe_eq->iopoll);
  4033. }
  4034. beiscsi_clean_port(phba);
  4035. beiscsi_free_mem(phba);
  4036. beiscsi_unmap_pci_function(phba);
  4037. pci_free_consistent(phba->pcidev,
  4038. phba->ctrl.mbox_mem_alloced.size,
  4039. phba->ctrl.mbox_mem_alloced.va,
  4040. phba->ctrl.mbox_mem_alloced.dma);
  4041. }
  4042. static void beiscsi_remove(struct pci_dev *pcidev)
  4043. {
  4044. struct beiscsi_hba *phba = NULL;
  4045. phba = pci_get_drvdata(pcidev);
  4046. if (!phba) {
  4047. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4048. return;
  4049. }
  4050. beiscsi_destroy_def_ifaces(phba);
  4051. beiscsi_quiesce(phba);
  4052. iscsi_boot_destroy_kset(phba->boot_kset);
  4053. iscsi_host_remove(phba->shost);
  4054. pci_dev_put(phba->pcidev);
  4055. iscsi_host_free(phba->shost);
  4056. pci_disable_device(pcidev);
  4057. }
  4058. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4059. {
  4060. struct beiscsi_hba *phba = NULL;
  4061. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4062. if (!phba) {
  4063. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4064. return;
  4065. }
  4066. beiscsi_quiesce(phba);
  4067. pci_disable_device(pcidev);
  4068. }
  4069. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4070. {
  4071. int i, status;
  4072. for (i = 0; i <= phba->num_cpus; i++)
  4073. phba->msix_entries[i].entry = i;
  4074. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4075. (phba->num_cpus + 1));
  4076. if (!status)
  4077. phba->msix_enabled = true;
  4078. return;
  4079. }
  4080. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  4081. const struct pci_device_id *id)
  4082. {
  4083. struct beiscsi_hba *phba = NULL;
  4084. struct hwi_controller *phwi_ctrlr;
  4085. struct hwi_context_memory *phwi_context;
  4086. struct be_eq_obj *pbe_eq;
  4087. int ret, i;
  4088. ret = beiscsi_enable_pci(pcidev);
  4089. if (ret < 0) {
  4090. dev_err(&pcidev->dev,
  4091. "beiscsi_dev_probe - Failed to enable pci device\n");
  4092. return ret;
  4093. }
  4094. phba = beiscsi_hba_alloc(pcidev);
  4095. if (!phba) {
  4096. dev_err(&pcidev->dev,
  4097. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4098. goto disable_pci;
  4099. }
  4100. /* Initialize Driver configuration Paramters */
  4101. beiscsi_hba_attrs_init(phba);
  4102. switch (pcidev->device) {
  4103. case BE_DEVICE_ID1:
  4104. case OC_DEVICE_ID1:
  4105. case OC_DEVICE_ID2:
  4106. phba->generation = BE_GEN2;
  4107. break;
  4108. case BE_DEVICE_ID2:
  4109. case OC_DEVICE_ID3:
  4110. phba->generation = BE_GEN3;
  4111. break;
  4112. default:
  4113. phba->generation = 0;
  4114. }
  4115. if (enable_msix)
  4116. find_num_cpus(phba);
  4117. else
  4118. phba->num_cpus = 1;
  4119. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4120. "BM_%d : num_cpus = %d\n",
  4121. phba->num_cpus);
  4122. if (enable_msix) {
  4123. beiscsi_msix_enable(phba);
  4124. if (!phba->msix_enabled)
  4125. phba->num_cpus = 1;
  4126. }
  4127. ret = be_ctrl_init(phba, pcidev);
  4128. if (ret) {
  4129. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4130. "BM_%d : beiscsi_dev_probe-"
  4131. "Failed in be_ctrl_init\n");
  4132. goto hba_free;
  4133. }
  4134. ret = beiscsi_cmd_reset_function(phba);
  4135. if (ret) {
  4136. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4137. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4138. goto hba_free;
  4139. }
  4140. ret = be_chk_reset_complete(phba);
  4141. if (ret) {
  4142. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4143. "BM_%d : Failed to get out of reset."
  4144. "Aborting Crashdump\n");
  4145. goto hba_free;
  4146. }
  4147. spin_lock_init(&phba->io_sgl_lock);
  4148. spin_lock_init(&phba->mgmt_sgl_lock);
  4149. spin_lock_init(&phba->isr_lock);
  4150. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4151. if (ret != 0) {
  4152. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4153. "BM_%d : Error getting fw config\n");
  4154. goto free_port;
  4155. }
  4156. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4157. beiscsi_get_params(phba);
  4158. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4159. ret = beiscsi_init_port(phba);
  4160. if (ret < 0) {
  4161. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4162. "BM_%d : beiscsi_dev_probe-"
  4163. "Failed in beiscsi_init_port\n");
  4164. goto free_port;
  4165. }
  4166. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4167. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4168. phba->ctrl.mcc_tag[i] = i + 1;
  4169. phba->ctrl.mcc_numtag[i + 1] = 0;
  4170. phba->ctrl.mcc_tag_available++;
  4171. }
  4172. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4173. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4174. phba->shost->host_no);
  4175. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4176. if (!phba->wq) {
  4177. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4178. "BM_%d : beiscsi_dev_probe-"
  4179. "Failed to allocate work queue\n");
  4180. goto free_twq;
  4181. }
  4182. phwi_ctrlr = phba->phwi_ctrlr;
  4183. phwi_context = phwi_ctrlr->phwi_ctxt;
  4184. if (blk_iopoll_enabled) {
  4185. for (i = 0; i < phba->num_cpus; i++) {
  4186. pbe_eq = &phwi_context->be_eq[i];
  4187. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4188. be_iopoll);
  4189. blk_iopoll_enable(&pbe_eq->iopoll);
  4190. }
  4191. i = (phba->msix_enabled) ? i : 0;
  4192. /* Work item for MCC handling */
  4193. pbe_eq = &phwi_context->be_eq[i];
  4194. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4195. } else {
  4196. if (phba->msix_enabled) {
  4197. for (i = 0; i <= phba->num_cpus; i++) {
  4198. pbe_eq = &phwi_context->be_eq[i];
  4199. INIT_WORK(&pbe_eq->work_cqs,
  4200. beiscsi_process_all_cqs);
  4201. }
  4202. } else {
  4203. pbe_eq = &phwi_context->be_eq[0];
  4204. INIT_WORK(&pbe_eq->work_cqs,
  4205. beiscsi_process_all_cqs);
  4206. }
  4207. }
  4208. ret = beiscsi_init_irqs(phba);
  4209. if (ret < 0) {
  4210. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4211. "BM_%d : beiscsi_dev_probe-"
  4212. "Failed to beiscsi_init_irqs\n");
  4213. goto free_blkenbld;
  4214. }
  4215. hwi_enable_intr(phba);
  4216. if (beiscsi_setup_boot_info(phba))
  4217. /*
  4218. * log error but continue, because we may not be using
  4219. * iscsi boot.
  4220. */
  4221. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4222. "BM_%d : Could not set up "
  4223. "iSCSI boot info.\n");
  4224. beiscsi_create_def_ifaces(phba);
  4225. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4226. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4227. return 0;
  4228. free_blkenbld:
  4229. destroy_workqueue(phba->wq);
  4230. if (blk_iopoll_enabled)
  4231. for (i = 0; i < phba->num_cpus; i++) {
  4232. pbe_eq = &phwi_context->be_eq[i];
  4233. blk_iopoll_disable(&pbe_eq->iopoll);
  4234. }
  4235. free_twq:
  4236. beiscsi_clean_port(phba);
  4237. beiscsi_free_mem(phba);
  4238. free_port:
  4239. pci_free_consistent(phba->pcidev,
  4240. phba->ctrl.mbox_mem_alloced.size,
  4241. phba->ctrl.mbox_mem_alloced.va,
  4242. phba->ctrl.mbox_mem_alloced.dma);
  4243. beiscsi_unmap_pci_function(phba);
  4244. hba_free:
  4245. if (phba->msix_enabled)
  4246. pci_disable_msix(phba->pcidev);
  4247. iscsi_host_remove(phba->shost);
  4248. pci_dev_put(phba->pcidev);
  4249. iscsi_host_free(phba->shost);
  4250. disable_pci:
  4251. pci_disable_device(pcidev);
  4252. return ret;
  4253. }
  4254. struct iscsi_transport beiscsi_iscsi_transport = {
  4255. .owner = THIS_MODULE,
  4256. .name = DRV_NAME,
  4257. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4258. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4259. .create_session = beiscsi_session_create,
  4260. .destroy_session = beiscsi_session_destroy,
  4261. .create_conn = beiscsi_conn_create,
  4262. .bind_conn = beiscsi_conn_bind,
  4263. .destroy_conn = iscsi_conn_teardown,
  4264. .attr_is_visible = be2iscsi_attr_is_visible,
  4265. .set_iface_param = be2iscsi_iface_set_param,
  4266. .get_iface_param = be2iscsi_iface_get_param,
  4267. .set_param = beiscsi_set_param,
  4268. .get_conn_param = iscsi_conn_get_param,
  4269. .get_session_param = iscsi_session_get_param,
  4270. .get_host_param = beiscsi_get_host_param,
  4271. .start_conn = beiscsi_conn_start,
  4272. .stop_conn = iscsi_conn_stop,
  4273. .send_pdu = iscsi_conn_send_pdu,
  4274. .xmit_task = beiscsi_task_xmit,
  4275. .cleanup_task = beiscsi_cleanup_task,
  4276. .alloc_pdu = beiscsi_alloc_pdu,
  4277. .parse_pdu_itt = beiscsi_parse_pdu,
  4278. .get_stats = beiscsi_conn_get_stats,
  4279. .get_ep_param = beiscsi_ep_get_param,
  4280. .ep_connect = beiscsi_ep_connect,
  4281. .ep_poll = beiscsi_ep_poll,
  4282. .ep_disconnect = beiscsi_ep_disconnect,
  4283. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4284. .bsg_request = beiscsi_bsg_request,
  4285. };
  4286. static struct pci_driver beiscsi_pci_driver = {
  4287. .name = DRV_NAME,
  4288. .probe = beiscsi_dev_probe,
  4289. .remove = beiscsi_remove,
  4290. .shutdown = beiscsi_shutdown,
  4291. .id_table = beiscsi_pci_id_table
  4292. };
  4293. static int __init beiscsi_module_init(void)
  4294. {
  4295. int ret;
  4296. beiscsi_scsi_transport =
  4297. iscsi_register_transport(&beiscsi_iscsi_transport);
  4298. if (!beiscsi_scsi_transport) {
  4299. printk(KERN_ERR
  4300. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4301. return -ENOMEM;
  4302. }
  4303. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4304. &beiscsi_iscsi_transport);
  4305. ret = pci_register_driver(&beiscsi_pci_driver);
  4306. if (ret) {
  4307. printk(KERN_ERR
  4308. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4309. goto unregister_iscsi_transport;
  4310. }
  4311. return 0;
  4312. unregister_iscsi_transport:
  4313. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4314. return ret;
  4315. }
  4316. static void __exit beiscsi_module_exit(void)
  4317. {
  4318. pci_unregister_driver(&beiscsi_pci_driver);
  4319. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4320. }
  4321. module_init(beiscsi_module_init);
  4322. module_exit(beiscsi_module_exit);