coda.c 67 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/genalloc.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/kfifo.h>
  21. #include <linux/module.h>
  22. #include <linux/of_device.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/slab.h>
  25. #include <linux/videodev2.h>
  26. #include <linux/of.h>
  27. #include <linux/platform_data/coda.h>
  28. #include <media/v4l2-ctrls.h>
  29. #include <media/v4l2-device.h>
  30. #include <media/v4l2-ioctl.h>
  31. #include <media/v4l2-mem2mem.h>
  32. #include <media/videobuf2-core.h>
  33. #include <media/videobuf2-dma-contig.h>
  34. #include "coda.h"
  35. #define CODA_NAME "coda"
  36. #define CODA_MAX_INSTANCES 4
  37. #define CODA_FMO_BUF_SIZE 32
  38. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  39. #define CODA7_WORK_BUF_SIZE (128 * 1024)
  40. #define CODA7_TEMP_BUF_SIZE (304 * 1024)
  41. #define CODA_PARA_BUF_SIZE (10 * 1024)
  42. #define CODA_ISRAM_SIZE (2048 * 2)
  43. #define CODADX6_IRAM_SIZE 0xb000
  44. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  45. #define CODA_MAX_FRAMEBUFFERS 2
  46. #define MAX_W 8192
  47. #define MAX_H 8192
  48. #define CODA_MAX_FRAME_SIZE 0x100000
  49. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  50. #define CODA_DEFAULT_GAMMA 4096
  51. #define MIN_W 176
  52. #define MIN_H 144
  53. #define S_ALIGN 1 /* multiple of 2 */
  54. #define W_ALIGN 1 /* multiple of 2 */
  55. #define H_ALIGN 1 /* multiple of 2 */
  56. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  57. static int coda_debug;
  58. module_param(coda_debug, int, 0644);
  59. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  60. enum {
  61. V4L2_M2M_SRC = 0,
  62. V4L2_M2M_DST = 1,
  63. };
  64. enum coda_inst_type {
  65. CODA_INST_ENCODER,
  66. CODA_INST_DECODER,
  67. };
  68. enum coda_product {
  69. CODA_DX6 = 0xf001,
  70. CODA_7541 = 0xf012,
  71. };
  72. struct coda_fmt {
  73. char *name;
  74. u32 fourcc;
  75. };
  76. struct coda_codec {
  77. u32 mode;
  78. u32 src_fourcc;
  79. u32 dst_fourcc;
  80. u32 max_w;
  81. u32 max_h;
  82. };
  83. struct coda_devtype {
  84. char *firmware;
  85. enum coda_product product;
  86. struct coda_codec *codecs;
  87. unsigned int num_codecs;
  88. size_t workbuf_size;
  89. };
  90. /* Per-queue, driver-specific private data */
  91. struct coda_q_data {
  92. unsigned int width;
  93. unsigned int height;
  94. unsigned int sizeimage;
  95. unsigned int fourcc;
  96. };
  97. struct coda_aux_buf {
  98. void *vaddr;
  99. dma_addr_t paddr;
  100. u32 size;
  101. };
  102. struct coda_dev {
  103. struct v4l2_device v4l2_dev;
  104. struct video_device vfd;
  105. struct platform_device *plat_dev;
  106. const struct coda_devtype *devtype;
  107. void __iomem *regs_base;
  108. struct clk *clk_per;
  109. struct clk *clk_ahb;
  110. struct coda_aux_buf codebuf;
  111. struct coda_aux_buf tempbuf;
  112. struct coda_aux_buf workbuf;
  113. struct gen_pool *iram_pool;
  114. long unsigned int iram_vaddr;
  115. long unsigned int iram_paddr;
  116. unsigned long iram_size;
  117. spinlock_t irqlock;
  118. struct mutex dev_mutex;
  119. struct mutex coda_mutex;
  120. struct v4l2_m2m_dev *m2m_dev;
  121. struct vb2_alloc_ctx *alloc_ctx;
  122. struct list_head instances;
  123. unsigned long instance_mask;
  124. struct delayed_work timeout;
  125. };
  126. struct coda_params {
  127. u8 rot_mode;
  128. u8 h264_intra_qp;
  129. u8 h264_inter_qp;
  130. u8 mpeg4_intra_qp;
  131. u8 mpeg4_inter_qp;
  132. u8 gop_size;
  133. int codec_mode;
  134. int codec_mode_aux;
  135. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  136. u32 framerate;
  137. u16 bitrate;
  138. u32 slice_max_bits;
  139. u32 slice_max_mb;
  140. };
  141. struct coda_iram_info {
  142. u32 axi_sram_use;
  143. phys_addr_t buf_bit_use;
  144. phys_addr_t buf_ip_ac_dc_use;
  145. phys_addr_t buf_dbk_y_use;
  146. phys_addr_t buf_dbk_c_use;
  147. phys_addr_t buf_ovl_use;
  148. phys_addr_t buf_btp_use;
  149. phys_addr_t search_ram_paddr;
  150. int search_ram_size;
  151. };
  152. struct coda_ctx {
  153. struct coda_dev *dev;
  154. struct list_head list;
  155. int aborting;
  156. int streamon_out;
  157. int streamon_cap;
  158. u32 isequence;
  159. u32 qsequence;
  160. struct coda_q_data q_data[2];
  161. enum coda_inst_type inst_type;
  162. struct coda_codec *codec;
  163. enum v4l2_colorspace colorspace;
  164. struct coda_params params;
  165. struct v4l2_m2m_ctx *m2m_ctx;
  166. struct v4l2_ctrl_handler ctrls;
  167. struct v4l2_fh fh;
  168. int gopcounter;
  169. char vpu_header[3][64];
  170. int vpu_header_size[3];
  171. struct kfifo bitstream_fifo;
  172. struct mutex bitstream_mutex;
  173. struct coda_aux_buf bitstream;
  174. struct coda_aux_buf parabuf;
  175. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  176. struct coda_aux_buf workbuf;
  177. int num_internal_frames;
  178. int idx;
  179. int reg_idx;
  180. struct coda_iram_info iram_info;
  181. u32 bit_stream_param;
  182. };
  183. static const u8 coda_filler_nal[14] = { 0x00, 0x00, 0x00, 0x01, 0x0c, 0xff,
  184. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80 };
  185. static const u8 coda_filler_size[8] = { 0, 7, 14, 13, 12, 11, 10, 9 };
  186. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  187. {
  188. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  189. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  190. writel(data, dev->regs_base + reg);
  191. }
  192. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  193. {
  194. u32 data;
  195. data = readl(dev->regs_base + reg);
  196. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  197. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  198. return data;
  199. }
  200. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  201. {
  202. return coda_read(dev, CODA_REG_BIT_BUSY);
  203. }
  204. static inline int coda_is_initialized(struct coda_dev *dev)
  205. {
  206. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  207. }
  208. static int coda_wait_timeout(struct coda_dev *dev)
  209. {
  210. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  211. while (coda_isbusy(dev)) {
  212. if (time_after(jiffies, timeout))
  213. return -ETIMEDOUT;
  214. }
  215. return 0;
  216. }
  217. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  218. {
  219. struct coda_dev *dev = ctx->dev;
  220. if (dev->devtype->product == CODA_7541) {
  221. /* Restore context related registers to CODA */
  222. coda_write(dev, ctx->bit_stream_param,
  223. CODA_REG_BIT_BIT_STREAM_PARAM);
  224. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  225. }
  226. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  227. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  228. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  229. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  230. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  231. }
  232. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  233. {
  234. struct coda_dev *dev = ctx->dev;
  235. coda_command_async(ctx, cmd);
  236. return coda_wait_timeout(dev);
  237. }
  238. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  239. enum v4l2_buf_type type)
  240. {
  241. switch (type) {
  242. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  243. return &(ctx->q_data[V4L2_M2M_SRC]);
  244. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  245. return &(ctx->q_data[V4L2_M2M_DST]);
  246. default:
  247. BUG();
  248. }
  249. return NULL;
  250. }
  251. /*
  252. * Array of all formats supported by any version of Coda:
  253. */
  254. static struct coda_fmt coda_formats[] = {
  255. {
  256. .name = "YUV 4:2:0 Planar, YCbCr",
  257. .fourcc = V4L2_PIX_FMT_YUV420,
  258. },
  259. {
  260. .name = "YUV 4:2:0 Planar, YCrCb",
  261. .fourcc = V4L2_PIX_FMT_YVU420,
  262. },
  263. {
  264. .name = "H264 Encoded Stream",
  265. .fourcc = V4L2_PIX_FMT_H264,
  266. },
  267. {
  268. .name = "MPEG4 Encoded Stream",
  269. .fourcc = V4L2_PIX_FMT_MPEG4,
  270. },
  271. };
  272. #define CODA_CODEC(mode, src_fourcc, dst_fourcc, max_w, max_h) \
  273. { mode, src_fourcc, dst_fourcc, max_w, max_h }
  274. /*
  275. * Arrays of codecs supported by each given version of Coda:
  276. * i.MX27 -> codadx6
  277. * i.MX5x -> coda7
  278. * i.MX6 -> coda960
  279. * Use V4L2_PIX_FMT_YUV420 as placeholder for all supported YUV 4:2:0 variants
  280. */
  281. static struct coda_codec codadx6_codecs[] = {
  282. CODA_CODEC(CODADX6_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264, 720, 576),
  283. CODA_CODEC(CODADX6_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 720, 576),
  284. };
  285. static struct coda_codec coda7_codecs[] = {
  286. CODA_CODEC(CODA7_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264, 1280, 720),
  287. CODA_CODEC(CODA7_MODE_ENCODE_MP4, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 1280, 720),
  288. };
  289. static bool coda_format_is_yuv(u32 fourcc)
  290. {
  291. switch (fourcc) {
  292. case V4L2_PIX_FMT_YUV420:
  293. case V4L2_PIX_FMT_YVU420:
  294. return true;
  295. default:
  296. return false;
  297. }
  298. }
  299. /*
  300. * Normalize all supported YUV 4:2:0 formats to the value used in the codec
  301. * tables.
  302. */
  303. static u32 coda_format_normalize_yuv(u32 fourcc)
  304. {
  305. return coda_format_is_yuv(fourcc) ? V4L2_PIX_FMT_YUV420 : fourcc;
  306. }
  307. static struct coda_codec *coda_find_codec(struct coda_dev *dev, int src_fourcc,
  308. int dst_fourcc)
  309. {
  310. struct coda_codec *codecs = dev->devtype->codecs;
  311. int num_codecs = dev->devtype->num_codecs;
  312. int k;
  313. src_fourcc = coda_format_normalize_yuv(src_fourcc);
  314. dst_fourcc = coda_format_normalize_yuv(dst_fourcc);
  315. if (src_fourcc == dst_fourcc)
  316. return NULL;
  317. for (k = 0; k < num_codecs; k++) {
  318. if (codecs[k].src_fourcc == src_fourcc &&
  319. codecs[k].dst_fourcc == dst_fourcc)
  320. break;
  321. }
  322. if (k == num_codecs)
  323. return NULL;
  324. return &codecs[k];
  325. }
  326. /*
  327. * V4L2 ioctl() operations.
  328. */
  329. static int vidioc_querycap(struct file *file, void *priv,
  330. struct v4l2_capability *cap)
  331. {
  332. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  333. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  334. strlcpy(cap->bus_info, "platform:" CODA_NAME, sizeof(cap->bus_info));
  335. /*
  336. * This is only a mem-to-mem video device. The capture and output
  337. * device capability flags are left only for backward compatibility
  338. * and are scheduled for removal.
  339. */
  340. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  341. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  342. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  343. return 0;
  344. }
  345. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  346. enum v4l2_buf_type type)
  347. {
  348. struct coda_ctx *ctx = fh_to_ctx(priv);
  349. struct coda_codec *codecs = ctx->dev->devtype->codecs;
  350. struct coda_fmt *formats = coda_formats;
  351. struct coda_fmt *fmt;
  352. int num_codecs = ctx->dev->devtype->num_codecs;
  353. int num_formats = ARRAY_SIZE(coda_formats);
  354. int i, k, num = 0;
  355. for (i = 0; i < num_formats; i++) {
  356. /* Both uncompressed formats are always supported */
  357. if (coda_format_is_yuv(formats[i].fourcc)) {
  358. if (num == f->index)
  359. break;
  360. ++num;
  361. continue;
  362. }
  363. /* Compressed formats may be supported, check the codec list */
  364. for (k = 0; k < num_codecs; k++) {
  365. if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE &&
  366. formats[i].fourcc == codecs[k].dst_fourcc)
  367. break;
  368. if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT &&
  369. formats[i].fourcc == codecs[k].src_fourcc)
  370. break;
  371. }
  372. if (k < num_codecs) {
  373. if (num == f->index)
  374. break;
  375. ++num;
  376. }
  377. }
  378. if (i < num_formats) {
  379. fmt = &formats[i];
  380. strlcpy(f->description, fmt->name, sizeof(f->description));
  381. f->pixelformat = fmt->fourcc;
  382. return 0;
  383. }
  384. /* Format not found */
  385. return -EINVAL;
  386. }
  387. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  388. struct v4l2_fmtdesc *f)
  389. {
  390. return enum_fmt(priv, f, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  391. }
  392. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  393. struct v4l2_fmtdesc *f)
  394. {
  395. return enum_fmt(priv, f, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  396. }
  397. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  398. {
  399. struct vb2_queue *vq;
  400. struct coda_q_data *q_data;
  401. struct coda_ctx *ctx = fh_to_ctx(priv);
  402. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  403. if (!vq)
  404. return -EINVAL;
  405. q_data = get_q_data(ctx, f->type);
  406. f->fmt.pix.field = V4L2_FIELD_NONE;
  407. f->fmt.pix.pixelformat = q_data->fourcc;
  408. f->fmt.pix.width = q_data->width;
  409. f->fmt.pix.height = q_data->height;
  410. if (coda_format_is_yuv(f->fmt.pix.pixelformat))
  411. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  412. else /* encoded formats h.264/mpeg4 */
  413. f->fmt.pix.bytesperline = 0;
  414. f->fmt.pix.sizeimage = q_data->sizeimage;
  415. f->fmt.pix.colorspace = ctx->colorspace;
  416. return 0;
  417. }
  418. static int vidioc_try_fmt(struct coda_codec *codec, struct v4l2_format *f)
  419. {
  420. unsigned int max_w, max_h;
  421. enum v4l2_field field;
  422. field = f->fmt.pix.field;
  423. if (field == V4L2_FIELD_ANY)
  424. field = V4L2_FIELD_NONE;
  425. else if (V4L2_FIELD_NONE != field)
  426. return -EINVAL;
  427. /* V4L2 specification suggests the driver corrects the format struct
  428. * if any of the dimensions is unsupported */
  429. f->fmt.pix.field = field;
  430. if (codec) {
  431. max_w = codec->max_w;
  432. max_h = codec->max_h;
  433. } else {
  434. max_w = MAX_W;
  435. max_h = MAX_H;
  436. }
  437. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, max_w,
  438. W_ALIGN, &f->fmt.pix.height,
  439. MIN_H, max_h, H_ALIGN, S_ALIGN);
  440. if (coda_format_is_yuv(f->fmt.pix.pixelformat)) {
  441. /* Frame stride must be multiple of 8 */
  442. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 8);
  443. f->fmt.pix.sizeimage = f->fmt.pix.bytesperline *
  444. f->fmt.pix.height * 3 / 2;
  445. } else { /*encoded formats h.264/mpeg4 */
  446. f->fmt.pix.bytesperline = 0;
  447. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  448. }
  449. return 0;
  450. }
  451. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  452. struct v4l2_format *f)
  453. {
  454. struct coda_ctx *ctx = fh_to_ctx(priv);
  455. struct coda_codec *codec = NULL;
  456. /* Determine codec by the encoded format */
  457. codec = coda_find_codec(ctx->dev, V4L2_PIX_FMT_YUV420,
  458. f->fmt.pix.pixelformat);
  459. f->fmt.pix.colorspace = ctx->colorspace;
  460. return vidioc_try_fmt(codec, f);
  461. }
  462. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  463. struct v4l2_format *f)
  464. {
  465. struct coda_ctx *ctx = fh_to_ctx(priv);
  466. struct coda_codec *codec;
  467. /* Determine codec by encoded format, returns NULL if raw or invalid */
  468. codec = coda_find_codec(ctx->dev, f->fmt.pix.pixelformat,
  469. V4L2_PIX_FMT_YUV420);
  470. if (!f->fmt.pix.colorspace)
  471. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  472. return vidioc_try_fmt(codec, f);
  473. }
  474. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  475. {
  476. struct coda_q_data *q_data;
  477. struct vb2_queue *vq;
  478. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  479. if (!vq)
  480. return -EINVAL;
  481. q_data = get_q_data(ctx, f->type);
  482. if (!q_data)
  483. return -EINVAL;
  484. if (vb2_is_busy(vq)) {
  485. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  486. return -EBUSY;
  487. }
  488. q_data->fourcc = f->fmt.pix.pixelformat;
  489. q_data->width = f->fmt.pix.width;
  490. q_data->height = f->fmt.pix.height;
  491. q_data->sizeimage = f->fmt.pix.sizeimage;
  492. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  493. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  494. f->type, q_data->width, q_data->height, q_data->fourcc);
  495. return 0;
  496. }
  497. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  498. struct v4l2_format *f)
  499. {
  500. struct coda_ctx *ctx = fh_to_ctx(priv);
  501. int ret;
  502. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  503. if (ret)
  504. return ret;
  505. return vidioc_s_fmt(ctx, f);
  506. }
  507. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  508. struct v4l2_format *f)
  509. {
  510. struct coda_ctx *ctx = fh_to_ctx(priv);
  511. int ret;
  512. ret = vidioc_try_fmt_vid_out(file, priv, f);
  513. if (ret)
  514. return ret;
  515. ret = vidioc_s_fmt(ctx, f);
  516. if (ret)
  517. ctx->colorspace = f->fmt.pix.colorspace;
  518. return ret;
  519. }
  520. static int vidioc_reqbufs(struct file *file, void *priv,
  521. struct v4l2_requestbuffers *reqbufs)
  522. {
  523. struct coda_ctx *ctx = fh_to_ctx(priv);
  524. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  525. }
  526. static int vidioc_querybuf(struct file *file, void *priv,
  527. struct v4l2_buffer *buf)
  528. {
  529. struct coda_ctx *ctx = fh_to_ctx(priv);
  530. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  531. }
  532. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  533. {
  534. struct coda_ctx *ctx = fh_to_ctx(priv);
  535. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  536. }
  537. static int vidioc_expbuf(struct file *file, void *priv,
  538. struct v4l2_exportbuffer *eb)
  539. {
  540. struct coda_ctx *ctx = fh_to_ctx(priv);
  541. return v4l2_m2m_expbuf(file, ctx->m2m_ctx, eb);
  542. }
  543. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  544. {
  545. struct coda_ctx *ctx = fh_to_ctx(priv);
  546. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  547. }
  548. static int vidioc_create_bufs(struct file *file, void *priv,
  549. struct v4l2_create_buffers *create)
  550. {
  551. struct coda_ctx *ctx = fh_to_ctx(priv);
  552. return v4l2_m2m_create_bufs(file, ctx->m2m_ctx, create);
  553. }
  554. static int vidioc_streamon(struct file *file, void *priv,
  555. enum v4l2_buf_type type)
  556. {
  557. struct coda_ctx *ctx = fh_to_ctx(priv);
  558. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  559. }
  560. static int vidioc_streamoff(struct file *file, void *priv,
  561. enum v4l2_buf_type type)
  562. {
  563. struct coda_ctx *ctx = fh_to_ctx(priv);
  564. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  565. }
  566. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  567. .vidioc_querycap = vidioc_querycap,
  568. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  569. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  570. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  571. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  572. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  573. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  574. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  575. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  576. .vidioc_reqbufs = vidioc_reqbufs,
  577. .vidioc_querybuf = vidioc_querybuf,
  578. .vidioc_qbuf = vidioc_qbuf,
  579. .vidioc_expbuf = vidioc_expbuf,
  580. .vidioc_dqbuf = vidioc_dqbuf,
  581. .vidioc_create_bufs = vidioc_create_bufs,
  582. .vidioc_streamon = vidioc_streamon,
  583. .vidioc_streamoff = vidioc_streamoff,
  584. };
  585. static inline int coda_get_bitstream_payload(struct coda_ctx *ctx)
  586. {
  587. return kfifo_len(&ctx->bitstream_fifo);
  588. }
  589. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  590. {
  591. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  592. struct coda_dev *dev = ctx->dev;
  593. u32 rd_ptr;
  594. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  595. kfifo->out = (kfifo->in & ~kfifo->mask) |
  596. (rd_ptr - ctx->bitstream.paddr);
  597. if (kfifo->out > kfifo->in)
  598. kfifo->out -= kfifo->mask + 1;
  599. }
  600. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  601. {
  602. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  603. struct coda_dev *dev = ctx->dev;
  604. u32 rd_ptr, wr_ptr;
  605. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  606. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  607. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  608. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  609. }
  610. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  611. {
  612. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  613. struct coda_dev *dev = ctx->dev;
  614. u32 wr_ptr;
  615. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  616. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  617. }
  618. static int coda_bitstream_queue(struct coda_ctx *ctx, struct vb2_buffer *src_buf)
  619. {
  620. u32 src_size = vb2_get_plane_payload(src_buf, 0);
  621. u32 n;
  622. n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0), src_size);
  623. if (n < src_size)
  624. return -ENOSPC;
  625. dma_sync_single_for_device(&ctx->dev->plat_dev->dev, ctx->bitstream.paddr,
  626. ctx->bitstream.size, DMA_TO_DEVICE);
  627. ctx->qsequence++;
  628. return 0;
  629. }
  630. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  631. struct vb2_buffer *src_buf)
  632. {
  633. int ret;
  634. if (coda_get_bitstream_payload(ctx) +
  635. vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
  636. return false;
  637. if (vb2_plane_vaddr(src_buf, 0) == NULL) {
  638. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  639. return true;
  640. }
  641. ret = coda_bitstream_queue(ctx, src_buf);
  642. if (ret < 0) {
  643. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  644. return false;
  645. }
  646. /* Sync read pointer to device */
  647. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  648. coda_kfifo_sync_to_device_write(ctx);
  649. return true;
  650. }
  651. static void coda_fill_bitstream(struct coda_ctx *ctx)
  652. {
  653. struct vb2_buffer *src_buf;
  654. while (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) > 0) {
  655. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  656. if (coda_bitstream_try_queue(ctx, src_buf)) {
  657. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  658. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  659. } else {
  660. break;
  661. }
  662. }
  663. }
  664. /*
  665. * Mem-to-mem operations.
  666. */
  667. static void coda_device_run(void *m2m_priv)
  668. {
  669. struct coda_ctx *ctx = m2m_priv;
  670. struct coda_q_data *q_data_src, *q_data_dst;
  671. struct vb2_buffer *src_buf, *dst_buf;
  672. struct coda_dev *dev = ctx->dev;
  673. int force_ipicture;
  674. int quant_param = 0;
  675. u32 picture_y, picture_cb, picture_cr;
  676. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  677. u32 dst_fourcc;
  678. mutex_lock(&dev->coda_mutex);
  679. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  680. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  681. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  682. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  683. dst_fourcc = q_data_dst->fourcc;
  684. src_buf->v4l2_buf.sequence = ctx->isequence;
  685. dst_buf->v4l2_buf.sequence = ctx->isequence;
  686. ctx->isequence++;
  687. /*
  688. * Workaround coda firmware BUG that only marks the first
  689. * frame as IDR. This is a problem for some decoders that can't
  690. * recover when a frame is lost.
  691. */
  692. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  693. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  694. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  695. } else {
  696. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  697. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  698. }
  699. /*
  700. * Copy headers at the beginning of the first frame for H.264 only.
  701. * In MPEG4 they are already copied by the coda.
  702. */
  703. if (src_buf->v4l2_buf.sequence == 0) {
  704. pic_stream_buffer_addr =
  705. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  706. ctx->vpu_header_size[0] +
  707. ctx->vpu_header_size[1] +
  708. ctx->vpu_header_size[2];
  709. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  710. ctx->vpu_header_size[0] -
  711. ctx->vpu_header_size[1] -
  712. ctx->vpu_header_size[2];
  713. memcpy(vb2_plane_vaddr(dst_buf, 0),
  714. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  715. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  716. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  717. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  718. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  719. ctx->vpu_header_size[2]);
  720. } else {
  721. pic_stream_buffer_addr =
  722. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  723. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  724. }
  725. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  726. force_ipicture = 1;
  727. switch (dst_fourcc) {
  728. case V4L2_PIX_FMT_H264:
  729. quant_param = ctx->params.h264_intra_qp;
  730. break;
  731. case V4L2_PIX_FMT_MPEG4:
  732. quant_param = ctx->params.mpeg4_intra_qp;
  733. break;
  734. default:
  735. v4l2_warn(&ctx->dev->v4l2_dev,
  736. "cannot set intra qp, fmt not supported\n");
  737. break;
  738. }
  739. } else {
  740. force_ipicture = 0;
  741. switch (dst_fourcc) {
  742. case V4L2_PIX_FMT_H264:
  743. quant_param = ctx->params.h264_inter_qp;
  744. break;
  745. case V4L2_PIX_FMT_MPEG4:
  746. quant_param = ctx->params.mpeg4_inter_qp;
  747. break;
  748. default:
  749. v4l2_warn(&ctx->dev->v4l2_dev,
  750. "cannot set inter qp, fmt not supported\n");
  751. break;
  752. }
  753. }
  754. /* submit */
  755. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  756. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  757. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  758. switch (q_data_src->fourcc) {
  759. case V4L2_PIX_FMT_YVU420:
  760. /* Switch Cb and Cr for YVU420 format */
  761. picture_cr = picture_y + q_data_src->width * q_data_src->height;
  762. picture_cb = picture_cr + q_data_src->width / 2 *
  763. q_data_src->height / 2;
  764. break;
  765. case V4L2_PIX_FMT_YUV420:
  766. default:
  767. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  768. picture_cr = picture_cb + q_data_src->width / 2 *
  769. q_data_src->height / 2;
  770. break;
  771. }
  772. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  773. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  774. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  775. coda_write(dev, force_ipicture << 1 & 0x2,
  776. CODA_CMD_ENC_PIC_OPTION);
  777. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  778. coda_write(dev, pic_stream_buffer_size / 1024,
  779. CODA_CMD_ENC_PIC_BB_SIZE);
  780. if (dev->devtype->product == CODA_7541) {
  781. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  782. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  783. CODA7_REG_BIT_AXI_SRAM_USE);
  784. }
  785. if (dev->devtype->product != CODA_DX6)
  786. coda_write(dev, ctx->iram_info.axi_sram_use,
  787. CODA7_REG_BIT_AXI_SRAM_USE);
  788. /* 1 second timeout in case CODA locks up */
  789. schedule_delayed_work(&dev->timeout, HZ);
  790. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  791. }
  792. static int coda_job_ready(void *m2m_priv)
  793. {
  794. struct coda_ctx *ctx = m2m_priv;
  795. /*
  796. * For both 'P' and 'key' frame cases 1 picture
  797. * and 1 frame are needed. In the decoder case,
  798. * the compressed frame can be in the bitstream.
  799. */
  800. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) &&
  801. ctx->inst_type != CODA_INST_DECODER) {
  802. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  803. "not ready: not enough video buffers.\n");
  804. return 0;
  805. }
  806. if (!v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  807. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  808. "not ready: not enough video capture buffers.\n");
  809. return 0;
  810. }
  811. if (ctx->aborting) {
  812. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  813. "not ready: aborting\n");
  814. return 0;
  815. }
  816. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  817. "job ready\n");
  818. return 1;
  819. }
  820. static void coda_job_abort(void *priv)
  821. {
  822. struct coda_ctx *ctx = priv;
  823. ctx->aborting = 1;
  824. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  825. "Aborting task\n");
  826. }
  827. static void coda_lock(void *m2m_priv)
  828. {
  829. struct coda_ctx *ctx = m2m_priv;
  830. struct coda_dev *pcdev = ctx->dev;
  831. mutex_lock(&pcdev->dev_mutex);
  832. }
  833. static void coda_unlock(void *m2m_priv)
  834. {
  835. struct coda_ctx *ctx = m2m_priv;
  836. struct coda_dev *pcdev = ctx->dev;
  837. mutex_unlock(&pcdev->dev_mutex);
  838. }
  839. static struct v4l2_m2m_ops coda_m2m_ops = {
  840. .device_run = coda_device_run,
  841. .job_ready = coda_job_ready,
  842. .job_abort = coda_job_abort,
  843. .lock = coda_lock,
  844. .unlock = coda_unlock,
  845. };
  846. static void set_default_params(struct coda_ctx *ctx)
  847. {
  848. int max_w;
  849. int max_h;
  850. ctx->codec = &ctx->dev->devtype->codecs[0];
  851. max_w = ctx->codec->max_w;
  852. max_h = ctx->codec->max_h;
  853. ctx->params.codec_mode = CODA_MODE_INVALID;
  854. ctx->colorspace = V4L2_COLORSPACE_REC709;
  855. ctx->params.framerate = 30;
  856. ctx->aborting = 0;
  857. /* Default formats for output and input queues */
  858. ctx->q_data[V4L2_M2M_SRC].fourcc = ctx->codec->src_fourcc;
  859. ctx->q_data[V4L2_M2M_DST].fourcc = ctx->codec->dst_fourcc;
  860. ctx->q_data[V4L2_M2M_SRC].width = max_w;
  861. ctx->q_data[V4L2_M2M_SRC].height = max_h;
  862. ctx->q_data[V4L2_M2M_SRC].sizeimage = (max_w * max_h * 3) / 2;
  863. ctx->q_data[V4L2_M2M_DST].width = max_w;
  864. ctx->q_data[V4L2_M2M_DST].height = max_h;
  865. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  866. }
  867. /*
  868. * Queue operations
  869. */
  870. static int coda_queue_setup(struct vb2_queue *vq,
  871. const struct v4l2_format *fmt,
  872. unsigned int *nbuffers, unsigned int *nplanes,
  873. unsigned int sizes[], void *alloc_ctxs[])
  874. {
  875. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  876. struct coda_q_data *q_data;
  877. unsigned int size;
  878. q_data = get_q_data(ctx, vq->type);
  879. size = q_data->sizeimage;
  880. *nplanes = 1;
  881. sizes[0] = size;
  882. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  883. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  884. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  885. return 0;
  886. }
  887. static int coda_buf_prepare(struct vb2_buffer *vb)
  888. {
  889. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  890. struct coda_q_data *q_data;
  891. q_data = get_q_data(ctx, vb->vb2_queue->type);
  892. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  893. v4l2_warn(&ctx->dev->v4l2_dev,
  894. "%s data will not fit into plane (%lu < %lu)\n",
  895. __func__, vb2_plane_size(vb, 0),
  896. (long)q_data->sizeimage);
  897. return -EINVAL;
  898. }
  899. return 0;
  900. }
  901. static void coda_buf_queue(struct vb2_buffer *vb)
  902. {
  903. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  904. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  905. }
  906. static void coda_wait_prepare(struct vb2_queue *q)
  907. {
  908. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  909. coda_unlock(ctx);
  910. }
  911. static void coda_wait_finish(struct vb2_queue *q)
  912. {
  913. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  914. coda_lock(ctx);
  915. }
  916. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  917. {
  918. struct coda_dev *dev = ctx->dev;
  919. u32 *p = ctx->parabuf.vaddr;
  920. if (dev->devtype->product == CODA_DX6)
  921. p[index] = value;
  922. else
  923. p[index ^ 1] = value;
  924. }
  925. static int coda_alloc_aux_buf(struct coda_dev *dev,
  926. struct coda_aux_buf *buf, size_t size)
  927. {
  928. buf->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size, &buf->paddr,
  929. GFP_KERNEL);
  930. if (!buf->vaddr)
  931. return -ENOMEM;
  932. buf->size = size;
  933. return 0;
  934. }
  935. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  936. struct coda_aux_buf *buf, size_t size)
  937. {
  938. return coda_alloc_aux_buf(ctx->dev, buf, size);
  939. }
  940. static void coda_free_aux_buf(struct coda_dev *dev,
  941. struct coda_aux_buf *buf)
  942. {
  943. if (buf->vaddr) {
  944. dma_free_coherent(&dev->plat_dev->dev, buf->size,
  945. buf->vaddr, buf->paddr);
  946. buf->vaddr = NULL;
  947. buf->size = 0;
  948. }
  949. }
  950. static void coda_free_framebuffers(struct coda_ctx *ctx)
  951. {
  952. int i;
  953. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  954. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  955. }
  956. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  957. {
  958. struct coda_dev *dev = ctx->dev;
  959. int height = q_data->height;
  960. dma_addr_t paddr;
  961. int ysize;
  962. int ret;
  963. int i;
  964. if (ctx->codec && ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
  965. height = round_up(height, 16);
  966. ysize = round_up(q_data->width, 8) * height;
  967. /* Allocate frame buffers */
  968. for (i = 0; i < ctx->num_internal_frames; i++) {
  969. size_t size;
  970. size = q_data->sizeimage;
  971. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  972. dev->devtype->product != CODA_DX6)
  973. ctx->internal_frames[i].size += ysize/4;
  974. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i], size);
  975. if (ret < 0) {
  976. coda_free_framebuffers(ctx);
  977. return ret;
  978. }
  979. }
  980. /* Register frame buffers in the parameter buffer */
  981. for (i = 0; i < ctx->num_internal_frames; i++) {
  982. paddr = ctx->internal_frames[i].paddr;
  983. coda_parabuf_write(ctx, i * 3 + 0, paddr); /* Y */
  984. coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize); /* Cb */
  985. coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize/4); /* Cr */
  986. /* mvcol buffer for h.264 */
  987. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  988. dev->devtype->product != CODA_DX6)
  989. coda_parabuf_write(ctx, 96 + i,
  990. ctx->internal_frames[i].paddr +
  991. ysize + ysize/4 + ysize/4);
  992. }
  993. /* mvcol buffer for mpeg4 */
  994. if ((dev->devtype->product != CODA_DX6) &&
  995. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  996. coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
  997. ysize + ysize/4 + ysize/4);
  998. return 0;
  999. }
  1000. static int coda_h264_padding(int size, char *p)
  1001. {
  1002. int nal_size;
  1003. int diff;
  1004. diff = size - (size & ~0x7);
  1005. if (diff == 0)
  1006. return 0;
  1007. nal_size = coda_filler_size[diff];
  1008. memcpy(p, coda_filler_nal, nal_size);
  1009. /* Add rbsp stop bit and trailing at the end */
  1010. *(p + nal_size - 1) = 0x80;
  1011. return nal_size;
  1012. }
  1013. static void coda_setup_iram(struct coda_ctx *ctx)
  1014. {
  1015. struct coda_iram_info *iram_info = &ctx->iram_info;
  1016. struct coda_dev *dev = ctx->dev;
  1017. int ipacdc_size;
  1018. int bitram_size;
  1019. int dbk_size;
  1020. int ovl_size;
  1021. int mb_width;
  1022. int me_size;
  1023. int size;
  1024. memset(iram_info, 0, sizeof(*iram_info));
  1025. size = dev->iram_size;
  1026. if (dev->devtype->product == CODA_DX6)
  1027. return;
  1028. if (ctx->inst_type == CODA_INST_ENCODER) {
  1029. struct coda_q_data *q_data_src;
  1030. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1031. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  1032. /* Prioritize in case IRAM is too small for everything */
  1033. me_size = round_up(round_up(q_data_src->width, 16) * 36 + 2048,
  1034. 1024);
  1035. iram_info->search_ram_size = me_size;
  1036. if (size >= iram_info->search_ram_size) {
  1037. if (dev->devtype->product == CODA_7541)
  1038. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE;
  1039. iram_info->search_ram_paddr = dev->iram_paddr;
  1040. size -= iram_info->search_ram_size;
  1041. } else {
  1042. pr_err("IRAM is smaller than the search ram size\n");
  1043. goto out;
  1044. }
  1045. /* Only H.264BP and H.263P3 are considered */
  1046. dbk_size = round_up(128 * mb_width, 1024);
  1047. if (size >= dbk_size) {
  1048. iram_info->axi_sram_use |= CODA7_USE_HOST_DBK_ENABLE;
  1049. iram_info->buf_dbk_y_use = dev->iram_paddr +
  1050. iram_info->search_ram_size;
  1051. iram_info->buf_dbk_c_use = iram_info->buf_dbk_y_use +
  1052. dbk_size / 2;
  1053. size -= dbk_size;
  1054. } else {
  1055. goto out;
  1056. }
  1057. bitram_size = round_up(128 * mb_width, 1024);
  1058. if (size >= bitram_size) {
  1059. iram_info->axi_sram_use |= CODA7_USE_HOST_BIT_ENABLE;
  1060. iram_info->buf_bit_use = iram_info->buf_dbk_c_use +
  1061. dbk_size / 2;
  1062. size -= bitram_size;
  1063. } else {
  1064. goto out;
  1065. }
  1066. ipacdc_size = round_up(128 * mb_width, 1024);
  1067. if (size >= ipacdc_size) {
  1068. iram_info->axi_sram_use |= CODA7_USE_HOST_IP_ENABLE;
  1069. iram_info->buf_ip_ac_dc_use = iram_info->buf_bit_use +
  1070. bitram_size;
  1071. size -= ipacdc_size;
  1072. }
  1073. /* OVL and BTP disabled for encoder */
  1074. } else if (ctx->inst_type == CODA_INST_DECODER) {
  1075. struct coda_q_data *q_data_dst;
  1076. int mb_height;
  1077. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1078. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  1079. mb_height = DIV_ROUND_UP(q_data_dst->height, 16);
  1080. dbk_size = round_up(256 * mb_width, 1024);
  1081. if (size >= dbk_size) {
  1082. iram_info->axi_sram_use |= CODA7_USE_HOST_DBK_ENABLE;
  1083. iram_info->buf_dbk_y_use = dev->iram_paddr;
  1084. iram_info->buf_dbk_c_use = dev->iram_paddr +
  1085. dbk_size / 2;
  1086. size -= dbk_size;
  1087. } else {
  1088. goto out;
  1089. }
  1090. bitram_size = round_up(128 * mb_width, 1024);
  1091. if (size >= bitram_size) {
  1092. iram_info->axi_sram_use |= CODA7_USE_HOST_BIT_ENABLE;
  1093. iram_info->buf_bit_use = iram_info->buf_dbk_c_use +
  1094. dbk_size / 2;
  1095. size -= bitram_size;
  1096. } else {
  1097. goto out;
  1098. }
  1099. ipacdc_size = round_up(128 * mb_width, 1024);
  1100. if (size >= ipacdc_size) {
  1101. iram_info->axi_sram_use |= CODA7_USE_HOST_IP_ENABLE;
  1102. iram_info->buf_ip_ac_dc_use = iram_info->buf_bit_use +
  1103. bitram_size;
  1104. size -= ipacdc_size;
  1105. } else {
  1106. goto out;
  1107. }
  1108. ovl_size = round_up(80 * mb_width, 1024);
  1109. }
  1110. out:
  1111. switch (dev->devtype->product) {
  1112. case CODA_DX6:
  1113. break;
  1114. case CODA_7541:
  1115. /* i.MX53 uses secondary AXI for IRAM access */
  1116. if (iram_info->axi_sram_use & CODA7_USE_HOST_BIT_ENABLE)
  1117. iram_info->axi_sram_use |= CODA7_USE_BIT_ENABLE;
  1118. if (iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE)
  1119. iram_info->axi_sram_use |= CODA7_USE_IP_ENABLE;
  1120. if (iram_info->axi_sram_use & CODA7_USE_HOST_DBK_ENABLE)
  1121. iram_info->axi_sram_use |= CODA7_USE_DBK_ENABLE;
  1122. if (iram_info->axi_sram_use & CODA7_USE_HOST_OVL_ENABLE)
  1123. iram_info->axi_sram_use |= CODA7_USE_OVL_ENABLE;
  1124. if (iram_info->axi_sram_use & CODA7_USE_HOST_ME_ENABLE)
  1125. iram_info->axi_sram_use |= CODA7_USE_ME_ENABLE;
  1126. }
  1127. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  1128. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1129. "IRAM smaller than needed\n");
  1130. if (dev->devtype->product == CODA_7541) {
  1131. /* TODO - Enabling these causes picture errors on CODA7541 */
  1132. if (ctx->inst_type == CODA_INST_DECODER) {
  1133. /* fw 1.4.50 */
  1134. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  1135. CODA7_USE_IP_ENABLE);
  1136. } else {
  1137. /* fw 13.4.29 */
  1138. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  1139. CODA7_USE_HOST_DBK_ENABLE |
  1140. CODA7_USE_IP_ENABLE |
  1141. CODA7_USE_DBK_ENABLE);
  1142. }
  1143. }
  1144. }
  1145. static void coda_free_context_buffers(struct coda_ctx *ctx)
  1146. {
  1147. struct coda_dev *dev = ctx->dev;
  1148. if (dev->devtype->product != CODA_DX6)
  1149. coda_free_aux_buf(dev, &ctx->workbuf);
  1150. }
  1151. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  1152. struct coda_q_data *q_data)
  1153. {
  1154. struct coda_dev *dev = ctx->dev;
  1155. size_t size;
  1156. int ret;
  1157. switch (dev->devtype->product) {
  1158. case CODA_7541:
  1159. size = CODA7_WORK_BUF_SIZE;
  1160. break;
  1161. default:
  1162. return 0;
  1163. }
  1164. if (ctx->workbuf.vaddr) {
  1165. v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
  1166. ret = -EBUSY;
  1167. return -ENOMEM;
  1168. }
  1169. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size);
  1170. if (ret < 0) {
  1171. v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte context buffer",
  1172. ctx->workbuf.size);
  1173. goto err;
  1174. }
  1175. return 0;
  1176. err:
  1177. coda_free_context_buffers(ctx);
  1178. return ret;
  1179. }
  1180. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
  1181. int header_code, u8 *header, int *size)
  1182. {
  1183. struct coda_dev *dev = ctx->dev;
  1184. int ret;
  1185. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
  1186. CODA_CMD_ENC_HEADER_BB_START);
  1187. coda_write(dev, vb2_plane_size(buf, 0), CODA_CMD_ENC_HEADER_BB_SIZE);
  1188. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  1189. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  1190. if (ret < 0) {
  1191. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1192. return ret;
  1193. }
  1194. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  1195. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1196. memcpy(header, vb2_plane_vaddr(buf, 0), *size);
  1197. return 0;
  1198. }
  1199. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  1200. {
  1201. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1202. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  1203. u32 bitstream_buf, bitstream_size;
  1204. struct coda_dev *dev = ctx->dev;
  1205. struct coda_q_data *q_data_src, *q_data_dst;
  1206. struct vb2_buffer *buf;
  1207. u32 dst_fourcc;
  1208. u32 value;
  1209. int ret = 0;
  1210. if (count < 1)
  1211. return -EINVAL;
  1212. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1213. ctx->streamon_out = 1;
  1214. else
  1215. ctx->streamon_cap = 1;
  1216. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1217. if (ctx->streamon_out) {
  1218. if (coda_format_is_yuv(q_data_src->fourcc))
  1219. ctx->inst_type = CODA_INST_ENCODER;
  1220. else
  1221. ctx->inst_type = CODA_INST_DECODER;
  1222. }
  1223. /* Don't start the coda unless both queues are on */
  1224. if (!(ctx->streamon_out & ctx->streamon_cap))
  1225. return 0;
  1226. ctx->gopcounter = ctx->params.gop_size - 1;
  1227. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  1228. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  1229. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1230. bitstream_size = q_data_dst->sizeimage;
  1231. dst_fourcc = q_data_dst->fourcc;
  1232. ctx->codec = coda_find_codec(ctx->dev, q_data_src->fourcc,
  1233. q_data_dst->fourcc);
  1234. if (!ctx->codec) {
  1235. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  1236. return -EINVAL;
  1237. }
  1238. /* Allocate per-instance buffers */
  1239. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1240. if (ret < 0)
  1241. return ret;
  1242. if (!coda_is_initialized(dev)) {
  1243. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  1244. return -EFAULT;
  1245. }
  1246. mutex_lock(&dev->coda_mutex);
  1247. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1248. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  1249. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1250. switch (dev->devtype->product) {
  1251. case CODA_DX6:
  1252. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  1253. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  1254. break;
  1255. default:
  1256. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  1257. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  1258. }
  1259. if (dev->devtype->product == CODA_DX6) {
  1260. /* Configure the coda */
  1261. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  1262. }
  1263. /* Could set rotation here if needed */
  1264. switch (dev->devtype->product) {
  1265. case CODA_DX6:
  1266. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  1267. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  1268. break;
  1269. default:
  1270. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  1271. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  1272. }
  1273. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  1274. coda_write(dev, ctx->params.framerate,
  1275. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  1276. ctx->params.codec_mode = ctx->codec->mode;
  1277. switch (dst_fourcc) {
  1278. case V4L2_PIX_FMT_MPEG4:
  1279. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  1280. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  1281. break;
  1282. case V4L2_PIX_FMT_H264:
  1283. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  1284. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  1285. break;
  1286. default:
  1287. v4l2_err(v4l2_dev,
  1288. "dst format (0x%08x) invalid.\n", dst_fourcc);
  1289. ret = -EINVAL;
  1290. goto out;
  1291. }
  1292. switch (ctx->params.slice_mode) {
  1293. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  1294. value = 0;
  1295. break;
  1296. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  1297. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  1298. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  1299. value |= 1 & CODA_SLICING_MODE_MASK;
  1300. break;
  1301. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  1302. value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  1303. value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  1304. value |= 1 & CODA_SLICING_MODE_MASK;
  1305. break;
  1306. }
  1307. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  1308. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  1309. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  1310. if (ctx->params.bitrate) {
  1311. /* Rate control enabled */
  1312. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  1313. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  1314. } else {
  1315. value = 0;
  1316. }
  1317. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  1318. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  1319. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  1320. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  1321. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  1322. /* set default gamma */
  1323. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  1324. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  1325. if (CODA_DEFAULT_GAMMA > 0) {
  1326. if (dev->devtype->product == CODA_DX6)
  1327. value = 1 << CODADX6_OPTION_GAMMA_OFFSET;
  1328. else
  1329. value = 1 << CODA7_OPTION_GAMMA_OFFSET;
  1330. } else {
  1331. value = 0;
  1332. }
  1333. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  1334. coda_setup_iram(ctx);
  1335. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  1336. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  1337. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  1338. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  1339. if (dev->devtype->product == CODA_DX6) {
  1340. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  1341. } else {
  1342. coda_write(dev, ctx->iram_info.search_ram_paddr,
  1343. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  1344. coda_write(dev, ctx->iram_info.search_ram_size,
  1345. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  1346. }
  1347. }
  1348. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  1349. if (ret < 0) {
  1350. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1351. goto out;
  1352. }
  1353. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  1354. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  1355. ret = -EFAULT;
  1356. goto out;
  1357. }
  1358. ctx->num_internal_frames = 2;
  1359. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  1360. if (ret < 0) {
  1361. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  1362. goto out;
  1363. }
  1364. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1365. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  1366. if (dev->devtype->product != CODA_DX6) {
  1367. coda_write(dev, ctx->iram_info.buf_bit_use,
  1368. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1369. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1370. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1371. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1372. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1373. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1374. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1375. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1376. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1377. }
  1378. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  1379. if (ret < 0) {
  1380. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1381. goto out;
  1382. }
  1383. /* Save stream headers */
  1384. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  1385. switch (dst_fourcc) {
  1386. case V4L2_PIX_FMT_H264:
  1387. /*
  1388. * Get SPS in the first frame and copy it to an
  1389. * intermediate buffer.
  1390. */
  1391. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  1392. &ctx->vpu_header[0][0],
  1393. &ctx->vpu_header_size[0]);
  1394. if (ret < 0)
  1395. goto out;
  1396. /*
  1397. * Get PPS in the first frame and copy it to an
  1398. * intermediate buffer.
  1399. */
  1400. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  1401. &ctx->vpu_header[1][0],
  1402. &ctx->vpu_header_size[1]);
  1403. if (ret < 0)
  1404. goto out;
  1405. /*
  1406. * Length of H.264 headers is variable and thus it might not be
  1407. * aligned for the coda to append the encoded frame. In that is
  1408. * the case a filler NAL must be added to header 2.
  1409. */
  1410. ctx->vpu_header_size[2] = coda_h264_padding(
  1411. (ctx->vpu_header_size[0] +
  1412. ctx->vpu_header_size[1]),
  1413. ctx->vpu_header[2]);
  1414. break;
  1415. case V4L2_PIX_FMT_MPEG4:
  1416. /*
  1417. * Get VOS in the first frame and copy it to an
  1418. * intermediate buffer
  1419. */
  1420. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  1421. &ctx->vpu_header[0][0],
  1422. &ctx->vpu_header_size[0]);
  1423. if (ret < 0)
  1424. goto out;
  1425. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  1426. &ctx->vpu_header[1][0],
  1427. &ctx->vpu_header_size[1]);
  1428. if (ret < 0)
  1429. goto out;
  1430. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  1431. &ctx->vpu_header[2][0],
  1432. &ctx->vpu_header_size[2]);
  1433. if (ret < 0)
  1434. goto out;
  1435. break;
  1436. default:
  1437. /* No more formats need to save headers at the moment */
  1438. break;
  1439. }
  1440. out:
  1441. mutex_unlock(&dev->coda_mutex);
  1442. return ret;
  1443. }
  1444. static int coda_stop_streaming(struct vb2_queue *q)
  1445. {
  1446. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1447. struct coda_dev *dev = ctx->dev;
  1448. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1449. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1450. "%s: output\n", __func__);
  1451. ctx->streamon_out = 0;
  1452. } else {
  1453. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1454. "%s: capture\n", __func__);
  1455. ctx->streamon_cap = 0;
  1456. }
  1457. /* Don't stop the coda unless both queues are off */
  1458. if (ctx->streamon_out || ctx->streamon_cap)
  1459. return 0;
  1460. cancel_delayed_work(&dev->timeout);
  1461. mutex_lock(&dev->coda_mutex);
  1462. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1463. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1464. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1465. v4l2_err(&dev->v4l2_dev,
  1466. "CODA_COMMAND_SEQ_END failed\n");
  1467. return -ETIMEDOUT;
  1468. }
  1469. mutex_unlock(&dev->coda_mutex);
  1470. coda_free_framebuffers(ctx);
  1471. return 0;
  1472. }
  1473. static struct vb2_ops coda_qops = {
  1474. .queue_setup = coda_queue_setup,
  1475. .buf_prepare = coda_buf_prepare,
  1476. .buf_queue = coda_buf_queue,
  1477. .wait_prepare = coda_wait_prepare,
  1478. .wait_finish = coda_wait_finish,
  1479. .start_streaming = coda_start_streaming,
  1480. .stop_streaming = coda_stop_streaming,
  1481. };
  1482. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1483. {
  1484. struct coda_ctx *ctx =
  1485. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1486. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1487. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1488. switch (ctrl->id) {
  1489. case V4L2_CID_HFLIP:
  1490. if (ctrl->val)
  1491. ctx->params.rot_mode |= CODA_MIR_HOR;
  1492. else
  1493. ctx->params.rot_mode &= ~CODA_MIR_HOR;
  1494. break;
  1495. case V4L2_CID_VFLIP:
  1496. if (ctrl->val)
  1497. ctx->params.rot_mode |= CODA_MIR_VER;
  1498. else
  1499. ctx->params.rot_mode &= ~CODA_MIR_VER;
  1500. break;
  1501. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1502. ctx->params.bitrate = ctrl->val / 1000;
  1503. break;
  1504. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1505. ctx->params.gop_size = ctrl->val;
  1506. break;
  1507. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1508. ctx->params.h264_intra_qp = ctrl->val;
  1509. break;
  1510. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1511. ctx->params.h264_inter_qp = ctrl->val;
  1512. break;
  1513. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1514. ctx->params.mpeg4_intra_qp = ctrl->val;
  1515. break;
  1516. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1517. ctx->params.mpeg4_inter_qp = ctrl->val;
  1518. break;
  1519. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1520. ctx->params.slice_mode = ctrl->val;
  1521. break;
  1522. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1523. ctx->params.slice_max_mb = ctrl->val;
  1524. break;
  1525. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
  1526. ctx->params.slice_max_bits = ctrl->val * 8;
  1527. break;
  1528. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1529. break;
  1530. default:
  1531. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1532. "Invalid control, id=%d, val=%d\n",
  1533. ctrl->id, ctrl->val);
  1534. return -EINVAL;
  1535. }
  1536. return 0;
  1537. }
  1538. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1539. .s_ctrl = coda_s_ctrl,
  1540. };
  1541. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1542. {
  1543. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1544. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1545. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1546. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1547. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1548. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1549. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1550. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1551. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1552. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1553. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1554. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1555. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1556. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1557. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1558. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1559. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1560. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1561. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1562. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
  1563. V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
  1564. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1565. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1566. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1567. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
  1568. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1569. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1570. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1571. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1572. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1573. if (ctx->ctrls.error) {
  1574. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1575. ctx->ctrls.error);
  1576. return -EINVAL;
  1577. }
  1578. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1579. }
  1580. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1581. struct vb2_queue *dst_vq)
  1582. {
  1583. struct coda_ctx *ctx = priv;
  1584. int ret;
  1585. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1586. src_vq->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
  1587. src_vq->drv_priv = ctx;
  1588. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1589. src_vq->ops = &coda_qops;
  1590. src_vq->mem_ops = &vb2_dma_contig_memops;
  1591. src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  1592. ret = vb2_queue_init(src_vq);
  1593. if (ret)
  1594. return ret;
  1595. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1596. dst_vq->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
  1597. dst_vq->drv_priv = ctx;
  1598. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1599. dst_vq->ops = &coda_qops;
  1600. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1601. dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
  1602. return vb2_queue_init(dst_vq);
  1603. }
  1604. static int coda_next_free_instance(struct coda_dev *dev)
  1605. {
  1606. return ffz(dev->instance_mask);
  1607. }
  1608. static int coda_open(struct file *file)
  1609. {
  1610. struct coda_dev *dev = video_drvdata(file);
  1611. struct coda_ctx *ctx = NULL;
  1612. int ret = 0;
  1613. int idx;
  1614. idx = coda_next_free_instance(dev);
  1615. if (idx >= CODA_MAX_INSTANCES)
  1616. return -EBUSY;
  1617. set_bit(idx, &dev->instance_mask);
  1618. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1619. if (!ctx)
  1620. return -ENOMEM;
  1621. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1622. file->private_data = &ctx->fh;
  1623. v4l2_fh_add(&ctx->fh);
  1624. ctx->dev = dev;
  1625. ctx->idx = idx;
  1626. switch (dev->devtype->product) {
  1627. case CODA_7541:
  1628. ctx->reg_idx = 0;
  1629. break;
  1630. default:
  1631. ctx->reg_idx = idx;
  1632. }
  1633. set_default_params(ctx);
  1634. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1635. &coda_queue_init);
  1636. if (IS_ERR(ctx->m2m_ctx)) {
  1637. ret = PTR_ERR(ctx->m2m_ctx);
  1638. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1639. __func__, ret);
  1640. goto err;
  1641. }
  1642. ret = coda_ctrls_setup(ctx);
  1643. if (ret) {
  1644. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1645. goto err;
  1646. }
  1647. ctx->fh.ctrl_handler = &ctx->ctrls;
  1648. ret = coda_alloc_context_buf(ctx, &ctx->parabuf, CODA_PARA_BUF_SIZE);
  1649. if (ret < 0) {
  1650. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1651. goto err;
  1652. }
  1653. ctx->bitstream.size = CODA_MAX_FRAME_SIZE;
  1654. ctx->bitstream.vaddr = dma_alloc_writecombine(&dev->plat_dev->dev,
  1655. ctx->bitstream.size, &ctx->bitstream.paddr, GFP_KERNEL);
  1656. if (!ctx->bitstream.vaddr) {
  1657. v4l2_err(&dev->v4l2_dev, "failed to allocate bitstream ringbuffer");
  1658. ret = -ENOMEM;
  1659. goto err;
  1660. }
  1661. kfifo_init(&ctx->bitstream_fifo,
  1662. ctx->bitstream.vaddr, ctx->bitstream.size);
  1663. mutex_init(&ctx->bitstream_mutex);
  1664. coda_lock(ctx);
  1665. list_add(&ctx->list, &dev->instances);
  1666. coda_unlock(ctx);
  1667. clk_prepare_enable(dev->clk_per);
  1668. clk_prepare_enable(dev->clk_ahb);
  1669. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1670. ctx->idx, ctx);
  1671. return 0;
  1672. err:
  1673. v4l2_fh_del(&ctx->fh);
  1674. v4l2_fh_exit(&ctx->fh);
  1675. kfree(ctx);
  1676. return ret;
  1677. }
  1678. static int coda_release(struct file *file)
  1679. {
  1680. struct coda_dev *dev = video_drvdata(file);
  1681. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1682. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1683. ctx);
  1684. coda_lock(ctx);
  1685. list_del(&ctx->list);
  1686. coda_unlock(ctx);
  1687. dma_free_writecombine(&dev->plat_dev->dev, ctx->bitstream.size,
  1688. ctx->bitstream.vaddr, ctx->bitstream.paddr);
  1689. coda_free_context_buffers(ctx);
  1690. if (ctx->dev->devtype->product == CODA_DX6)
  1691. coda_free_aux_buf(dev, &ctx->workbuf);
  1692. coda_free_aux_buf(dev, &ctx->parabuf);
  1693. v4l2_ctrl_handler_free(&ctx->ctrls);
  1694. clk_disable_unprepare(dev->clk_per);
  1695. clk_disable_unprepare(dev->clk_ahb);
  1696. v4l2_fh_del(&ctx->fh);
  1697. v4l2_fh_exit(&ctx->fh);
  1698. clear_bit(ctx->idx, &dev->instance_mask);
  1699. kfree(ctx);
  1700. return 0;
  1701. }
  1702. static unsigned int coda_poll(struct file *file,
  1703. struct poll_table_struct *wait)
  1704. {
  1705. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1706. int ret;
  1707. coda_lock(ctx);
  1708. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1709. coda_unlock(ctx);
  1710. return ret;
  1711. }
  1712. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1713. {
  1714. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1715. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1716. }
  1717. static const struct v4l2_file_operations coda_fops = {
  1718. .owner = THIS_MODULE,
  1719. .open = coda_open,
  1720. .release = coda_release,
  1721. .poll = coda_poll,
  1722. .unlocked_ioctl = video_ioctl2,
  1723. .mmap = coda_mmap,
  1724. };
  1725. static irqreturn_t coda_irq_handler(int irq, void *data)
  1726. {
  1727. struct vb2_buffer *src_buf, *dst_buf;
  1728. struct coda_dev *dev = data;
  1729. u32 wr_ptr, start_ptr;
  1730. struct coda_ctx *ctx;
  1731. cancel_delayed_work(&dev->timeout);
  1732. /* read status register to attend the IRQ */
  1733. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1734. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1735. CODA_REG_BIT_INT_CLEAR);
  1736. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1737. if (ctx == NULL) {
  1738. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1739. mutex_unlock(&dev->coda_mutex);
  1740. return IRQ_HANDLED;
  1741. }
  1742. if (ctx->aborting) {
  1743. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1744. "task has been aborted\n");
  1745. mutex_unlock(&dev->coda_mutex);
  1746. return IRQ_HANDLED;
  1747. }
  1748. if (coda_isbusy(ctx->dev)) {
  1749. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1750. "coda is still busy!!!!\n");
  1751. return IRQ_NONE;
  1752. }
  1753. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1754. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1755. /* Get results from the coda */
  1756. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1757. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1758. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1759. /* Calculate bytesused field */
  1760. if (dst_buf->v4l2_buf.sequence == 0) {
  1761. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
  1762. ctx->vpu_header_size[0] +
  1763. ctx->vpu_header_size[1] +
  1764. ctx->vpu_header_size[2]);
  1765. } else {
  1766. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
  1767. }
  1768. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1769. wr_ptr - start_ptr);
  1770. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1771. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1772. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1773. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1774. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1775. } else {
  1776. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1777. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1778. }
  1779. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1780. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1781. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1782. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1783. ctx->gopcounter--;
  1784. if (ctx->gopcounter < 0)
  1785. ctx->gopcounter = ctx->params.gop_size - 1;
  1786. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1787. "job finished: encoding frame (%d) (%s)\n",
  1788. dst_buf->v4l2_buf.sequence,
  1789. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1790. "KEYFRAME" : "PFRAME");
  1791. mutex_unlock(&dev->coda_mutex);
  1792. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1793. return IRQ_HANDLED;
  1794. }
  1795. static void coda_timeout(struct work_struct *work)
  1796. {
  1797. struct coda_ctx *ctx;
  1798. struct coda_dev *dev = container_of(to_delayed_work(work),
  1799. struct coda_dev, timeout);
  1800. dev_err(&dev->plat_dev->dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1801. mutex_lock(&dev->dev_mutex);
  1802. list_for_each_entry(ctx, &dev->instances, list) {
  1803. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1804. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1805. }
  1806. mutex_unlock(&dev->dev_mutex);
  1807. mutex_unlock(&dev->coda_mutex);
  1808. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1809. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1810. }
  1811. static u32 coda_supported_firmwares[] = {
  1812. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1813. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  1814. };
  1815. static bool coda_firmware_supported(u32 vernum)
  1816. {
  1817. int i;
  1818. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1819. if (vernum == coda_supported_firmwares[i])
  1820. return true;
  1821. return false;
  1822. }
  1823. static char *coda_product_name(int product)
  1824. {
  1825. static char buf[9];
  1826. switch (product) {
  1827. case CODA_DX6:
  1828. return "CodaDx6";
  1829. case CODA_7541:
  1830. return "CODA7541";
  1831. default:
  1832. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1833. return buf;
  1834. }
  1835. }
  1836. static int coda_hw_init(struct coda_dev *dev)
  1837. {
  1838. u16 product, major, minor, release;
  1839. u32 data;
  1840. u16 *p;
  1841. int i;
  1842. clk_prepare_enable(dev->clk_per);
  1843. clk_prepare_enable(dev->clk_ahb);
  1844. /*
  1845. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1846. * The 16-bit chars in the code buffer are in memory access
  1847. * order, re-sort them to CODA order for register download.
  1848. * Data in this SRAM survives a reboot.
  1849. */
  1850. p = (u16 *)dev->codebuf.vaddr;
  1851. if (dev->devtype->product == CODA_DX6) {
  1852. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1853. data = CODA_DOWN_ADDRESS_SET(i) |
  1854. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1855. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1856. }
  1857. } else {
  1858. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1859. data = CODA_DOWN_ADDRESS_SET(i) |
  1860. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1861. 3 - (i % 4)]);
  1862. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1863. }
  1864. }
  1865. /* Clear registers */
  1866. for (i = 0; i < 64; i++)
  1867. coda_write(dev, 0, CODA_REG_BIT_CODE_BUF_ADDR + i * 4);
  1868. /* Tell the BIT where to find everything it needs */
  1869. if (dev->devtype->product == CODA_7541) {
  1870. coda_write(dev, dev->tempbuf.paddr,
  1871. CODA_REG_BIT_TEMP_BUF_ADDR);
  1872. } else {
  1873. coda_write(dev, dev->workbuf.paddr,
  1874. CODA_REG_BIT_WORK_BUF_ADDR);
  1875. }
  1876. coda_write(dev, dev->codebuf.paddr,
  1877. CODA_REG_BIT_CODE_BUF_ADDR);
  1878. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1879. /* Set default values */
  1880. switch (dev->devtype->product) {
  1881. case CODA_DX6:
  1882. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1883. break;
  1884. default:
  1885. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1886. }
  1887. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1888. if (dev->devtype->product != CODA_DX6)
  1889. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1890. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1891. CODA_REG_BIT_INT_ENABLE);
  1892. /* Reset VPU and start processor */
  1893. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1894. data |= CODA_REG_RESET_ENABLE;
  1895. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1896. udelay(10);
  1897. data &= ~CODA_REG_RESET_ENABLE;
  1898. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1899. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1900. /* Load firmware */
  1901. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1902. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1903. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1904. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1905. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1906. if (coda_wait_timeout(dev)) {
  1907. clk_disable_unprepare(dev->clk_per);
  1908. clk_disable_unprepare(dev->clk_ahb);
  1909. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1910. return -EIO;
  1911. }
  1912. /* Check we are compatible with the loaded firmware */
  1913. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1914. product = CODA_FIRMWARE_PRODUCT(data);
  1915. major = CODA_FIRMWARE_MAJOR(data);
  1916. minor = CODA_FIRMWARE_MINOR(data);
  1917. release = CODA_FIRMWARE_RELEASE(data);
  1918. clk_disable_unprepare(dev->clk_per);
  1919. clk_disable_unprepare(dev->clk_ahb);
  1920. if (product != dev->devtype->product) {
  1921. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1922. " Version: %u.%u.%u\n",
  1923. coda_product_name(dev->devtype->product),
  1924. coda_product_name(product), major, minor, release);
  1925. return -EINVAL;
  1926. }
  1927. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1928. coda_product_name(product));
  1929. if (coda_firmware_supported(data)) {
  1930. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1931. major, minor, release);
  1932. } else {
  1933. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1934. "%u.%u.%u\n", major, minor, release);
  1935. }
  1936. return 0;
  1937. }
  1938. static void coda_fw_callback(const struct firmware *fw, void *context)
  1939. {
  1940. struct coda_dev *dev = context;
  1941. struct platform_device *pdev = dev->plat_dev;
  1942. int ret;
  1943. if (!fw) {
  1944. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1945. return;
  1946. }
  1947. /* allocate auxiliary per-device code buffer for the BIT processor */
  1948. ret = coda_alloc_aux_buf(dev, &dev->codebuf, fw->size);
  1949. if (ret < 0) {
  1950. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1951. return;
  1952. }
  1953. /* Copy the whole firmware image to the code buffer */
  1954. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1955. release_firmware(fw);
  1956. ret = coda_hw_init(dev);
  1957. if (ret) {
  1958. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1959. return;
  1960. }
  1961. dev->vfd.fops = &coda_fops,
  1962. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1963. dev->vfd.release = video_device_release_empty,
  1964. dev->vfd.lock = &dev->dev_mutex;
  1965. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1966. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1967. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1968. video_set_drvdata(&dev->vfd, dev);
  1969. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1970. if (IS_ERR(dev->alloc_ctx)) {
  1971. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1972. return;
  1973. }
  1974. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1975. if (IS_ERR(dev->m2m_dev)) {
  1976. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1977. goto rel_ctx;
  1978. }
  1979. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1980. if (ret) {
  1981. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1982. goto rel_m2m;
  1983. }
  1984. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1985. dev->vfd.num);
  1986. return;
  1987. rel_m2m:
  1988. v4l2_m2m_release(dev->m2m_dev);
  1989. rel_ctx:
  1990. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1991. }
  1992. static int coda_firmware_request(struct coda_dev *dev)
  1993. {
  1994. char *fw = dev->devtype->firmware;
  1995. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1996. coda_product_name(dev->devtype->product));
  1997. return request_firmware_nowait(THIS_MODULE, true,
  1998. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1999. }
  2000. enum coda_platform {
  2001. CODA_IMX27,
  2002. CODA_IMX53,
  2003. };
  2004. static const struct coda_devtype coda_devdata[] = {
  2005. [CODA_IMX27] = {
  2006. .firmware = "v4l-codadx6-imx27.bin",
  2007. .product = CODA_DX6,
  2008. .codecs = codadx6_codecs,
  2009. .num_codecs = ARRAY_SIZE(codadx6_codecs),
  2010. },
  2011. [CODA_IMX53] = {
  2012. .firmware = "v4l-coda7541-imx53.bin",
  2013. .product = CODA_7541,
  2014. .codecs = coda7_codecs,
  2015. .num_codecs = ARRAY_SIZE(coda7_codecs),
  2016. },
  2017. };
  2018. static struct platform_device_id coda_platform_ids[] = {
  2019. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  2020. { .name = "coda-imx53", .driver_data = CODA_IMX53 },
  2021. { /* sentinel */ }
  2022. };
  2023. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  2024. #ifdef CONFIG_OF
  2025. static const struct of_device_id coda_dt_ids[] = {
  2026. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  2027. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  2028. { /* sentinel */ }
  2029. };
  2030. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  2031. #endif
  2032. static int coda_probe(struct platform_device *pdev)
  2033. {
  2034. const struct of_device_id *of_id =
  2035. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  2036. const struct platform_device_id *pdev_id;
  2037. struct coda_platform_data *pdata = pdev->dev.platform_data;
  2038. struct device_node *np = pdev->dev.of_node;
  2039. struct gen_pool *pool;
  2040. struct coda_dev *dev;
  2041. struct resource *res;
  2042. int ret, irq;
  2043. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  2044. if (!dev) {
  2045. dev_err(&pdev->dev, "Not enough memory for %s\n",
  2046. CODA_NAME);
  2047. return -ENOMEM;
  2048. }
  2049. spin_lock_init(&dev->irqlock);
  2050. INIT_LIST_HEAD(&dev->instances);
  2051. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  2052. dev->plat_dev = pdev;
  2053. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  2054. if (IS_ERR(dev->clk_per)) {
  2055. dev_err(&pdev->dev, "Could not get per clock\n");
  2056. return PTR_ERR(dev->clk_per);
  2057. }
  2058. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  2059. if (IS_ERR(dev->clk_ahb)) {
  2060. dev_err(&pdev->dev, "Could not get ahb clock\n");
  2061. return PTR_ERR(dev->clk_ahb);
  2062. }
  2063. /* Get memory for physical registers */
  2064. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2065. if (res == NULL) {
  2066. dev_err(&pdev->dev, "failed to get memory region resource\n");
  2067. return -ENOENT;
  2068. }
  2069. dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
  2070. if (IS_ERR(dev->regs_base))
  2071. return PTR_ERR(dev->regs_base);
  2072. /* IRQ */
  2073. irq = platform_get_irq(pdev, 0);
  2074. if (irq < 0) {
  2075. dev_err(&pdev->dev, "failed to get irq resource\n");
  2076. return -ENOENT;
  2077. }
  2078. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  2079. 0, CODA_NAME, dev) < 0) {
  2080. dev_err(&pdev->dev, "failed to request irq\n");
  2081. return -ENOENT;
  2082. }
  2083. /* Get IRAM pool from device tree or platform data */
  2084. pool = of_get_named_gen_pool(np, "iram", 0);
  2085. if (!pool && pdata)
  2086. pool = dev_get_gen_pool(pdata->iram_dev);
  2087. if (!pool) {
  2088. dev_err(&pdev->dev, "iram pool not available\n");
  2089. return -ENOMEM;
  2090. }
  2091. dev->iram_pool = pool;
  2092. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  2093. if (ret)
  2094. return ret;
  2095. mutex_init(&dev->dev_mutex);
  2096. mutex_init(&dev->coda_mutex);
  2097. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  2098. if (of_id) {
  2099. dev->devtype = of_id->data;
  2100. } else if (pdev_id) {
  2101. dev->devtype = &coda_devdata[pdev_id->driver_data];
  2102. } else {
  2103. v4l2_device_unregister(&dev->v4l2_dev);
  2104. return -EINVAL;
  2105. }
  2106. /* allocate auxiliary per-device buffers for the BIT processor */
  2107. switch (dev->devtype->product) {
  2108. case CODA_DX6:
  2109. ret = coda_alloc_aux_buf(dev, &dev->workbuf,
  2110. CODADX6_WORK_BUF_SIZE);
  2111. if (ret < 0) {
  2112. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  2113. v4l2_device_unregister(&dev->v4l2_dev);
  2114. return ret;
  2115. }
  2116. break;
  2117. case CODA_7541:
  2118. dev->tempbuf.size = CODA7_TEMP_BUF_SIZE;
  2119. break;
  2120. }
  2121. if (dev->tempbuf.size) {
  2122. ret = coda_alloc_aux_buf(dev, &dev->tempbuf,
  2123. dev->tempbuf.size);
  2124. if (ret < 0) {
  2125. dev_err(&pdev->dev, "failed to allocate temp buffer\n");
  2126. v4l2_device_unregister(&dev->v4l2_dev);
  2127. return ret;
  2128. }
  2129. }
  2130. if (dev->devtype->product == CODA_DX6)
  2131. dev->iram_size = CODADX6_IRAM_SIZE;
  2132. else
  2133. dev->iram_size = CODA7_IRAM_SIZE;
  2134. dev->iram_vaddr = gen_pool_alloc(dev->iram_pool, dev->iram_size);
  2135. if (!dev->iram_vaddr) {
  2136. dev_err(&pdev->dev, "unable to alloc iram\n");
  2137. return -ENOMEM;
  2138. }
  2139. dev->iram_paddr = gen_pool_virt_to_phys(dev->iram_pool,
  2140. dev->iram_vaddr);
  2141. platform_set_drvdata(pdev, dev);
  2142. return coda_firmware_request(dev);
  2143. }
  2144. static int coda_remove(struct platform_device *pdev)
  2145. {
  2146. struct coda_dev *dev = platform_get_drvdata(pdev);
  2147. video_unregister_device(&dev->vfd);
  2148. if (dev->m2m_dev)
  2149. v4l2_m2m_release(dev->m2m_dev);
  2150. if (dev->alloc_ctx)
  2151. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  2152. v4l2_device_unregister(&dev->v4l2_dev);
  2153. if (dev->iram_vaddr)
  2154. gen_pool_free(dev->iram_pool, dev->iram_vaddr, dev->iram_size);
  2155. coda_free_aux_buf(dev, &dev->codebuf);
  2156. coda_free_aux_buf(dev, &dev->tempbuf);
  2157. coda_free_aux_buf(dev, &dev->workbuf);
  2158. return 0;
  2159. }
  2160. static struct platform_driver coda_driver = {
  2161. .probe = coda_probe,
  2162. .remove = coda_remove,
  2163. .driver = {
  2164. .name = CODA_NAME,
  2165. .owner = THIS_MODULE,
  2166. .of_match_table = of_match_ptr(coda_dt_ids),
  2167. },
  2168. .id_table = coda_platform_ids,
  2169. };
  2170. module_platform_driver(coda_driver);
  2171. MODULE_LICENSE("GPL");
  2172. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  2173. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");