iwl3945-base.c 242 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL3945_DEBUG
  48. u32 iwl3945_debug_level;
  49. #endif
  50. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  51. struct iwl3945_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  59. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  60. static int iwl3945_param_disable; /* def: 0 = enable radio */
  61. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  63. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  64. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.2.23k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. /* Change firmware file name, using "-" and incrementing number,
  85. * *only* when uCode interface or architecture changes so that it
  86. * is not compatible with earlier drivers.
  87. * This number will also appear in << 8 position of 1st dword of uCode file */
  88. #define IWL3945_UCODE_API "-1"
  89. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  90. MODULE_VERSION(DRV_VERSION);
  91. MODULE_AUTHOR(DRV_COPYRIGHT);
  92. MODULE_LICENSE("GPL");
  93. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  94. {
  95. u16 fc = le16_to_cpu(hdr->frame_control);
  96. int hdr_len = ieee80211_get_hdrlen(fc);
  97. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  98. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  99. return NULL;
  100. }
  101. static const struct ieee80211_supported_band *iwl3945_get_band(
  102. struct iwl3945_priv *priv, enum ieee80211_band band)
  103. {
  104. return priv->hw->wiphy->bands[band];
  105. }
  106. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  107. {
  108. /* Single white space is for Linksys APs */
  109. if (essid_len == 1 && essid[0] == ' ')
  110. return 1;
  111. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  112. while (essid_len) {
  113. essid_len--;
  114. if (essid[essid_len] != '\0')
  115. return 0;
  116. }
  117. return 1;
  118. }
  119. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  120. {
  121. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  122. const char *s = essid;
  123. char *d = escaped;
  124. if (iwl3945_is_empty_essid(essid, essid_len)) {
  125. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  126. return escaped;
  127. }
  128. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  129. while (essid_len--) {
  130. if (*s == '\0') {
  131. *d++ = '\\';
  132. *d++ = '0';
  133. s++;
  134. } else
  135. *d++ = *s++;
  136. }
  137. *d = '\0';
  138. return escaped;
  139. }
  140. static void iwl3945_print_hex_dump(int level, void *p, u32 len)
  141. {
  142. #ifdef CONFIG_IWL3945_DEBUG
  143. if (!(iwl3945_debug_level & level))
  144. return;
  145. print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
  146. p, len, 1);
  147. #endif
  148. }
  149. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  150. * DMA services
  151. *
  152. * Theory of operation
  153. *
  154. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  155. * of buffer descriptors, each of which points to one or more data buffers for
  156. * the device to read from or fill. Driver and device exchange status of each
  157. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  158. * entries in each circular buffer, to protect against confusing empty and full
  159. * queue states.
  160. *
  161. * The device reads or writes the data in the queues via the device's several
  162. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  163. *
  164. * For Tx queue, there are low mark and high mark limits. If, after queuing
  165. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  166. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  167. * Tx queue resumed.
  168. *
  169. * The 3945 operates with six queues: One receive queue, one transmit queue
  170. * (#4) for sending commands to the device firmware, and four transmit queues
  171. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  172. ***************************************************/
  173. static int iwl3945_queue_space(const struct iwl3945_queue *q)
  174. {
  175. int s = q->read_ptr - q->write_ptr;
  176. if (q->read_ptr > q->write_ptr)
  177. s -= q->n_bd;
  178. if (s <= 0)
  179. s += q->n_window;
  180. /* keep some reserve to not confuse empty and full situations */
  181. s -= 2;
  182. if (s < 0)
  183. s = 0;
  184. return s;
  185. }
  186. /**
  187. * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
  188. * @index -- current index
  189. * @n_bd -- total number of entries in queue (must be power of 2)
  190. */
  191. static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
  192. {
  193. return ++index & (n_bd - 1);
  194. }
  195. /**
  196. * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
  197. * @index -- current index
  198. * @n_bd -- total number of entries in queue (must be power of 2)
  199. */
  200. static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
  201. {
  202. return --index & (n_bd - 1);
  203. }
  204. static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
  205. {
  206. return q->write_ptr > q->read_ptr ?
  207. (i >= q->read_ptr && i < q->write_ptr) :
  208. !(i < q->read_ptr && i >= q->write_ptr);
  209. }
  210. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  211. {
  212. /* This is for scan command, the big buffer at end of command array */
  213. if (is_huge)
  214. return q->n_window; /* must be power of 2 */
  215. /* Otherwise, use normal size buffers */
  216. return index & (q->n_window - 1);
  217. }
  218. /**
  219. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  220. */
  221. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  222. int count, int slots_num, u32 id)
  223. {
  224. q->n_bd = count;
  225. q->n_window = slots_num;
  226. q->id = id;
  227. /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
  228. * and iwl3945_queue_dec_wrap are broken. */
  229. BUG_ON(!is_power_of_2(count));
  230. /* slots_num must be power-of-two size, otherwise
  231. * get_cmd_index is broken. */
  232. BUG_ON(!is_power_of_2(slots_num));
  233. q->low_mark = q->n_window / 4;
  234. if (q->low_mark < 4)
  235. q->low_mark = 4;
  236. q->high_mark = q->n_window / 8;
  237. if (q->high_mark < 2)
  238. q->high_mark = 2;
  239. q->write_ptr = q->read_ptr = 0;
  240. return 0;
  241. }
  242. /**
  243. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  244. */
  245. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  246. struct iwl3945_tx_queue *txq, u32 id)
  247. {
  248. struct pci_dev *dev = priv->pci_dev;
  249. /* Driver private data, only for Tx (not command) queues,
  250. * not shared with device. */
  251. if (id != IWL_CMD_QUEUE_NUM) {
  252. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  253. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  254. if (!txq->txb) {
  255. IWL_ERROR("kmalloc for auxiliary BD "
  256. "structures failed\n");
  257. goto error;
  258. }
  259. } else
  260. txq->txb = NULL;
  261. /* Circular buffer of transmit frame descriptors (TFDs),
  262. * shared with device */
  263. txq->bd = pci_alloc_consistent(dev,
  264. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  265. &txq->q.dma_addr);
  266. if (!txq->bd) {
  267. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  268. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  269. goto error;
  270. }
  271. txq->q.id = id;
  272. return 0;
  273. error:
  274. if (txq->txb) {
  275. kfree(txq->txb);
  276. txq->txb = NULL;
  277. }
  278. return -ENOMEM;
  279. }
  280. /**
  281. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  282. */
  283. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  284. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  285. {
  286. struct pci_dev *dev = priv->pci_dev;
  287. int len;
  288. int rc = 0;
  289. /*
  290. * Alloc buffer array for commands (Tx or other types of commands).
  291. * For the command queue (#4), allocate command space + one big
  292. * command for scan, since scan command is very huge; the system will
  293. * not have two scans at the same time, so only one is needed.
  294. * For data Tx queues (all other queues), no super-size command
  295. * space is needed.
  296. */
  297. len = sizeof(struct iwl3945_cmd) * slots_num;
  298. if (txq_id == IWL_CMD_QUEUE_NUM)
  299. len += IWL_MAX_SCAN_SIZE;
  300. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  301. if (!txq->cmd)
  302. return -ENOMEM;
  303. /* Alloc driver data array and TFD circular buffer */
  304. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  305. if (rc) {
  306. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  307. return -ENOMEM;
  308. }
  309. txq->need_update = 0;
  310. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  311. * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
  312. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  313. /* Initialize queue high/low-water, head/tail indexes */
  314. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  315. /* Tell device where to find queue, enable DMA channel. */
  316. iwl3945_hw_tx_queue_init(priv, txq);
  317. return 0;
  318. }
  319. /**
  320. * iwl3945_tx_queue_free - Deallocate DMA queue.
  321. * @txq: Transmit queue to deallocate.
  322. *
  323. * Empty queue by removing and destroying all BD's.
  324. * Free all buffers.
  325. * 0-fill, but do not free "txq" descriptor structure.
  326. */
  327. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  328. {
  329. struct iwl3945_queue *q = &txq->q;
  330. struct pci_dev *dev = priv->pci_dev;
  331. int len;
  332. if (q->n_bd == 0)
  333. return;
  334. /* first, empty all BD's */
  335. for (; q->write_ptr != q->read_ptr;
  336. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
  337. iwl3945_hw_txq_free_tfd(priv, txq);
  338. len = sizeof(struct iwl3945_cmd) * q->n_window;
  339. if (q->id == IWL_CMD_QUEUE_NUM)
  340. len += IWL_MAX_SCAN_SIZE;
  341. /* De-alloc array of command/tx buffers */
  342. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  343. /* De-alloc circular buffer of TFDs */
  344. if (txq->q.n_bd)
  345. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  346. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  347. /* De-alloc array of per-TFD driver data */
  348. if (txq->txb) {
  349. kfree(txq->txb);
  350. txq->txb = NULL;
  351. }
  352. /* 0-fill queue descriptor structure */
  353. memset(txq, 0, sizeof(*txq));
  354. }
  355. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  356. /*************** STATION TABLE MANAGEMENT ****
  357. * mac80211 should be examined to determine if sta_info is duplicating
  358. * the functionality provided here
  359. */
  360. /**************************************************************/
  361. #if 0 /* temporary disable till we add real remove station */
  362. /**
  363. * iwl3945_remove_station - Remove driver's knowledge of station.
  364. *
  365. * NOTE: This does not remove station from device's station table.
  366. */
  367. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  368. {
  369. int index = IWL_INVALID_STATION;
  370. int i;
  371. unsigned long flags;
  372. spin_lock_irqsave(&priv->sta_lock, flags);
  373. if (is_ap)
  374. index = IWL_AP_ID;
  375. else if (is_broadcast_ether_addr(addr))
  376. index = priv->hw_setting.bcast_sta_id;
  377. else
  378. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  379. if (priv->stations[i].used &&
  380. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  381. addr)) {
  382. index = i;
  383. break;
  384. }
  385. if (unlikely(index == IWL_INVALID_STATION))
  386. goto out;
  387. if (priv->stations[index].used) {
  388. priv->stations[index].used = 0;
  389. priv->num_stations--;
  390. }
  391. BUG_ON(priv->num_stations < 0);
  392. out:
  393. spin_unlock_irqrestore(&priv->sta_lock, flags);
  394. return 0;
  395. }
  396. #endif
  397. /**
  398. * iwl3945_clear_stations_table - Clear the driver's station table
  399. *
  400. * NOTE: This does not clear or otherwise alter the device's station table.
  401. */
  402. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  403. {
  404. unsigned long flags;
  405. spin_lock_irqsave(&priv->sta_lock, flags);
  406. priv->num_stations = 0;
  407. memset(priv->stations, 0, sizeof(priv->stations));
  408. spin_unlock_irqrestore(&priv->sta_lock, flags);
  409. }
  410. /**
  411. * iwl3945_add_station - Add station to station tables in driver and device
  412. */
  413. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  414. {
  415. int i;
  416. int index = IWL_INVALID_STATION;
  417. struct iwl3945_station_entry *station;
  418. unsigned long flags_spin;
  419. DECLARE_MAC_BUF(mac);
  420. u8 rate;
  421. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  422. if (is_ap)
  423. index = IWL_AP_ID;
  424. else if (is_broadcast_ether_addr(addr))
  425. index = priv->hw_setting.bcast_sta_id;
  426. else
  427. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  428. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  429. addr)) {
  430. index = i;
  431. break;
  432. }
  433. if (!priv->stations[i].used &&
  434. index == IWL_INVALID_STATION)
  435. index = i;
  436. }
  437. /* These two conditions has the same outcome but keep them separate
  438. since they have different meaning */
  439. if (unlikely(index == IWL_INVALID_STATION)) {
  440. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  441. return index;
  442. }
  443. if (priv->stations[index].used &&
  444. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  445. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  446. return index;
  447. }
  448. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  449. station = &priv->stations[index];
  450. station->used = 1;
  451. priv->num_stations++;
  452. /* Set up the REPLY_ADD_STA command to send to device */
  453. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  454. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  455. station->sta.mode = 0;
  456. station->sta.sta.sta_id = index;
  457. station->sta.station_flags = 0;
  458. if (priv->band == IEEE80211_BAND_5GHZ)
  459. rate = IWL_RATE_6M_PLCP;
  460. else
  461. rate = IWL_RATE_1M_PLCP;
  462. /* Turn on both antennas for the station... */
  463. station->sta.rate_n_flags =
  464. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  465. station->current_rate.rate_n_flags =
  466. le16_to_cpu(station->sta.rate_n_flags);
  467. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  468. /* Add station to device's station table */
  469. iwl3945_send_add_station(priv, &station->sta, flags);
  470. return index;
  471. }
  472. /*************** DRIVER STATUS FUNCTIONS *****/
  473. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  474. {
  475. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  476. * set but EXIT_PENDING is not */
  477. return test_bit(STATUS_READY, &priv->status) &&
  478. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  479. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  480. }
  481. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  482. {
  483. return test_bit(STATUS_ALIVE, &priv->status);
  484. }
  485. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  486. {
  487. return test_bit(STATUS_INIT, &priv->status);
  488. }
  489. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  490. {
  491. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  492. test_bit(STATUS_RF_KILL_SW, &priv->status);
  493. }
  494. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  495. {
  496. if (iwl3945_is_rfkill(priv))
  497. return 0;
  498. return iwl3945_is_ready(priv);
  499. }
  500. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  501. #define IWL_CMD(x) case x : return #x
  502. static const char *get_cmd_string(u8 cmd)
  503. {
  504. switch (cmd) {
  505. IWL_CMD(REPLY_ALIVE);
  506. IWL_CMD(REPLY_ERROR);
  507. IWL_CMD(REPLY_RXON);
  508. IWL_CMD(REPLY_RXON_ASSOC);
  509. IWL_CMD(REPLY_QOS_PARAM);
  510. IWL_CMD(REPLY_RXON_TIMING);
  511. IWL_CMD(REPLY_ADD_STA);
  512. IWL_CMD(REPLY_REMOVE_STA);
  513. IWL_CMD(REPLY_REMOVE_ALL_STA);
  514. IWL_CMD(REPLY_3945_RX);
  515. IWL_CMD(REPLY_TX);
  516. IWL_CMD(REPLY_RATE_SCALE);
  517. IWL_CMD(REPLY_LEDS_CMD);
  518. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  519. IWL_CMD(RADAR_NOTIFICATION);
  520. IWL_CMD(REPLY_QUIET_CMD);
  521. IWL_CMD(REPLY_CHANNEL_SWITCH);
  522. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  523. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  524. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  525. IWL_CMD(POWER_TABLE_CMD);
  526. IWL_CMD(PM_SLEEP_NOTIFICATION);
  527. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  528. IWL_CMD(REPLY_SCAN_CMD);
  529. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  530. IWL_CMD(SCAN_START_NOTIFICATION);
  531. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  532. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  533. IWL_CMD(BEACON_NOTIFICATION);
  534. IWL_CMD(REPLY_TX_BEACON);
  535. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  536. IWL_CMD(QUIET_NOTIFICATION);
  537. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  538. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  539. IWL_CMD(REPLY_BT_CONFIG);
  540. IWL_CMD(REPLY_STATISTICS_CMD);
  541. IWL_CMD(STATISTICS_NOTIFICATION);
  542. IWL_CMD(REPLY_CARD_STATE_CMD);
  543. IWL_CMD(CARD_STATE_NOTIFICATION);
  544. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  545. default:
  546. return "UNKNOWN";
  547. }
  548. }
  549. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  550. /**
  551. * iwl3945_enqueue_hcmd - enqueue a uCode command
  552. * @priv: device private data point
  553. * @cmd: a point to the ucode command structure
  554. *
  555. * The function returns < 0 values to indicate the operation is
  556. * failed. On success, it turns the index (> 0) of command in the
  557. * command queue.
  558. */
  559. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  560. {
  561. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  562. struct iwl3945_queue *q = &txq->q;
  563. struct iwl3945_tfd_frame *tfd;
  564. u32 *control_flags;
  565. struct iwl3945_cmd *out_cmd;
  566. u32 idx;
  567. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  568. dma_addr_t phys_addr;
  569. int pad;
  570. u16 count;
  571. int ret;
  572. unsigned long flags;
  573. /* If any of the command structures end up being larger than
  574. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  575. * we will need to increase the size of the TFD entries */
  576. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  577. !(cmd->meta.flags & CMD_SIZE_HUGE));
  578. if (iwl3945_is_rfkill(priv)) {
  579. IWL_DEBUG_INFO("Not sending command - RF KILL");
  580. return -EIO;
  581. }
  582. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  583. IWL_ERROR("No space for Tx\n");
  584. return -ENOSPC;
  585. }
  586. spin_lock_irqsave(&priv->hcmd_lock, flags);
  587. tfd = &txq->bd[q->write_ptr];
  588. memset(tfd, 0, sizeof(*tfd));
  589. control_flags = (u32 *) tfd;
  590. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  591. out_cmd = &txq->cmd[idx];
  592. out_cmd->hdr.cmd = cmd->id;
  593. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  594. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  595. /* At this point, the out_cmd now has all of the incoming cmd
  596. * information */
  597. out_cmd->hdr.flags = 0;
  598. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  599. INDEX_TO_SEQ(q->write_ptr));
  600. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  601. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  602. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  603. offsetof(struct iwl3945_cmd, hdr);
  604. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  605. pad = U32_PAD(cmd->len);
  606. count = TFD_CTL_COUNT_GET(*control_flags);
  607. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  608. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  609. "%d bytes at %d[%d]:%d\n",
  610. get_cmd_string(out_cmd->hdr.cmd),
  611. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  612. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  613. txq->need_update = 1;
  614. /* Increment and update queue's write index */
  615. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  616. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  617. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  618. return ret ? ret : idx;
  619. }
  620. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  621. {
  622. int ret;
  623. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  624. /* An asynchronous command can not expect an SKB to be set. */
  625. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  626. /* An asynchronous command MUST have a callback. */
  627. BUG_ON(!cmd->meta.u.callback);
  628. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  629. return -EBUSY;
  630. ret = iwl3945_enqueue_hcmd(priv, cmd);
  631. if (ret < 0) {
  632. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  633. get_cmd_string(cmd->id), ret);
  634. return ret;
  635. }
  636. return 0;
  637. }
  638. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  639. {
  640. int cmd_idx;
  641. int ret;
  642. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  643. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  644. /* A synchronous command can not have a callback set. */
  645. BUG_ON(cmd->meta.u.callback != NULL);
  646. if (atomic_xchg(&entry, 1)) {
  647. IWL_ERROR("Error sending %s: Already sending a host command\n",
  648. get_cmd_string(cmd->id));
  649. return -EBUSY;
  650. }
  651. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  652. if (cmd->meta.flags & CMD_WANT_SKB)
  653. cmd->meta.source = &cmd->meta;
  654. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  655. if (cmd_idx < 0) {
  656. ret = cmd_idx;
  657. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  658. get_cmd_string(cmd->id), ret);
  659. goto out;
  660. }
  661. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  662. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  663. HOST_COMPLETE_TIMEOUT);
  664. if (!ret) {
  665. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  666. IWL_ERROR("Error sending %s: time out after %dms.\n",
  667. get_cmd_string(cmd->id),
  668. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  669. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  670. ret = -ETIMEDOUT;
  671. goto cancel;
  672. }
  673. }
  674. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  675. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  676. get_cmd_string(cmd->id));
  677. ret = -ECANCELED;
  678. goto fail;
  679. }
  680. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  681. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  682. get_cmd_string(cmd->id));
  683. ret = -EIO;
  684. goto fail;
  685. }
  686. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  687. IWL_ERROR("Error: Response NULL in '%s'\n",
  688. get_cmd_string(cmd->id));
  689. ret = -EIO;
  690. goto out;
  691. }
  692. ret = 0;
  693. goto out;
  694. cancel:
  695. if (cmd->meta.flags & CMD_WANT_SKB) {
  696. struct iwl3945_cmd *qcmd;
  697. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  698. * TX cmd queue. Otherwise in case the cmd comes
  699. * in later, it will possibly set an invalid
  700. * address (cmd->meta.source). */
  701. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  702. qcmd->meta.flags &= ~CMD_WANT_SKB;
  703. }
  704. fail:
  705. if (cmd->meta.u.skb) {
  706. dev_kfree_skb_any(cmd->meta.u.skb);
  707. cmd->meta.u.skb = NULL;
  708. }
  709. out:
  710. atomic_set(&entry, 0);
  711. return ret;
  712. }
  713. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  714. {
  715. if (cmd->meta.flags & CMD_ASYNC)
  716. return iwl3945_send_cmd_async(priv, cmd);
  717. return iwl3945_send_cmd_sync(priv, cmd);
  718. }
  719. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  720. {
  721. struct iwl3945_host_cmd cmd = {
  722. .id = id,
  723. .len = len,
  724. .data = data,
  725. };
  726. return iwl3945_send_cmd_sync(priv, &cmd);
  727. }
  728. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  729. {
  730. struct iwl3945_host_cmd cmd = {
  731. .id = id,
  732. .len = sizeof(val),
  733. .data = &val,
  734. };
  735. return iwl3945_send_cmd_sync(priv, &cmd);
  736. }
  737. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  738. {
  739. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  740. }
  741. /**
  742. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  743. * @band: 2.4 or 5 GHz band
  744. * @channel: Any channel valid for the requested band
  745. * In addition to setting the staging RXON, priv->band is also set.
  746. *
  747. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  748. * in the staging RXON flag structure based on the band
  749. */
  750. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  751. enum ieee80211_band band,
  752. u16 channel)
  753. {
  754. if (!iwl3945_get_channel_info(priv, band, channel)) {
  755. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  756. channel, band);
  757. return -EINVAL;
  758. }
  759. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  760. (priv->band == band))
  761. return 0;
  762. priv->staging_rxon.channel = cpu_to_le16(channel);
  763. if (band == IEEE80211_BAND_5GHZ)
  764. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  765. else
  766. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  767. priv->band = band;
  768. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  769. return 0;
  770. }
  771. /**
  772. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  773. *
  774. * NOTE: This is really only useful during development and can eventually
  775. * be #ifdef'd out once the driver is stable and folks aren't actively
  776. * making changes
  777. */
  778. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  779. {
  780. int error = 0;
  781. int counter = 1;
  782. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  783. error |= le32_to_cpu(rxon->flags &
  784. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  785. RXON_FLG_RADAR_DETECT_MSK));
  786. if (error)
  787. IWL_WARNING("check 24G fields %d | %d\n",
  788. counter++, error);
  789. } else {
  790. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  791. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  792. if (error)
  793. IWL_WARNING("check 52 fields %d | %d\n",
  794. counter++, error);
  795. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  796. if (error)
  797. IWL_WARNING("check 52 CCK %d | %d\n",
  798. counter++, error);
  799. }
  800. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  801. if (error)
  802. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  803. /* make sure basic rates 6Mbps and 1Mbps are supported */
  804. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  805. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  806. if (error)
  807. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  808. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  809. if (error)
  810. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  811. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  812. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  813. if (error)
  814. IWL_WARNING("check CCK and short slot %d | %d\n",
  815. counter++, error);
  816. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  817. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  818. if (error)
  819. IWL_WARNING("check CCK & auto detect %d | %d\n",
  820. counter++, error);
  821. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  822. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  823. if (error)
  824. IWL_WARNING("check TGG and auto detect %d | %d\n",
  825. counter++, error);
  826. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  827. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  828. RXON_FLG_ANT_A_MSK)) == 0);
  829. if (error)
  830. IWL_WARNING("check antenna %d %d\n", counter++, error);
  831. if (error)
  832. IWL_WARNING("Tuning to channel %d\n",
  833. le16_to_cpu(rxon->channel));
  834. if (error) {
  835. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  836. return -1;
  837. }
  838. return 0;
  839. }
  840. /**
  841. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  842. * @priv: staging_rxon is compared to active_rxon
  843. *
  844. * If the RXON structure is changing enough to require a new tune,
  845. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  846. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  847. */
  848. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  849. {
  850. /* These items are only settable from the full RXON command */
  851. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  852. compare_ether_addr(priv->staging_rxon.bssid_addr,
  853. priv->active_rxon.bssid_addr) ||
  854. compare_ether_addr(priv->staging_rxon.node_addr,
  855. priv->active_rxon.node_addr) ||
  856. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  857. priv->active_rxon.wlap_bssid_addr) ||
  858. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  859. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  860. (priv->staging_rxon.air_propagation !=
  861. priv->active_rxon.air_propagation) ||
  862. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  863. return 1;
  864. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  865. * be updated with the RXON_ASSOC command -- however only some
  866. * flag transitions are allowed using RXON_ASSOC */
  867. /* Check if we are not switching bands */
  868. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  869. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  870. return 1;
  871. /* Check if we are switching association toggle */
  872. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  873. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  874. return 1;
  875. return 0;
  876. }
  877. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  878. {
  879. int rc = 0;
  880. struct iwl3945_rx_packet *res = NULL;
  881. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  882. struct iwl3945_host_cmd cmd = {
  883. .id = REPLY_RXON_ASSOC,
  884. .len = sizeof(rxon_assoc),
  885. .meta.flags = CMD_WANT_SKB,
  886. .data = &rxon_assoc,
  887. };
  888. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  889. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  890. if ((rxon1->flags == rxon2->flags) &&
  891. (rxon1->filter_flags == rxon2->filter_flags) &&
  892. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  893. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  894. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  895. return 0;
  896. }
  897. rxon_assoc.flags = priv->staging_rxon.flags;
  898. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  899. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  900. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  901. rxon_assoc.reserved = 0;
  902. rc = iwl3945_send_cmd_sync(priv, &cmd);
  903. if (rc)
  904. return rc;
  905. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  906. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  907. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  908. rc = -EIO;
  909. }
  910. priv->alloc_rxb_skb--;
  911. dev_kfree_skb_any(cmd.meta.u.skb);
  912. return rc;
  913. }
  914. /**
  915. * iwl3945_commit_rxon - commit staging_rxon to hardware
  916. *
  917. * The RXON command in staging_rxon is committed to the hardware and
  918. * the active_rxon structure is updated with the new data. This
  919. * function correctly transitions out of the RXON_ASSOC_MSK state if
  920. * a HW tune is required based on the RXON structure changes.
  921. */
  922. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  923. {
  924. /* cast away the const for active_rxon in this function */
  925. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  926. int rc = 0;
  927. DECLARE_MAC_BUF(mac);
  928. if (!iwl3945_is_alive(priv))
  929. return -1;
  930. /* always get timestamp with Rx frame */
  931. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  932. /* select antenna */
  933. priv->staging_rxon.flags &=
  934. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  935. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  936. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  937. if (rc) {
  938. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  939. return -EINVAL;
  940. }
  941. /* If we don't need to send a full RXON, we can use
  942. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  943. * and other flags for the current radio configuration. */
  944. if (!iwl3945_full_rxon_required(priv)) {
  945. rc = iwl3945_send_rxon_assoc(priv);
  946. if (rc) {
  947. IWL_ERROR("Error setting RXON_ASSOC "
  948. "configuration (%d).\n", rc);
  949. return rc;
  950. }
  951. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  952. return 0;
  953. }
  954. /* If we are currently associated and the new config requires
  955. * an RXON_ASSOC and the new config wants the associated mask enabled,
  956. * we must clear the associated from the active configuration
  957. * before we apply the new config */
  958. if (iwl3945_is_associated(priv) &&
  959. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  960. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  961. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  962. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  963. sizeof(struct iwl3945_rxon_cmd),
  964. &priv->active_rxon);
  965. /* If the mask clearing failed then we set
  966. * active_rxon back to what it was previously */
  967. if (rc) {
  968. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  969. IWL_ERROR("Error clearing ASSOC_MSK on current "
  970. "configuration (%d).\n", rc);
  971. return rc;
  972. }
  973. }
  974. IWL_DEBUG_INFO("Sending RXON\n"
  975. "* with%s RXON_FILTER_ASSOC_MSK\n"
  976. "* channel = %d\n"
  977. "* bssid = %s\n",
  978. ((priv->staging_rxon.filter_flags &
  979. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  980. le16_to_cpu(priv->staging_rxon.channel),
  981. print_mac(mac, priv->staging_rxon.bssid_addr));
  982. /* Apply the new configuration */
  983. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  984. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  985. if (rc) {
  986. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  987. return rc;
  988. }
  989. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  990. iwl3945_clear_stations_table(priv);
  991. /* If we issue a new RXON command which required a tune then we must
  992. * send a new TXPOWER command or we won't be able to Tx any frames */
  993. rc = iwl3945_hw_reg_send_txpower(priv);
  994. if (rc) {
  995. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  996. return rc;
  997. }
  998. /* Add the broadcast address so we can send broadcast frames */
  999. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  1000. IWL_INVALID_STATION) {
  1001. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  1002. return -EIO;
  1003. }
  1004. /* If we have set the ASSOC_MSK and we are in BSS mode then
  1005. * add the IWL_AP_ID to the station rate table */
  1006. if (iwl3945_is_associated(priv) &&
  1007. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  1008. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  1009. == IWL_INVALID_STATION) {
  1010. IWL_ERROR("Error adding AP address for transmit.\n");
  1011. return -EIO;
  1012. }
  1013. /* Init the hardware's rate fallback order based on the band */
  1014. rc = iwl3945_init_hw_rate_table(priv);
  1015. if (rc) {
  1016. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  1017. return -EIO;
  1018. }
  1019. return 0;
  1020. }
  1021. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  1022. {
  1023. struct iwl3945_bt_cmd bt_cmd = {
  1024. .flags = 3,
  1025. .lead_time = 0xAA,
  1026. .max_kill = 1,
  1027. .kill_ack_mask = 0,
  1028. .kill_cts_mask = 0,
  1029. };
  1030. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1031. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1032. }
  1033. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1034. {
  1035. int rc = 0;
  1036. struct iwl3945_rx_packet *res;
  1037. struct iwl3945_host_cmd cmd = {
  1038. .id = REPLY_SCAN_ABORT_CMD,
  1039. .meta.flags = CMD_WANT_SKB,
  1040. };
  1041. /* If there isn't a scan actively going on in the hardware
  1042. * then we are in between scan bands and not actually
  1043. * actively scanning, so don't send the abort command */
  1044. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1045. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1046. return 0;
  1047. }
  1048. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1049. if (rc) {
  1050. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1051. return rc;
  1052. }
  1053. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1054. if (res->u.status != CAN_ABORT_STATUS) {
  1055. /* The scan abort will return 1 for success or
  1056. * 2 for "failure". A failure condition can be
  1057. * due to simply not being in an active scan which
  1058. * can occur if we send the scan abort before we
  1059. * the microcode has notified us that a scan is
  1060. * completed. */
  1061. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1062. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1063. clear_bit(STATUS_SCAN_HW, &priv->status);
  1064. }
  1065. dev_kfree_skb_any(cmd.meta.u.skb);
  1066. return rc;
  1067. }
  1068. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1069. struct iwl3945_cmd *cmd,
  1070. struct sk_buff *skb)
  1071. {
  1072. return 1;
  1073. }
  1074. /*
  1075. * CARD_STATE_CMD
  1076. *
  1077. * Use: Sets the device's internal card state to enable, disable, or halt
  1078. *
  1079. * When in the 'enable' state the card operates as normal.
  1080. * When in the 'disable' state, the card enters into a low power mode.
  1081. * When in the 'halt' state, the card is shut down and must be fully
  1082. * restarted to come back on.
  1083. */
  1084. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1085. {
  1086. struct iwl3945_host_cmd cmd = {
  1087. .id = REPLY_CARD_STATE_CMD,
  1088. .len = sizeof(u32),
  1089. .data = &flags,
  1090. .meta.flags = meta_flag,
  1091. };
  1092. if (meta_flag & CMD_ASYNC)
  1093. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1094. return iwl3945_send_cmd(priv, &cmd);
  1095. }
  1096. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1097. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1098. {
  1099. struct iwl3945_rx_packet *res = NULL;
  1100. if (!skb) {
  1101. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1102. return 1;
  1103. }
  1104. res = (struct iwl3945_rx_packet *)skb->data;
  1105. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1106. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1107. res->hdr.flags);
  1108. return 1;
  1109. }
  1110. switch (res->u.add_sta.status) {
  1111. case ADD_STA_SUCCESS_MSK:
  1112. break;
  1113. default:
  1114. break;
  1115. }
  1116. /* We didn't cache the SKB; let the caller free it */
  1117. return 1;
  1118. }
  1119. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1120. struct iwl3945_addsta_cmd *sta, u8 flags)
  1121. {
  1122. struct iwl3945_rx_packet *res = NULL;
  1123. int rc = 0;
  1124. struct iwl3945_host_cmd cmd = {
  1125. .id = REPLY_ADD_STA,
  1126. .len = sizeof(struct iwl3945_addsta_cmd),
  1127. .meta.flags = flags,
  1128. .data = sta,
  1129. };
  1130. if (flags & CMD_ASYNC)
  1131. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1132. else
  1133. cmd.meta.flags |= CMD_WANT_SKB;
  1134. rc = iwl3945_send_cmd(priv, &cmd);
  1135. if (rc || (flags & CMD_ASYNC))
  1136. return rc;
  1137. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1138. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1139. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1140. res->hdr.flags);
  1141. rc = -EIO;
  1142. }
  1143. if (rc == 0) {
  1144. switch (res->u.add_sta.status) {
  1145. case ADD_STA_SUCCESS_MSK:
  1146. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1147. break;
  1148. default:
  1149. rc = -EIO;
  1150. IWL_WARNING("REPLY_ADD_STA failed\n");
  1151. break;
  1152. }
  1153. }
  1154. priv->alloc_rxb_skb--;
  1155. dev_kfree_skb_any(cmd.meta.u.skb);
  1156. return rc;
  1157. }
  1158. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1159. struct ieee80211_key_conf *keyconf,
  1160. u8 sta_id)
  1161. {
  1162. unsigned long flags;
  1163. __le16 key_flags = 0;
  1164. switch (keyconf->alg) {
  1165. case ALG_CCMP:
  1166. key_flags |= STA_KEY_FLG_CCMP;
  1167. key_flags |= cpu_to_le16(
  1168. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1169. key_flags &= ~STA_KEY_FLG_INVALID;
  1170. break;
  1171. case ALG_TKIP:
  1172. case ALG_WEP:
  1173. default:
  1174. return -EINVAL;
  1175. }
  1176. spin_lock_irqsave(&priv->sta_lock, flags);
  1177. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1178. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1179. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1180. keyconf->keylen);
  1181. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1182. keyconf->keylen);
  1183. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1184. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1185. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1186. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1187. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1188. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1189. return 0;
  1190. }
  1191. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1192. {
  1193. unsigned long flags;
  1194. spin_lock_irqsave(&priv->sta_lock, flags);
  1195. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1196. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1197. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1198. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1199. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1200. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1201. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1202. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1203. return 0;
  1204. }
  1205. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1206. {
  1207. struct list_head *element;
  1208. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1209. priv->frames_count);
  1210. while (!list_empty(&priv->free_frames)) {
  1211. element = priv->free_frames.next;
  1212. list_del(element);
  1213. kfree(list_entry(element, struct iwl3945_frame, list));
  1214. priv->frames_count--;
  1215. }
  1216. if (priv->frames_count) {
  1217. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1218. priv->frames_count);
  1219. priv->frames_count = 0;
  1220. }
  1221. }
  1222. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1223. {
  1224. struct iwl3945_frame *frame;
  1225. struct list_head *element;
  1226. if (list_empty(&priv->free_frames)) {
  1227. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1228. if (!frame) {
  1229. IWL_ERROR("Could not allocate frame!\n");
  1230. return NULL;
  1231. }
  1232. priv->frames_count++;
  1233. return frame;
  1234. }
  1235. element = priv->free_frames.next;
  1236. list_del(element);
  1237. return list_entry(element, struct iwl3945_frame, list);
  1238. }
  1239. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1240. {
  1241. memset(frame, 0, sizeof(*frame));
  1242. list_add(&frame->list, &priv->free_frames);
  1243. }
  1244. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1245. struct ieee80211_hdr *hdr,
  1246. const u8 *dest, int left)
  1247. {
  1248. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1249. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1250. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1251. return 0;
  1252. if (priv->ibss_beacon->len > left)
  1253. return 0;
  1254. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1255. return priv->ibss_beacon->len;
  1256. }
  1257. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1258. {
  1259. u8 i;
  1260. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1261. i = iwl3945_rates[i].next_ieee) {
  1262. if (rate_mask & (1 << i))
  1263. return iwl3945_rates[i].plcp;
  1264. }
  1265. return IWL_RATE_INVALID;
  1266. }
  1267. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1268. {
  1269. struct iwl3945_frame *frame;
  1270. unsigned int frame_size;
  1271. int rc;
  1272. u8 rate;
  1273. frame = iwl3945_get_free_frame(priv);
  1274. if (!frame) {
  1275. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1276. "command.\n");
  1277. return -ENOMEM;
  1278. }
  1279. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1280. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1281. 0xFF0);
  1282. if (rate == IWL_INVALID_RATE)
  1283. rate = IWL_RATE_6M_PLCP;
  1284. } else {
  1285. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1286. if (rate == IWL_INVALID_RATE)
  1287. rate = IWL_RATE_1M_PLCP;
  1288. }
  1289. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1290. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1291. &frame->u.cmd[0]);
  1292. iwl3945_free_frame(priv, frame);
  1293. return rc;
  1294. }
  1295. /******************************************************************************
  1296. *
  1297. * EEPROM related functions
  1298. *
  1299. ******************************************************************************/
  1300. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1301. {
  1302. memcpy(mac, priv->eeprom.mac_address, 6);
  1303. }
  1304. /*
  1305. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1306. * embedded controller) as EEPROM reader; each read is a series of pulses
  1307. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1308. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1309. * simply claims ownership, which should be safe when this function is called
  1310. * (i.e. before loading uCode!).
  1311. */
  1312. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1313. {
  1314. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1315. return 0;
  1316. }
  1317. /**
  1318. * iwl3945_eeprom_init - read EEPROM contents
  1319. *
  1320. * Load the EEPROM contents from adapter into priv->eeprom
  1321. *
  1322. * NOTE: This routine uses the non-debug IO access functions.
  1323. */
  1324. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1325. {
  1326. u16 *e = (u16 *)&priv->eeprom;
  1327. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1328. u32 r;
  1329. int sz = sizeof(priv->eeprom);
  1330. int rc;
  1331. int i;
  1332. u16 addr;
  1333. /* The EEPROM structure has several padding buffers within it
  1334. * and when adding new EEPROM maps is subject to programmer errors
  1335. * which may be very difficult to identify without explicitly
  1336. * checking the resulting size of the eeprom map. */
  1337. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1338. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1339. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1340. return -ENOENT;
  1341. }
  1342. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1343. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1344. if (rc < 0) {
  1345. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1346. return -ENOENT;
  1347. }
  1348. /* eeprom is an array of 16bit values */
  1349. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1350. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1351. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1352. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1353. i += IWL_EEPROM_ACCESS_DELAY) {
  1354. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1355. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1356. break;
  1357. udelay(IWL_EEPROM_ACCESS_DELAY);
  1358. }
  1359. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1360. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1361. return -ETIMEDOUT;
  1362. }
  1363. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1364. }
  1365. return 0;
  1366. }
  1367. /******************************************************************************
  1368. *
  1369. * Misc. internal state and helper functions
  1370. *
  1371. ******************************************************************************/
  1372. #ifdef CONFIG_IWL3945_DEBUG
  1373. /**
  1374. * iwl3945_report_frame - dump frame to syslog during debug sessions
  1375. *
  1376. * You may hack this function to show different aspects of received frames,
  1377. * including selective frame dumps.
  1378. * group100 parameter selects whether to show 1 out of 100 good frames.
  1379. */
  1380. void iwl3945_report_frame(struct iwl3945_priv *priv,
  1381. struct iwl3945_rx_packet *pkt,
  1382. struct ieee80211_hdr *header, int group100)
  1383. {
  1384. u32 to_us;
  1385. u32 print_summary = 0;
  1386. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  1387. u32 hundred = 0;
  1388. u32 dataframe = 0;
  1389. u16 fc;
  1390. u16 seq_ctl;
  1391. u16 channel;
  1392. u16 phy_flags;
  1393. int rate_sym;
  1394. u16 length;
  1395. u16 status;
  1396. u16 bcn_tmr;
  1397. u32 tsf_low;
  1398. u64 tsf;
  1399. u8 rssi;
  1400. u8 agc;
  1401. u16 sig_avg;
  1402. u16 noise_diff;
  1403. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  1404. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  1405. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  1406. u8 *data = IWL_RX_DATA(pkt);
  1407. /* MAC header */
  1408. fc = le16_to_cpu(header->frame_control);
  1409. seq_ctl = le16_to_cpu(header->seq_ctrl);
  1410. /* metadata */
  1411. channel = le16_to_cpu(rx_hdr->channel);
  1412. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  1413. rate_sym = rx_hdr->rate;
  1414. length = le16_to_cpu(rx_hdr->len);
  1415. /* end-of-frame status and timestamp */
  1416. status = le32_to_cpu(rx_end->status);
  1417. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  1418. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  1419. tsf = le64_to_cpu(rx_end->timestamp);
  1420. /* signal statistics */
  1421. rssi = rx_stats->rssi;
  1422. agc = rx_stats->agc;
  1423. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  1424. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  1425. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  1426. /* if data frame is to us and all is good,
  1427. * (optionally) print summary for only 1 out of every 100 */
  1428. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  1429. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  1430. dataframe = 1;
  1431. if (!group100)
  1432. print_summary = 1; /* print each frame */
  1433. else if (priv->framecnt_to_us < 100) {
  1434. priv->framecnt_to_us++;
  1435. print_summary = 0;
  1436. } else {
  1437. priv->framecnt_to_us = 0;
  1438. print_summary = 1;
  1439. hundred = 1;
  1440. }
  1441. } else {
  1442. /* print summary for all other frames */
  1443. print_summary = 1;
  1444. }
  1445. if (print_summary) {
  1446. char *title;
  1447. u32 rate;
  1448. if (hundred)
  1449. title = "100Frames";
  1450. else if (fc & IEEE80211_FCTL_RETRY)
  1451. title = "Retry";
  1452. else if (ieee80211_is_assoc_response(fc))
  1453. title = "AscRsp";
  1454. else if (ieee80211_is_reassoc_response(fc))
  1455. title = "RasRsp";
  1456. else if (ieee80211_is_probe_response(fc)) {
  1457. title = "PrbRsp";
  1458. print_dump = 1; /* dump frame contents */
  1459. } else if (ieee80211_is_beacon(fc)) {
  1460. title = "Beacon";
  1461. print_dump = 1; /* dump frame contents */
  1462. } else if (ieee80211_is_atim(fc))
  1463. title = "ATIM";
  1464. else if (ieee80211_is_auth(fc))
  1465. title = "Auth";
  1466. else if (ieee80211_is_deauth(fc))
  1467. title = "DeAuth";
  1468. else if (ieee80211_is_disassoc(fc))
  1469. title = "DisAssoc";
  1470. else
  1471. title = "Frame";
  1472. rate = iwl3945_rate_index_from_plcp(rate_sym);
  1473. if (rate == -1)
  1474. rate = 0;
  1475. else
  1476. rate = iwl3945_rates[rate].ieee / 2;
  1477. /* print frame summary.
  1478. * MAC addresses show just the last byte (for brevity),
  1479. * but you can hack it to show more, if you'd like to. */
  1480. if (dataframe)
  1481. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  1482. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  1483. title, fc, header->addr1[5],
  1484. length, rssi, channel, rate);
  1485. else {
  1486. /* src/dst addresses assume managed mode */
  1487. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  1488. "src=0x%02x, rssi=%u, tim=%lu usec, "
  1489. "phy=0x%02x, chnl=%d\n",
  1490. title, fc, header->addr1[5],
  1491. header->addr3[5], rssi,
  1492. tsf_low - priv->scan_start_tsf,
  1493. phy_flags, channel);
  1494. }
  1495. }
  1496. if (print_dump)
  1497. iwl3945_print_hex_dump(IWL_DL_RX, data, length);
  1498. }
  1499. #endif
  1500. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1501. {
  1502. if (priv->hw_setting.shared_virt)
  1503. pci_free_consistent(priv->pci_dev,
  1504. sizeof(struct iwl3945_shared),
  1505. priv->hw_setting.shared_virt,
  1506. priv->hw_setting.shared_phys);
  1507. }
  1508. /**
  1509. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1510. *
  1511. * return : set the bit for each supported rate insert in ie
  1512. */
  1513. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1514. u16 basic_rate, int *left)
  1515. {
  1516. u16 ret_rates = 0, bit;
  1517. int i;
  1518. u8 *cnt = ie;
  1519. u8 *rates = ie + 1;
  1520. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1521. if (bit & supported_rate) {
  1522. ret_rates |= bit;
  1523. rates[*cnt] = iwl3945_rates[i].ieee |
  1524. ((bit & basic_rate) ? 0x80 : 0x00);
  1525. (*cnt)++;
  1526. (*left)--;
  1527. if ((*left <= 0) ||
  1528. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1529. break;
  1530. }
  1531. }
  1532. return ret_rates;
  1533. }
  1534. /**
  1535. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1536. */
  1537. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1538. struct ieee80211_mgmt *frame,
  1539. int left, int is_direct)
  1540. {
  1541. int len = 0;
  1542. u8 *pos = NULL;
  1543. u16 active_rates, ret_rates, cck_rates;
  1544. /* Make sure there is enough space for the probe request,
  1545. * two mandatory IEs and the data */
  1546. left -= 24;
  1547. if (left < 0)
  1548. return 0;
  1549. len += 24;
  1550. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1551. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1552. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1553. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1554. frame->seq_ctrl = 0;
  1555. /* fill in our indirect SSID IE */
  1556. /* ...next IE... */
  1557. left -= 2;
  1558. if (left < 0)
  1559. return 0;
  1560. len += 2;
  1561. pos = &(frame->u.probe_req.variable[0]);
  1562. *pos++ = WLAN_EID_SSID;
  1563. *pos++ = 0;
  1564. /* fill in our direct SSID IE... */
  1565. if (is_direct) {
  1566. /* ...next IE... */
  1567. left -= 2 + priv->essid_len;
  1568. if (left < 0)
  1569. return 0;
  1570. /* ... fill it in... */
  1571. *pos++ = WLAN_EID_SSID;
  1572. *pos++ = priv->essid_len;
  1573. memcpy(pos, priv->essid, priv->essid_len);
  1574. pos += priv->essid_len;
  1575. len += 2 + priv->essid_len;
  1576. }
  1577. /* fill in supported rate */
  1578. /* ...next IE... */
  1579. left -= 2;
  1580. if (left < 0)
  1581. return 0;
  1582. /* ... fill it in... */
  1583. *pos++ = WLAN_EID_SUPP_RATES;
  1584. *pos = 0;
  1585. priv->active_rate = priv->rates_mask;
  1586. active_rates = priv->active_rate;
  1587. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1588. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1589. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1590. priv->active_rate_basic, &left);
  1591. active_rates &= ~ret_rates;
  1592. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1593. priv->active_rate_basic, &left);
  1594. active_rates &= ~ret_rates;
  1595. len += 2 + *pos;
  1596. pos += (*pos) + 1;
  1597. if (active_rates == 0)
  1598. goto fill_end;
  1599. /* fill in supported extended rate */
  1600. /* ...next IE... */
  1601. left -= 2;
  1602. if (left < 0)
  1603. return 0;
  1604. /* ... fill it in... */
  1605. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1606. *pos = 0;
  1607. iwl3945_supported_rate_to_ie(pos, active_rates,
  1608. priv->active_rate_basic, &left);
  1609. if (*pos > 0)
  1610. len += 2 + *pos;
  1611. fill_end:
  1612. return (u16)len;
  1613. }
  1614. /*
  1615. * QoS support
  1616. */
  1617. #ifdef CONFIG_IWL3945_QOS
  1618. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1619. struct iwl3945_qosparam_cmd *qos)
  1620. {
  1621. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1622. sizeof(struct iwl3945_qosparam_cmd), qos);
  1623. }
  1624. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1625. {
  1626. u16 cw_min = 15;
  1627. u16 cw_max = 1023;
  1628. u8 aifs = 2;
  1629. u8 is_legacy = 0;
  1630. unsigned long flags;
  1631. int i;
  1632. spin_lock_irqsave(&priv->lock, flags);
  1633. priv->qos_data.qos_active = 0;
  1634. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1635. if (priv->qos_data.qos_enable)
  1636. priv->qos_data.qos_active = 1;
  1637. if (!(priv->active_rate & 0xfff0)) {
  1638. cw_min = 31;
  1639. is_legacy = 1;
  1640. }
  1641. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1642. if (priv->qos_data.qos_enable)
  1643. priv->qos_data.qos_active = 1;
  1644. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1645. cw_min = 31;
  1646. is_legacy = 1;
  1647. }
  1648. if (priv->qos_data.qos_active)
  1649. aifs = 3;
  1650. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1651. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1652. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1653. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1654. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1655. if (priv->qos_data.qos_active) {
  1656. i = 1;
  1657. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1658. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1659. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1660. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1661. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1662. i = 2;
  1663. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1664. cpu_to_le16((cw_min + 1) / 2 - 1);
  1665. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1666. cpu_to_le16(cw_max);
  1667. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1668. if (is_legacy)
  1669. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1670. cpu_to_le16(6016);
  1671. else
  1672. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1673. cpu_to_le16(3008);
  1674. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1675. i = 3;
  1676. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1677. cpu_to_le16((cw_min + 1) / 4 - 1);
  1678. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1679. cpu_to_le16((cw_max + 1) / 2 - 1);
  1680. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1681. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1682. if (is_legacy)
  1683. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1684. cpu_to_le16(3264);
  1685. else
  1686. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1687. cpu_to_le16(1504);
  1688. } else {
  1689. for (i = 1; i < 4; i++) {
  1690. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1691. cpu_to_le16(cw_min);
  1692. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1693. cpu_to_le16(cw_max);
  1694. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1695. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1696. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1697. }
  1698. }
  1699. IWL_DEBUG_QOS("set QoS to default \n");
  1700. spin_unlock_irqrestore(&priv->lock, flags);
  1701. }
  1702. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1703. {
  1704. unsigned long flags;
  1705. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1706. return;
  1707. if (!priv->qos_data.qos_enable)
  1708. return;
  1709. spin_lock_irqsave(&priv->lock, flags);
  1710. priv->qos_data.def_qos_parm.qos_flags = 0;
  1711. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1712. !priv->qos_data.qos_cap.q_AP.txop_request)
  1713. priv->qos_data.def_qos_parm.qos_flags |=
  1714. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1715. if (priv->qos_data.qos_active)
  1716. priv->qos_data.def_qos_parm.qos_flags |=
  1717. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1718. spin_unlock_irqrestore(&priv->lock, flags);
  1719. if (force || iwl3945_is_associated(priv)) {
  1720. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1721. priv->qos_data.qos_active);
  1722. iwl3945_send_qos_params_command(priv,
  1723. &(priv->qos_data.def_qos_parm));
  1724. }
  1725. }
  1726. #endif /* CONFIG_IWL3945_QOS */
  1727. /*
  1728. * Power management (not Tx power!) functions
  1729. */
  1730. #define MSEC_TO_USEC 1024
  1731. #define NOSLP __constant_cpu_to_le32(0)
  1732. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1733. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1734. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1735. __constant_cpu_to_le32(X1), \
  1736. __constant_cpu_to_le32(X2), \
  1737. __constant_cpu_to_le32(X3), \
  1738. __constant_cpu_to_le32(X4)}
  1739. /* default power management (not Tx power) table values */
  1740. /* for tim 0-10 */
  1741. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1742. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1743. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1744. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1745. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1746. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1747. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1748. };
  1749. /* for tim > 10 */
  1750. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1751. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1752. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1753. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1754. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1755. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1756. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1757. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1758. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1759. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1760. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1761. };
  1762. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1763. {
  1764. int rc = 0, i;
  1765. struct iwl3945_power_mgr *pow_data;
  1766. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1767. u16 pci_pm;
  1768. IWL_DEBUG_POWER("Initialize power \n");
  1769. pow_data = &(priv->power_data);
  1770. memset(pow_data, 0, sizeof(*pow_data));
  1771. pow_data->active_index = IWL_POWER_RANGE_0;
  1772. pow_data->dtim_val = 0xffff;
  1773. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1774. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1775. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1776. if (rc != 0)
  1777. return 0;
  1778. else {
  1779. struct iwl3945_powertable_cmd *cmd;
  1780. IWL_DEBUG_POWER("adjust power command flags\n");
  1781. for (i = 0; i < IWL_POWER_AC; i++) {
  1782. cmd = &pow_data->pwr_range_0[i].cmd;
  1783. if (pci_pm & 0x1)
  1784. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1785. else
  1786. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1787. }
  1788. }
  1789. return rc;
  1790. }
  1791. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1792. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1793. {
  1794. int rc = 0, i;
  1795. u8 skip;
  1796. u32 max_sleep = 0;
  1797. struct iwl3945_power_vec_entry *range;
  1798. u8 period = 0;
  1799. struct iwl3945_power_mgr *pow_data;
  1800. if (mode > IWL_POWER_INDEX_5) {
  1801. IWL_DEBUG_POWER("Error invalid power mode \n");
  1802. return -1;
  1803. }
  1804. pow_data = &(priv->power_data);
  1805. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1806. range = &pow_data->pwr_range_0[0];
  1807. else
  1808. range = &pow_data->pwr_range_1[1];
  1809. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1810. #ifdef IWL_MAC80211_DISABLE
  1811. if (priv->assoc_network != NULL) {
  1812. unsigned long flags;
  1813. period = priv->assoc_network->tim.tim_period;
  1814. }
  1815. #endif /*IWL_MAC80211_DISABLE */
  1816. skip = range[mode].no_dtim;
  1817. if (period == 0) {
  1818. period = 1;
  1819. skip = 0;
  1820. }
  1821. if (skip == 0) {
  1822. max_sleep = period;
  1823. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1824. } else {
  1825. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1826. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1827. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1828. }
  1829. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1830. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1831. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1832. }
  1833. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1834. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1835. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1836. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1837. le32_to_cpu(cmd->sleep_interval[0]),
  1838. le32_to_cpu(cmd->sleep_interval[1]),
  1839. le32_to_cpu(cmd->sleep_interval[2]),
  1840. le32_to_cpu(cmd->sleep_interval[3]),
  1841. le32_to_cpu(cmd->sleep_interval[4]));
  1842. return rc;
  1843. }
  1844. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1845. {
  1846. u32 uninitialized_var(final_mode);
  1847. int rc;
  1848. struct iwl3945_powertable_cmd cmd;
  1849. /* If on battery, set to 3,
  1850. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1851. * else user level */
  1852. switch (mode) {
  1853. case IWL_POWER_BATTERY:
  1854. final_mode = IWL_POWER_INDEX_3;
  1855. break;
  1856. case IWL_POWER_AC:
  1857. final_mode = IWL_POWER_MODE_CAM;
  1858. break;
  1859. default:
  1860. final_mode = mode;
  1861. break;
  1862. }
  1863. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1864. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1865. if (final_mode == IWL_POWER_MODE_CAM)
  1866. clear_bit(STATUS_POWER_PMI, &priv->status);
  1867. else
  1868. set_bit(STATUS_POWER_PMI, &priv->status);
  1869. return rc;
  1870. }
  1871. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1872. {
  1873. /* Filter incoming packets to determine if they are targeted toward
  1874. * this network, discarding packets coming from ourselves */
  1875. switch (priv->iw_mode) {
  1876. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1877. /* packets from our adapter are dropped (echo) */
  1878. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1879. return 0;
  1880. /* {broad,multi}cast packets to our IBSS go through */
  1881. if (is_multicast_ether_addr(header->addr1))
  1882. return !compare_ether_addr(header->addr3, priv->bssid);
  1883. /* packets to our adapter go through */
  1884. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1885. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1886. /* packets from our adapter are dropped (echo) */
  1887. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1888. return 0;
  1889. /* {broad,multi}cast packets to our BSS go through */
  1890. if (is_multicast_ether_addr(header->addr1))
  1891. return !compare_ether_addr(header->addr2, priv->bssid);
  1892. /* packets to our adapter go through */
  1893. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1894. }
  1895. return 1;
  1896. }
  1897. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1898. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1899. {
  1900. switch (status & TX_STATUS_MSK) {
  1901. case TX_STATUS_SUCCESS:
  1902. return "SUCCESS";
  1903. TX_STATUS_ENTRY(SHORT_LIMIT);
  1904. TX_STATUS_ENTRY(LONG_LIMIT);
  1905. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1906. TX_STATUS_ENTRY(MGMNT_ABORT);
  1907. TX_STATUS_ENTRY(NEXT_FRAG);
  1908. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1909. TX_STATUS_ENTRY(DEST_PS);
  1910. TX_STATUS_ENTRY(ABORTED);
  1911. TX_STATUS_ENTRY(BT_RETRY);
  1912. TX_STATUS_ENTRY(STA_INVALID);
  1913. TX_STATUS_ENTRY(FRAG_DROPPED);
  1914. TX_STATUS_ENTRY(TID_DISABLE);
  1915. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1916. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1917. TX_STATUS_ENTRY(TX_LOCKED);
  1918. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1919. }
  1920. return "UNKNOWN";
  1921. }
  1922. /**
  1923. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1924. *
  1925. * NOTE: priv->mutex is not required before calling this function
  1926. */
  1927. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1928. {
  1929. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1930. clear_bit(STATUS_SCANNING, &priv->status);
  1931. return 0;
  1932. }
  1933. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1934. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1935. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1936. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1937. queue_work(priv->workqueue, &priv->abort_scan);
  1938. } else
  1939. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1940. return test_bit(STATUS_SCANNING, &priv->status);
  1941. }
  1942. return 0;
  1943. }
  1944. /**
  1945. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1946. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1947. *
  1948. * NOTE: priv->mutex must be held before calling this function
  1949. */
  1950. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1951. {
  1952. unsigned long now = jiffies;
  1953. int ret;
  1954. ret = iwl3945_scan_cancel(priv);
  1955. if (ret && ms) {
  1956. mutex_unlock(&priv->mutex);
  1957. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1958. test_bit(STATUS_SCANNING, &priv->status))
  1959. msleep(1);
  1960. mutex_lock(&priv->mutex);
  1961. return test_bit(STATUS_SCANNING, &priv->status);
  1962. }
  1963. return ret;
  1964. }
  1965. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1966. {
  1967. /* Reset ieee stats */
  1968. /* We don't reset the net_device_stats (ieee->stats) on
  1969. * re-association */
  1970. priv->last_seq_num = -1;
  1971. priv->last_frag_num = -1;
  1972. priv->last_packet_time = 0;
  1973. iwl3945_scan_cancel(priv);
  1974. }
  1975. #define MAX_UCODE_BEACON_INTERVAL 1024
  1976. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1977. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1978. {
  1979. u16 new_val = 0;
  1980. u16 beacon_factor = 0;
  1981. beacon_factor =
  1982. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1983. / MAX_UCODE_BEACON_INTERVAL;
  1984. new_val = beacon_val / beacon_factor;
  1985. return cpu_to_le16(new_val);
  1986. }
  1987. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1988. {
  1989. u64 interval_tm_unit;
  1990. u64 tsf, result;
  1991. unsigned long flags;
  1992. struct ieee80211_conf *conf = NULL;
  1993. u16 beacon_int = 0;
  1994. conf = ieee80211_get_hw_conf(priv->hw);
  1995. spin_lock_irqsave(&priv->lock, flags);
  1996. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1997. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1998. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1999. tsf = priv->timestamp1;
  2000. tsf = ((tsf << 32) | priv->timestamp0);
  2001. beacon_int = priv->beacon_int;
  2002. spin_unlock_irqrestore(&priv->lock, flags);
  2003. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  2004. if (beacon_int == 0) {
  2005. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  2006. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  2007. } else {
  2008. priv->rxon_timing.beacon_interval =
  2009. cpu_to_le16(beacon_int);
  2010. priv->rxon_timing.beacon_interval =
  2011. iwl3945_adjust_beacon_interval(
  2012. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2013. }
  2014. priv->rxon_timing.atim_window = 0;
  2015. } else {
  2016. priv->rxon_timing.beacon_interval =
  2017. iwl3945_adjust_beacon_interval(conf->beacon_int);
  2018. /* TODO: we need to get atim_window from upper stack
  2019. * for now we set to 0 */
  2020. priv->rxon_timing.atim_window = 0;
  2021. }
  2022. interval_tm_unit =
  2023. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  2024. result = do_div(tsf, interval_tm_unit);
  2025. priv->rxon_timing.beacon_init_val =
  2026. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  2027. IWL_DEBUG_ASSOC
  2028. ("beacon interval %d beacon timer %d beacon tim %d\n",
  2029. le16_to_cpu(priv->rxon_timing.beacon_interval),
  2030. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  2031. le16_to_cpu(priv->rxon_timing.atim_window));
  2032. }
  2033. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  2034. {
  2035. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  2036. IWL_ERROR("APs don't scan.\n");
  2037. return 0;
  2038. }
  2039. if (!iwl3945_is_ready_rf(priv)) {
  2040. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  2041. return -EIO;
  2042. }
  2043. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2044. IWL_DEBUG_SCAN("Scan already in progress.\n");
  2045. return -EAGAIN;
  2046. }
  2047. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2048. IWL_DEBUG_SCAN("Scan request while abort pending. "
  2049. "Queuing.\n");
  2050. return -EAGAIN;
  2051. }
  2052. IWL_DEBUG_INFO("Starting scan...\n");
  2053. priv->scan_bands = 2;
  2054. set_bit(STATUS_SCANNING, &priv->status);
  2055. priv->scan_start = jiffies;
  2056. priv->scan_pass_start = priv->scan_start;
  2057. queue_work(priv->workqueue, &priv->request_scan);
  2058. return 0;
  2059. }
  2060. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  2061. {
  2062. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  2063. if (hw_decrypt)
  2064. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  2065. else
  2066. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  2067. return 0;
  2068. }
  2069. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  2070. enum ieee80211_band band)
  2071. {
  2072. if (band == IEEE80211_BAND_5GHZ) {
  2073. priv->staging_rxon.flags &=
  2074. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  2075. | RXON_FLG_CCK_MSK);
  2076. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2077. } else {
  2078. /* Copied from iwl3945_bg_post_associate() */
  2079. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2080. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2081. else
  2082. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2083. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  2084. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2085. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  2086. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  2087. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  2088. }
  2089. }
  2090. /*
  2091. * initialize rxon structure with default values from eeprom
  2092. */
  2093. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  2094. {
  2095. const struct iwl3945_channel_info *ch_info;
  2096. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  2097. switch (priv->iw_mode) {
  2098. case IEEE80211_IF_TYPE_AP:
  2099. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  2100. break;
  2101. case IEEE80211_IF_TYPE_STA:
  2102. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  2103. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  2104. break;
  2105. case IEEE80211_IF_TYPE_IBSS:
  2106. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  2107. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  2108. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  2109. RXON_FILTER_ACCEPT_GRP_MSK;
  2110. break;
  2111. case IEEE80211_IF_TYPE_MNTR:
  2112. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  2113. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  2114. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  2115. break;
  2116. }
  2117. #if 0
  2118. /* TODO: Figure out when short_preamble would be set and cache from
  2119. * that */
  2120. if (!hw_to_local(priv->hw)->short_preamble)
  2121. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2122. else
  2123. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2124. #endif
  2125. ch_info = iwl3945_get_channel_info(priv, priv->band,
  2126. le16_to_cpu(priv->staging_rxon.channel));
  2127. if (!ch_info)
  2128. ch_info = &priv->channel_info[0];
  2129. /*
  2130. * in some case A channels are all non IBSS
  2131. * in this case force B/G channel
  2132. */
  2133. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  2134. !(is_channel_ibss(ch_info)))
  2135. ch_info = &priv->channel_info[0];
  2136. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  2137. if (is_channel_a_band(ch_info))
  2138. priv->band = IEEE80211_BAND_5GHZ;
  2139. else
  2140. priv->band = IEEE80211_BAND_2GHZ;
  2141. iwl3945_set_flags_for_phymode(priv, priv->band);
  2142. priv->staging_rxon.ofdm_basic_rates =
  2143. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2144. priv->staging_rxon.cck_basic_rates =
  2145. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2146. }
  2147. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  2148. {
  2149. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2150. const struct iwl3945_channel_info *ch_info;
  2151. ch_info = iwl3945_get_channel_info(priv,
  2152. priv->band,
  2153. le16_to_cpu(priv->staging_rxon.channel));
  2154. if (!ch_info || !is_channel_ibss(ch_info)) {
  2155. IWL_ERROR("channel %d not IBSS channel\n",
  2156. le16_to_cpu(priv->staging_rxon.channel));
  2157. return -EINVAL;
  2158. }
  2159. }
  2160. priv->iw_mode = mode;
  2161. iwl3945_connection_init_rx_config(priv);
  2162. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2163. iwl3945_clear_stations_table(priv);
  2164. /* dont commit rxon if rf-kill is on*/
  2165. if (!iwl3945_is_ready_rf(priv))
  2166. return -EAGAIN;
  2167. cancel_delayed_work(&priv->scan_check);
  2168. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2169. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2170. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2171. return -EAGAIN;
  2172. }
  2173. iwl3945_commit_rxon(priv);
  2174. return 0;
  2175. }
  2176. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2177. struct ieee80211_tx_control *ctl,
  2178. struct iwl3945_cmd *cmd,
  2179. struct sk_buff *skb_frag,
  2180. int last_frag)
  2181. {
  2182. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2183. switch (keyinfo->alg) {
  2184. case ALG_CCMP:
  2185. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2186. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2187. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2188. break;
  2189. case ALG_TKIP:
  2190. #if 0
  2191. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2192. if (last_frag)
  2193. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2194. 8);
  2195. else
  2196. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2197. #endif
  2198. break;
  2199. case ALG_WEP:
  2200. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2201. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2202. if (keyinfo->keylen == 13)
  2203. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2204. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2205. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2206. "with key %d\n", ctl->key_idx);
  2207. break;
  2208. default:
  2209. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2210. break;
  2211. }
  2212. }
  2213. /*
  2214. * handle build REPLY_TX command notification.
  2215. */
  2216. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2217. struct iwl3945_cmd *cmd,
  2218. struct ieee80211_tx_control *ctrl,
  2219. struct ieee80211_hdr *hdr,
  2220. int is_unicast, u8 std_id)
  2221. {
  2222. __le16 *qc;
  2223. u16 fc = le16_to_cpu(hdr->frame_control);
  2224. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2225. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2226. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2227. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2228. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2229. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2230. if (ieee80211_is_probe_response(fc) &&
  2231. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2232. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2233. } else {
  2234. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2235. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2236. }
  2237. cmd->cmd.tx.sta_id = std_id;
  2238. if (ieee80211_get_morefrag(hdr))
  2239. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2240. qc = ieee80211_get_qos_ctrl(hdr);
  2241. if (qc) {
  2242. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2243. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2244. } else
  2245. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2246. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2247. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2248. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2249. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2250. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2251. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2252. }
  2253. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2254. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2255. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2256. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2257. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2258. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2259. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2260. else
  2261. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2262. } else
  2263. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2264. cmd->cmd.tx.driver_txop = 0;
  2265. cmd->cmd.tx.tx_flags = tx_flags;
  2266. cmd->cmd.tx.next_frame_len = 0;
  2267. }
  2268. /**
  2269. * iwl3945_get_sta_id - Find station's index within station table
  2270. */
  2271. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2272. {
  2273. int sta_id;
  2274. u16 fc = le16_to_cpu(hdr->frame_control);
  2275. /* If this frame is broadcast or management, use broadcast station id */
  2276. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2277. is_multicast_ether_addr(hdr->addr1))
  2278. return priv->hw_setting.bcast_sta_id;
  2279. switch (priv->iw_mode) {
  2280. /* If we are a client station in a BSS network, use the special
  2281. * AP station entry (that's the only station we communicate with) */
  2282. case IEEE80211_IF_TYPE_STA:
  2283. return IWL_AP_ID;
  2284. /* If we are an AP, then find the station, or use BCAST */
  2285. case IEEE80211_IF_TYPE_AP:
  2286. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2287. if (sta_id != IWL_INVALID_STATION)
  2288. return sta_id;
  2289. return priv->hw_setting.bcast_sta_id;
  2290. /* If this frame is going out to an IBSS network, find the station,
  2291. * or create a new station table entry */
  2292. case IEEE80211_IF_TYPE_IBSS: {
  2293. DECLARE_MAC_BUF(mac);
  2294. /* Create new station table entry */
  2295. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2296. if (sta_id != IWL_INVALID_STATION)
  2297. return sta_id;
  2298. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2299. if (sta_id != IWL_INVALID_STATION)
  2300. return sta_id;
  2301. IWL_DEBUG_DROP("Station %s not in station map. "
  2302. "Defaulting to broadcast...\n",
  2303. print_mac(mac, hdr->addr1));
  2304. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2305. return priv->hw_setting.bcast_sta_id;
  2306. }
  2307. default:
  2308. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2309. return priv->hw_setting.bcast_sta_id;
  2310. }
  2311. }
  2312. /*
  2313. * start REPLY_TX command process
  2314. */
  2315. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2316. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2317. {
  2318. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2319. struct iwl3945_tfd_frame *tfd;
  2320. u32 *control_flags;
  2321. int txq_id = ctl->queue;
  2322. struct iwl3945_tx_queue *txq = NULL;
  2323. struct iwl3945_queue *q = NULL;
  2324. dma_addr_t phys_addr;
  2325. dma_addr_t txcmd_phys;
  2326. struct iwl3945_cmd *out_cmd = NULL;
  2327. u16 len, idx, len_org;
  2328. u8 id, hdr_len, unicast;
  2329. u8 sta_id;
  2330. u16 seq_number = 0;
  2331. u16 fc;
  2332. __le16 *qc;
  2333. u8 wait_write_ptr = 0;
  2334. unsigned long flags;
  2335. int rc;
  2336. spin_lock_irqsave(&priv->lock, flags);
  2337. if (iwl3945_is_rfkill(priv)) {
  2338. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2339. goto drop_unlock;
  2340. }
  2341. if (!priv->vif) {
  2342. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2343. goto drop_unlock;
  2344. }
  2345. if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2346. IWL_ERROR("ERROR: No TX rate available.\n");
  2347. goto drop_unlock;
  2348. }
  2349. unicast = !is_multicast_ether_addr(hdr->addr1);
  2350. id = 0;
  2351. fc = le16_to_cpu(hdr->frame_control);
  2352. #ifdef CONFIG_IWL3945_DEBUG
  2353. if (ieee80211_is_auth(fc))
  2354. IWL_DEBUG_TX("Sending AUTH frame\n");
  2355. else if (ieee80211_is_assoc_request(fc))
  2356. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2357. else if (ieee80211_is_reassoc_request(fc))
  2358. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2359. #endif
  2360. /* drop all data frame if we are not associated */
  2361. if ((!iwl3945_is_associated(priv) ||
  2362. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2363. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2364. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2365. goto drop_unlock;
  2366. }
  2367. spin_unlock_irqrestore(&priv->lock, flags);
  2368. hdr_len = ieee80211_get_hdrlen(fc);
  2369. /* Find (or create) index into station table for destination station */
  2370. sta_id = iwl3945_get_sta_id(priv, hdr);
  2371. if (sta_id == IWL_INVALID_STATION) {
  2372. DECLARE_MAC_BUF(mac);
  2373. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2374. print_mac(mac, hdr->addr1));
  2375. goto drop;
  2376. }
  2377. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2378. qc = ieee80211_get_qos_ctrl(hdr);
  2379. if (qc) {
  2380. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2381. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2382. IEEE80211_SCTL_SEQ;
  2383. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2384. (hdr->seq_ctrl &
  2385. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2386. seq_number += 0x10;
  2387. }
  2388. /* Descriptor for chosen Tx queue */
  2389. txq = &priv->txq[txq_id];
  2390. q = &txq->q;
  2391. spin_lock_irqsave(&priv->lock, flags);
  2392. /* Set up first empty TFD within this queue's circular TFD buffer */
  2393. tfd = &txq->bd[q->write_ptr];
  2394. memset(tfd, 0, sizeof(*tfd));
  2395. control_flags = (u32 *) tfd;
  2396. idx = get_cmd_index(q, q->write_ptr, 0);
  2397. /* Set up driver data for this TFD */
  2398. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2399. txq->txb[q->write_ptr].skb[0] = skb;
  2400. memcpy(&(txq->txb[q->write_ptr].status.control),
  2401. ctl, sizeof(struct ieee80211_tx_control));
  2402. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2403. out_cmd = &txq->cmd[idx];
  2404. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2405. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2406. /*
  2407. * Set up the Tx-command (not MAC!) header.
  2408. * Store the chosen Tx queue and TFD index within the sequence field;
  2409. * after Tx, uCode's Tx response will return this value so driver can
  2410. * locate the frame within the tx queue and do post-tx processing.
  2411. */
  2412. out_cmd->hdr.cmd = REPLY_TX;
  2413. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2414. INDEX_TO_SEQ(q->write_ptr)));
  2415. /* Copy MAC header from skb into command buffer */
  2416. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2417. /*
  2418. * Use the first empty entry in this queue's command buffer array
  2419. * to contain the Tx command and MAC header concatenated together
  2420. * (payload data will be in another buffer).
  2421. * Size of this varies, due to varying MAC header length.
  2422. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2423. * of the MAC header (device reads on dword boundaries).
  2424. * We'll tell device about this padding later.
  2425. */
  2426. len = priv->hw_setting.tx_cmd_len +
  2427. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2428. len_org = len;
  2429. len = (len + 3) & ~3;
  2430. if (len_org != len)
  2431. len_org = 1;
  2432. else
  2433. len_org = 0;
  2434. /* Physical address of this Tx command's header (not MAC header!),
  2435. * within command buffer array. */
  2436. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2437. offsetof(struct iwl3945_cmd, hdr);
  2438. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2439. * first entry */
  2440. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2441. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2442. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2443. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2444. * if any (802.11 null frames have no payload). */
  2445. len = skb->len - hdr_len;
  2446. if (len) {
  2447. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2448. len, PCI_DMA_TODEVICE);
  2449. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2450. }
  2451. if (!len)
  2452. /* If there is no payload, then we use only one Tx buffer */
  2453. *control_flags = TFD_CTL_COUNT_SET(1);
  2454. else
  2455. /* Else use 2 buffers.
  2456. * Tell 3945 about any padding after MAC header */
  2457. *control_flags = TFD_CTL_COUNT_SET(2) |
  2458. TFD_CTL_PAD_SET(U32_PAD(len));
  2459. /* Total # bytes to be transmitted */
  2460. len = (u16)skb->len;
  2461. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2462. /* TODO need this for burst mode later on */
  2463. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2464. /* set is_hcca to 0; it probably will never be implemented */
  2465. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2466. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2467. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2468. if (!ieee80211_get_morefrag(hdr)) {
  2469. txq->need_update = 1;
  2470. if (qc) {
  2471. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2472. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2473. }
  2474. } else {
  2475. wait_write_ptr = 1;
  2476. txq->need_update = 0;
  2477. }
  2478. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2479. sizeof(out_cmd->cmd.tx));
  2480. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2481. ieee80211_get_hdrlen(fc));
  2482. /* Tell device the write index *just past* this latest filled TFD */
  2483. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  2484. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2485. spin_unlock_irqrestore(&priv->lock, flags);
  2486. if (rc)
  2487. return rc;
  2488. if ((iwl3945_queue_space(q) < q->high_mark)
  2489. && priv->mac80211_registered) {
  2490. if (wait_write_ptr) {
  2491. spin_lock_irqsave(&priv->lock, flags);
  2492. txq->need_update = 1;
  2493. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2494. spin_unlock_irqrestore(&priv->lock, flags);
  2495. }
  2496. ieee80211_stop_queue(priv->hw, ctl->queue);
  2497. }
  2498. return 0;
  2499. drop_unlock:
  2500. spin_unlock_irqrestore(&priv->lock, flags);
  2501. drop:
  2502. return -1;
  2503. }
  2504. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2505. {
  2506. const struct ieee80211_supported_band *sband = NULL;
  2507. struct ieee80211_rate *rate;
  2508. int i;
  2509. sband = iwl3945_get_band(priv, priv->band);
  2510. if (!sband) {
  2511. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2512. return;
  2513. }
  2514. priv->active_rate = 0;
  2515. priv->active_rate_basic = 0;
  2516. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2517. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2518. for (i = 0; i < sband->n_bitrates; i++) {
  2519. rate = &sband->bitrates[i];
  2520. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2521. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2522. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2523. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2524. priv->active_rate |= (1 << rate->hw_value);
  2525. }
  2526. }
  2527. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2528. priv->active_rate, priv->active_rate_basic);
  2529. /*
  2530. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2531. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2532. * OFDM
  2533. */
  2534. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2535. priv->staging_rxon.cck_basic_rates =
  2536. ((priv->active_rate_basic &
  2537. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2538. else
  2539. priv->staging_rxon.cck_basic_rates =
  2540. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2541. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2542. priv->staging_rxon.ofdm_basic_rates =
  2543. ((priv->active_rate_basic &
  2544. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2545. IWL_FIRST_OFDM_RATE) & 0xFF;
  2546. else
  2547. priv->staging_rxon.ofdm_basic_rates =
  2548. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2549. }
  2550. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2551. {
  2552. unsigned long flags;
  2553. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2554. return;
  2555. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2556. disable_radio ? "OFF" : "ON");
  2557. if (disable_radio) {
  2558. iwl3945_scan_cancel(priv);
  2559. /* FIXME: This is a workaround for AP */
  2560. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2561. spin_lock_irqsave(&priv->lock, flags);
  2562. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2563. CSR_UCODE_SW_BIT_RFKILL);
  2564. spin_unlock_irqrestore(&priv->lock, flags);
  2565. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2566. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2567. }
  2568. return;
  2569. }
  2570. spin_lock_irqsave(&priv->lock, flags);
  2571. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2572. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2573. spin_unlock_irqrestore(&priv->lock, flags);
  2574. /* wake up ucode */
  2575. msleep(10);
  2576. spin_lock_irqsave(&priv->lock, flags);
  2577. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2578. if (!iwl3945_grab_nic_access(priv))
  2579. iwl3945_release_nic_access(priv);
  2580. spin_unlock_irqrestore(&priv->lock, flags);
  2581. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2582. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2583. "disabled by HW switch\n");
  2584. return;
  2585. }
  2586. queue_work(priv->workqueue, &priv->restart);
  2587. return;
  2588. }
  2589. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2590. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2591. {
  2592. u16 fc =
  2593. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2594. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2595. return;
  2596. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2597. return;
  2598. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2599. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2600. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2601. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2602. RX_RES_STATUS_BAD_ICV_MIC)
  2603. stats->flag |= RX_FLAG_MMIC_ERROR;
  2604. case RX_RES_STATUS_SEC_TYPE_WEP:
  2605. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2606. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2607. RX_RES_STATUS_DECRYPT_OK) {
  2608. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2609. stats->flag |= RX_FLAG_DECRYPTED;
  2610. }
  2611. break;
  2612. default:
  2613. break;
  2614. }
  2615. }
  2616. #define IWL_PACKET_RETRY_TIME HZ
  2617. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2618. {
  2619. u16 sc = le16_to_cpu(header->seq_ctrl);
  2620. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2621. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2622. u16 *last_seq, *last_frag;
  2623. unsigned long *last_time;
  2624. switch (priv->iw_mode) {
  2625. case IEEE80211_IF_TYPE_IBSS:{
  2626. struct list_head *p;
  2627. struct iwl3945_ibss_seq *entry = NULL;
  2628. u8 *mac = header->addr2;
  2629. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2630. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2631. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2632. if (!compare_ether_addr(entry->mac, mac))
  2633. break;
  2634. }
  2635. if (p == &priv->ibss_mac_hash[index]) {
  2636. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2637. if (!entry) {
  2638. IWL_ERROR("Cannot malloc new mac entry\n");
  2639. return 0;
  2640. }
  2641. memcpy(entry->mac, mac, ETH_ALEN);
  2642. entry->seq_num = seq;
  2643. entry->frag_num = frag;
  2644. entry->packet_time = jiffies;
  2645. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2646. return 0;
  2647. }
  2648. last_seq = &entry->seq_num;
  2649. last_frag = &entry->frag_num;
  2650. last_time = &entry->packet_time;
  2651. break;
  2652. }
  2653. case IEEE80211_IF_TYPE_STA:
  2654. last_seq = &priv->last_seq_num;
  2655. last_frag = &priv->last_frag_num;
  2656. last_time = &priv->last_packet_time;
  2657. break;
  2658. default:
  2659. return 0;
  2660. }
  2661. if ((*last_seq == seq) &&
  2662. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2663. if (*last_frag == frag)
  2664. goto drop;
  2665. if (*last_frag + 1 != frag)
  2666. /* out-of-order fragment */
  2667. goto drop;
  2668. } else
  2669. *last_seq = seq;
  2670. *last_frag = frag;
  2671. *last_time = jiffies;
  2672. return 0;
  2673. drop:
  2674. return 1;
  2675. }
  2676. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2677. #include "iwl-spectrum.h"
  2678. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2679. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2680. #define TIME_UNIT 1024
  2681. /*
  2682. * extended beacon time format
  2683. * time in usec will be changed into a 32-bit value in 8:24 format
  2684. * the high 1 byte is the beacon counts
  2685. * the lower 3 bytes is the time in usec within one beacon interval
  2686. */
  2687. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2688. {
  2689. u32 quot;
  2690. u32 rem;
  2691. u32 interval = beacon_interval * 1024;
  2692. if (!interval || !usec)
  2693. return 0;
  2694. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2695. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2696. return (quot << 24) + rem;
  2697. }
  2698. /* base is usually what we get from ucode with each received frame,
  2699. * the same as HW timer counter counting down
  2700. */
  2701. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2702. {
  2703. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2704. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2705. u32 interval = beacon_interval * TIME_UNIT;
  2706. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2707. (addon & BEACON_TIME_MASK_HIGH);
  2708. if (base_low > addon_low)
  2709. res += base_low - addon_low;
  2710. else if (base_low < addon_low) {
  2711. res += interval + base_low - addon_low;
  2712. res += (1 << 24);
  2713. } else
  2714. res += (1 << 24);
  2715. return cpu_to_le32(res);
  2716. }
  2717. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2718. struct ieee80211_measurement_params *params,
  2719. u8 type)
  2720. {
  2721. struct iwl3945_spectrum_cmd spectrum;
  2722. struct iwl3945_rx_packet *res;
  2723. struct iwl3945_host_cmd cmd = {
  2724. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2725. .data = (void *)&spectrum,
  2726. .meta.flags = CMD_WANT_SKB,
  2727. };
  2728. u32 add_time = le64_to_cpu(params->start_time);
  2729. int rc;
  2730. int spectrum_resp_status;
  2731. int duration = le16_to_cpu(params->duration);
  2732. if (iwl3945_is_associated(priv))
  2733. add_time =
  2734. iwl3945_usecs_to_beacons(
  2735. le64_to_cpu(params->start_time) - priv->last_tsf,
  2736. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2737. memset(&spectrum, 0, sizeof(spectrum));
  2738. spectrum.channel_count = cpu_to_le16(1);
  2739. spectrum.flags =
  2740. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2741. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2742. cmd.len = sizeof(spectrum);
  2743. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2744. if (iwl3945_is_associated(priv))
  2745. spectrum.start_time =
  2746. iwl3945_add_beacon_time(priv->last_beacon_time,
  2747. add_time,
  2748. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2749. else
  2750. spectrum.start_time = 0;
  2751. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2752. spectrum.channels[0].channel = params->channel;
  2753. spectrum.channels[0].type = type;
  2754. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2755. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2756. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2757. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2758. if (rc)
  2759. return rc;
  2760. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2761. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2762. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2763. rc = -EIO;
  2764. }
  2765. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2766. switch (spectrum_resp_status) {
  2767. case 0: /* Command will be handled */
  2768. if (res->u.spectrum.id != 0xff) {
  2769. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2770. res->u.spectrum.id);
  2771. priv->measurement_status &= ~MEASUREMENT_READY;
  2772. }
  2773. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2774. rc = 0;
  2775. break;
  2776. case 1: /* Command will not be handled */
  2777. rc = -EAGAIN;
  2778. break;
  2779. }
  2780. dev_kfree_skb_any(cmd.meta.u.skb);
  2781. return rc;
  2782. }
  2783. #endif
  2784. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2785. struct iwl3945_tx_info *tx_sta)
  2786. {
  2787. tx_sta->status.ack_signal = 0;
  2788. tx_sta->status.excessive_retries = 0;
  2789. tx_sta->status.queue_length = 0;
  2790. tx_sta->status.queue_number = 0;
  2791. if (in_interrupt())
  2792. ieee80211_tx_status_irqsafe(priv->hw,
  2793. tx_sta->skb[0], &(tx_sta->status));
  2794. else
  2795. ieee80211_tx_status(priv->hw,
  2796. tx_sta->skb[0], &(tx_sta->status));
  2797. tx_sta->skb[0] = NULL;
  2798. }
  2799. /**
  2800. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  2801. *
  2802. * When FW advances 'R' index, all entries between old and new 'R' index
  2803. * need to be reclaimed. As result, some free space forms. If there is
  2804. * enough free space (> low mark), wake the stack that feeds us.
  2805. */
  2806. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2807. {
  2808. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2809. struct iwl3945_queue *q = &txq->q;
  2810. int nfreed = 0;
  2811. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2812. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2813. "is out of range [0-%d] %d %d.\n", txq_id,
  2814. index, q->n_bd, q->write_ptr, q->read_ptr);
  2815. return 0;
  2816. }
  2817. for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
  2818. q->read_ptr != index;
  2819. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2820. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2821. iwl3945_txstatus_to_ieee(priv,
  2822. &(txq->txb[txq->q.read_ptr]));
  2823. iwl3945_hw_txq_free_tfd(priv, txq);
  2824. } else if (nfreed > 1) {
  2825. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2826. q->write_ptr, q->read_ptr);
  2827. queue_work(priv->workqueue, &priv->restart);
  2828. }
  2829. nfreed++;
  2830. }
  2831. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2832. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2833. priv->mac80211_registered)
  2834. ieee80211_wake_queue(priv->hw, txq_id);
  2835. return nfreed;
  2836. }
  2837. static int iwl3945_is_tx_success(u32 status)
  2838. {
  2839. return (status & 0xFF) == 0x1;
  2840. }
  2841. /******************************************************************************
  2842. *
  2843. * Generic RX handler implementations
  2844. *
  2845. ******************************************************************************/
  2846. /**
  2847. * iwl3945_rx_reply_tx - Handle Tx response
  2848. */
  2849. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2850. struct iwl3945_rx_mem_buffer *rxb)
  2851. {
  2852. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2853. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2854. int txq_id = SEQ_TO_QUEUE(sequence);
  2855. int index = SEQ_TO_INDEX(sequence);
  2856. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2857. struct ieee80211_tx_status *tx_status;
  2858. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2859. u32 status = le32_to_cpu(tx_resp->status);
  2860. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  2861. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2862. "is out of range [0-%d] %d %d\n", txq_id,
  2863. index, txq->q.n_bd, txq->q.write_ptr,
  2864. txq->q.read_ptr);
  2865. return;
  2866. }
  2867. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2868. tx_status->retry_count = tx_resp->failure_frame;
  2869. tx_status->queue_number = status;
  2870. tx_status->queue_length = tx_resp->bt_kill_count;
  2871. tx_status->queue_length |= tx_resp->failure_rts;
  2872. tx_status->flags =
  2873. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2874. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2875. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2876. tx_resp->rate, tx_resp->failure_frame);
  2877. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2878. if (index != -1)
  2879. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2880. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2881. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2882. }
  2883. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2884. struct iwl3945_rx_mem_buffer *rxb)
  2885. {
  2886. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2887. struct iwl3945_alive_resp *palive;
  2888. struct delayed_work *pwork;
  2889. palive = &pkt->u.alive_frame;
  2890. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2891. "0x%01X 0x%01X\n",
  2892. palive->is_valid, palive->ver_type,
  2893. palive->ver_subtype);
  2894. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2895. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2896. memcpy(&priv->card_alive_init,
  2897. &pkt->u.alive_frame,
  2898. sizeof(struct iwl3945_init_alive_resp));
  2899. pwork = &priv->init_alive_start;
  2900. } else {
  2901. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2902. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2903. sizeof(struct iwl3945_alive_resp));
  2904. pwork = &priv->alive_start;
  2905. iwl3945_disable_events(priv);
  2906. }
  2907. /* We delay the ALIVE response by 5ms to
  2908. * give the HW RF Kill time to activate... */
  2909. if (palive->is_valid == UCODE_VALID_OK)
  2910. queue_delayed_work(priv->workqueue, pwork,
  2911. msecs_to_jiffies(5));
  2912. else
  2913. IWL_WARNING("uCode did not respond OK.\n");
  2914. }
  2915. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2916. struct iwl3945_rx_mem_buffer *rxb)
  2917. {
  2918. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2919. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2920. return;
  2921. }
  2922. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2923. struct iwl3945_rx_mem_buffer *rxb)
  2924. {
  2925. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2926. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2927. "seq 0x%04X ser 0x%08X\n",
  2928. le32_to_cpu(pkt->u.err_resp.error_type),
  2929. get_cmd_string(pkt->u.err_resp.cmd_id),
  2930. pkt->u.err_resp.cmd_id,
  2931. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2932. le32_to_cpu(pkt->u.err_resp.error_info));
  2933. }
  2934. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2935. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2936. {
  2937. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2938. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2939. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2940. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2941. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2942. rxon->channel = csa->channel;
  2943. priv->staging_rxon.channel = csa->channel;
  2944. }
  2945. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2946. struct iwl3945_rx_mem_buffer *rxb)
  2947. {
  2948. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2949. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2950. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2951. if (!report->state) {
  2952. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2953. "Spectrum Measure Notification: Start\n");
  2954. return;
  2955. }
  2956. memcpy(&priv->measure_report, report, sizeof(*report));
  2957. priv->measurement_status |= MEASUREMENT_READY;
  2958. #endif
  2959. }
  2960. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2961. struct iwl3945_rx_mem_buffer *rxb)
  2962. {
  2963. #ifdef CONFIG_IWL3945_DEBUG
  2964. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2965. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2966. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2967. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2968. #endif
  2969. }
  2970. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2971. struct iwl3945_rx_mem_buffer *rxb)
  2972. {
  2973. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2974. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2975. "notification for %s:\n",
  2976. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2977. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2978. }
  2979. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2980. {
  2981. struct iwl3945_priv *priv =
  2982. container_of(work, struct iwl3945_priv, beacon_update);
  2983. struct sk_buff *beacon;
  2984. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2985. beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
  2986. if (!beacon) {
  2987. IWL_ERROR("update beacon failed\n");
  2988. return;
  2989. }
  2990. mutex_lock(&priv->mutex);
  2991. /* new beacon skb is allocated every time; dispose previous.*/
  2992. if (priv->ibss_beacon)
  2993. dev_kfree_skb(priv->ibss_beacon);
  2994. priv->ibss_beacon = beacon;
  2995. mutex_unlock(&priv->mutex);
  2996. iwl3945_send_beacon_cmd(priv);
  2997. }
  2998. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2999. struct iwl3945_rx_mem_buffer *rxb)
  3000. {
  3001. #ifdef CONFIG_IWL3945_DEBUG
  3002. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3003. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  3004. u8 rate = beacon->beacon_notify_hdr.rate;
  3005. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  3006. "tsf %d %d rate %d\n",
  3007. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  3008. beacon->beacon_notify_hdr.failure_frame,
  3009. le32_to_cpu(beacon->ibss_mgr_status),
  3010. le32_to_cpu(beacon->high_tsf),
  3011. le32_to_cpu(beacon->low_tsf), rate);
  3012. #endif
  3013. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  3014. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  3015. queue_work(priv->workqueue, &priv->beacon_update);
  3016. }
  3017. /* Service response to REPLY_SCAN_CMD (0x80) */
  3018. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  3019. struct iwl3945_rx_mem_buffer *rxb)
  3020. {
  3021. #ifdef CONFIG_IWL3945_DEBUG
  3022. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3023. struct iwl3945_scanreq_notification *notif =
  3024. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  3025. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  3026. #endif
  3027. }
  3028. /* Service SCAN_START_NOTIFICATION (0x82) */
  3029. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  3030. struct iwl3945_rx_mem_buffer *rxb)
  3031. {
  3032. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3033. struct iwl3945_scanstart_notification *notif =
  3034. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  3035. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  3036. IWL_DEBUG_SCAN("Scan start: "
  3037. "%d [802.11%s] "
  3038. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  3039. notif->channel,
  3040. notif->band ? "bg" : "a",
  3041. notif->tsf_high,
  3042. notif->tsf_low, notif->status, notif->beacon_timer);
  3043. }
  3044. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  3045. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  3046. struct iwl3945_rx_mem_buffer *rxb)
  3047. {
  3048. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3049. struct iwl3945_scanresults_notification *notif =
  3050. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  3051. IWL_DEBUG_SCAN("Scan ch.res: "
  3052. "%d [802.11%s] "
  3053. "(TSF: 0x%08X:%08X) - %d "
  3054. "elapsed=%lu usec (%dms since last)\n",
  3055. notif->channel,
  3056. notif->band ? "bg" : "a",
  3057. le32_to_cpu(notif->tsf_high),
  3058. le32_to_cpu(notif->tsf_low),
  3059. le32_to_cpu(notif->statistics[0]),
  3060. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  3061. jiffies_to_msecs(elapsed_jiffies
  3062. (priv->last_scan_jiffies, jiffies)));
  3063. priv->last_scan_jiffies = jiffies;
  3064. priv->next_scan_jiffies = 0;
  3065. }
  3066. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  3067. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  3068. struct iwl3945_rx_mem_buffer *rxb)
  3069. {
  3070. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3071. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  3072. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  3073. scan_notif->scanned_channels,
  3074. scan_notif->tsf_low,
  3075. scan_notif->tsf_high, scan_notif->status);
  3076. /* The HW is no longer scanning */
  3077. clear_bit(STATUS_SCAN_HW, &priv->status);
  3078. /* The scan completion notification came in, so kill that timer... */
  3079. cancel_delayed_work(&priv->scan_check);
  3080. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  3081. (priv->scan_bands == 2) ? "2.4" : "5.2",
  3082. jiffies_to_msecs(elapsed_jiffies
  3083. (priv->scan_pass_start, jiffies)));
  3084. /* Remove this scanned band from the list
  3085. * of pending bands to scan */
  3086. priv->scan_bands--;
  3087. /* If a request to abort was given, or the scan did not succeed
  3088. * then we reset the scan state machine and terminate,
  3089. * re-queuing another scan if one has been requested */
  3090. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  3091. IWL_DEBUG_INFO("Aborted scan completed.\n");
  3092. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  3093. } else {
  3094. /* If there are more bands on this scan pass reschedule */
  3095. if (priv->scan_bands > 0)
  3096. goto reschedule;
  3097. }
  3098. priv->last_scan_jiffies = jiffies;
  3099. priv->next_scan_jiffies = 0;
  3100. IWL_DEBUG_INFO("Setting scan to off\n");
  3101. clear_bit(STATUS_SCANNING, &priv->status);
  3102. IWL_DEBUG_INFO("Scan took %dms\n",
  3103. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  3104. queue_work(priv->workqueue, &priv->scan_completed);
  3105. return;
  3106. reschedule:
  3107. priv->scan_pass_start = jiffies;
  3108. queue_work(priv->workqueue, &priv->request_scan);
  3109. }
  3110. /* Handle notification from uCode that card's power state is changing
  3111. * due to software, hardware, or critical temperature RFKILL */
  3112. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  3113. struct iwl3945_rx_mem_buffer *rxb)
  3114. {
  3115. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3116. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  3117. unsigned long status = priv->status;
  3118. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  3119. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  3120. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  3121. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3122. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3123. if (flags & HW_CARD_DISABLED)
  3124. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3125. else
  3126. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3127. if (flags & SW_CARD_DISABLED)
  3128. set_bit(STATUS_RF_KILL_SW, &priv->status);
  3129. else
  3130. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  3131. iwl3945_scan_cancel(priv);
  3132. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  3133. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  3134. (test_bit(STATUS_RF_KILL_SW, &status) !=
  3135. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  3136. queue_work(priv->workqueue, &priv->rf_kill);
  3137. else
  3138. wake_up_interruptible(&priv->wait_command_queue);
  3139. }
  3140. /**
  3141. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  3142. *
  3143. * Setup the RX handlers for each of the reply types sent from the uCode
  3144. * to the host.
  3145. *
  3146. * This function chains into the hardware specific files for them to setup
  3147. * any hardware specific handlers as well.
  3148. */
  3149. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  3150. {
  3151. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  3152. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  3153. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  3154. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  3155. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3156. iwl3945_rx_spectrum_measure_notif;
  3157. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  3158. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3159. iwl3945_rx_pm_debug_statistics_notif;
  3160. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  3161. /*
  3162. * The same handler is used for both the REPLY to a discrete
  3163. * statistics request from the host as well as for the periodic
  3164. * statistics notifications (after received beacons) from the uCode.
  3165. */
  3166. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3167. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3168. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3169. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3170. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3171. iwl3945_rx_scan_results_notif;
  3172. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3173. iwl3945_rx_scan_complete_notif;
  3174. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3175. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3176. /* Set up hardware specific Rx handlers */
  3177. iwl3945_hw_rx_handler_setup(priv);
  3178. }
  3179. /**
  3180. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3181. * @rxb: Rx buffer to reclaim
  3182. *
  3183. * If an Rx buffer has an async callback associated with it the callback
  3184. * will be executed. The attached skb (if present) will only be freed
  3185. * if the callback returns 1
  3186. */
  3187. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3188. struct iwl3945_rx_mem_buffer *rxb)
  3189. {
  3190. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3191. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3192. int txq_id = SEQ_TO_QUEUE(sequence);
  3193. int index = SEQ_TO_INDEX(sequence);
  3194. int huge = sequence & SEQ_HUGE_FRAME;
  3195. int cmd_index;
  3196. struct iwl3945_cmd *cmd;
  3197. /* If a Tx command is being handled and it isn't in the actual
  3198. * command queue then there a command routing bug has been introduced
  3199. * in the queue management code. */
  3200. if (txq_id != IWL_CMD_QUEUE_NUM)
  3201. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3202. txq_id, pkt->hdr.cmd);
  3203. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3204. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3205. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3206. /* Input error checking is done when commands are added to queue. */
  3207. if (cmd->meta.flags & CMD_WANT_SKB) {
  3208. cmd->meta.source->u.skb = rxb->skb;
  3209. rxb->skb = NULL;
  3210. } else if (cmd->meta.u.callback &&
  3211. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3212. rxb->skb = NULL;
  3213. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3214. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3215. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3216. wake_up_interruptible(&priv->wait_command_queue);
  3217. }
  3218. }
  3219. /************************** RX-FUNCTIONS ****************************/
  3220. /*
  3221. * Rx theory of operation
  3222. *
  3223. * The host allocates 32 DMA target addresses and passes the host address
  3224. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3225. * 0 to 31
  3226. *
  3227. * Rx Queue Indexes
  3228. * The host/firmware share two index registers for managing the Rx buffers.
  3229. *
  3230. * The READ index maps to the first position that the firmware may be writing
  3231. * to -- the driver can read up to (but not including) this position and get
  3232. * good data.
  3233. * The READ index is managed by the firmware once the card is enabled.
  3234. *
  3235. * The WRITE index maps to the last position the driver has read from -- the
  3236. * position preceding WRITE is the last slot the firmware can place a packet.
  3237. *
  3238. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3239. * WRITE = READ.
  3240. *
  3241. * During initialization, the host sets up the READ queue position to the first
  3242. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3243. *
  3244. * When the firmware places a packet in a buffer, it will advance the READ index
  3245. * and fire the RX interrupt. The driver can then query the READ index and
  3246. * process as many packets as possible, moving the WRITE index forward as it
  3247. * resets the Rx queue buffers with new memory.
  3248. *
  3249. * The management in the driver is as follows:
  3250. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3251. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3252. * to replenish the iwl->rxq->rx_free.
  3253. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3254. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3255. * 'processed' and 'read' driver indexes as well)
  3256. * + A received packet is processed and handed to the kernel network stack,
  3257. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3258. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3259. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3260. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3261. * were enough free buffers and RX_STALLED is set it is cleared.
  3262. *
  3263. *
  3264. * Driver sequence:
  3265. *
  3266. * iwl3945_rx_queue_alloc() Allocates rx_free
  3267. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3268. * iwl3945_rx_queue_restock
  3269. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3270. * queue, updates firmware pointers, and updates
  3271. * the WRITE index. If insufficient rx_free buffers
  3272. * are available, schedules iwl3945_rx_replenish
  3273. *
  3274. * -- enable interrupts --
  3275. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3276. * READ INDEX, detaching the SKB from the pool.
  3277. * Moves the packet buffer from queue to rx_used.
  3278. * Calls iwl3945_rx_queue_restock to refill any empty
  3279. * slots.
  3280. * ...
  3281. *
  3282. */
  3283. /**
  3284. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3285. */
  3286. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3287. {
  3288. int s = q->read - q->write;
  3289. if (s <= 0)
  3290. s += RX_QUEUE_SIZE;
  3291. /* keep some buffer to not confuse full and empty queue */
  3292. s -= 2;
  3293. if (s < 0)
  3294. s = 0;
  3295. return s;
  3296. }
  3297. /**
  3298. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3299. */
  3300. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3301. {
  3302. u32 reg = 0;
  3303. int rc = 0;
  3304. unsigned long flags;
  3305. spin_lock_irqsave(&q->lock, flags);
  3306. if (q->need_update == 0)
  3307. goto exit_unlock;
  3308. /* If power-saving is in use, make sure device is awake */
  3309. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3310. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3311. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3312. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3313. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3314. goto exit_unlock;
  3315. }
  3316. rc = iwl3945_grab_nic_access(priv);
  3317. if (rc)
  3318. goto exit_unlock;
  3319. /* Device expects a multiple of 8 */
  3320. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3321. q->write & ~0x7);
  3322. iwl3945_release_nic_access(priv);
  3323. /* Else device is assumed to be awake */
  3324. } else
  3325. /* Device expects a multiple of 8 */
  3326. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3327. q->need_update = 0;
  3328. exit_unlock:
  3329. spin_unlock_irqrestore(&q->lock, flags);
  3330. return rc;
  3331. }
  3332. /**
  3333. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3334. */
  3335. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3336. dma_addr_t dma_addr)
  3337. {
  3338. return cpu_to_le32((u32)dma_addr);
  3339. }
  3340. /**
  3341. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3342. *
  3343. * If there are slots in the RX queue that need to be restocked,
  3344. * and we have free pre-allocated buffers, fill the ranks as much
  3345. * as we can, pulling from rx_free.
  3346. *
  3347. * This moves the 'write' index forward to catch up with 'processed', and
  3348. * also updates the memory address in the firmware to reference the new
  3349. * target buffer.
  3350. */
  3351. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3352. {
  3353. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3354. struct list_head *element;
  3355. struct iwl3945_rx_mem_buffer *rxb;
  3356. unsigned long flags;
  3357. int write, rc;
  3358. spin_lock_irqsave(&rxq->lock, flags);
  3359. write = rxq->write & ~0x7;
  3360. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3361. /* Get next free Rx buffer, remove from free list */
  3362. element = rxq->rx_free.next;
  3363. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3364. list_del(element);
  3365. /* Point to Rx buffer via next RBD in circular buffer */
  3366. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3367. rxq->queue[rxq->write] = rxb;
  3368. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3369. rxq->free_count--;
  3370. }
  3371. spin_unlock_irqrestore(&rxq->lock, flags);
  3372. /* If the pre-allocated buffer pool is dropping low, schedule to
  3373. * refill it */
  3374. if (rxq->free_count <= RX_LOW_WATERMARK)
  3375. queue_work(priv->workqueue, &priv->rx_replenish);
  3376. /* If we've added more space for the firmware to place data, tell it.
  3377. * Increment device's write pointer in multiples of 8. */
  3378. if ((write != (rxq->write & ~0x7))
  3379. || (abs(rxq->write - rxq->read) > 7)) {
  3380. spin_lock_irqsave(&rxq->lock, flags);
  3381. rxq->need_update = 1;
  3382. spin_unlock_irqrestore(&rxq->lock, flags);
  3383. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3384. if (rc)
  3385. return rc;
  3386. }
  3387. return 0;
  3388. }
  3389. /**
  3390. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3391. *
  3392. * When moving to rx_free an SKB is allocated for the slot.
  3393. *
  3394. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3395. * This is called as a scheduled work item (except for during initialization)
  3396. */
  3397. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3398. {
  3399. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3400. struct list_head *element;
  3401. struct iwl3945_rx_mem_buffer *rxb;
  3402. unsigned long flags;
  3403. spin_lock_irqsave(&rxq->lock, flags);
  3404. while (!list_empty(&rxq->rx_used)) {
  3405. element = rxq->rx_used.next;
  3406. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3407. /* Alloc a new receive buffer */
  3408. rxb->skb =
  3409. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3410. if (!rxb->skb) {
  3411. if (net_ratelimit())
  3412. printk(KERN_CRIT DRV_NAME
  3413. ": Can not allocate SKB buffers\n");
  3414. /* We don't reschedule replenish work here -- we will
  3415. * call the restock method and if it still needs
  3416. * more buffers it will schedule replenish */
  3417. break;
  3418. }
  3419. /* If radiotap head is required, reserve some headroom here.
  3420. * The physical head count is a variable rx_stats->phy_count.
  3421. * We reserve 4 bytes here. Plus these extra bytes, the
  3422. * headroom of the physical head should be enough for the
  3423. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3424. */
  3425. skb_reserve(rxb->skb, 4);
  3426. priv->alloc_rxb_skb++;
  3427. list_del(element);
  3428. /* Get physical address of RB/SKB */
  3429. rxb->dma_addr =
  3430. pci_map_single(priv->pci_dev, rxb->skb->data,
  3431. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3432. list_add_tail(&rxb->list, &rxq->rx_free);
  3433. rxq->free_count++;
  3434. }
  3435. spin_unlock_irqrestore(&rxq->lock, flags);
  3436. }
  3437. /*
  3438. * this should be called while priv->lock is locked
  3439. */
  3440. static void __iwl3945_rx_replenish(void *data)
  3441. {
  3442. struct iwl3945_priv *priv = data;
  3443. iwl3945_rx_allocate(priv);
  3444. iwl3945_rx_queue_restock(priv);
  3445. }
  3446. void iwl3945_rx_replenish(void *data)
  3447. {
  3448. struct iwl3945_priv *priv = data;
  3449. unsigned long flags;
  3450. iwl3945_rx_allocate(priv);
  3451. spin_lock_irqsave(&priv->lock, flags);
  3452. iwl3945_rx_queue_restock(priv);
  3453. spin_unlock_irqrestore(&priv->lock, flags);
  3454. }
  3455. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3456. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3457. * This free routine walks the list of POOL entries and if SKB is set to
  3458. * non NULL it is unmapped and freed
  3459. */
  3460. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3461. {
  3462. int i;
  3463. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3464. if (rxq->pool[i].skb != NULL) {
  3465. pci_unmap_single(priv->pci_dev,
  3466. rxq->pool[i].dma_addr,
  3467. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3468. dev_kfree_skb(rxq->pool[i].skb);
  3469. }
  3470. }
  3471. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3472. rxq->dma_addr);
  3473. rxq->bd = NULL;
  3474. }
  3475. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3476. {
  3477. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3478. struct pci_dev *dev = priv->pci_dev;
  3479. int i;
  3480. spin_lock_init(&rxq->lock);
  3481. INIT_LIST_HEAD(&rxq->rx_free);
  3482. INIT_LIST_HEAD(&rxq->rx_used);
  3483. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3484. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3485. if (!rxq->bd)
  3486. return -ENOMEM;
  3487. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3488. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3489. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3490. /* Set us so that we have processed and used all buffers, but have
  3491. * not restocked the Rx queue with fresh buffers */
  3492. rxq->read = rxq->write = 0;
  3493. rxq->free_count = 0;
  3494. rxq->need_update = 0;
  3495. return 0;
  3496. }
  3497. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3498. {
  3499. unsigned long flags;
  3500. int i;
  3501. spin_lock_irqsave(&rxq->lock, flags);
  3502. INIT_LIST_HEAD(&rxq->rx_free);
  3503. INIT_LIST_HEAD(&rxq->rx_used);
  3504. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3505. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3506. /* In the reset function, these buffers may have been allocated
  3507. * to an SKB, so we need to unmap and free potential storage */
  3508. if (rxq->pool[i].skb != NULL) {
  3509. pci_unmap_single(priv->pci_dev,
  3510. rxq->pool[i].dma_addr,
  3511. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3512. priv->alloc_rxb_skb--;
  3513. dev_kfree_skb(rxq->pool[i].skb);
  3514. rxq->pool[i].skb = NULL;
  3515. }
  3516. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3517. }
  3518. /* Set us so that we have processed and used all buffers, but have
  3519. * not restocked the Rx queue with fresh buffers */
  3520. rxq->read = rxq->write = 0;
  3521. rxq->free_count = 0;
  3522. spin_unlock_irqrestore(&rxq->lock, flags);
  3523. }
  3524. /* Convert linear signal-to-noise ratio into dB */
  3525. static u8 ratio2dB[100] = {
  3526. /* 0 1 2 3 4 5 6 7 8 9 */
  3527. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3528. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3529. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3530. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3531. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3532. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3533. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3534. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3535. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3536. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3537. };
  3538. /* Calculates a relative dB value from a ratio of linear
  3539. * (i.e. not dB) signal levels.
  3540. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3541. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3542. {
  3543. /* 1000:1 or higher just report as 60 dB */
  3544. if (sig_ratio >= 1000)
  3545. return 60;
  3546. /* 100:1 or higher, divide by 10 and use table,
  3547. * add 20 dB to make up for divide by 10 */
  3548. if (sig_ratio >= 100)
  3549. return (20 + (int)ratio2dB[sig_ratio/10]);
  3550. /* We shouldn't see this */
  3551. if (sig_ratio < 1)
  3552. return 0;
  3553. /* Use table for ratios 1:1 - 99:1 */
  3554. return (int)ratio2dB[sig_ratio];
  3555. }
  3556. #define PERFECT_RSSI (-20) /* dBm */
  3557. #define WORST_RSSI (-95) /* dBm */
  3558. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3559. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3560. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3561. * about formulas used below. */
  3562. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3563. {
  3564. int sig_qual;
  3565. int degradation = PERFECT_RSSI - rssi_dbm;
  3566. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3567. * as indicator; formula is (signal dbm - noise dbm).
  3568. * SNR at or above 40 is a great signal (100%).
  3569. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3570. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3571. if (noise_dbm) {
  3572. if (rssi_dbm - noise_dbm >= 40)
  3573. return 100;
  3574. else if (rssi_dbm < noise_dbm)
  3575. return 0;
  3576. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3577. /* Else use just the signal level.
  3578. * This formula is a least squares fit of data points collected and
  3579. * compared with a reference system that had a percentage (%) display
  3580. * for signal quality. */
  3581. } else
  3582. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3583. (15 * RSSI_RANGE + 62 * degradation)) /
  3584. (RSSI_RANGE * RSSI_RANGE);
  3585. if (sig_qual > 100)
  3586. sig_qual = 100;
  3587. else if (sig_qual < 1)
  3588. sig_qual = 0;
  3589. return sig_qual;
  3590. }
  3591. /**
  3592. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3593. *
  3594. * Uses the priv->rx_handlers callback function array to invoke
  3595. * the appropriate handlers, including command responses,
  3596. * frame-received notifications, and other notifications.
  3597. */
  3598. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3599. {
  3600. struct iwl3945_rx_mem_buffer *rxb;
  3601. struct iwl3945_rx_packet *pkt;
  3602. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3603. u32 r, i;
  3604. int reclaim;
  3605. unsigned long flags;
  3606. u8 fill_rx = 0;
  3607. u32 count = 8;
  3608. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3609. * buffer that the driver may process (last buffer filled by ucode). */
  3610. r = iwl3945_hw_get_rx_read(priv);
  3611. i = rxq->read;
  3612. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3613. fill_rx = 1;
  3614. /* Rx interrupt, but nothing sent from uCode */
  3615. if (i == r)
  3616. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3617. while (i != r) {
  3618. rxb = rxq->queue[i];
  3619. /* If an RXB doesn't have a Rx queue slot associated with it,
  3620. * then a bug has been introduced in the queue refilling
  3621. * routines -- catch it here */
  3622. BUG_ON(rxb == NULL);
  3623. rxq->queue[i] = NULL;
  3624. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3625. IWL_RX_BUF_SIZE,
  3626. PCI_DMA_FROMDEVICE);
  3627. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3628. /* Reclaim a command buffer only if this packet is a response
  3629. * to a (driver-originated) command.
  3630. * If the packet (e.g. Rx frame) originated from uCode,
  3631. * there is no command buffer to reclaim.
  3632. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3633. * but apparently a few don't get set; catch them here. */
  3634. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3635. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3636. (pkt->hdr.cmd != REPLY_TX);
  3637. /* Based on type of command response or notification,
  3638. * handle those that need handling via function in
  3639. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3640. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3641. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3642. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3643. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3644. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3645. } else {
  3646. /* No handling needed */
  3647. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3648. "r %d i %d No handler needed for %s, 0x%02x\n",
  3649. r, i, get_cmd_string(pkt->hdr.cmd),
  3650. pkt->hdr.cmd);
  3651. }
  3652. if (reclaim) {
  3653. /* Invoke any callbacks, transfer the skb to caller, and
  3654. * fire off the (possibly) blocking iwl3945_send_cmd()
  3655. * as we reclaim the driver command queue */
  3656. if (rxb && rxb->skb)
  3657. iwl3945_tx_cmd_complete(priv, rxb);
  3658. else
  3659. IWL_WARNING("Claim null rxb?\n");
  3660. }
  3661. /* For now we just don't re-use anything. We can tweak this
  3662. * later to try and re-use notification packets and SKBs that
  3663. * fail to Rx correctly */
  3664. if (rxb->skb != NULL) {
  3665. priv->alloc_rxb_skb--;
  3666. dev_kfree_skb_any(rxb->skb);
  3667. rxb->skb = NULL;
  3668. }
  3669. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3670. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3671. spin_lock_irqsave(&rxq->lock, flags);
  3672. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3673. spin_unlock_irqrestore(&rxq->lock, flags);
  3674. i = (i + 1) & RX_QUEUE_MASK;
  3675. /* If there are a lot of unused frames,
  3676. * restock the Rx queue so ucode won't assert. */
  3677. if (fill_rx) {
  3678. count++;
  3679. if (count >= 8) {
  3680. priv->rxq.read = i;
  3681. __iwl3945_rx_replenish(priv);
  3682. count = 0;
  3683. }
  3684. }
  3685. }
  3686. /* Backtrack one entry */
  3687. priv->rxq.read = i;
  3688. iwl3945_rx_queue_restock(priv);
  3689. }
  3690. /**
  3691. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3692. */
  3693. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3694. struct iwl3945_tx_queue *txq)
  3695. {
  3696. u32 reg = 0;
  3697. int rc = 0;
  3698. int txq_id = txq->q.id;
  3699. if (txq->need_update == 0)
  3700. return rc;
  3701. /* if we're trying to save power */
  3702. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3703. /* wake up nic if it's powered down ...
  3704. * uCode will wake up, and interrupt us again, so next
  3705. * time we'll skip this part. */
  3706. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3707. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3708. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3709. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3710. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3711. return rc;
  3712. }
  3713. /* restore this queue's parameters in nic hardware. */
  3714. rc = iwl3945_grab_nic_access(priv);
  3715. if (rc)
  3716. return rc;
  3717. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3718. txq->q.write_ptr | (txq_id << 8));
  3719. iwl3945_release_nic_access(priv);
  3720. /* else not in power-save mode, uCode will never sleep when we're
  3721. * trying to tx (during RFKILL, we're not trying to tx). */
  3722. } else
  3723. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3724. txq->q.write_ptr | (txq_id << 8));
  3725. txq->need_update = 0;
  3726. return rc;
  3727. }
  3728. #ifdef CONFIG_IWL3945_DEBUG
  3729. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3730. {
  3731. DECLARE_MAC_BUF(mac);
  3732. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3733. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3734. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3735. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3736. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3737. le32_to_cpu(rxon->filter_flags));
  3738. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3739. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3740. rxon->ofdm_basic_rates);
  3741. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3742. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3743. print_mac(mac, rxon->node_addr));
  3744. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3745. print_mac(mac, rxon->bssid_addr));
  3746. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3747. }
  3748. #endif
  3749. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3750. {
  3751. IWL_DEBUG_ISR("Enabling interrupts\n");
  3752. set_bit(STATUS_INT_ENABLED, &priv->status);
  3753. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3754. }
  3755. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3756. {
  3757. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3758. /* disable interrupts from uCode/NIC to host */
  3759. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3760. /* acknowledge/clear/reset any interrupts still pending
  3761. * from uCode or flow handler (Rx/Tx DMA) */
  3762. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3763. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3764. IWL_DEBUG_ISR("Disabled interrupts\n");
  3765. }
  3766. static const char *desc_lookup(int i)
  3767. {
  3768. switch (i) {
  3769. case 1:
  3770. return "FAIL";
  3771. case 2:
  3772. return "BAD_PARAM";
  3773. case 3:
  3774. return "BAD_CHECKSUM";
  3775. case 4:
  3776. return "NMI_INTERRUPT";
  3777. case 5:
  3778. return "SYSASSERT";
  3779. case 6:
  3780. return "FATAL_ERROR";
  3781. }
  3782. return "UNKNOWN";
  3783. }
  3784. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3785. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3786. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3787. {
  3788. u32 i;
  3789. u32 desc, time, count, base, data1;
  3790. u32 blink1, blink2, ilink1, ilink2;
  3791. int rc;
  3792. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3793. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3794. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3795. return;
  3796. }
  3797. rc = iwl3945_grab_nic_access(priv);
  3798. if (rc) {
  3799. IWL_WARNING("Can not read from adapter at this time.\n");
  3800. return;
  3801. }
  3802. count = iwl3945_read_targ_mem(priv, base);
  3803. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3804. IWL_ERROR("Start IWL Error Log Dump:\n");
  3805. IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
  3806. priv->status, priv->config, count);
  3807. }
  3808. IWL_ERROR("Desc Time asrtPC blink2 "
  3809. "ilink1 nmiPC Line\n");
  3810. for (i = ERROR_START_OFFSET;
  3811. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3812. i += ERROR_ELEM_SIZE) {
  3813. desc = iwl3945_read_targ_mem(priv, base + i);
  3814. time =
  3815. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3816. blink1 =
  3817. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3818. blink2 =
  3819. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3820. ilink1 =
  3821. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3822. ilink2 =
  3823. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3824. data1 =
  3825. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3826. IWL_ERROR
  3827. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3828. desc_lookup(desc), desc, time, blink1, blink2,
  3829. ilink1, ilink2, data1);
  3830. }
  3831. iwl3945_release_nic_access(priv);
  3832. }
  3833. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3834. /**
  3835. * iwl3945_print_event_log - Dump error event log to syslog
  3836. *
  3837. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3838. */
  3839. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3840. u32 num_events, u32 mode)
  3841. {
  3842. u32 i;
  3843. u32 base; /* SRAM byte address of event log header */
  3844. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3845. u32 ptr; /* SRAM byte address of log data */
  3846. u32 ev, time, data; /* event log data */
  3847. if (num_events == 0)
  3848. return;
  3849. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3850. if (mode == 0)
  3851. event_size = 2 * sizeof(u32);
  3852. else
  3853. event_size = 3 * sizeof(u32);
  3854. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3855. /* "time" is actually "data" for mode 0 (no timestamp).
  3856. * place event id # at far right for easier visual parsing. */
  3857. for (i = 0; i < num_events; i++) {
  3858. ev = iwl3945_read_targ_mem(priv, ptr);
  3859. ptr += sizeof(u32);
  3860. time = iwl3945_read_targ_mem(priv, ptr);
  3861. ptr += sizeof(u32);
  3862. if (mode == 0)
  3863. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3864. else {
  3865. data = iwl3945_read_targ_mem(priv, ptr);
  3866. ptr += sizeof(u32);
  3867. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3868. }
  3869. }
  3870. }
  3871. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3872. {
  3873. int rc;
  3874. u32 base; /* SRAM byte address of event log header */
  3875. u32 capacity; /* event log capacity in # entries */
  3876. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3877. u32 num_wraps; /* # times uCode wrapped to top of log */
  3878. u32 next_entry; /* index of next entry to be written by uCode */
  3879. u32 size; /* # entries that we'll print */
  3880. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3881. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3882. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3883. return;
  3884. }
  3885. rc = iwl3945_grab_nic_access(priv);
  3886. if (rc) {
  3887. IWL_WARNING("Can not read from adapter at this time.\n");
  3888. return;
  3889. }
  3890. /* event log header */
  3891. capacity = iwl3945_read_targ_mem(priv, base);
  3892. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3893. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3894. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3895. size = num_wraps ? capacity : next_entry;
  3896. /* bail out if nothing in log */
  3897. if (size == 0) {
  3898. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3899. iwl3945_release_nic_access(priv);
  3900. return;
  3901. }
  3902. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3903. size, num_wraps);
  3904. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3905. * i.e the next one that uCode would fill. */
  3906. if (num_wraps)
  3907. iwl3945_print_event_log(priv, next_entry,
  3908. capacity - next_entry, mode);
  3909. /* (then/else) start at top of log */
  3910. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3911. iwl3945_release_nic_access(priv);
  3912. }
  3913. /**
  3914. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3915. */
  3916. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3917. {
  3918. /* Set the FW error flag -- cleared on iwl3945_down */
  3919. set_bit(STATUS_FW_ERROR, &priv->status);
  3920. /* Cancel currently queued command. */
  3921. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3922. #ifdef CONFIG_IWL3945_DEBUG
  3923. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3924. iwl3945_dump_nic_error_log(priv);
  3925. iwl3945_dump_nic_event_log(priv);
  3926. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3927. }
  3928. #endif
  3929. wake_up_interruptible(&priv->wait_command_queue);
  3930. /* Keep the restart process from trying to send host
  3931. * commands by clearing the INIT status bit */
  3932. clear_bit(STATUS_READY, &priv->status);
  3933. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3934. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3935. "Restarting adapter due to uCode error.\n");
  3936. if (iwl3945_is_associated(priv)) {
  3937. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3938. sizeof(priv->recovery_rxon));
  3939. priv->error_recovering = 1;
  3940. }
  3941. queue_work(priv->workqueue, &priv->restart);
  3942. }
  3943. }
  3944. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3945. {
  3946. unsigned long flags;
  3947. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3948. sizeof(priv->staging_rxon));
  3949. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3950. iwl3945_commit_rxon(priv);
  3951. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3952. spin_lock_irqsave(&priv->lock, flags);
  3953. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3954. priv->error_recovering = 0;
  3955. spin_unlock_irqrestore(&priv->lock, flags);
  3956. }
  3957. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3958. {
  3959. u32 inta, handled = 0;
  3960. u32 inta_fh;
  3961. unsigned long flags;
  3962. #ifdef CONFIG_IWL3945_DEBUG
  3963. u32 inta_mask;
  3964. #endif
  3965. spin_lock_irqsave(&priv->lock, flags);
  3966. /* Ack/clear/reset pending uCode interrupts.
  3967. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3968. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3969. inta = iwl3945_read32(priv, CSR_INT);
  3970. iwl3945_write32(priv, CSR_INT, inta);
  3971. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3972. * Any new interrupts that happen after this, either while we're
  3973. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3974. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3975. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3976. #ifdef CONFIG_IWL3945_DEBUG
  3977. if (iwl3945_debug_level & IWL_DL_ISR) {
  3978. /* just for debug */
  3979. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3980. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3981. inta, inta_mask, inta_fh);
  3982. }
  3983. #endif
  3984. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3985. * atomic, make sure that inta covers all the interrupts that
  3986. * we've discovered, even if FH interrupt came in just after
  3987. * reading CSR_INT. */
  3988. if (inta_fh & CSR_FH_INT_RX_MASK)
  3989. inta |= CSR_INT_BIT_FH_RX;
  3990. if (inta_fh & CSR_FH_INT_TX_MASK)
  3991. inta |= CSR_INT_BIT_FH_TX;
  3992. /* Now service all interrupt bits discovered above. */
  3993. if (inta & CSR_INT_BIT_HW_ERR) {
  3994. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3995. /* Tell the device to stop sending interrupts */
  3996. iwl3945_disable_interrupts(priv);
  3997. iwl3945_irq_handle_error(priv);
  3998. handled |= CSR_INT_BIT_HW_ERR;
  3999. spin_unlock_irqrestore(&priv->lock, flags);
  4000. return;
  4001. }
  4002. #ifdef CONFIG_IWL3945_DEBUG
  4003. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4004. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  4005. if (inta & CSR_INT_BIT_SCD)
  4006. IWL_DEBUG_ISR("Scheduler finished to transmit "
  4007. "the frame/frames.\n");
  4008. /* Alive notification via Rx interrupt will do the real work */
  4009. if (inta & CSR_INT_BIT_ALIVE)
  4010. IWL_DEBUG_ISR("Alive interrupt\n");
  4011. }
  4012. #endif
  4013. /* Safely ignore these bits for debug checks below */
  4014. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  4015. /* HW RF KILL switch toggled (4965 only) */
  4016. if (inta & CSR_INT_BIT_RF_KILL) {
  4017. int hw_rf_kill = 0;
  4018. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  4019. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4020. hw_rf_kill = 1;
  4021. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  4022. "RF_KILL bit toggled to %s.\n",
  4023. hw_rf_kill ? "disable radio":"enable radio");
  4024. /* Queue restart only if RF_KILL switch was set to "kill"
  4025. * when we loaded driver, and is now set to "enable".
  4026. * After we're Alive, RF_KILL gets handled by
  4027. * iwl_rx_card_state_notif() */
  4028. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  4029. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4030. queue_work(priv->workqueue, &priv->restart);
  4031. }
  4032. handled |= CSR_INT_BIT_RF_KILL;
  4033. }
  4034. /* Chip got too hot and stopped itself (4965 only) */
  4035. if (inta & CSR_INT_BIT_CT_KILL) {
  4036. IWL_ERROR("Microcode CT kill error detected.\n");
  4037. handled |= CSR_INT_BIT_CT_KILL;
  4038. }
  4039. /* Error detected by uCode */
  4040. if (inta & CSR_INT_BIT_SW_ERR) {
  4041. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  4042. inta);
  4043. iwl3945_irq_handle_error(priv);
  4044. handled |= CSR_INT_BIT_SW_ERR;
  4045. }
  4046. /* uCode wakes up after power-down sleep */
  4047. if (inta & CSR_INT_BIT_WAKEUP) {
  4048. IWL_DEBUG_ISR("Wakeup interrupt\n");
  4049. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  4050. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  4051. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  4052. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  4053. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  4054. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  4055. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  4056. handled |= CSR_INT_BIT_WAKEUP;
  4057. }
  4058. /* All uCode command responses, including Tx command responses,
  4059. * Rx "responses" (frame-received notification), and other
  4060. * notifications from uCode come through here*/
  4061. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  4062. iwl3945_rx_handle(priv);
  4063. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  4064. }
  4065. if (inta & CSR_INT_BIT_FH_TX) {
  4066. IWL_DEBUG_ISR("Tx interrupt\n");
  4067. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  4068. if (!iwl3945_grab_nic_access(priv)) {
  4069. iwl3945_write_direct32(priv,
  4070. FH_TCSR_CREDIT
  4071. (ALM_FH_SRVC_CHNL), 0x0);
  4072. iwl3945_release_nic_access(priv);
  4073. }
  4074. handled |= CSR_INT_BIT_FH_TX;
  4075. }
  4076. if (inta & ~handled)
  4077. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  4078. if (inta & ~CSR_INI_SET_MASK) {
  4079. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  4080. inta & ~CSR_INI_SET_MASK);
  4081. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  4082. }
  4083. /* Re-enable all interrupts */
  4084. iwl3945_enable_interrupts(priv);
  4085. #ifdef CONFIG_IWL3945_DEBUG
  4086. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4087. inta = iwl3945_read32(priv, CSR_INT);
  4088. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  4089. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4090. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  4091. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  4092. }
  4093. #endif
  4094. spin_unlock_irqrestore(&priv->lock, flags);
  4095. }
  4096. static irqreturn_t iwl3945_isr(int irq, void *data)
  4097. {
  4098. struct iwl3945_priv *priv = data;
  4099. u32 inta, inta_mask;
  4100. u32 inta_fh;
  4101. if (!priv)
  4102. return IRQ_NONE;
  4103. spin_lock(&priv->lock);
  4104. /* Disable (but don't clear!) interrupts here to avoid
  4105. * back-to-back ISRs and sporadic interrupts from our NIC.
  4106. * If we have something to service, the tasklet will re-enable ints.
  4107. * If we *don't* have something, we'll re-enable before leaving here. */
  4108. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  4109. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  4110. /* Discover which interrupts are active/pending */
  4111. inta = iwl3945_read32(priv, CSR_INT);
  4112. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4113. /* Ignore interrupt if there's nothing in NIC to service.
  4114. * This may be due to IRQ shared with another device,
  4115. * or due to sporadic interrupts thrown from our NIC. */
  4116. if (!inta && !inta_fh) {
  4117. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4118. goto none;
  4119. }
  4120. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  4121. /* Hardware disappeared */
  4122. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  4123. goto unplugged;
  4124. }
  4125. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4126. inta, inta_mask, inta_fh);
  4127. inta &= ~CSR_INT_BIT_SCD;
  4128. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  4129. if (likely(inta || inta_fh))
  4130. tasklet_schedule(&priv->irq_tasklet);
  4131. unplugged:
  4132. spin_unlock(&priv->lock);
  4133. return IRQ_HANDLED;
  4134. none:
  4135. /* re-enable interrupts here since we don't have anything to service. */
  4136. iwl3945_enable_interrupts(priv);
  4137. spin_unlock(&priv->lock);
  4138. return IRQ_NONE;
  4139. }
  4140. /************************** EEPROM BANDS ****************************
  4141. *
  4142. * The iwl3945_eeprom_band definitions below provide the mapping from the
  4143. * EEPROM contents to the specific channel number supported for each
  4144. * band.
  4145. *
  4146. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  4147. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4148. * The specific geography and calibration information for that channel
  4149. * is contained in the eeprom map itself.
  4150. *
  4151. * During init, we copy the eeprom information and channel map
  4152. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4153. *
  4154. * channel_map_24/52 provides the index in the channel_info array for a
  4155. * given channel. We have to have two separate maps as there is channel
  4156. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4157. * band_2
  4158. *
  4159. * A value of 0xff stored in the channel_map indicates that the channel
  4160. * is not supported by the hardware at all.
  4161. *
  4162. * A value of 0xfe in the channel_map indicates that the channel is not
  4163. * valid for Tx with the current hardware. This means that
  4164. * while the system can tune and receive on a given channel, it may not
  4165. * be able to associate or transmit any frames on that
  4166. * channel. There is no corresponding channel information for that
  4167. * entry.
  4168. *
  4169. *********************************************************************/
  4170. /* 2.4 GHz */
  4171. static const u8 iwl3945_eeprom_band_1[14] = {
  4172. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4173. };
  4174. /* 5.2 GHz bands */
  4175. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  4176. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4177. };
  4178. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  4179. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4180. };
  4181. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4182. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4183. };
  4184. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4185. 145, 149, 153, 157, 161, 165
  4186. };
  4187. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4188. int *eeprom_ch_count,
  4189. const struct iwl3945_eeprom_channel
  4190. **eeprom_ch_info,
  4191. const u8 **eeprom_ch_index)
  4192. {
  4193. switch (band) {
  4194. case 1: /* 2.4GHz band */
  4195. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4196. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4197. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4198. break;
  4199. case 2: /* 4.9GHz band */
  4200. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4201. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4202. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4203. break;
  4204. case 3: /* 5.2GHz band */
  4205. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4206. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4207. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4208. break;
  4209. case 4: /* 5.5GHz band */
  4210. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4211. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4212. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4213. break;
  4214. case 5: /* 5.7GHz band */
  4215. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4216. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4217. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4218. break;
  4219. default:
  4220. BUG();
  4221. return;
  4222. }
  4223. }
  4224. /**
  4225. * iwl3945_get_channel_info - Find driver's private channel info
  4226. *
  4227. * Based on band and channel number.
  4228. */
  4229. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4230. enum ieee80211_band band, u16 channel)
  4231. {
  4232. int i;
  4233. switch (band) {
  4234. case IEEE80211_BAND_5GHZ:
  4235. for (i = 14; i < priv->channel_count; i++) {
  4236. if (priv->channel_info[i].channel == channel)
  4237. return &priv->channel_info[i];
  4238. }
  4239. break;
  4240. case IEEE80211_BAND_2GHZ:
  4241. if (channel >= 1 && channel <= 14)
  4242. return &priv->channel_info[channel - 1];
  4243. break;
  4244. case IEEE80211_NUM_BANDS:
  4245. WARN_ON(1);
  4246. }
  4247. return NULL;
  4248. }
  4249. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4250. ? # x " " : "")
  4251. /**
  4252. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4253. */
  4254. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4255. {
  4256. int eeprom_ch_count = 0;
  4257. const u8 *eeprom_ch_index = NULL;
  4258. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4259. int band, ch;
  4260. struct iwl3945_channel_info *ch_info;
  4261. if (priv->channel_count) {
  4262. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4263. return 0;
  4264. }
  4265. if (priv->eeprom.version < 0x2f) {
  4266. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4267. priv->eeprom.version);
  4268. return -EINVAL;
  4269. }
  4270. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4271. priv->channel_count =
  4272. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4273. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4274. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4275. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4276. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4277. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4278. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4279. priv->channel_count, GFP_KERNEL);
  4280. if (!priv->channel_info) {
  4281. IWL_ERROR("Could not allocate channel_info\n");
  4282. priv->channel_count = 0;
  4283. return -ENOMEM;
  4284. }
  4285. ch_info = priv->channel_info;
  4286. /* Loop through the 5 EEPROM bands adding them in order to the
  4287. * channel map we maintain (that contains additional information than
  4288. * what just in the EEPROM) */
  4289. for (band = 1; band <= 5; band++) {
  4290. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4291. &eeprom_ch_info, &eeprom_ch_index);
  4292. /* Loop through each band adding each of the channels */
  4293. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4294. ch_info->channel = eeprom_ch_index[ch];
  4295. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4296. IEEE80211_BAND_5GHZ;
  4297. /* permanently store EEPROM's channel regulatory flags
  4298. * and max power in channel info database. */
  4299. ch_info->eeprom = eeprom_ch_info[ch];
  4300. /* Copy the run-time flags so they are there even on
  4301. * invalid channels */
  4302. ch_info->flags = eeprom_ch_info[ch].flags;
  4303. if (!(is_channel_valid(ch_info))) {
  4304. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4305. "No traffic\n",
  4306. ch_info->channel,
  4307. ch_info->flags,
  4308. is_channel_a_band(ch_info) ?
  4309. "5.2" : "2.4");
  4310. ch_info++;
  4311. continue;
  4312. }
  4313. /* Initialize regulatory-based run-time data */
  4314. ch_info->max_power_avg = ch_info->curr_txpow =
  4315. eeprom_ch_info[ch].max_power_avg;
  4316. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4317. ch_info->min_power = 0;
  4318. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4319. " %ddBm): Ad-Hoc %ssupported\n",
  4320. ch_info->channel,
  4321. is_channel_a_band(ch_info) ?
  4322. "5.2" : "2.4",
  4323. CHECK_AND_PRINT(IBSS),
  4324. CHECK_AND_PRINT(ACTIVE),
  4325. CHECK_AND_PRINT(RADAR),
  4326. CHECK_AND_PRINT(WIDE),
  4327. CHECK_AND_PRINT(NARROW),
  4328. CHECK_AND_PRINT(DFS),
  4329. eeprom_ch_info[ch].flags,
  4330. eeprom_ch_info[ch].max_power_avg,
  4331. ((eeprom_ch_info[ch].
  4332. flags & EEPROM_CHANNEL_IBSS)
  4333. && !(eeprom_ch_info[ch].
  4334. flags & EEPROM_CHANNEL_RADAR))
  4335. ? "" : "not ");
  4336. /* Set the user_txpower_limit to the highest power
  4337. * supported by any channel */
  4338. if (eeprom_ch_info[ch].max_power_avg >
  4339. priv->user_txpower_limit)
  4340. priv->user_txpower_limit =
  4341. eeprom_ch_info[ch].max_power_avg;
  4342. ch_info++;
  4343. }
  4344. }
  4345. /* Set up txpower settings in driver for all channels */
  4346. if (iwl3945_txpower_set_from_eeprom(priv))
  4347. return -EIO;
  4348. return 0;
  4349. }
  4350. /*
  4351. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4352. */
  4353. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4354. {
  4355. kfree(priv->channel_info);
  4356. priv->channel_count = 0;
  4357. }
  4358. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4359. * sending probe req. This should be set long enough to hear probe responses
  4360. * from more than one AP. */
  4361. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4362. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4363. /* For faster active scanning, scan will move to the next channel if fewer than
  4364. * PLCP_QUIET_THRESH packets are heard on this channel within
  4365. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4366. * time if it's a quiet channel (nothing responded to our probe, and there's
  4367. * no other traffic).
  4368. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4369. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4370. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4371. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4372. * Must be set longer than active dwell time.
  4373. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4374. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4375. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4376. #define IWL_PASSIVE_DWELL_BASE (100)
  4377. #define IWL_CHANNEL_TUNE_TIME 5
  4378. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4379. enum ieee80211_band band)
  4380. {
  4381. if (band == IEEE80211_BAND_5GHZ)
  4382. return IWL_ACTIVE_DWELL_TIME_52;
  4383. else
  4384. return IWL_ACTIVE_DWELL_TIME_24;
  4385. }
  4386. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4387. enum ieee80211_band band)
  4388. {
  4389. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4390. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4391. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4392. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4393. if (iwl3945_is_associated(priv)) {
  4394. /* If we're associated, we clamp the maximum passive
  4395. * dwell time to be 98% of the beacon interval (minus
  4396. * 2 * channel tune time) */
  4397. passive = priv->beacon_int;
  4398. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4399. passive = IWL_PASSIVE_DWELL_BASE;
  4400. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4401. }
  4402. if (passive <= active)
  4403. passive = active + 1;
  4404. return passive;
  4405. }
  4406. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4407. enum ieee80211_band band,
  4408. u8 is_active, u8 direct_mask,
  4409. struct iwl3945_scan_channel *scan_ch)
  4410. {
  4411. const struct ieee80211_channel *channels = NULL;
  4412. const struct ieee80211_supported_band *sband;
  4413. const struct iwl3945_channel_info *ch_info;
  4414. u16 passive_dwell = 0;
  4415. u16 active_dwell = 0;
  4416. int added, i;
  4417. sband = iwl3945_get_band(priv, band);
  4418. if (!sband)
  4419. return 0;
  4420. channels = sband->channels;
  4421. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4422. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4423. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4424. if (channels[i].hw_value ==
  4425. le16_to_cpu(priv->active_rxon.channel)) {
  4426. if (iwl3945_is_associated(priv)) {
  4427. IWL_DEBUG_SCAN
  4428. ("Skipping current channel %d\n",
  4429. le16_to_cpu(priv->active_rxon.channel));
  4430. continue;
  4431. }
  4432. } else if (priv->only_active_channel)
  4433. continue;
  4434. scan_ch->channel = channels[i].hw_value;
  4435. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4436. if (!is_channel_valid(ch_info)) {
  4437. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4438. scan_ch->channel);
  4439. continue;
  4440. }
  4441. if (!is_active || is_channel_passive(ch_info) ||
  4442. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4443. scan_ch->type = 0; /* passive */
  4444. else
  4445. scan_ch->type = 1; /* active */
  4446. if (scan_ch->type & 1)
  4447. scan_ch->type |= (direct_mask << 1);
  4448. if (is_channel_narrow(ch_info))
  4449. scan_ch->type |= (1 << 7);
  4450. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4451. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4452. /* Set txpower levels to defaults */
  4453. scan_ch->tpc.dsp_atten = 110;
  4454. /* scan_pwr_info->tpc.dsp_atten; */
  4455. /*scan_pwr_info->tpc.tx_gain; */
  4456. if (band == IEEE80211_BAND_5GHZ)
  4457. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4458. else {
  4459. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4460. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4461. * power level:
  4462. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4463. */
  4464. }
  4465. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4466. scan_ch->channel,
  4467. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4468. (scan_ch->type & 1) ?
  4469. active_dwell : passive_dwell);
  4470. scan_ch++;
  4471. added++;
  4472. }
  4473. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4474. return added;
  4475. }
  4476. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4477. struct ieee80211_rate *rates)
  4478. {
  4479. int i;
  4480. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4481. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4482. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4483. rates[i].hw_value_short = i;
  4484. rates[i].flags = 0;
  4485. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4486. /*
  4487. * If CCK != 1M then set short preamble rate flag.
  4488. */
  4489. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4490. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4491. }
  4492. }
  4493. }
  4494. /**
  4495. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4496. */
  4497. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4498. {
  4499. struct iwl3945_channel_info *ch;
  4500. struct ieee80211_supported_band *band;
  4501. struct ieee80211_channel *channels;
  4502. struct ieee80211_channel *geo_ch;
  4503. struct ieee80211_rate *rates;
  4504. int i = 0;
  4505. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4506. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4507. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4508. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4509. return 0;
  4510. }
  4511. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4512. priv->channel_count, GFP_KERNEL);
  4513. if (!channels)
  4514. return -ENOMEM;
  4515. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
  4516. GFP_KERNEL);
  4517. if (!rates) {
  4518. kfree(channels);
  4519. return -ENOMEM;
  4520. }
  4521. /* 5.2GHz channels start after the 2.4GHz channels */
  4522. band = &priv->bands[IEEE80211_BAND_5GHZ];
  4523. band->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4524. band->bitrates = &rates[4];
  4525. band->n_bitrates = 8; /* just OFDM */
  4526. band = &priv->bands[IEEE80211_BAND_2GHZ];
  4527. band->channels = channels;
  4528. band->bitrates = rates;
  4529. band->n_bitrates = 12; /* OFDM & CCK */
  4530. priv->ieee_channels = channels;
  4531. priv->ieee_rates = rates;
  4532. iwl3945_init_hw_rates(priv, rates);
  4533. for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
  4534. ch = &priv->channel_info[i];
  4535. if (!is_channel_valid(ch)) {
  4536. IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
  4537. "skipping.\n",
  4538. ch->channel, is_channel_a_band(ch) ?
  4539. "5.2" : "2.4");
  4540. continue;
  4541. }
  4542. if (is_channel_a_band(ch))
  4543. geo_ch = &priv->bands[IEEE80211_BAND_5GHZ].channels[priv->bands[IEEE80211_BAND_5GHZ].n_channels++];
  4544. else
  4545. geo_ch = &priv->bands[IEEE80211_BAND_2GHZ].channels[priv->bands[IEEE80211_BAND_2GHZ].n_channels++];
  4546. geo_ch->center_freq = ieee80211chan2mhz(ch->channel);
  4547. geo_ch->max_power = ch->max_power_avg;
  4548. geo_ch->max_antenna_gain = 0xff;
  4549. if (is_channel_valid(ch)) {
  4550. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4551. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4552. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4553. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4554. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4555. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4556. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4557. priv->max_channel_txpower_limit =
  4558. ch->max_power_avg;
  4559. } else
  4560. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4561. }
  4562. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) {
  4563. printk(KERN_INFO DRV_NAME
  4564. ": Incorrectly detected BG card as ABG. Please send "
  4565. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4566. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4567. priv->is_abg = 0;
  4568. }
  4569. printk(KERN_INFO DRV_NAME
  4570. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4571. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4572. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4573. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
  4574. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
  4575. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4576. return 0;
  4577. }
  4578. /*
  4579. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4580. */
  4581. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4582. {
  4583. kfree(priv->ieee_channels);
  4584. kfree(priv->ieee_rates);
  4585. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4586. }
  4587. /******************************************************************************
  4588. *
  4589. * uCode download functions
  4590. *
  4591. ******************************************************************************/
  4592. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4593. {
  4594. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4595. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4596. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4597. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4598. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4599. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4600. }
  4601. /**
  4602. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4603. * looking at all data.
  4604. */
  4605. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4606. {
  4607. u32 val;
  4608. u32 save_len = len;
  4609. int rc = 0;
  4610. u32 errcnt;
  4611. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4612. rc = iwl3945_grab_nic_access(priv);
  4613. if (rc)
  4614. return rc;
  4615. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4616. errcnt = 0;
  4617. for (; len > 0; len -= sizeof(u32), image++) {
  4618. /* read data comes through single port, auto-incr addr */
  4619. /* NOTE: Use the debugless read so we don't flood kernel log
  4620. * if IWL_DL_IO is set */
  4621. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4622. if (val != le32_to_cpu(*image)) {
  4623. IWL_ERROR("uCode INST section is invalid at "
  4624. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4625. save_len - len, val, le32_to_cpu(*image));
  4626. rc = -EIO;
  4627. errcnt++;
  4628. if (errcnt >= 20)
  4629. break;
  4630. }
  4631. }
  4632. iwl3945_release_nic_access(priv);
  4633. if (!errcnt)
  4634. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4635. return rc;
  4636. }
  4637. /**
  4638. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4639. * using sample data 100 bytes apart. If these sample points are good,
  4640. * it's a pretty good bet that everything between them is good, too.
  4641. */
  4642. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4643. {
  4644. u32 val;
  4645. int rc = 0;
  4646. u32 errcnt = 0;
  4647. u32 i;
  4648. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4649. rc = iwl3945_grab_nic_access(priv);
  4650. if (rc)
  4651. return rc;
  4652. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4653. /* read data comes through single port, auto-incr addr */
  4654. /* NOTE: Use the debugless read so we don't flood kernel log
  4655. * if IWL_DL_IO is set */
  4656. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4657. i + RTC_INST_LOWER_BOUND);
  4658. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4659. if (val != le32_to_cpu(*image)) {
  4660. #if 0 /* Enable this if you want to see details */
  4661. IWL_ERROR("uCode INST section is invalid at "
  4662. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4663. i, val, *image);
  4664. #endif
  4665. rc = -EIO;
  4666. errcnt++;
  4667. if (errcnt >= 3)
  4668. break;
  4669. }
  4670. }
  4671. iwl3945_release_nic_access(priv);
  4672. return rc;
  4673. }
  4674. /**
  4675. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4676. * and verify its contents
  4677. */
  4678. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4679. {
  4680. __le32 *image;
  4681. u32 len;
  4682. int rc = 0;
  4683. /* Try bootstrap */
  4684. image = (__le32 *)priv->ucode_boot.v_addr;
  4685. len = priv->ucode_boot.len;
  4686. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4687. if (rc == 0) {
  4688. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4689. return 0;
  4690. }
  4691. /* Try initialize */
  4692. image = (__le32 *)priv->ucode_init.v_addr;
  4693. len = priv->ucode_init.len;
  4694. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4695. if (rc == 0) {
  4696. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4697. return 0;
  4698. }
  4699. /* Try runtime/protocol */
  4700. image = (__le32 *)priv->ucode_code.v_addr;
  4701. len = priv->ucode_code.len;
  4702. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4703. if (rc == 0) {
  4704. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4705. return 0;
  4706. }
  4707. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4708. /* Since nothing seems to match, show first several data entries in
  4709. * instruction SRAM, so maybe visual inspection will give a clue.
  4710. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4711. image = (__le32 *)priv->ucode_boot.v_addr;
  4712. len = priv->ucode_boot.len;
  4713. rc = iwl3945_verify_inst_full(priv, image, len);
  4714. return rc;
  4715. }
  4716. /* check contents of special bootstrap uCode SRAM */
  4717. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4718. {
  4719. __le32 *image = priv->ucode_boot.v_addr;
  4720. u32 len = priv->ucode_boot.len;
  4721. u32 reg;
  4722. u32 val;
  4723. IWL_DEBUG_INFO("Begin verify bsm\n");
  4724. /* verify BSM SRAM contents */
  4725. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4726. for (reg = BSM_SRAM_LOWER_BOUND;
  4727. reg < BSM_SRAM_LOWER_BOUND + len;
  4728. reg += sizeof(u32), image ++) {
  4729. val = iwl3945_read_prph(priv, reg);
  4730. if (val != le32_to_cpu(*image)) {
  4731. IWL_ERROR("BSM uCode verification failed at "
  4732. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4733. BSM_SRAM_LOWER_BOUND,
  4734. reg - BSM_SRAM_LOWER_BOUND, len,
  4735. val, le32_to_cpu(*image));
  4736. return -EIO;
  4737. }
  4738. }
  4739. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4740. return 0;
  4741. }
  4742. /**
  4743. * iwl3945_load_bsm - Load bootstrap instructions
  4744. *
  4745. * BSM operation:
  4746. *
  4747. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4748. * in special SRAM that does not power down during RFKILL. When powering back
  4749. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4750. * the bootstrap program into the on-board processor, and starts it.
  4751. *
  4752. * The bootstrap program loads (via DMA) instructions and data for a new
  4753. * program from host DRAM locations indicated by the host driver in the
  4754. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4755. * automatically.
  4756. *
  4757. * When initializing the NIC, the host driver points the BSM to the
  4758. * "initialize" uCode image. This uCode sets up some internal data, then
  4759. * notifies host via "initialize alive" that it is complete.
  4760. *
  4761. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4762. * normal runtime uCode instructions and a backup uCode data cache buffer
  4763. * (filled initially with starting data values for the on-board processor),
  4764. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4765. * which begins normal operation.
  4766. *
  4767. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4768. * the backup data cache in DRAM before SRAM is powered down.
  4769. *
  4770. * When powering back up, the BSM loads the bootstrap program. This reloads
  4771. * the runtime uCode instructions and the backup data cache into SRAM,
  4772. * and re-launches the runtime uCode from where it left off.
  4773. */
  4774. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4775. {
  4776. __le32 *image = priv->ucode_boot.v_addr;
  4777. u32 len = priv->ucode_boot.len;
  4778. dma_addr_t pinst;
  4779. dma_addr_t pdata;
  4780. u32 inst_len;
  4781. u32 data_len;
  4782. int rc;
  4783. int i;
  4784. u32 done;
  4785. u32 reg_offset;
  4786. IWL_DEBUG_INFO("Begin load bsm\n");
  4787. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4788. if (len > IWL_MAX_BSM_SIZE)
  4789. return -EINVAL;
  4790. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4791. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4792. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4793. * after the "initialize" uCode has run, to point to
  4794. * runtime/protocol instructions and backup data cache. */
  4795. pinst = priv->ucode_init.p_addr;
  4796. pdata = priv->ucode_init_data.p_addr;
  4797. inst_len = priv->ucode_init.len;
  4798. data_len = priv->ucode_init_data.len;
  4799. rc = iwl3945_grab_nic_access(priv);
  4800. if (rc)
  4801. return rc;
  4802. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4803. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4804. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4805. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4806. /* Fill BSM memory with bootstrap instructions */
  4807. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4808. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4809. reg_offset += sizeof(u32), image++)
  4810. _iwl3945_write_prph(priv, reg_offset,
  4811. le32_to_cpu(*image));
  4812. rc = iwl3945_verify_bsm(priv);
  4813. if (rc) {
  4814. iwl3945_release_nic_access(priv);
  4815. return rc;
  4816. }
  4817. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4818. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4819. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4820. RTC_INST_LOWER_BOUND);
  4821. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4822. /* Load bootstrap code into instruction SRAM now,
  4823. * to prepare to load "initialize" uCode */
  4824. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4825. BSM_WR_CTRL_REG_BIT_START);
  4826. /* Wait for load of bootstrap uCode to finish */
  4827. for (i = 0; i < 100; i++) {
  4828. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4829. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4830. break;
  4831. udelay(10);
  4832. }
  4833. if (i < 100)
  4834. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4835. else {
  4836. IWL_ERROR("BSM write did not complete!\n");
  4837. return -EIO;
  4838. }
  4839. /* Enable future boot loads whenever power management unit triggers it
  4840. * (e.g. when powering back up after power-save shutdown) */
  4841. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4842. BSM_WR_CTRL_REG_BIT_START_EN);
  4843. iwl3945_release_nic_access(priv);
  4844. return 0;
  4845. }
  4846. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4847. {
  4848. /* Remove all resets to allow NIC to operate */
  4849. iwl3945_write32(priv, CSR_RESET, 0);
  4850. }
  4851. /**
  4852. * iwl3945_read_ucode - Read uCode images from disk file.
  4853. *
  4854. * Copy into buffers for card to fetch via bus-mastering
  4855. */
  4856. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4857. {
  4858. struct iwl3945_ucode *ucode;
  4859. int ret = 0;
  4860. const struct firmware *ucode_raw;
  4861. /* firmware file name contains uCode/driver compatibility version */
  4862. const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
  4863. u8 *src;
  4864. size_t len;
  4865. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4866. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4867. * request_firmware() is synchronous, file is in memory on return. */
  4868. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4869. if (ret < 0) {
  4870. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4871. name, ret);
  4872. goto error;
  4873. }
  4874. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4875. name, ucode_raw->size);
  4876. /* Make sure that we got at least our header! */
  4877. if (ucode_raw->size < sizeof(*ucode)) {
  4878. IWL_ERROR("File size way too small!\n");
  4879. ret = -EINVAL;
  4880. goto err_release;
  4881. }
  4882. /* Data from ucode file: header followed by uCode images */
  4883. ucode = (void *)ucode_raw->data;
  4884. ver = le32_to_cpu(ucode->ver);
  4885. inst_size = le32_to_cpu(ucode->inst_size);
  4886. data_size = le32_to_cpu(ucode->data_size);
  4887. init_size = le32_to_cpu(ucode->init_size);
  4888. init_data_size = le32_to_cpu(ucode->init_data_size);
  4889. boot_size = le32_to_cpu(ucode->boot_size);
  4890. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4891. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4892. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4893. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4894. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4895. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4896. /* Verify size of file vs. image size info in file's header */
  4897. if (ucode_raw->size < sizeof(*ucode) +
  4898. inst_size + data_size + init_size +
  4899. init_data_size + boot_size) {
  4900. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4901. (int)ucode_raw->size);
  4902. ret = -EINVAL;
  4903. goto err_release;
  4904. }
  4905. /* Verify that uCode images will fit in card's SRAM */
  4906. if (inst_size > IWL_MAX_INST_SIZE) {
  4907. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4908. inst_size);
  4909. ret = -EINVAL;
  4910. goto err_release;
  4911. }
  4912. if (data_size > IWL_MAX_DATA_SIZE) {
  4913. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4914. data_size);
  4915. ret = -EINVAL;
  4916. goto err_release;
  4917. }
  4918. if (init_size > IWL_MAX_INST_SIZE) {
  4919. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4920. init_size);
  4921. ret = -EINVAL;
  4922. goto err_release;
  4923. }
  4924. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4925. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4926. init_data_size);
  4927. ret = -EINVAL;
  4928. goto err_release;
  4929. }
  4930. if (boot_size > IWL_MAX_BSM_SIZE) {
  4931. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4932. boot_size);
  4933. ret = -EINVAL;
  4934. goto err_release;
  4935. }
  4936. /* Allocate ucode buffers for card's bus-master loading ... */
  4937. /* Runtime instructions and 2 copies of data:
  4938. * 1) unmodified from disk
  4939. * 2) backup cache for save/restore during power-downs */
  4940. priv->ucode_code.len = inst_size;
  4941. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4942. priv->ucode_data.len = data_size;
  4943. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4944. priv->ucode_data_backup.len = data_size;
  4945. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4946. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4947. !priv->ucode_data_backup.v_addr)
  4948. goto err_pci_alloc;
  4949. /* Initialization instructions and data */
  4950. if (init_size && init_data_size) {
  4951. priv->ucode_init.len = init_size;
  4952. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4953. priv->ucode_init_data.len = init_data_size;
  4954. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4955. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4956. goto err_pci_alloc;
  4957. }
  4958. /* Bootstrap (instructions only, no data) */
  4959. if (boot_size) {
  4960. priv->ucode_boot.len = boot_size;
  4961. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4962. if (!priv->ucode_boot.v_addr)
  4963. goto err_pci_alloc;
  4964. }
  4965. /* Copy images into buffers for card's bus-master reads ... */
  4966. /* Runtime instructions (first block of data in file) */
  4967. src = &ucode->data[0];
  4968. len = priv->ucode_code.len;
  4969. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4970. memcpy(priv->ucode_code.v_addr, src, len);
  4971. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4972. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4973. /* Runtime data (2nd block)
  4974. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4975. src = &ucode->data[inst_size];
  4976. len = priv->ucode_data.len;
  4977. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4978. memcpy(priv->ucode_data.v_addr, src, len);
  4979. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4980. /* Initialization instructions (3rd block) */
  4981. if (init_size) {
  4982. src = &ucode->data[inst_size + data_size];
  4983. len = priv->ucode_init.len;
  4984. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4985. len);
  4986. memcpy(priv->ucode_init.v_addr, src, len);
  4987. }
  4988. /* Initialization data (4th block) */
  4989. if (init_data_size) {
  4990. src = &ucode->data[inst_size + data_size + init_size];
  4991. len = priv->ucode_init_data.len;
  4992. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4993. (int)len);
  4994. memcpy(priv->ucode_init_data.v_addr, src, len);
  4995. }
  4996. /* Bootstrap instructions (5th block) */
  4997. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4998. len = priv->ucode_boot.len;
  4999. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  5000. (int)len);
  5001. memcpy(priv->ucode_boot.v_addr, src, len);
  5002. /* We have our copies now, allow OS release its copies */
  5003. release_firmware(ucode_raw);
  5004. return 0;
  5005. err_pci_alloc:
  5006. IWL_ERROR("failed to allocate pci memory\n");
  5007. ret = -ENOMEM;
  5008. iwl3945_dealloc_ucode_pci(priv);
  5009. err_release:
  5010. release_firmware(ucode_raw);
  5011. error:
  5012. return ret;
  5013. }
  5014. /**
  5015. * iwl3945_set_ucode_ptrs - Set uCode address location
  5016. *
  5017. * Tell initialization uCode where to find runtime uCode.
  5018. *
  5019. * BSM registers initially contain pointers to initialization uCode.
  5020. * We need to replace them to load runtime uCode inst and data,
  5021. * and to save runtime data when powering down.
  5022. */
  5023. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  5024. {
  5025. dma_addr_t pinst;
  5026. dma_addr_t pdata;
  5027. int rc = 0;
  5028. unsigned long flags;
  5029. /* bits 31:0 for 3945 */
  5030. pinst = priv->ucode_code.p_addr;
  5031. pdata = priv->ucode_data_backup.p_addr;
  5032. spin_lock_irqsave(&priv->lock, flags);
  5033. rc = iwl3945_grab_nic_access(priv);
  5034. if (rc) {
  5035. spin_unlock_irqrestore(&priv->lock, flags);
  5036. return rc;
  5037. }
  5038. /* Tell bootstrap uCode where to find image to load */
  5039. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5040. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5041. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  5042. priv->ucode_data.len);
  5043. /* Inst bytecount must be last to set up, bit 31 signals uCode
  5044. * that all new ptr/size info is in place */
  5045. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  5046. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  5047. iwl3945_release_nic_access(priv);
  5048. spin_unlock_irqrestore(&priv->lock, flags);
  5049. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  5050. return rc;
  5051. }
  5052. /**
  5053. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  5054. *
  5055. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  5056. *
  5057. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  5058. */
  5059. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  5060. {
  5061. /* Check alive response for "valid" sign from uCode */
  5062. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  5063. /* We had an error bringing up the hardware, so take it
  5064. * all the way back down so we can try again */
  5065. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  5066. goto restart;
  5067. }
  5068. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  5069. * This is a paranoid check, because we would not have gotten the
  5070. * "initialize" alive if code weren't properly loaded. */
  5071. if (iwl3945_verify_ucode(priv)) {
  5072. /* Runtime instruction load was bad;
  5073. * take it all the way back down so we can try again */
  5074. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  5075. goto restart;
  5076. }
  5077. /* Send pointers to protocol/runtime uCode image ... init code will
  5078. * load and launch runtime uCode, which will send us another "Alive"
  5079. * notification. */
  5080. IWL_DEBUG_INFO("Initialization Alive received.\n");
  5081. if (iwl3945_set_ucode_ptrs(priv)) {
  5082. /* Runtime instruction load won't happen;
  5083. * take it all the way back down so we can try again */
  5084. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  5085. goto restart;
  5086. }
  5087. return;
  5088. restart:
  5089. queue_work(priv->workqueue, &priv->restart);
  5090. }
  5091. /**
  5092. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  5093. * from protocol/runtime uCode (initialization uCode's
  5094. * Alive gets handled by iwl3945_init_alive_start()).
  5095. */
  5096. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  5097. {
  5098. int rc = 0;
  5099. int thermal_spin = 0;
  5100. u32 rfkill;
  5101. IWL_DEBUG_INFO("Runtime Alive received.\n");
  5102. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  5103. /* We had an error bringing up the hardware, so take it
  5104. * all the way back down so we can try again */
  5105. IWL_DEBUG_INFO("Alive failed.\n");
  5106. goto restart;
  5107. }
  5108. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  5109. * This is a paranoid check, because we would not have gotten the
  5110. * "runtime" alive if code weren't properly loaded. */
  5111. if (iwl3945_verify_ucode(priv)) {
  5112. /* Runtime instruction load was bad;
  5113. * take it all the way back down so we can try again */
  5114. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  5115. goto restart;
  5116. }
  5117. iwl3945_clear_stations_table(priv);
  5118. rc = iwl3945_grab_nic_access(priv);
  5119. if (rc) {
  5120. IWL_WARNING("Can not read rfkill status from adapter\n");
  5121. return;
  5122. }
  5123. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  5124. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  5125. iwl3945_release_nic_access(priv);
  5126. if (rfkill & 0x1) {
  5127. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5128. /* if rfkill is not on, then wait for thermal
  5129. * sensor in adapter to kick in */
  5130. while (iwl3945_hw_get_temperature(priv) == 0) {
  5131. thermal_spin++;
  5132. udelay(10);
  5133. }
  5134. if (thermal_spin)
  5135. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  5136. thermal_spin * 10);
  5137. } else
  5138. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5139. /* After the ALIVE response, we can send commands to 3945 uCode */
  5140. set_bit(STATUS_ALIVE, &priv->status);
  5141. /* Clear out the uCode error bit if it is set */
  5142. clear_bit(STATUS_FW_ERROR, &priv->status);
  5143. if (iwl3945_is_rfkill(priv))
  5144. return;
  5145. ieee80211_start_queues(priv->hw);
  5146. priv->active_rate = priv->rates_mask;
  5147. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5148. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5149. if (iwl3945_is_associated(priv)) {
  5150. struct iwl3945_rxon_cmd *active_rxon =
  5151. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  5152. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5153. sizeof(priv->staging_rxon));
  5154. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5155. } else {
  5156. /* Initialize our rx_config data */
  5157. iwl3945_connection_init_rx_config(priv);
  5158. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5159. }
  5160. /* Configure Bluetooth device coexistence support */
  5161. iwl3945_send_bt_config(priv);
  5162. /* Configure the adapter for unassociated operation */
  5163. iwl3945_commit_rxon(priv);
  5164. /* At this point, the NIC is initialized and operational */
  5165. priv->notif_missed_beacons = 0;
  5166. set_bit(STATUS_READY, &priv->status);
  5167. iwl3945_reg_txpower_periodic(priv);
  5168. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5169. wake_up_interruptible(&priv->wait_command_queue);
  5170. if (priv->error_recovering)
  5171. iwl3945_error_recovery(priv);
  5172. return;
  5173. restart:
  5174. queue_work(priv->workqueue, &priv->restart);
  5175. }
  5176. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5177. static void __iwl3945_down(struct iwl3945_priv *priv)
  5178. {
  5179. unsigned long flags;
  5180. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5181. struct ieee80211_conf *conf = NULL;
  5182. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5183. conf = ieee80211_get_hw_conf(priv->hw);
  5184. if (!exit_pending)
  5185. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5186. iwl3945_clear_stations_table(priv);
  5187. /* Unblock any waiting calls */
  5188. wake_up_interruptible_all(&priv->wait_command_queue);
  5189. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5190. * exiting the module */
  5191. if (!exit_pending)
  5192. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5193. /* stop and reset the on-board processor */
  5194. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5195. /* tell the device to stop sending interrupts */
  5196. iwl3945_disable_interrupts(priv);
  5197. if (priv->mac80211_registered)
  5198. ieee80211_stop_queues(priv->hw);
  5199. /* If we have not previously called iwl3945_init() then
  5200. * clear all bits but the RF Kill and SUSPEND bits and return */
  5201. if (!iwl3945_is_init(priv)) {
  5202. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5203. STATUS_RF_KILL_HW |
  5204. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5205. STATUS_RF_KILL_SW |
  5206. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5207. STATUS_GEO_CONFIGURED |
  5208. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5209. STATUS_IN_SUSPEND;
  5210. goto exit;
  5211. }
  5212. /* ...otherwise clear out all the status bits but the RF Kill and
  5213. * SUSPEND bits and continue taking the NIC down. */
  5214. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5215. STATUS_RF_KILL_HW |
  5216. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5217. STATUS_RF_KILL_SW |
  5218. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5219. STATUS_GEO_CONFIGURED |
  5220. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5221. STATUS_IN_SUSPEND |
  5222. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5223. STATUS_FW_ERROR;
  5224. spin_lock_irqsave(&priv->lock, flags);
  5225. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5226. spin_unlock_irqrestore(&priv->lock, flags);
  5227. iwl3945_hw_txq_ctx_stop(priv);
  5228. iwl3945_hw_rxq_stop(priv);
  5229. spin_lock_irqsave(&priv->lock, flags);
  5230. if (!iwl3945_grab_nic_access(priv)) {
  5231. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5232. APMG_CLK_VAL_DMA_CLK_RQT);
  5233. iwl3945_release_nic_access(priv);
  5234. }
  5235. spin_unlock_irqrestore(&priv->lock, flags);
  5236. udelay(5);
  5237. iwl3945_hw_nic_stop_master(priv);
  5238. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5239. iwl3945_hw_nic_reset(priv);
  5240. exit:
  5241. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5242. if (priv->ibss_beacon)
  5243. dev_kfree_skb(priv->ibss_beacon);
  5244. priv->ibss_beacon = NULL;
  5245. /* clear out any free frames */
  5246. iwl3945_clear_free_frames(priv);
  5247. }
  5248. static void iwl3945_down(struct iwl3945_priv *priv)
  5249. {
  5250. mutex_lock(&priv->mutex);
  5251. __iwl3945_down(priv);
  5252. mutex_unlock(&priv->mutex);
  5253. iwl3945_cancel_deferred_work(priv);
  5254. }
  5255. #define MAX_HW_RESTARTS 5
  5256. static int __iwl3945_up(struct iwl3945_priv *priv)
  5257. {
  5258. int rc, i;
  5259. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5260. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5261. return -EIO;
  5262. }
  5263. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5264. IWL_WARNING("Radio disabled by SW RF kill (module "
  5265. "parameter)\n");
  5266. return -ENODEV;
  5267. }
  5268. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5269. IWL_ERROR("ucode not available for device bringup\n");
  5270. return -EIO;
  5271. }
  5272. /* If platform's RF_KILL switch is NOT set to KILL */
  5273. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5274. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5275. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5276. else {
  5277. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5278. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5279. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5280. return -ENODEV;
  5281. }
  5282. }
  5283. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5284. rc = iwl3945_hw_nic_init(priv);
  5285. if (rc) {
  5286. IWL_ERROR("Unable to int nic\n");
  5287. return rc;
  5288. }
  5289. /* make sure rfkill handshake bits are cleared */
  5290. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5291. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5292. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5293. /* clear (again), then enable host interrupts */
  5294. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5295. iwl3945_enable_interrupts(priv);
  5296. /* really make sure rfkill handshake bits are cleared */
  5297. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5298. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5299. /* Copy original ucode data image from disk into backup cache.
  5300. * This will be used to initialize the on-board processor's
  5301. * data SRAM for a clean start when the runtime program first loads. */
  5302. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5303. priv->ucode_data.len);
  5304. /* We return success when we resume from suspend and rf_kill is on. */
  5305. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5306. return 0;
  5307. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5308. iwl3945_clear_stations_table(priv);
  5309. /* load bootstrap state machine,
  5310. * load bootstrap program into processor's memory,
  5311. * prepare to load the "initialize" uCode */
  5312. rc = iwl3945_load_bsm(priv);
  5313. if (rc) {
  5314. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5315. continue;
  5316. }
  5317. /* start card; "initialize" will load runtime ucode */
  5318. iwl3945_nic_start(priv);
  5319. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5320. return 0;
  5321. }
  5322. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5323. __iwl3945_down(priv);
  5324. /* tried to restart and config the device for as long as our
  5325. * patience could withstand */
  5326. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5327. return -EIO;
  5328. }
  5329. /*****************************************************************************
  5330. *
  5331. * Workqueue callbacks
  5332. *
  5333. *****************************************************************************/
  5334. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5335. {
  5336. struct iwl3945_priv *priv =
  5337. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5338. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5339. return;
  5340. mutex_lock(&priv->mutex);
  5341. iwl3945_init_alive_start(priv);
  5342. mutex_unlock(&priv->mutex);
  5343. }
  5344. static void iwl3945_bg_alive_start(struct work_struct *data)
  5345. {
  5346. struct iwl3945_priv *priv =
  5347. container_of(data, struct iwl3945_priv, alive_start.work);
  5348. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5349. return;
  5350. mutex_lock(&priv->mutex);
  5351. iwl3945_alive_start(priv);
  5352. mutex_unlock(&priv->mutex);
  5353. }
  5354. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5355. {
  5356. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5357. wake_up_interruptible(&priv->wait_command_queue);
  5358. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5359. return;
  5360. mutex_lock(&priv->mutex);
  5361. if (!iwl3945_is_rfkill(priv)) {
  5362. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5363. "HW and/or SW RF Kill no longer active, restarting "
  5364. "device\n");
  5365. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5366. queue_work(priv->workqueue, &priv->restart);
  5367. } else {
  5368. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5369. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5370. "disabled by SW switch\n");
  5371. else
  5372. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5373. "Kill switch must be turned off for "
  5374. "wireless networking to work.\n");
  5375. }
  5376. mutex_unlock(&priv->mutex);
  5377. }
  5378. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5379. static void iwl3945_bg_scan_check(struct work_struct *data)
  5380. {
  5381. struct iwl3945_priv *priv =
  5382. container_of(data, struct iwl3945_priv, scan_check.work);
  5383. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5384. return;
  5385. mutex_lock(&priv->mutex);
  5386. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5387. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5388. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5389. "Scan completion watchdog resetting adapter (%dms)\n",
  5390. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5391. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5392. iwl3945_send_scan_abort(priv);
  5393. }
  5394. mutex_unlock(&priv->mutex);
  5395. }
  5396. static void iwl3945_bg_request_scan(struct work_struct *data)
  5397. {
  5398. struct iwl3945_priv *priv =
  5399. container_of(data, struct iwl3945_priv, request_scan);
  5400. struct iwl3945_host_cmd cmd = {
  5401. .id = REPLY_SCAN_CMD,
  5402. .len = sizeof(struct iwl3945_scan_cmd),
  5403. .meta.flags = CMD_SIZE_HUGE,
  5404. };
  5405. int rc = 0;
  5406. struct iwl3945_scan_cmd *scan;
  5407. struct ieee80211_conf *conf = NULL;
  5408. u8 direct_mask;
  5409. enum ieee80211_band band;
  5410. conf = ieee80211_get_hw_conf(priv->hw);
  5411. mutex_lock(&priv->mutex);
  5412. if (!iwl3945_is_ready(priv)) {
  5413. IWL_WARNING("request scan called when driver not ready.\n");
  5414. goto done;
  5415. }
  5416. /* Make sure the scan wasn't cancelled before this queued work
  5417. * was given the chance to run... */
  5418. if (!test_bit(STATUS_SCANNING, &priv->status))
  5419. goto done;
  5420. /* This should never be called or scheduled if there is currently
  5421. * a scan active in the hardware. */
  5422. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5423. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5424. "Ignoring second request.\n");
  5425. rc = -EIO;
  5426. goto done;
  5427. }
  5428. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5429. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5430. goto done;
  5431. }
  5432. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5433. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5434. goto done;
  5435. }
  5436. if (iwl3945_is_rfkill(priv)) {
  5437. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5438. goto done;
  5439. }
  5440. if (!test_bit(STATUS_READY, &priv->status)) {
  5441. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5442. goto done;
  5443. }
  5444. if (!priv->scan_bands) {
  5445. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5446. goto done;
  5447. }
  5448. if (!priv->scan) {
  5449. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5450. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5451. if (!priv->scan) {
  5452. rc = -ENOMEM;
  5453. goto done;
  5454. }
  5455. }
  5456. scan = priv->scan;
  5457. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5458. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5459. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5460. if (iwl3945_is_associated(priv)) {
  5461. u16 interval = 0;
  5462. u32 extra;
  5463. u32 suspend_time = 100;
  5464. u32 scan_suspend_time = 100;
  5465. unsigned long flags;
  5466. IWL_DEBUG_INFO("Scanning while associated...\n");
  5467. spin_lock_irqsave(&priv->lock, flags);
  5468. interval = priv->beacon_int;
  5469. spin_unlock_irqrestore(&priv->lock, flags);
  5470. scan->suspend_time = 0;
  5471. scan->max_out_time = cpu_to_le32(200 * 1024);
  5472. if (!interval)
  5473. interval = suspend_time;
  5474. /*
  5475. * suspend time format:
  5476. * 0-19: beacon interval in usec (time before exec.)
  5477. * 20-23: 0
  5478. * 24-31: number of beacons (suspend between channels)
  5479. */
  5480. extra = (suspend_time / interval) << 24;
  5481. scan_suspend_time = 0xFF0FFFFF &
  5482. (extra | ((suspend_time % interval) * 1024));
  5483. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5484. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5485. scan_suspend_time, interval);
  5486. }
  5487. /* We should add the ability for user to lock to PASSIVE ONLY */
  5488. if (priv->one_direct_scan) {
  5489. IWL_DEBUG_SCAN
  5490. ("Kicking off one direct scan for '%s'\n",
  5491. iwl3945_escape_essid(priv->direct_ssid,
  5492. priv->direct_ssid_len));
  5493. scan->direct_scan[0].id = WLAN_EID_SSID;
  5494. scan->direct_scan[0].len = priv->direct_ssid_len;
  5495. memcpy(scan->direct_scan[0].ssid,
  5496. priv->direct_ssid, priv->direct_ssid_len);
  5497. direct_mask = 1;
  5498. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5499. scan->direct_scan[0].id = WLAN_EID_SSID;
  5500. scan->direct_scan[0].len = priv->essid_len;
  5501. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5502. direct_mask = 1;
  5503. } else
  5504. direct_mask = 0;
  5505. /* We don't build a direct scan probe request; the uCode will do
  5506. * that based on the direct_mask added to each channel entry */
  5507. scan->tx_cmd.len = cpu_to_le16(
  5508. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5509. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5510. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5511. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5512. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5513. /* flags + rate selection */
  5514. switch (priv->scan_bands) {
  5515. case 2:
  5516. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5517. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5518. scan->good_CRC_th = 0;
  5519. band = IEEE80211_BAND_2GHZ;
  5520. break;
  5521. case 1:
  5522. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5523. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5524. band = IEEE80211_BAND_5GHZ;
  5525. break;
  5526. default:
  5527. IWL_WARNING("Invalid scan band count\n");
  5528. goto done;
  5529. }
  5530. /* select Rx antennas */
  5531. scan->flags |= iwl3945_get_antenna_flags(priv);
  5532. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5533. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5534. if (direct_mask)
  5535. IWL_DEBUG_SCAN
  5536. ("Initiating direct scan for %s.\n",
  5537. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5538. else
  5539. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5540. scan->channel_count =
  5541. iwl3945_get_channels_for_scan(
  5542. priv, band, 1, /* active */
  5543. direct_mask,
  5544. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5545. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5546. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5547. cmd.data = scan;
  5548. scan->len = cpu_to_le16(cmd.len);
  5549. set_bit(STATUS_SCAN_HW, &priv->status);
  5550. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5551. if (rc)
  5552. goto done;
  5553. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5554. IWL_SCAN_CHECK_WATCHDOG);
  5555. mutex_unlock(&priv->mutex);
  5556. return;
  5557. done:
  5558. /* inform mac80211 scan aborted */
  5559. queue_work(priv->workqueue, &priv->scan_completed);
  5560. mutex_unlock(&priv->mutex);
  5561. }
  5562. static void iwl3945_bg_up(struct work_struct *data)
  5563. {
  5564. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5565. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5566. return;
  5567. mutex_lock(&priv->mutex);
  5568. __iwl3945_up(priv);
  5569. mutex_unlock(&priv->mutex);
  5570. }
  5571. static void iwl3945_bg_restart(struct work_struct *data)
  5572. {
  5573. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5574. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5575. return;
  5576. iwl3945_down(priv);
  5577. queue_work(priv->workqueue, &priv->up);
  5578. }
  5579. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5580. {
  5581. struct iwl3945_priv *priv =
  5582. container_of(data, struct iwl3945_priv, rx_replenish);
  5583. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5584. return;
  5585. mutex_lock(&priv->mutex);
  5586. iwl3945_rx_replenish(priv);
  5587. mutex_unlock(&priv->mutex);
  5588. }
  5589. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5590. static void iwl3945_bg_post_associate(struct work_struct *data)
  5591. {
  5592. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5593. post_associate.work);
  5594. int rc = 0;
  5595. struct ieee80211_conf *conf = NULL;
  5596. DECLARE_MAC_BUF(mac);
  5597. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5598. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5599. return;
  5600. }
  5601. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5602. priv->assoc_id,
  5603. print_mac(mac, priv->active_rxon.bssid_addr));
  5604. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5605. return;
  5606. mutex_lock(&priv->mutex);
  5607. if (!priv->vif || !priv->is_open) {
  5608. mutex_unlock(&priv->mutex);
  5609. return;
  5610. }
  5611. iwl3945_scan_cancel_timeout(priv, 200);
  5612. conf = ieee80211_get_hw_conf(priv->hw);
  5613. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5614. iwl3945_commit_rxon(priv);
  5615. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5616. iwl3945_setup_rxon_timing(priv);
  5617. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5618. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5619. if (rc)
  5620. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5621. "Attempting to continue.\n");
  5622. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5623. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5624. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5625. priv->assoc_id, priv->beacon_int);
  5626. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5627. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5628. else
  5629. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5630. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5631. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5632. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5633. else
  5634. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5635. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5636. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5637. }
  5638. iwl3945_commit_rxon(priv);
  5639. switch (priv->iw_mode) {
  5640. case IEEE80211_IF_TYPE_STA:
  5641. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5642. break;
  5643. case IEEE80211_IF_TYPE_IBSS:
  5644. /* clear out the station table */
  5645. iwl3945_clear_stations_table(priv);
  5646. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5647. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5648. iwl3945_sync_sta(priv, IWL_STA_ID,
  5649. (priv->band == IEEE80211_BAND_5GHZ) ?
  5650. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5651. CMD_ASYNC);
  5652. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5653. iwl3945_send_beacon_cmd(priv);
  5654. break;
  5655. default:
  5656. IWL_ERROR("%s Should not be called in %d mode\n",
  5657. __FUNCTION__, priv->iw_mode);
  5658. break;
  5659. }
  5660. iwl3945_sequence_reset(priv);
  5661. #ifdef CONFIG_IWL3945_QOS
  5662. iwl3945_activate_qos(priv, 0);
  5663. #endif /* CONFIG_IWL3945_QOS */
  5664. /* we have just associated, don't start scan too early */
  5665. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5666. mutex_unlock(&priv->mutex);
  5667. }
  5668. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5669. {
  5670. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5671. if (!iwl3945_is_ready(priv))
  5672. return;
  5673. mutex_lock(&priv->mutex);
  5674. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5675. iwl3945_send_scan_abort(priv);
  5676. mutex_unlock(&priv->mutex);
  5677. }
  5678. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5679. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5680. {
  5681. struct iwl3945_priv *priv =
  5682. container_of(work, struct iwl3945_priv, scan_completed);
  5683. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5684. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5685. return;
  5686. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5687. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5688. ieee80211_scan_completed(priv->hw);
  5689. /* Since setting the TXPOWER may have been deferred while
  5690. * performing the scan, fire one off */
  5691. mutex_lock(&priv->mutex);
  5692. iwl3945_hw_reg_send_txpower(priv);
  5693. mutex_unlock(&priv->mutex);
  5694. }
  5695. /*****************************************************************************
  5696. *
  5697. * mac80211 entry point functions
  5698. *
  5699. *****************************************************************************/
  5700. #define UCODE_READY_TIMEOUT (2 * HZ)
  5701. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5702. {
  5703. struct iwl3945_priv *priv = hw->priv;
  5704. int ret;
  5705. IWL_DEBUG_MAC80211("enter\n");
  5706. if (pci_enable_device(priv->pci_dev)) {
  5707. IWL_ERROR("Fail to pci_enable_device\n");
  5708. return -ENODEV;
  5709. }
  5710. pci_restore_state(priv->pci_dev);
  5711. pci_enable_msi(priv->pci_dev);
  5712. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5713. DRV_NAME, priv);
  5714. if (ret) {
  5715. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5716. goto out_disable_msi;
  5717. }
  5718. /* we should be verifying the device is ready to be opened */
  5719. mutex_lock(&priv->mutex);
  5720. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5721. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5722. * ucode filename and max sizes are card-specific. */
  5723. if (!priv->ucode_code.len) {
  5724. ret = iwl3945_read_ucode(priv);
  5725. if (ret) {
  5726. IWL_ERROR("Could not read microcode: %d\n", ret);
  5727. mutex_unlock(&priv->mutex);
  5728. goto out_release_irq;
  5729. }
  5730. }
  5731. ret = __iwl3945_up(priv);
  5732. mutex_unlock(&priv->mutex);
  5733. if (ret)
  5734. goto out_release_irq;
  5735. IWL_DEBUG_INFO("Start UP work.\n");
  5736. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5737. return 0;
  5738. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5739. * mac80211 will not be run successfully. */
  5740. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5741. test_bit(STATUS_READY, &priv->status),
  5742. UCODE_READY_TIMEOUT);
  5743. if (!ret) {
  5744. if (!test_bit(STATUS_READY, &priv->status)) {
  5745. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5746. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5747. ret = -ETIMEDOUT;
  5748. goto out_release_irq;
  5749. }
  5750. }
  5751. priv->is_open = 1;
  5752. IWL_DEBUG_MAC80211("leave\n");
  5753. return 0;
  5754. out_release_irq:
  5755. free_irq(priv->pci_dev->irq, priv);
  5756. out_disable_msi:
  5757. pci_disable_msi(priv->pci_dev);
  5758. pci_disable_device(priv->pci_dev);
  5759. priv->is_open = 0;
  5760. IWL_DEBUG_MAC80211("leave - failed\n");
  5761. return ret;
  5762. }
  5763. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5764. {
  5765. struct iwl3945_priv *priv = hw->priv;
  5766. IWL_DEBUG_MAC80211("enter\n");
  5767. if (!priv->is_open) {
  5768. IWL_DEBUG_MAC80211("leave - skip\n");
  5769. return;
  5770. }
  5771. priv->is_open = 0;
  5772. if (iwl3945_is_ready_rf(priv)) {
  5773. /* stop mac, cancel any scan request and clear
  5774. * RXON_FILTER_ASSOC_MSK BIT
  5775. */
  5776. mutex_lock(&priv->mutex);
  5777. iwl3945_scan_cancel_timeout(priv, 100);
  5778. cancel_delayed_work(&priv->post_associate);
  5779. mutex_unlock(&priv->mutex);
  5780. }
  5781. iwl3945_down(priv);
  5782. flush_workqueue(priv->workqueue);
  5783. free_irq(priv->pci_dev->irq, priv);
  5784. pci_disable_msi(priv->pci_dev);
  5785. pci_save_state(priv->pci_dev);
  5786. pci_disable_device(priv->pci_dev);
  5787. IWL_DEBUG_MAC80211("leave\n");
  5788. }
  5789. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5790. struct ieee80211_tx_control *ctl)
  5791. {
  5792. struct iwl3945_priv *priv = hw->priv;
  5793. IWL_DEBUG_MAC80211("enter\n");
  5794. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5795. IWL_DEBUG_MAC80211("leave - monitor\n");
  5796. return -1;
  5797. }
  5798. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5799. ctl->tx_rate->bitrate);
  5800. if (iwl3945_tx_skb(priv, skb, ctl))
  5801. dev_kfree_skb_any(skb);
  5802. IWL_DEBUG_MAC80211("leave\n");
  5803. return 0;
  5804. }
  5805. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5806. struct ieee80211_if_init_conf *conf)
  5807. {
  5808. struct iwl3945_priv *priv = hw->priv;
  5809. unsigned long flags;
  5810. DECLARE_MAC_BUF(mac);
  5811. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5812. if (priv->vif) {
  5813. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5814. return -EOPNOTSUPP;
  5815. }
  5816. spin_lock_irqsave(&priv->lock, flags);
  5817. priv->vif = conf->vif;
  5818. spin_unlock_irqrestore(&priv->lock, flags);
  5819. mutex_lock(&priv->mutex);
  5820. if (conf->mac_addr) {
  5821. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5822. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5823. }
  5824. if (iwl3945_is_ready(priv))
  5825. iwl3945_set_mode(priv, conf->type);
  5826. mutex_unlock(&priv->mutex);
  5827. IWL_DEBUG_MAC80211("leave\n");
  5828. return 0;
  5829. }
  5830. /**
  5831. * iwl3945_mac_config - mac80211 config callback
  5832. *
  5833. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5834. * be set inappropriately and the driver currently sets the hardware up to
  5835. * use it whenever needed.
  5836. */
  5837. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5838. {
  5839. struct iwl3945_priv *priv = hw->priv;
  5840. const struct iwl3945_channel_info *ch_info;
  5841. unsigned long flags;
  5842. int ret = 0;
  5843. mutex_lock(&priv->mutex);
  5844. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5845. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5846. if (!iwl3945_is_ready(priv)) {
  5847. IWL_DEBUG_MAC80211("leave - not ready\n");
  5848. ret = -EIO;
  5849. goto out;
  5850. }
  5851. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5852. test_bit(STATUS_SCANNING, &priv->status))) {
  5853. IWL_DEBUG_MAC80211("leave - scanning\n");
  5854. set_bit(STATUS_CONF_PENDING, &priv->status);
  5855. mutex_unlock(&priv->mutex);
  5856. return 0;
  5857. }
  5858. spin_lock_irqsave(&priv->lock, flags);
  5859. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5860. conf->channel->hw_value);
  5861. if (!is_channel_valid(ch_info)) {
  5862. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5863. conf->channel->hw_value, conf->channel->band);
  5864. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5865. spin_unlock_irqrestore(&priv->lock, flags);
  5866. ret = -EINVAL;
  5867. goto out;
  5868. }
  5869. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5870. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5871. /* The list of supported rates and rate mask can be different
  5872. * for each phymode; since the phymode may have changed, reset
  5873. * the rate mask to what mac80211 lists */
  5874. iwl3945_set_rate(priv);
  5875. spin_unlock_irqrestore(&priv->lock, flags);
  5876. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5877. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5878. iwl3945_hw_channel_switch(priv, conf->channel);
  5879. goto out;
  5880. }
  5881. #endif
  5882. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5883. if (!conf->radio_enabled) {
  5884. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5885. goto out;
  5886. }
  5887. if (iwl3945_is_rfkill(priv)) {
  5888. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5889. ret = -EIO;
  5890. goto out;
  5891. }
  5892. iwl3945_set_rate(priv);
  5893. if (memcmp(&priv->active_rxon,
  5894. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5895. iwl3945_commit_rxon(priv);
  5896. else
  5897. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5898. IWL_DEBUG_MAC80211("leave\n");
  5899. out:
  5900. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5901. mutex_unlock(&priv->mutex);
  5902. return ret;
  5903. }
  5904. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5905. {
  5906. int rc = 0;
  5907. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5908. return;
  5909. /* The following should be done only at AP bring up */
  5910. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5911. /* RXON - unassoc (to set timing command) */
  5912. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5913. iwl3945_commit_rxon(priv);
  5914. /* RXON Timing */
  5915. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5916. iwl3945_setup_rxon_timing(priv);
  5917. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5918. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5919. if (rc)
  5920. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5921. "Attempting to continue.\n");
  5922. /* FIXME: what should be the assoc_id for AP? */
  5923. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5924. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5925. priv->staging_rxon.flags |=
  5926. RXON_FLG_SHORT_PREAMBLE_MSK;
  5927. else
  5928. priv->staging_rxon.flags &=
  5929. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5930. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5931. if (priv->assoc_capability &
  5932. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5933. priv->staging_rxon.flags |=
  5934. RXON_FLG_SHORT_SLOT_MSK;
  5935. else
  5936. priv->staging_rxon.flags &=
  5937. ~RXON_FLG_SHORT_SLOT_MSK;
  5938. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5939. priv->staging_rxon.flags &=
  5940. ~RXON_FLG_SHORT_SLOT_MSK;
  5941. }
  5942. /* restore RXON assoc */
  5943. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5944. iwl3945_commit_rxon(priv);
  5945. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5946. }
  5947. iwl3945_send_beacon_cmd(priv);
  5948. /* FIXME - we need to add code here to detect a totally new
  5949. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5950. * clear sta table, add BCAST sta... */
  5951. }
  5952. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5953. struct ieee80211_vif *vif,
  5954. struct ieee80211_if_conf *conf)
  5955. {
  5956. struct iwl3945_priv *priv = hw->priv;
  5957. DECLARE_MAC_BUF(mac);
  5958. unsigned long flags;
  5959. int rc;
  5960. if (conf == NULL)
  5961. return -EIO;
  5962. /* XXX: this MUST use conf->mac_addr */
  5963. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5964. (!conf->beacon || !conf->ssid_len)) {
  5965. IWL_DEBUG_MAC80211
  5966. ("Leaving in AP mode because HostAPD is not ready.\n");
  5967. return 0;
  5968. }
  5969. if (!iwl3945_is_alive(priv))
  5970. return -EAGAIN;
  5971. mutex_lock(&priv->mutex);
  5972. if (conf->bssid)
  5973. IWL_DEBUG_MAC80211("bssid: %s\n",
  5974. print_mac(mac, conf->bssid));
  5975. /*
  5976. * very dubious code was here; the probe filtering flag is never set:
  5977. *
  5978. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5979. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5980. */
  5981. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  5982. IWL_DEBUG_MAC80211("leave - scanning\n");
  5983. mutex_unlock(&priv->mutex);
  5984. return 0;
  5985. }
  5986. if (priv->vif != vif) {
  5987. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5988. mutex_unlock(&priv->mutex);
  5989. return 0;
  5990. }
  5991. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5992. if (!conf->bssid) {
  5993. conf->bssid = priv->mac_addr;
  5994. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5995. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5996. print_mac(mac, conf->bssid));
  5997. }
  5998. if (priv->ibss_beacon)
  5999. dev_kfree_skb(priv->ibss_beacon);
  6000. priv->ibss_beacon = conf->beacon;
  6001. }
  6002. if (iwl3945_is_rfkill(priv))
  6003. goto done;
  6004. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  6005. !is_multicast_ether_addr(conf->bssid)) {
  6006. /* If there is currently a HW scan going on in the background
  6007. * then we need to cancel it else the RXON below will fail. */
  6008. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  6009. IWL_WARNING("Aborted scan still in progress "
  6010. "after 100ms\n");
  6011. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  6012. mutex_unlock(&priv->mutex);
  6013. return -EAGAIN;
  6014. }
  6015. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  6016. /* TODO: Audit driver for usage of these members and see
  6017. * if mac80211 deprecates them (priv->bssid looks like it
  6018. * shouldn't be there, but I haven't scanned the IBSS code
  6019. * to verify) - jpk */
  6020. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  6021. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6022. iwl3945_config_ap(priv);
  6023. else {
  6024. rc = iwl3945_commit_rxon(priv);
  6025. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  6026. iwl3945_add_station(priv,
  6027. priv->active_rxon.bssid_addr, 1, 0);
  6028. }
  6029. } else {
  6030. iwl3945_scan_cancel_timeout(priv, 100);
  6031. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6032. iwl3945_commit_rxon(priv);
  6033. }
  6034. done:
  6035. spin_lock_irqsave(&priv->lock, flags);
  6036. if (!conf->ssid_len)
  6037. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6038. else
  6039. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  6040. priv->essid_len = conf->ssid_len;
  6041. spin_unlock_irqrestore(&priv->lock, flags);
  6042. IWL_DEBUG_MAC80211("leave\n");
  6043. mutex_unlock(&priv->mutex);
  6044. return 0;
  6045. }
  6046. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  6047. unsigned int changed_flags,
  6048. unsigned int *total_flags,
  6049. int mc_count, struct dev_addr_list *mc_list)
  6050. {
  6051. /*
  6052. * XXX: dummy
  6053. * see also iwl3945_connection_init_rx_config
  6054. */
  6055. *total_flags = 0;
  6056. }
  6057. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  6058. struct ieee80211_if_init_conf *conf)
  6059. {
  6060. struct iwl3945_priv *priv = hw->priv;
  6061. IWL_DEBUG_MAC80211("enter\n");
  6062. mutex_lock(&priv->mutex);
  6063. if (iwl3945_is_ready_rf(priv)) {
  6064. iwl3945_scan_cancel_timeout(priv, 100);
  6065. cancel_delayed_work(&priv->post_associate);
  6066. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6067. iwl3945_commit_rxon(priv);
  6068. }
  6069. if (priv->vif == conf->vif) {
  6070. priv->vif = NULL;
  6071. memset(priv->bssid, 0, ETH_ALEN);
  6072. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6073. priv->essid_len = 0;
  6074. }
  6075. mutex_unlock(&priv->mutex);
  6076. IWL_DEBUG_MAC80211("leave\n");
  6077. }
  6078. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  6079. {
  6080. int rc = 0;
  6081. unsigned long flags;
  6082. struct iwl3945_priv *priv = hw->priv;
  6083. IWL_DEBUG_MAC80211("enter\n");
  6084. mutex_lock(&priv->mutex);
  6085. spin_lock_irqsave(&priv->lock, flags);
  6086. if (!iwl3945_is_ready_rf(priv)) {
  6087. rc = -EIO;
  6088. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  6089. goto out_unlock;
  6090. }
  6091. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  6092. rc = -EIO;
  6093. IWL_ERROR("ERROR: APs don't scan\n");
  6094. goto out_unlock;
  6095. }
  6096. /* we don't schedule scan within next_scan_jiffies period */
  6097. if (priv->next_scan_jiffies &&
  6098. time_after(priv->next_scan_jiffies, jiffies)) {
  6099. rc = -EAGAIN;
  6100. goto out_unlock;
  6101. }
  6102. /* if we just finished scan ask for delay */
  6103. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  6104. IWL_DELAY_NEXT_SCAN, jiffies)) {
  6105. rc = -EAGAIN;
  6106. goto out_unlock;
  6107. }
  6108. if (len) {
  6109. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  6110. iwl3945_escape_essid(ssid, len), (int)len);
  6111. priv->one_direct_scan = 1;
  6112. priv->direct_ssid_len = (u8)
  6113. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  6114. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  6115. } else
  6116. priv->one_direct_scan = 0;
  6117. rc = iwl3945_scan_initiate(priv);
  6118. IWL_DEBUG_MAC80211("leave\n");
  6119. out_unlock:
  6120. spin_unlock_irqrestore(&priv->lock, flags);
  6121. mutex_unlock(&priv->mutex);
  6122. return rc;
  6123. }
  6124. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  6125. const u8 *local_addr, const u8 *addr,
  6126. struct ieee80211_key_conf *key)
  6127. {
  6128. struct iwl3945_priv *priv = hw->priv;
  6129. int rc = 0;
  6130. u8 sta_id;
  6131. IWL_DEBUG_MAC80211("enter\n");
  6132. if (!iwl3945_param_hwcrypto) {
  6133. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  6134. return -EOPNOTSUPP;
  6135. }
  6136. if (is_zero_ether_addr(addr))
  6137. /* only support pairwise keys */
  6138. return -EOPNOTSUPP;
  6139. sta_id = iwl3945_hw_find_station(priv, addr);
  6140. if (sta_id == IWL_INVALID_STATION) {
  6141. DECLARE_MAC_BUF(mac);
  6142. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6143. print_mac(mac, addr));
  6144. return -EINVAL;
  6145. }
  6146. mutex_lock(&priv->mutex);
  6147. iwl3945_scan_cancel_timeout(priv, 100);
  6148. switch (cmd) {
  6149. case SET_KEY:
  6150. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  6151. if (!rc) {
  6152. iwl3945_set_rxon_hwcrypto(priv, 1);
  6153. iwl3945_commit_rxon(priv);
  6154. key->hw_key_idx = sta_id;
  6155. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6156. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6157. }
  6158. break;
  6159. case DISABLE_KEY:
  6160. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  6161. if (!rc) {
  6162. iwl3945_set_rxon_hwcrypto(priv, 0);
  6163. iwl3945_commit_rxon(priv);
  6164. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6165. }
  6166. break;
  6167. default:
  6168. rc = -EINVAL;
  6169. }
  6170. IWL_DEBUG_MAC80211("leave\n");
  6171. mutex_unlock(&priv->mutex);
  6172. return rc;
  6173. }
  6174. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6175. const struct ieee80211_tx_queue_params *params)
  6176. {
  6177. struct iwl3945_priv *priv = hw->priv;
  6178. #ifdef CONFIG_IWL3945_QOS
  6179. unsigned long flags;
  6180. int q;
  6181. #endif /* CONFIG_IWL3945_QOS */
  6182. IWL_DEBUG_MAC80211("enter\n");
  6183. if (!iwl3945_is_ready_rf(priv)) {
  6184. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6185. return -EIO;
  6186. }
  6187. if (queue >= AC_NUM) {
  6188. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6189. return 0;
  6190. }
  6191. #ifdef CONFIG_IWL3945_QOS
  6192. if (!priv->qos_data.qos_enable) {
  6193. priv->qos_data.qos_active = 0;
  6194. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6195. return 0;
  6196. }
  6197. q = AC_NUM - 1 - queue;
  6198. spin_lock_irqsave(&priv->lock, flags);
  6199. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6200. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6201. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6202. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6203. cpu_to_le16((params->burst_time * 100));
  6204. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6205. priv->qos_data.qos_active = 1;
  6206. spin_unlock_irqrestore(&priv->lock, flags);
  6207. mutex_lock(&priv->mutex);
  6208. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6209. iwl3945_activate_qos(priv, 1);
  6210. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6211. iwl3945_activate_qos(priv, 0);
  6212. mutex_unlock(&priv->mutex);
  6213. #endif /*CONFIG_IWL3945_QOS */
  6214. IWL_DEBUG_MAC80211("leave\n");
  6215. return 0;
  6216. }
  6217. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6218. struct ieee80211_tx_queue_stats *stats)
  6219. {
  6220. struct iwl3945_priv *priv = hw->priv;
  6221. int i, avail;
  6222. struct iwl3945_tx_queue *txq;
  6223. struct iwl3945_queue *q;
  6224. unsigned long flags;
  6225. IWL_DEBUG_MAC80211("enter\n");
  6226. if (!iwl3945_is_ready_rf(priv)) {
  6227. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6228. return -EIO;
  6229. }
  6230. spin_lock_irqsave(&priv->lock, flags);
  6231. for (i = 0; i < AC_NUM; i++) {
  6232. txq = &priv->txq[i];
  6233. q = &txq->q;
  6234. avail = iwl3945_queue_space(q);
  6235. stats->data[i].len = q->n_window - avail;
  6236. stats->data[i].limit = q->n_window - q->high_mark;
  6237. stats->data[i].count = q->n_window;
  6238. }
  6239. spin_unlock_irqrestore(&priv->lock, flags);
  6240. IWL_DEBUG_MAC80211("leave\n");
  6241. return 0;
  6242. }
  6243. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6244. struct ieee80211_low_level_stats *stats)
  6245. {
  6246. IWL_DEBUG_MAC80211("enter\n");
  6247. IWL_DEBUG_MAC80211("leave\n");
  6248. return 0;
  6249. }
  6250. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6251. {
  6252. IWL_DEBUG_MAC80211("enter\n");
  6253. IWL_DEBUG_MAC80211("leave\n");
  6254. return 0;
  6255. }
  6256. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6257. {
  6258. struct iwl3945_priv *priv = hw->priv;
  6259. unsigned long flags;
  6260. mutex_lock(&priv->mutex);
  6261. IWL_DEBUG_MAC80211("enter\n");
  6262. #ifdef CONFIG_IWL3945_QOS
  6263. iwl3945_reset_qos(priv);
  6264. #endif
  6265. cancel_delayed_work(&priv->post_associate);
  6266. spin_lock_irqsave(&priv->lock, flags);
  6267. priv->assoc_id = 0;
  6268. priv->assoc_capability = 0;
  6269. priv->call_post_assoc_from_beacon = 0;
  6270. /* new association get rid of ibss beacon skb */
  6271. if (priv->ibss_beacon)
  6272. dev_kfree_skb(priv->ibss_beacon);
  6273. priv->ibss_beacon = NULL;
  6274. priv->beacon_int = priv->hw->conf.beacon_int;
  6275. priv->timestamp1 = 0;
  6276. priv->timestamp0 = 0;
  6277. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6278. priv->beacon_int = 0;
  6279. spin_unlock_irqrestore(&priv->lock, flags);
  6280. if (!iwl3945_is_ready_rf(priv)) {
  6281. IWL_DEBUG_MAC80211("leave - not ready\n");
  6282. mutex_unlock(&priv->mutex);
  6283. return;
  6284. }
  6285. /* we are restarting association process
  6286. * clear RXON_FILTER_ASSOC_MSK bit
  6287. */
  6288. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6289. iwl3945_scan_cancel_timeout(priv, 100);
  6290. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6291. iwl3945_commit_rxon(priv);
  6292. }
  6293. /* Per mac80211.h: This is only used in IBSS mode... */
  6294. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6295. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6296. mutex_unlock(&priv->mutex);
  6297. return;
  6298. }
  6299. priv->only_active_channel = 0;
  6300. iwl3945_set_rate(priv);
  6301. mutex_unlock(&priv->mutex);
  6302. IWL_DEBUG_MAC80211("leave\n");
  6303. }
  6304. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6305. struct ieee80211_tx_control *control)
  6306. {
  6307. struct iwl3945_priv *priv = hw->priv;
  6308. unsigned long flags;
  6309. mutex_lock(&priv->mutex);
  6310. IWL_DEBUG_MAC80211("enter\n");
  6311. if (!iwl3945_is_ready_rf(priv)) {
  6312. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6313. mutex_unlock(&priv->mutex);
  6314. return -EIO;
  6315. }
  6316. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6317. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6318. mutex_unlock(&priv->mutex);
  6319. return -EIO;
  6320. }
  6321. spin_lock_irqsave(&priv->lock, flags);
  6322. if (priv->ibss_beacon)
  6323. dev_kfree_skb(priv->ibss_beacon);
  6324. priv->ibss_beacon = skb;
  6325. priv->assoc_id = 0;
  6326. IWL_DEBUG_MAC80211("leave\n");
  6327. spin_unlock_irqrestore(&priv->lock, flags);
  6328. #ifdef CONFIG_IWL3945_QOS
  6329. iwl3945_reset_qos(priv);
  6330. #endif
  6331. queue_work(priv->workqueue, &priv->post_associate.work);
  6332. mutex_unlock(&priv->mutex);
  6333. return 0;
  6334. }
  6335. /*****************************************************************************
  6336. *
  6337. * sysfs attributes
  6338. *
  6339. *****************************************************************************/
  6340. #ifdef CONFIG_IWL3945_DEBUG
  6341. /*
  6342. * The following adds a new attribute to the sysfs representation
  6343. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6344. * used for controlling the debug level.
  6345. *
  6346. * See the level definitions in iwl for details.
  6347. */
  6348. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6349. {
  6350. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6351. }
  6352. static ssize_t store_debug_level(struct device_driver *d,
  6353. const char *buf, size_t count)
  6354. {
  6355. char *p = (char *)buf;
  6356. u32 val;
  6357. val = simple_strtoul(p, &p, 0);
  6358. if (p == buf)
  6359. printk(KERN_INFO DRV_NAME
  6360. ": %s is not in hex or decimal form.\n", buf);
  6361. else
  6362. iwl3945_debug_level = val;
  6363. return strnlen(buf, count);
  6364. }
  6365. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6366. show_debug_level, store_debug_level);
  6367. #endif /* CONFIG_IWL3945_DEBUG */
  6368. static ssize_t show_rf_kill(struct device *d,
  6369. struct device_attribute *attr, char *buf)
  6370. {
  6371. /*
  6372. * 0 - RF kill not enabled
  6373. * 1 - SW based RF kill active (sysfs)
  6374. * 2 - HW based RF kill active
  6375. * 3 - Both HW and SW based RF kill active
  6376. */
  6377. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6378. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6379. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6380. return sprintf(buf, "%i\n", val);
  6381. }
  6382. static ssize_t store_rf_kill(struct device *d,
  6383. struct device_attribute *attr,
  6384. const char *buf, size_t count)
  6385. {
  6386. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6387. mutex_lock(&priv->mutex);
  6388. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6389. mutex_unlock(&priv->mutex);
  6390. return count;
  6391. }
  6392. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6393. static ssize_t show_temperature(struct device *d,
  6394. struct device_attribute *attr, char *buf)
  6395. {
  6396. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6397. if (!iwl3945_is_alive(priv))
  6398. return -EAGAIN;
  6399. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6400. }
  6401. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6402. static ssize_t show_rs_window(struct device *d,
  6403. struct device_attribute *attr,
  6404. char *buf)
  6405. {
  6406. struct iwl3945_priv *priv = d->driver_data;
  6407. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6408. }
  6409. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6410. static ssize_t show_tx_power(struct device *d,
  6411. struct device_attribute *attr, char *buf)
  6412. {
  6413. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6414. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6415. }
  6416. static ssize_t store_tx_power(struct device *d,
  6417. struct device_attribute *attr,
  6418. const char *buf, size_t count)
  6419. {
  6420. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6421. char *p = (char *)buf;
  6422. u32 val;
  6423. val = simple_strtoul(p, &p, 10);
  6424. if (p == buf)
  6425. printk(KERN_INFO DRV_NAME
  6426. ": %s is not in decimal form.\n", buf);
  6427. else
  6428. iwl3945_hw_reg_set_txpower(priv, val);
  6429. return count;
  6430. }
  6431. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6432. static ssize_t show_flags(struct device *d,
  6433. struct device_attribute *attr, char *buf)
  6434. {
  6435. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6436. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6437. }
  6438. static ssize_t store_flags(struct device *d,
  6439. struct device_attribute *attr,
  6440. const char *buf, size_t count)
  6441. {
  6442. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6443. u32 flags = simple_strtoul(buf, NULL, 0);
  6444. mutex_lock(&priv->mutex);
  6445. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6446. /* Cancel any currently running scans... */
  6447. if (iwl3945_scan_cancel_timeout(priv, 100))
  6448. IWL_WARNING("Could not cancel scan.\n");
  6449. else {
  6450. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6451. flags);
  6452. priv->staging_rxon.flags = cpu_to_le32(flags);
  6453. iwl3945_commit_rxon(priv);
  6454. }
  6455. }
  6456. mutex_unlock(&priv->mutex);
  6457. return count;
  6458. }
  6459. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6460. static ssize_t show_filter_flags(struct device *d,
  6461. struct device_attribute *attr, char *buf)
  6462. {
  6463. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6464. return sprintf(buf, "0x%04X\n",
  6465. le32_to_cpu(priv->active_rxon.filter_flags));
  6466. }
  6467. static ssize_t store_filter_flags(struct device *d,
  6468. struct device_attribute *attr,
  6469. const char *buf, size_t count)
  6470. {
  6471. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6472. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6473. mutex_lock(&priv->mutex);
  6474. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6475. /* Cancel any currently running scans... */
  6476. if (iwl3945_scan_cancel_timeout(priv, 100))
  6477. IWL_WARNING("Could not cancel scan.\n");
  6478. else {
  6479. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6480. "0x%04X\n", filter_flags);
  6481. priv->staging_rxon.filter_flags =
  6482. cpu_to_le32(filter_flags);
  6483. iwl3945_commit_rxon(priv);
  6484. }
  6485. }
  6486. mutex_unlock(&priv->mutex);
  6487. return count;
  6488. }
  6489. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6490. store_filter_flags);
  6491. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6492. static ssize_t show_measurement(struct device *d,
  6493. struct device_attribute *attr, char *buf)
  6494. {
  6495. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6496. struct iwl3945_spectrum_notification measure_report;
  6497. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6498. u8 *data = (u8 *) & measure_report;
  6499. unsigned long flags;
  6500. spin_lock_irqsave(&priv->lock, flags);
  6501. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6502. spin_unlock_irqrestore(&priv->lock, flags);
  6503. return 0;
  6504. }
  6505. memcpy(&measure_report, &priv->measure_report, size);
  6506. priv->measurement_status = 0;
  6507. spin_unlock_irqrestore(&priv->lock, flags);
  6508. while (size && (PAGE_SIZE - len)) {
  6509. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6510. PAGE_SIZE - len, 1);
  6511. len = strlen(buf);
  6512. if (PAGE_SIZE - len)
  6513. buf[len++] = '\n';
  6514. ofs += 16;
  6515. size -= min(size, 16U);
  6516. }
  6517. return len;
  6518. }
  6519. static ssize_t store_measurement(struct device *d,
  6520. struct device_attribute *attr,
  6521. const char *buf, size_t count)
  6522. {
  6523. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6524. struct ieee80211_measurement_params params = {
  6525. .channel = le16_to_cpu(priv->active_rxon.channel),
  6526. .start_time = cpu_to_le64(priv->last_tsf),
  6527. .duration = cpu_to_le16(1),
  6528. };
  6529. u8 type = IWL_MEASURE_BASIC;
  6530. u8 buffer[32];
  6531. u8 channel;
  6532. if (count) {
  6533. char *p = buffer;
  6534. strncpy(buffer, buf, min(sizeof(buffer), count));
  6535. channel = simple_strtoul(p, NULL, 0);
  6536. if (channel)
  6537. params.channel = channel;
  6538. p = buffer;
  6539. while (*p && *p != ' ')
  6540. p++;
  6541. if (*p)
  6542. type = simple_strtoul(p + 1, NULL, 0);
  6543. }
  6544. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6545. "channel %d (for '%s')\n", type, params.channel, buf);
  6546. iwl3945_get_measurement(priv, &params, type);
  6547. return count;
  6548. }
  6549. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6550. show_measurement, store_measurement);
  6551. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6552. static ssize_t show_rate(struct device *d,
  6553. struct device_attribute *attr, char *buf)
  6554. {
  6555. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6556. unsigned long flags;
  6557. int i;
  6558. spin_lock_irqsave(&priv->sta_lock, flags);
  6559. if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
  6560. i = priv->stations[IWL_AP_ID].current_rate.s.rate;
  6561. else
  6562. i = priv->stations[IWL_STA_ID].current_rate.s.rate;
  6563. spin_unlock_irqrestore(&priv->sta_lock, flags);
  6564. i = iwl3945_rate_index_from_plcp(i);
  6565. if (i == -1)
  6566. return sprintf(buf, "0\n");
  6567. return sprintf(buf, "%d%s\n",
  6568. (iwl3945_rates[i].ieee >> 1),
  6569. (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
  6570. }
  6571. static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
  6572. static ssize_t store_retry_rate(struct device *d,
  6573. struct device_attribute *attr,
  6574. const char *buf, size_t count)
  6575. {
  6576. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6577. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6578. if (priv->retry_rate <= 0)
  6579. priv->retry_rate = 1;
  6580. return count;
  6581. }
  6582. static ssize_t show_retry_rate(struct device *d,
  6583. struct device_attribute *attr, char *buf)
  6584. {
  6585. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6586. return sprintf(buf, "%d", priv->retry_rate);
  6587. }
  6588. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6589. store_retry_rate);
  6590. static ssize_t store_power_level(struct device *d,
  6591. struct device_attribute *attr,
  6592. const char *buf, size_t count)
  6593. {
  6594. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6595. int rc;
  6596. int mode;
  6597. mode = simple_strtoul(buf, NULL, 0);
  6598. mutex_lock(&priv->mutex);
  6599. if (!iwl3945_is_ready(priv)) {
  6600. rc = -EAGAIN;
  6601. goto out;
  6602. }
  6603. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6604. mode = IWL_POWER_AC;
  6605. else
  6606. mode |= IWL_POWER_ENABLED;
  6607. if (mode != priv->power_mode) {
  6608. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6609. if (rc) {
  6610. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6611. goto out;
  6612. }
  6613. priv->power_mode = mode;
  6614. }
  6615. rc = count;
  6616. out:
  6617. mutex_unlock(&priv->mutex);
  6618. return rc;
  6619. }
  6620. #define MAX_WX_STRING 80
  6621. /* Values are in microsecond */
  6622. static const s32 timeout_duration[] = {
  6623. 350000,
  6624. 250000,
  6625. 75000,
  6626. 37000,
  6627. 25000,
  6628. };
  6629. static const s32 period_duration[] = {
  6630. 400000,
  6631. 700000,
  6632. 1000000,
  6633. 1000000,
  6634. 1000000
  6635. };
  6636. static ssize_t show_power_level(struct device *d,
  6637. struct device_attribute *attr, char *buf)
  6638. {
  6639. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6640. int level = IWL_POWER_LEVEL(priv->power_mode);
  6641. char *p = buf;
  6642. p += sprintf(p, "%d ", level);
  6643. switch (level) {
  6644. case IWL_POWER_MODE_CAM:
  6645. case IWL_POWER_AC:
  6646. p += sprintf(p, "(AC)");
  6647. break;
  6648. case IWL_POWER_BATTERY:
  6649. p += sprintf(p, "(BATTERY)");
  6650. break;
  6651. default:
  6652. p += sprintf(p,
  6653. "(Timeout %dms, Period %dms)",
  6654. timeout_duration[level - 1] / 1000,
  6655. period_duration[level - 1] / 1000);
  6656. }
  6657. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6658. p += sprintf(p, " OFF\n");
  6659. else
  6660. p += sprintf(p, " \n");
  6661. return (p - buf + 1);
  6662. }
  6663. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6664. store_power_level);
  6665. static ssize_t show_channels(struct device *d,
  6666. struct device_attribute *attr, char *buf)
  6667. {
  6668. /* all this shit doesn't belong into sysfs anyway */
  6669. return 0;
  6670. }
  6671. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6672. static ssize_t show_statistics(struct device *d,
  6673. struct device_attribute *attr, char *buf)
  6674. {
  6675. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6676. u32 size = sizeof(struct iwl3945_notif_statistics);
  6677. u32 len = 0, ofs = 0;
  6678. u8 *data = (u8 *) & priv->statistics;
  6679. int rc = 0;
  6680. if (!iwl3945_is_alive(priv))
  6681. return -EAGAIN;
  6682. mutex_lock(&priv->mutex);
  6683. rc = iwl3945_send_statistics_request(priv);
  6684. mutex_unlock(&priv->mutex);
  6685. if (rc) {
  6686. len = sprintf(buf,
  6687. "Error sending statistics request: 0x%08X\n", rc);
  6688. return len;
  6689. }
  6690. while (size && (PAGE_SIZE - len)) {
  6691. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6692. PAGE_SIZE - len, 1);
  6693. len = strlen(buf);
  6694. if (PAGE_SIZE - len)
  6695. buf[len++] = '\n';
  6696. ofs += 16;
  6697. size -= min(size, 16U);
  6698. }
  6699. return len;
  6700. }
  6701. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6702. static ssize_t show_antenna(struct device *d,
  6703. struct device_attribute *attr, char *buf)
  6704. {
  6705. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6706. if (!iwl3945_is_alive(priv))
  6707. return -EAGAIN;
  6708. return sprintf(buf, "%d\n", priv->antenna);
  6709. }
  6710. static ssize_t store_antenna(struct device *d,
  6711. struct device_attribute *attr,
  6712. const char *buf, size_t count)
  6713. {
  6714. int ant;
  6715. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6716. if (count == 0)
  6717. return 0;
  6718. if (sscanf(buf, "%1i", &ant) != 1) {
  6719. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6720. return count;
  6721. }
  6722. if ((ant >= 0) && (ant <= 2)) {
  6723. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6724. priv->antenna = (enum iwl3945_antenna)ant;
  6725. } else
  6726. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6727. return count;
  6728. }
  6729. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6730. static ssize_t show_status(struct device *d,
  6731. struct device_attribute *attr, char *buf)
  6732. {
  6733. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6734. if (!iwl3945_is_alive(priv))
  6735. return -EAGAIN;
  6736. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6737. }
  6738. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6739. static ssize_t dump_error_log(struct device *d,
  6740. struct device_attribute *attr,
  6741. const char *buf, size_t count)
  6742. {
  6743. char *p = (char *)buf;
  6744. if (p[0] == '1')
  6745. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6746. return strnlen(buf, count);
  6747. }
  6748. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6749. static ssize_t dump_event_log(struct device *d,
  6750. struct device_attribute *attr,
  6751. const char *buf, size_t count)
  6752. {
  6753. char *p = (char *)buf;
  6754. if (p[0] == '1')
  6755. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6756. return strnlen(buf, count);
  6757. }
  6758. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6759. /*****************************************************************************
  6760. *
  6761. * driver setup and teardown
  6762. *
  6763. *****************************************************************************/
  6764. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6765. {
  6766. priv->workqueue = create_workqueue(DRV_NAME);
  6767. init_waitqueue_head(&priv->wait_command_queue);
  6768. INIT_WORK(&priv->up, iwl3945_bg_up);
  6769. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6770. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6771. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6772. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6773. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6774. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6775. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6776. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6777. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6778. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6779. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6780. iwl3945_hw_setup_deferred_work(priv);
  6781. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6782. iwl3945_irq_tasklet, (unsigned long)priv);
  6783. }
  6784. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6785. {
  6786. iwl3945_hw_cancel_deferred_work(priv);
  6787. cancel_delayed_work_sync(&priv->init_alive_start);
  6788. cancel_delayed_work(&priv->scan_check);
  6789. cancel_delayed_work(&priv->alive_start);
  6790. cancel_delayed_work(&priv->post_associate);
  6791. cancel_work_sync(&priv->beacon_update);
  6792. }
  6793. static struct attribute *iwl3945_sysfs_entries[] = {
  6794. &dev_attr_antenna.attr,
  6795. &dev_attr_channels.attr,
  6796. &dev_attr_dump_errors.attr,
  6797. &dev_attr_dump_events.attr,
  6798. &dev_attr_flags.attr,
  6799. &dev_attr_filter_flags.attr,
  6800. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6801. &dev_attr_measurement.attr,
  6802. #endif
  6803. &dev_attr_power_level.attr,
  6804. &dev_attr_rate.attr,
  6805. &dev_attr_retry_rate.attr,
  6806. &dev_attr_rf_kill.attr,
  6807. &dev_attr_rs_window.attr,
  6808. &dev_attr_statistics.attr,
  6809. &dev_attr_status.attr,
  6810. &dev_attr_temperature.attr,
  6811. &dev_attr_tx_power.attr,
  6812. NULL
  6813. };
  6814. static struct attribute_group iwl3945_attribute_group = {
  6815. .name = NULL, /* put in device directory */
  6816. .attrs = iwl3945_sysfs_entries,
  6817. };
  6818. static struct ieee80211_ops iwl3945_hw_ops = {
  6819. .tx = iwl3945_mac_tx,
  6820. .start = iwl3945_mac_start,
  6821. .stop = iwl3945_mac_stop,
  6822. .add_interface = iwl3945_mac_add_interface,
  6823. .remove_interface = iwl3945_mac_remove_interface,
  6824. .config = iwl3945_mac_config,
  6825. .config_interface = iwl3945_mac_config_interface,
  6826. .configure_filter = iwl3945_configure_filter,
  6827. .set_key = iwl3945_mac_set_key,
  6828. .get_stats = iwl3945_mac_get_stats,
  6829. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6830. .conf_tx = iwl3945_mac_conf_tx,
  6831. .get_tsf = iwl3945_mac_get_tsf,
  6832. .reset_tsf = iwl3945_mac_reset_tsf,
  6833. .beacon_update = iwl3945_mac_beacon_update,
  6834. .hw_scan = iwl3945_mac_hw_scan
  6835. };
  6836. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6837. {
  6838. int err = 0;
  6839. u32 pci_id;
  6840. struct iwl3945_priv *priv;
  6841. struct ieee80211_hw *hw;
  6842. int i;
  6843. DECLARE_MAC_BUF(mac);
  6844. /* Disabling hardware scan means that mac80211 will perform scans
  6845. * "the hard way", rather than using device's scan. */
  6846. if (iwl3945_param_disable_hw_scan) {
  6847. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6848. iwl3945_hw_ops.hw_scan = NULL;
  6849. }
  6850. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  6851. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6852. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6853. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  6854. err = -EINVAL;
  6855. goto out;
  6856. }
  6857. /* mac80211 allocates memory for this device instance, including
  6858. * space for this driver's private structure */
  6859. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6860. if (hw == NULL) {
  6861. IWL_ERROR("Can not allocate network device\n");
  6862. err = -ENOMEM;
  6863. goto out;
  6864. }
  6865. SET_IEEE80211_DEV(hw, &pdev->dev);
  6866. hw->rate_control_algorithm = "iwl-3945-rs";
  6867. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6868. priv = hw->priv;
  6869. priv->hw = hw;
  6870. priv->pci_dev = pdev;
  6871. /* Select antenna (may be helpful if only one antenna is connected) */
  6872. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6873. #ifdef CONFIG_IWL3945_DEBUG
  6874. iwl3945_debug_level = iwl3945_param_debug;
  6875. atomic_set(&priv->restrict_refcnt, 0);
  6876. #endif
  6877. priv->retry_rate = 1;
  6878. priv->ibss_beacon = NULL;
  6879. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6880. * the range of signal quality values that we'll provide.
  6881. * Negative values for level/noise indicate that we'll provide dBm.
  6882. * For WE, at least, non-0 values here *enable* display of values
  6883. * in app (iwconfig). */
  6884. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6885. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6886. hw->max_signal = 100; /* link quality indication (%) */
  6887. /* Tell mac80211 our Tx characteristics */
  6888. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6889. /* 4 EDCA QOS priorities */
  6890. hw->queues = 4;
  6891. spin_lock_init(&priv->lock);
  6892. spin_lock_init(&priv->power_data.lock);
  6893. spin_lock_init(&priv->sta_lock);
  6894. spin_lock_init(&priv->hcmd_lock);
  6895. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6896. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6897. INIT_LIST_HEAD(&priv->free_frames);
  6898. mutex_init(&priv->mutex);
  6899. if (pci_enable_device(pdev)) {
  6900. err = -ENODEV;
  6901. goto out_ieee80211_free_hw;
  6902. }
  6903. pci_set_master(pdev);
  6904. /* Clear the driver's (not device's) station table */
  6905. iwl3945_clear_stations_table(priv);
  6906. priv->data_retry_limit = -1;
  6907. priv->ieee_channels = NULL;
  6908. priv->ieee_rates = NULL;
  6909. priv->band = IEEE80211_BAND_2GHZ;
  6910. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6911. if (!err)
  6912. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6913. if (err) {
  6914. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6915. goto out_pci_disable_device;
  6916. }
  6917. pci_set_drvdata(pdev, priv);
  6918. err = pci_request_regions(pdev, DRV_NAME);
  6919. if (err)
  6920. goto out_pci_disable_device;
  6921. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6922. * PCI Tx retries from interfering with C3 CPU state */
  6923. pci_write_config_byte(pdev, 0x41, 0x00);
  6924. priv->hw_base = pci_iomap(pdev, 0, 0);
  6925. if (!priv->hw_base) {
  6926. err = -ENODEV;
  6927. goto out_pci_release_regions;
  6928. }
  6929. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6930. (unsigned long long) pci_resource_len(pdev, 0));
  6931. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6932. /* Initialize module parameter values here */
  6933. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6934. if (iwl3945_param_disable) {
  6935. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6936. IWL_DEBUG_INFO("Radio disabled.\n");
  6937. }
  6938. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6939. pci_id =
  6940. (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
  6941. switch (pci_id) {
  6942. case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
  6943. case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
  6944. case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
  6945. case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
  6946. priv->is_abg = 0;
  6947. break;
  6948. /*
  6949. * Rest are assumed ABG SKU -- if this is not the
  6950. * case then the card will get the wrong 'Detected'
  6951. * line in the kernel log however the code that
  6952. * initializes the GEO table will detect no A-band
  6953. * channels and remove the is_abg mask.
  6954. */
  6955. default:
  6956. priv->is_abg = 1;
  6957. break;
  6958. }
  6959. printk(KERN_INFO DRV_NAME
  6960. ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
  6961. priv->is_abg ? "A" : "");
  6962. /* Device-specific setup */
  6963. if (iwl3945_hw_set_hw_setting(priv)) {
  6964. IWL_ERROR("failed to set hw settings\n");
  6965. goto out_iounmap;
  6966. }
  6967. #ifdef CONFIG_IWL3945_QOS
  6968. if (iwl3945_param_qos_enable)
  6969. priv->qos_data.qos_enable = 1;
  6970. iwl3945_reset_qos(priv);
  6971. priv->qos_data.qos_active = 0;
  6972. priv->qos_data.qos_cap.val = 0;
  6973. #endif /* CONFIG_IWL3945_QOS */
  6974. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6975. iwl3945_setup_deferred_work(priv);
  6976. iwl3945_setup_rx_handlers(priv);
  6977. priv->rates_mask = IWL_RATES_MASK;
  6978. /* If power management is turned on, default to AC mode */
  6979. priv->power_mode = IWL_POWER_AC;
  6980. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6981. iwl3945_disable_interrupts(priv);
  6982. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6983. if (err) {
  6984. IWL_ERROR("failed to create sysfs device attributes\n");
  6985. goto out_release_irq;
  6986. }
  6987. /* nic init */
  6988. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6989. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6990. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6991. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6992. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6993. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6994. if (err < 0) {
  6995. IWL_DEBUG_INFO("Failed to init the card\n");
  6996. goto out_remove_sysfs;
  6997. }
  6998. /* Read the EEPROM */
  6999. err = iwl3945_eeprom_init(priv);
  7000. if (err) {
  7001. IWL_ERROR("Unable to init EEPROM\n");
  7002. goto out_remove_sysfs;
  7003. }
  7004. /* MAC Address location in EEPROM same for 3945/4965 */
  7005. get_eeprom_mac(priv, priv->mac_addr);
  7006. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  7007. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  7008. err = iwl3945_init_channel_map(priv);
  7009. if (err) {
  7010. IWL_ERROR("initializing regulatory failed: %d\n", err);
  7011. goto out_remove_sysfs;
  7012. }
  7013. err = iwl3945_init_geos(priv);
  7014. if (err) {
  7015. IWL_ERROR("initializing geos failed: %d\n", err);
  7016. goto out_free_channel_map;
  7017. }
  7018. iwl3945_rate_control_register(priv->hw);
  7019. err = ieee80211_register_hw(priv->hw);
  7020. if (err) {
  7021. IWL_ERROR("Failed to register network device (error %d)\n", err);
  7022. goto out_free_geos;
  7023. }
  7024. priv->hw->conf.beacon_int = 100;
  7025. priv->mac80211_registered = 1;
  7026. pci_save_state(pdev);
  7027. pci_disable_device(pdev);
  7028. return 0;
  7029. out_free_geos:
  7030. iwl3945_free_geos(priv);
  7031. out_free_channel_map:
  7032. iwl3945_free_channel_map(priv);
  7033. out_remove_sysfs:
  7034. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7035. out_release_irq:
  7036. destroy_workqueue(priv->workqueue);
  7037. priv->workqueue = NULL;
  7038. iwl3945_unset_hw_setting(priv);
  7039. out_iounmap:
  7040. pci_iounmap(pdev, priv->hw_base);
  7041. out_pci_release_regions:
  7042. pci_release_regions(pdev);
  7043. out_pci_disable_device:
  7044. pci_disable_device(pdev);
  7045. pci_set_drvdata(pdev, NULL);
  7046. out_ieee80211_free_hw:
  7047. ieee80211_free_hw(priv->hw);
  7048. out:
  7049. return err;
  7050. }
  7051. static void iwl3945_pci_remove(struct pci_dev *pdev)
  7052. {
  7053. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7054. struct list_head *p, *q;
  7055. int i;
  7056. if (!priv)
  7057. return;
  7058. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  7059. set_bit(STATUS_EXIT_PENDING, &priv->status);
  7060. iwl3945_down(priv);
  7061. /* Free MAC hash list for ADHOC */
  7062. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  7063. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  7064. list_del(p);
  7065. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  7066. }
  7067. }
  7068. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7069. iwl3945_dealloc_ucode_pci(priv);
  7070. if (priv->rxq.bd)
  7071. iwl3945_rx_queue_free(priv, &priv->rxq);
  7072. iwl3945_hw_txq_ctx_free(priv);
  7073. iwl3945_unset_hw_setting(priv);
  7074. iwl3945_clear_stations_table(priv);
  7075. if (priv->mac80211_registered) {
  7076. ieee80211_unregister_hw(priv->hw);
  7077. iwl3945_rate_control_unregister(priv->hw);
  7078. }
  7079. /*netif_stop_queue(dev); */
  7080. flush_workqueue(priv->workqueue);
  7081. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  7082. * priv->workqueue... so we can't take down the workqueue
  7083. * until now... */
  7084. destroy_workqueue(priv->workqueue);
  7085. priv->workqueue = NULL;
  7086. pci_iounmap(pdev, priv->hw_base);
  7087. pci_release_regions(pdev);
  7088. pci_disable_device(pdev);
  7089. pci_set_drvdata(pdev, NULL);
  7090. iwl3945_free_channel_map(priv);
  7091. iwl3945_free_geos(priv);
  7092. if (priv->ibss_beacon)
  7093. dev_kfree_skb(priv->ibss_beacon);
  7094. ieee80211_free_hw(priv->hw);
  7095. }
  7096. #ifdef CONFIG_PM
  7097. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  7098. {
  7099. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7100. if (priv->is_open) {
  7101. set_bit(STATUS_IN_SUSPEND, &priv->status);
  7102. iwl3945_mac_stop(priv->hw);
  7103. priv->is_open = 1;
  7104. }
  7105. pci_set_power_state(pdev, PCI_D3hot);
  7106. return 0;
  7107. }
  7108. static int iwl3945_pci_resume(struct pci_dev *pdev)
  7109. {
  7110. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7111. pci_set_power_state(pdev, PCI_D0);
  7112. if (priv->is_open)
  7113. iwl3945_mac_start(priv->hw);
  7114. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  7115. return 0;
  7116. }
  7117. #endif /* CONFIG_PM */
  7118. /*****************************************************************************
  7119. *
  7120. * driver and module entry point
  7121. *
  7122. *****************************************************************************/
  7123. static struct pci_driver iwl3945_driver = {
  7124. .name = DRV_NAME,
  7125. .id_table = iwl3945_hw_card_ids,
  7126. .probe = iwl3945_pci_probe,
  7127. .remove = __devexit_p(iwl3945_pci_remove),
  7128. #ifdef CONFIG_PM
  7129. .suspend = iwl3945_pci_suspend,
  7130. .resume = iwl3945_pci_resume,
  7131. #endif
  7132. };
  7133. static int __init iwl3945_init(void)
  7134. {
  7135. int ret;
  7136. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  7137. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  7138. ret = pci_register_driver(&iwl3945_driver);
  7139. if (ret) {
  7140. IWL_ERROR("Unable to initialize PCI module\n");
  7141. return ret;
  7142. }
  7143. #ifdef CONFIG_IWL3945_DEBUG
  7144. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7145. if (ret) {
  7146. IWL_ERROR("Unable to create driver sysfs file\n");
  7147. pci_unregister_driver(&iwl3945_driver);
  7148. return ret;
  7149. }
  7150. #endif
  7151. return ret;
  7152. }
  7153. static void __exit iwl3945_exit(void)
  7154. {
  7155. #ifdef CONFIG_IWL3945_DEBUG
  7156. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7157. #endif
  7158. pci_unregister_driver(&iwl3945_driver);
  7159. }
  7160. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  7161. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  7162. module_param_named(disable, iwl3945_param_disable, int, 0444);
  7163. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  7164. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  7165. MODULE_PARM_DESC(hwcrypto,
  7166. "using hardware crypto engine (default 0 [software])\n");
  7167. module_param_named(debug, iwl3945_param_debug, int, 0444);
  7168. MODULE_PARM_DESC(debug, "debug output mask");
  7169. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  7170. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7171. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  7172. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7173. /* QoS */
  7174. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  7175. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7176. module_exit(iwl3945_exit);
  7177. module_init(iwl3945_init);