swim3.c 29 KB

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  1. /*
  2. * Driver for the SWIM3 (Super Woz Integrated Machine 3)
  3. * floppy controller found on Power Macintoshes.
  4. *
  5. * Copyright (C) 1996 Paul Mackerras.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. /*
  13. * TODO:
  14. * handle 2 drives
  15. * handle GCR disks
  16. */
  17. #include <linux/stddef.h>
  18. #include <linux/kernel.h>
  19. #include <linux/sched.h>
  20. #include <linux/timer.h>
  21. #include <linux/delay.h>
  22. #include <linux/fd.h>
  23. #include <linux/ioctl.h>
  24. #include <linux/blkdev.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/spinlock.h>
  28. #include <asm/io.h>
  29. #include <asm/dbdma.h>
  30. #include <asm/prom.h>
  31. #include <asm/uaccess.h>
  32. #include <asm/mediabay.h>
  33. #include <asm/machdep.h>
  34. #include <asm/pmac_feature.h>
  35. static struct request_queue *swim3_queue;
  36. static struct gendisk *disks[2];
  37. static struct request *fd_req;
  38. #define MAX_FLOPPIES 2
  39. enum swim_state {
  40. idle,
  41. locating,
  42. seeking,
  43. settling,
  44. do_transfer,
  45. jogging,
  46. available,
  47. revalidating,
  48. ejecting
  49. };
  50. #define REG(x) unsigned char x; char x ## _pad[15];
  51. /*
  52. * The names for these registers mostly represent speculation on my part.
  53. * It will be interesting to see how close they are to the names Apple uses.
  54. */
  55. struct swim3 {
  56. REG(data);
  57. REG(timer); /* counts down at 1MHz */
  58. REG(error);
  59. REG(mode);
  60. REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */
  61. REG(setup);
  62. REG(control); /* writing bits clears them */
  63. REG(status); /* writing bits sets them in control */
  64. REG(intr);
  65. REG(nseek); /* # tracks to seek */
  66. REG(ctrack); /* current track number */
  67. REG(csect); /* current sector number */
  68. REG(gap3); /* size of gap 3 in track format */
  69. REG(sector); /* sector # to read or write */
  70. REG(nsect); /* # sectors to read or write */
  71. REG(intr_enable);
  72. };
  73. #define control_bic control
  74. #define control_bis status
  75. /* Bits in select register */
  76. #define CA_MASK 7
  77. #define LSTRB 8
  78. /* Bits in control register */
  79. #define DO_SEEK 0x80
  80. #define FORMAT 0x40
  81. #define SELECT 0x20
  82. #define WRITE_SECTORS 0x10
  83. #define DO_ACTION 0x08
  84. #define DRIVE2_ENABLE 0x04
  85. #define DRIVE_ENABLE 0x02
  86. #define INTR_ENABLE 0x01
  87. /* Bits in status register */
  88. #define FIFO_1BYTE 0x80
  89. #define FIFO_2BYTE 0x40
  90. #define ERROR 0x20
  91. #define DATA 0x08
  92. #define RDDATA 0x04
  93. #define INTR_PENDING 0x02
  94. #define MARK_BYTE 0x01
  95. /* Bits in intr and intr_enable registers */
  96. #define ERROR_INTR 0x20
  97. #define DATA_CHANGED 0x10
  98. #define TRANSFER_DONE 0x08
  99. #define SEEN_SECTOR 0x04
  100. #define SEEK_DONE 0x02
  101. #define TIMER_DONE 0x01
  102. /* Bits in error register */
  103. #define ERR_DATA_CRC 0x80
  104. #define ERR_ADDR_CRC 0x40
  105. #define ERR_OVERRUN 0x04
  106. #define ERR_UNDERRUN 0x01
  107. /* Bits in setup register */
  108. #define S_SW_RESET 0x80
  109. #define S_GCR_WRITE 0x40
  110. #define S_IBM_DRIVE 0x20
  111. #define S_TEST_MODE 0x10
  112. #define S_FCLK_DIV2 0x08
  113. #define S_GCR 0x04
  114. #define S_COPY_PROT 0x02
  115. #define S_INV_WDATA 0x01
  116. /* Select values for swim3_action */
  117. #define SEEK_POSITIVE 0
  118. #define SEEK_NEGATIVE 4
  119. #define STEP 1
  120. #define MOTOR_ON 2
  121. #define MOTOR_OFF 6
  122. #define INDEX 3
  123. #define EJECT 7
  124. #define SETMFM 9
  125. #define SETGCR 13
  126. /* Select values for swim3_select and swim3_readbit */
  127. #define STEP_DIR 0
  128. #define STEPPING 1
  129. #define MOTOR_ON 2
  130. #define RELAX 3 /* also eject in progress */
  131. #define READ_DATA_0 4
  132. #define TWOMEG_DRIVE 5
  133. #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */
  134. #define DRIVE_PRESENT 7
  135. #define DISK_IN 8
  136. #define WRITE_PROT 9
  137. #define TRACK_ZERO 10
  138. #define TACHO 11
  139. #define READ_DATA_1 12
  140. #define MFM_MODE 13
  141. #define SEEK_COMPLETE 14
  142. #define ONEMEG_MEDIA 15
  143. /* Definitions of values used in writing and formatting */
  144. #define DATA_ESCAPE 0x99
  145. #define GCR_SYNC_EXC 0x3f
  146. #define GCR_SYNC_CONV 0x80
  147. #define GCR_FIRST_MARK 0xd5
  148. #define GCR_SECOND_MARK 0xaa
  149. #define GCR_ADDR_MARK "\xd5\xaa\x00"
  150. #define GCR_DATA_MARK "\xd5\xaa\x0b"
  151. #define GCR_SLIP_BYTE "\x27\xaa"
  152. #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f"
  153. #define DATA_99 "\x99\x99"
  154. #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe"
  155. #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc"
  156. #define MFM_GAP_LEN 12
  157. struct floppy_state {
  158. enum swim_state state;
  159. spinlock_t lock;
  160. struct swim3 __iomem *swim3; /* hardware registers */
  161. struct dbdma_regs __iomem *dma; /* DMA controller registers */
  162. int swim3_intr; /* interrupt number for SWIM3 */
  163. int dma_intr; /* interrupt number for DMA channel */
  164. int cur_cyl; /* cylinder head is on, or -1 */
  165. int cur_sector; /* last sector we saw go past */
  166. int req_cyl; /* the cylinder for the current r/w request */
  167. int head; /* head number ditto */
  168. int req_sector; /* sector number ditto */
  169. int scount; /* # sectors we're transferring at present */
  170. int retries;
  171. int settle_time;
  172. int secpercyl; /* disk geometry information */
  173. int secpertrack;
  174. int total_secs;
  175. int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */
  176. struct dbdma_cmd *dma_cmd;
  177. int ref_count;
  178. int expect_cyl;
  179. struct timer_list timeout;
  180. int timeout_pending;
  181. int ejected;
  182. wait_queue_head_t wait;
  183. int wanted;
  184. struct device_node* media_bay; /* NULL when not in bay */
  185. char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)];
  186. };
  187. static struct floppy_state floppy_states[MAX_FLOPPIES];
  188. static int floppy_count = 0;
  189. static DEFINE_SPINLOCK(swim3_lock);
  190. static unsigned short write_preamble[] = {
  191. 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */
  192. 0, 0, 0, 0, 0, 0, /* sync field */
  193. 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */
  194. 0x990f /* no escape for 512 bytes */
  195. };
  196. static unsigned short write_postamble[] = {
  197. 0x9904, /* insert CRC */
  198. 0x4e4e, 0x4e4e,
  199. 0x9908, /* stop writing */
  200. 0, 0, 0, 0, 0, 0
  201. };
  202. static void swim3_select(struct floppy_state *fs, int sel);
  203. static void swim3_action(struct floppy_state *fs, int action);
  204. static int swim3_readbit(struct floppy_state *fs, int bit);
  205. static void do_fd_request(struct request_queue * q);
  206. static void start_request(struct floppy_state *fs);
  207. static void set_timeout(struct floppy_state *fs, int nticks,
  208. void (*proc)(unsigned long));
  209. static void scan_track(struct floppy_state *fs);
  210. static void seek_track(struct floppy_state *fs, int n);
  211. static void init_dma(struct dbdma_cmd *cp, int cmd, void *buf, int count);
  212. static void setup_transfer(struct floppy_state *fs);
  213. static void act(struct floppy_state *fs);
  214. static void scan_timeout(unsigned long data);
  215. static void seek_timeout(unsigned long data);
  216. static void settle_timeout(unsigned long data);
  217. static void xfer_timeout(unsigned long data);
  218. static irqreturn_t swim3_interrupt(int irq, void *dev_id);
  219. /*static void fd_dma_interrupt(int irq, void *dev_id);*/
  220. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  221. int interruptible);
  222. static void release_drive(struct floppy_state *fs);
  223. static int fd_eject(struct floppy_state *fs);
  224. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  225. unsigned int cmd, unsigned long param);
  226. static int floppy_open(struct block_device *bdev, fmode_t mode);
  227. static int floppy_release(struct gendisk *disk, fmode_t mode);
  228. static int floppy_check_change(struct gendisk *disk);
  229. static int floppy_revalidate(struct gendisk *disk);
  230. static void swim3_select(struct floppy_state *fs, int sel)
  231. {
  232. struct swim3 __iomem *sw = fs->swim3;
  233. out_8(&sw->select, RELAX);
  234. if (sel & 8)
  235. out_8(&sw->control_bis, SELECT);
  236. else
  237. out_8(&sw->control_bic, SELECT);
  238. out_8(&sw->select, sel & CA_MASK);
  239. }
  240. static void swim3_action(struct floppy_state *fs, int action)
  241. {
  242. struct swim3 __iomem *sw = fs->swim3;
  243. swim3_select(fs, action);
  244. udelay(1);
  245. out_8(&sw->select, sw->select | LSTRB);
  246. udelay(2);
  247. out_8(&sw->select, sw->select & ~LSTRB);
  248. udelay(1);
  249. }
  250. static int swim3_readbit(struct floppy_state *fs, int bit)
  251. {
  252. struct swim3 __iomem *sw = fs->swim3;
  253. int stat;
  254. swim3_select(fs, bit);
  255. udelay(1);
  256. stat = in_8(&sw->status);
  257. return (stat & DATA) == 0;
  258. }
  259. static void do_fd_request(struct request_queue * q)
  260. {
  261. int i;
  262. for(i=0;i<floppy_count;i++)
  263. {
  264. #ifdef CONFIG_PMAC_MEDIABAY
  265. if (floppy_states[i].media_bay &&
  266. check_media_bay(floppy_states[i].media_bay, MB_FD))
  267. continue;
  268. #endif /* CONFIG_PMAC_MEDIABAY */
  269. start_request(&floppy_states[i]);
  270. }
  271. }
  272. static void start_request(struct floppy_state *fs)
  273. {
  274. struct request *req;
  275. unsigned long x;
  276. if (fs->state == idle && fs->wanted) {
  277. fs->state = available;
  278. wake_up(&fs->wait);
  279. return;
  280. }
  281. while (fs->state == idle && (req = elv_next_request(swim3_queue))) {
  282. #if 0
  283. printk("do_fd_req: dev=%s cmd=%d sec=%ld nr_sec=%u buf=%p\n",
  284. req->rq_disk->disk_name, req->cmd,
  285. (long)blk_rq_pos(req), blk_rq_sectors(req), req->buffer);
  286. printk(" errors=%d current_nr_sectors=%u\n",
  287. req->errors, blk_rq_cur_sectors(req));
  288. #endif
  289. if (blk_rq_pos(req) >= fs->total_secs) {
  290. __blk_end_request_cur(req, -EIO);
  291. continue;
  292. }
  293. if (fs->ejected) {
  294. __blk_end_request_cur(req, -EIO);
  295. continue;
  296. }
  297. if (rq_data_dir(req) == WRITE) {
  298. if (fs->write_prot < 0)
  299. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  300. if (fs->write_prot) {
  301. __blk_end_request_cur(req, -EIO);
  302. continue;
  303. }
  304. }
  305. /* Do not remove the cast. blk_rq_pos(req) is now a
  306. * sector_t and can be 64 bits, but it will never go
  307. * past 32 bits for this driver anyway, so we can
  308. * safely cast it down and not have to do a 64/32
  309. * division
  310. */
  311. fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl;
  312. x = ((long)blk_rq_pos(req)) % fs->secpercyl;
  313. fs->head = x / fs->secpertrack;
  314. fs->req_sector = x % fs->secpertrack + 1;
  315. fd_req = req;
  316. fs->state = do_transfer;
  317. fs->retries = 0;
  318. act(fs);
  319. }
  320. }
  321. static void set_timeout(struct floppy_state *fs, int nticks,
  322. void (*proc)(unsigned long))
  323. {
  324. unsigned long flags;
  325. spin_lock_irqsave(&fs->lock, flags);
  326. if (fs->timeout_pending)
  327. del_timer(&fs->timeout);
  328. fs->timeout.expires = jiffies + nticks;
  329. fs->timeout.function = proc;
  330. fs->timeout.data = (unsigned long) fs;
  331. add_timer(&fs->timeout);
  332. fs->timeout_pending = 1;
  333. spin_unlock_irqrestore(&fs->lock, flags);
  334. }
  335. static inline void scan_track(struct floppy_state *fs)
  336. {
  337. struct swim3 __iomem *sw = fs->swim3;
  338. swim3_select(fs, READ_DATA_0);
  339. in_8(&sw->intr); /* clear SEEN_SECTOR bit */
  340. in_8(&sw->error);
  341. out_8(&sw->intr_enable, SEEN_SECTOR);
  342. out_8(&sw->control_bis, DO_ACTION);
  343. /* enable intr when track found */
  344. set_timeout(fs, HZ, scan_timeout); /* enable timeout */
  345. }
  346. static inline void seek_track(struct floppy_state *fs, int n)
  347. {
  348. struct swim3 __iomem *sw = fs->swim3;
  349. if (n >= 0) {
  350. swim3_action(fs, SEEK_POSITIVE);
  351. sw->nseek = n;
  352. } else {
  353. swim3_action(fs, SEEK_NEGATIVE);
  354. sw->nseek = -n;
  355. }
  356. fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1;
  357. swim3_select(fs, STEP);
  358. in_8(&sw->error);
  359. /* enable intr when seek finished */
  360. out_8(&sw->intr_enable, SEEK_DONE);
  361. out_8(&sw->control_bis, DO_SEEK);
  362. set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */
  363. fs->settle_time = 0;
  364. }
  365. static inline void init_dma(struct dbdma_cmd *cp, int cmd,
  366. void *buf, int count)
  367. {
  368. st_le16(&cp->req_count, count);
  369. st_le16(&cp->command, cmd);
  370. st_le32(&cp->phy_addr, virt_to_bus(buf));
  371. cp->xfer_status = 0;
  372. }
  373. static inline void setup_transfer(struct floppy_state *fs)
  374. {
  375. int n;
  376. struct swim3 __iomem *sw = fs->swim3;
  377. struct dbdma_cmd *cp = fs->dma_cmd;
  378. struct dbdma_regs __iomem *dr = fs->dma;
  379. if (blk_rq_cur_sectors(fd_req) <= 0) {
  380. printk(KERN_ERR "swim3: transfer 0 sectors?\n");
  381. return;
  382. }
  383. if (rq_data_dir(fd_req) == WRITE)
  384. n = 1;
  385. else {
  386. n = fs->secpertrack - fs->req_sector + 1;
  387. if (n > blk_rq_cur_sectors(fd_req))
  388. n = blk_rq_cur_sectors(fd_req);
  389. }
  390. fs->scount = n;
  391. swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0);
  392. out_8(&sw->sector, fs->req_sector);
  393. out_8(&sw->nsect, n);
  394. out_8(&sw->gap3, 0);
  395. out_le32(&dr->cmdptr, virt_to_bus(cp));
  396. if (rq_data_dir(fd_req) == WRITE) {
  397. /* Set up 3 dma commands: write preamble, data, postamble */
  398. init_dma(cp, OUTPUT_MORE, write_preamble, sizeof(write_preamble));
  399. ++cp;
  400. init_dma(cp, OUTPUT_MORE, fd_req->buffer, 512);
  401. ++cp;
  402. init_dma(cp, OUTPUT_LAST, write_postamble, sizeof(write_postamble));
  403. } else {
  404. init_dma(cp, INPUT_LAST, fd_req->buffer, n * 512);
  405. }
  406. ++cp;
  407. out_le16(&cp->command, DBDMA_STOP);
  408. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  409. in_8(&sw->error);
  410. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  411. if (rq_data_dir(fd_req) == WRITE)
  412. out_8(&sw->control_bis, WRITE_SECTORS);
  413. in_8(&sw->intr);
  414. out_le32(&dr->control, (RUN << 16) | RUN);
  415. /* enable intr when transfer complete */
  416. out_8(&sw->intr_enable, TRANSFER_DONE);
  417. out_8(&sw->control_bis, DO_ACTION);
  418. set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */
  419. }
  420. static void act(struct floppy_state *fs)
  421. {
  422. for (;;) {
  423. switch (fs->state) {
  424. case idle:
  425. return; /* XXX shouldn't get here */
  426. case locating:
  427. if (swim3_readbit(fs, TRACK_ZERO)) {
  428. fs->cur_cyl = 0;
  429. if (fs->req_cyl == 0)
  430. fs->state = do_transfer;
  431. else
  432. fs->state = seeking;
  433. break;
  434. }
  435. scan_track(fs);
  436. return;
  437. case seeking:
  438. if (fs->cur_cyl < 0) {
  439. fs->expect_cyl = -1;
  440. fs->state = locating;
  441. break;
  442. }
  443. if (fs->req_cyl == fs->cur_cyl) {
  444. printk("whoops, seeking 0\n");
  445. fs->state = do_transfer;
  446. break;
  447. }
  448. seek_track(fs, fs->req_cyl - fs->cur_cyl);
  449. return;
  450. case settling:
  451. /* check for SEEK_COMPLETE after 30ms */
  452. fs->settle_time = (HZ + 32) / 33;
  453. set_timeout(fs, fs->settle_time, settle_timeout);
  454. return;
  455. case do_transfer:
  456. if (fs->cur_cyl != fs->req_cyl) {
  457. if (fs->retries > 5) {
  458. __blk_end_request_cur(fd_req, -EIO);
  459. fs->state = idle;
  460. return;
  461. }
  462. fs->state = seeking;
  463. break;
  464. }
  465. setup_transfer(fs);
  466. return;
  467. case jogging:
  468. seek_track(fs, -5);
  469. return;
  470. default:
  471. printk(KERN_ERR"swim3: unknown state %d\n", fs->state);
  472. return;
  473. }
  474. }
  475. }
  476. static void scan_timeout(unsigned long data)
  477. {
  478. struct floppy_state *fs = (struct floppy_state *) data;
  479. struct swim3 __iomem *sw = fs->swim3;
  480. fs->timeout_pending = 0;
  481. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  482. out_8(&sw->select, RELAX);
  483. out_8(&sw->intr_enable, 0);
  484. fs->cur_cyl = -1;
  485. if (fs->retries > 5) {
  486. __blk_end_request_cur(fd_req, -EIO);
  487. fs->state = idle;
  488. start_request(fs);
  489. } else {
  490. fs->state = jogging;
  491. act(fs);
  492. }
  493. }
  494. static void seek_timeout(unsigned long data)
  495. {
  496. struct floppy_state *fs = (struct floppy_state *) data;
  497. struct swim3 __iomem *sw = fs->swim3;
  498. fs->timeout_pending = 0;
  499. out_8(&sw->control_bic, DO_SEEK);
  500. out_8(&sw->select, RELAX);
  501. out_8(&sw->intr_enable, 0);
  502. printk(KERN_ERR "swim3: seek timeout\n");
  503. __blk_end_request_cur(fd_req, -EIO);
  504. fs->state = idle;
  505. start_request(fs);
  506. }
  507. static void settle_timeout(unsigned long data)
  508. {
  509. struct floppy_state *fs = (struct floppy_state *) data;
  510. struct swim3 __iomem *sw = fs->swim3;
  511. fs->timeout_pending = 0;
  512. if (swim3_readbit(fs, SEEK_COMPLETE)) {
  513. out_8(&sw->select, RELAX);
  514. fs->state = locating;
  515. act(fs);
  516. return;
  517. }
  518. out_8(&sw->select, RELAX);
  519. if (fs->settle_time < 2*HZ) {
  520. ++fs->settle_time;
  521. set_timeout(fs, 1, settle_timeout);
  522. return;
  523. }
  524. printk(KERN_ERR "swim3: seek settle timeout\n");
  525. __blk_end_request_cur(fd_req, -EIO);
  526. fs->state = idle;
  527. start_request(fs);
  528. }
  529. static void xfer_timeout(unsigned long data)
  530. {
  531. struct floppy_state *fs = (struct floppy_state *) data;
  532. struct swim3 __iomem *sw = fs->swim3;
  533. struct dbdma_regs __iomem *dr = fs->dma;
  534. int n;
  535. fs->timeout_pending = 0;
  536. out_le32(&dr->control, RUN << 16);
  537. /* We must wait a bit for dbdma to stop */
  538. for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++)
  539. udelay(1);
  540. out_8(&sw->intr_enable, 0);
  541. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  542. out_8(&sw->select, RELAX);
  543. printk(KERN_ERR "swim3: timeout %sing sector %ld\n",
  544. (rq_data_dir(fd_req)==WRITE? "writ": "read"),
  545. (long)blk_rq_pos(fd_req));
  546. __blk_end_request_cur(fd_req, -EIO);
  547. fs->state = idle;
  548. start_request(fs);
  549. }
  550. static irqreturn_t swim3_interrupt(int irq, void *dev_id)
  551. {
  552. struct floppy_state *fs = (struct floppy_state *) dev_id;
  553. struct swim3 __iomem *sw = fs->swim3;
  554. int intr, err, n;
  555. int stat, resid;
  556. struct dbdma_regs __iomem *dr;
  557. struct dbdma_cmd *cp;
  558. intr = in_8(&sw->intr);
  559. err = (intr & ERROR_INTR)? in_8(&sw->error): 0;
  560. if ((intr & ERROR_INTR) && fs->state != do_transfer)
  561. printk(KERN_ERR "swim3_interrupt, state=%d, dir=%x, intr=%x, err=%x\n",
  562. fs->state, rq_data_dir(fd_req), intr, err);
  563. switch (fs->state) {
  564. case locating:
  565. if (intr & SEEN_SECTOR) {
  566. out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS);
  567. out_8(&sw->select, RELAX);
  568. out_8(&sw->intr_enable, 0);
  569. del_timer(&fs->timeout);
  570. fs->timeout_pending = 0;
  571. if (sw->ctrack == 0xff) {
  572. printk(KERN_ERR "swim3: seen sector but cyl=ff?\n");
  573. fs->cur_cyl = -1;
  574. if (fs->retries > 5) {
  575. __blk_end_request_cur(fd_req, -EIO);
  576. fs->state = idle;
  577. start_request(fs);
  578. } else {
  579. fs->state = jogging;
  580. act(fs);
  581. }
  582. break;
  583. }
  584. fs->cur_cyl = sw->ctrack;
  585. fs->cur_sector = sw->csect;
  586. if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl)
  587. printk(KERN_ERR "swim3: expected cyl %d, got %d\n",
  588. fs->expect_cyl, fs->cur_cyl);
  589. fs->state = do_transfer;
  590. act(fs);
  591. }
  592. break;
  593. case seeking:
  594. case jogging:
  595. if (sw->nseek == 0) {
  596. out_8(&sw->control_bic, DO_SEEK);
  597. out_8(&sw->select, RELAX);
  598. out_8(&sw->intr_enable, 0);
  599. del_timer(&fs->timeout);
  600. fs->timeout_pending = 0;
  601. if (fs->state == seeking)
  602. ++fs->retries;
  603. fs->state = settling;
  604. act(fs);
  605. }
  606. break;
  607. case settling:
  608. out_8(&sw->intr_enable, 0);
  609. del_timer(&fs->timeout);
  610. fs->timeout_pending = 0;
  611. act(fs);
  612. break;
  613. case do_transfer:
  614. if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0)
  615. break;
  616. out_8(&sw->intr_enable, 0);
  617. out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION);
  618. out_8(&sw->select, RELAX);
  619. del_timer(&fs->timeout);
  620. fs->timeout_pending = 0;
  621. dr = fs->dma;
  622. cp = fs->dma_cmd;
  623. if (rq_data_dir(fd_req) == WRITE)
  624. ++cp;
  625. /*
  626. * Check that the main data transfer has finished.
  627. * On writing, the swim3 sometimes doesn't use
  628. * up all the bytes of the postamble, so we can still
  629. * see DMA active here. That doesn't matter as long
  630. * as all the sector data has been transferred.
  631. */
  632. if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) {
  633. /* wait a little while for DMA to complete */
  634. for (n = 0; n < 100; ++n) {
  635. if (cp->xfer_status != 0)
  636. break;
  637. udelay(1);
  638. barrier();
  639. }
  640. }
  641. /* turn off DMA */
  642. out_le32(&dr->control, (RUN | PAUSE) << 16);
  643. stat = ld_le16(&cp->xfer_status);
  644. resid = ld_le16(&cp->res_count);
  645. if (intr & ERROR_INTR) {
  646. n = fs->scount - 1 - resid / 512;
  647. if (n > 0) {
  648. blk_update_request(fd_req, 0, n << 9);
  649. fs->req_sector += n;
  650. }
  651. if (fs->retries < 5) {
  652. ++fs->retries;
  653. act(fs);
  654. } else {
  655. printk("swim3: error %sing block %ld (err=%x)\n",
  656. rq_data_dir(fd_req) == WRITE? "writ": "read",
  657. (long)blk_rq_pos(fd_req), err);
  658. __blk_end_request_cur(fd_req, -EIO);
  659. fs->state = idle;
  660. }
  661. } else {
  662. if ((stat & ACTIVE) == 0 || resid != 0) {
  663. /* musta been an error */
  664. printk(KERN_ERR "swim3: fd dma: stat=%x resid=%d\n", stat, resid);
  665. printk(KERN_ERR " state=%d, dir=%x, intr=%x, err=%x\n",
  666. fs->state, rq_data_dir(fd_req), intr, err);
  667. __blk_end_request_cur(fd_req, -EIO);
  668. fs->state = idle;
  669. start_request(fs);
  670. break;
  671. }
  672. if (__blk_end_request(fd_req, 0, fs->scount << 9)) {
  673. fs->req_sector += fs->scount;
  674. if (fs->req_sector > fs->secpertrack) {
  675. fs->req_sector -= fs->secpertrack;
  676. if (++fs->head > 1) {
  677. fs->head = 0;
  678. ++fs->req_cyl;
  679. }
  680. }
  681. act(fs);
  682. } else
  683. fs->state = idle;
  684. }
  685. if (fs->state == idle)
  686. start_request(fs);
  687. break;
  688. default:
  689. printk(KERN_ERR "swim3: don't know what to do in state %d\n", fs->state);
  690. }
  691. return IRQ_HANDLED;
  692. }
  693. /*
  694. static void fd_dma_interrupt(int irq, void *dev_id)
  695. {
  696. }
  697. */
  698. static int grab_drive(struct floppy_state *fs, enum swim_state state,
  699. int interruptible)
  700. {
  701. unsigned long flags;
  702. spin_lock_irqsave(&fs->lock, flags);
  703. if (fs->state != idle) {
  704. ++fs->wanted;
  705. while (fs->state != available) {
  706. if (interruptible && signal_pending(current)) {
  707. --fs->wanted;
  708. spin_unlock_irqrestore(&fs->lock, flags);
  709. return -EINTR;
  710. }
  711. interruptible_sleep_on(&fs->wait);
  712. }
  713. --fs->wanted;
  714. }
  715. fs->state = state;
  716. spin_unlock_irqrestore(&fs->lock, flags);
  717. return 0;
  718. }
  719. static void release_drive(struct floppy_state *fs)
  720. {
  721. unsigned long flags;
  722. spin_lock_irqsave(&fs->lock, flags);
  723. fs->state = idle;
  724. start_request(fs);
  725. spin_unlock_irqrestore(&fs->lock, flags);
  726. }
  727. static int fd_eject(struct floppy_state *fs)
  728. {
  729. int err, n;
  730. err = grab_drive(fs, ejecting, 1);
  731. if (err)
  732. return err;
  733. swim3_action(fs, EJECT);
  734. for (n = 20; n > 0; --n) {
  735. if (signal_pending(current)) {
  736. err = -EINTR;
  737. break;
  738. }
  739. swim3_select(fs, RELAX);
  740. schedule_timeout_interruptible(1);
  741. if (swim3_readbit(fs, DISK_IN) == 0)
  742. break;
  743. }
  744. swim3_select(fs, RELAX);
  745. udelay(150);
  746. fs->ejected = 1;
  747. release_drive(fs);
  748. return err;
  749. }
  750. static struct floppy_struct floppy_type =
  751. { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */
  752. static int floppy_ioctl(struct block_device *bdev, fmode_t mode,
  753. unsigned int cmd, unsigned long param)
  754. {
  755. struct floppy_state *fs = bdev->bd_disk->private_data;
  756. int err;
  757. if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN))
  758. return -EPERM;
  759. #ifdef CONFIG_PMAC_MEDIABAY
  760. if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
  761. return -ENXIO;
  762. #endif
  763. switch (cmd) {
  764. case FDEJECT:
  765. if (fs->ref_count != 1)
  766. return -EBUSY;
  767. err = fd_eject(fs);
  768. return err;
  769. case FDGETPRM:
  770. if (copy_to_user((void __user *) param, &floppy_type,
  771. sizeof(struct floppy_struct)))
  772. return -EFAULT;
  773. return 0;
  774. }
  775. return -ENOTTY;
  776. }
  777. static int floppy_open(struct block_device *bdev, fmode_t mode)
  778. {
  779. struct floppy_state *fs = bdev->bd_disk->private_data;
  780. struct swim3 __iomem *sw = fs->swim3;
  781. int n, err = 0;
  782. if (fs->ref_count == 0) {
  783. #ifdef CONFIG_PMAC_MEDIABAY
  784. if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
  785. return -ENXIO;
  786. #endif
  787. out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2);
  788. out_8(&sw->control_bic, 0xff);
  789. out_8(&sw->mode, 0x95);
  790. udelay(10);
  791. out_8(&sw->intr_enable, 0);
  792. out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE);
  793. swim3_action(fs, MOTOR_ON);
  794. fs->write_prot = -1;
  795. fs->cur_cyl = -1;
  796. for (n = 0; n < 2 * HZ; ++n) {
  797. if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE))
  798. break;
  799. if (signal_pending(current)) {
  800. err = -EINTR;
  801. break;
  802. }
  803. swim3_select(fs, RELAX);
  804. schedule_timeout_interruptible(1);
  805. }
  806. if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0
  807. || swim3_readbit(fs, DISK_IN) == 0))
  808. err = -ENXIO;
  809. swim3_action(fs, SETMFM);
  810. swim3_select(fs, RELAX);
  811. } else if (fs->ref_count == -1 || mode & FMODE_EXCL)
  812. return -EBUSY;
  813. if (err == 0 && (mode & FMODE_NDELAY) == 0
  814. && (mode & (FMODE_READ|FMODE_WRITE))) {
  815. check_disk_change(bdev);
  816. if (fs->ejected)
  817. err = -ENXIO;
  818. }
  819. if (err == 0 && (mode & FMODE_WRITE)) {
  820. if (fs->write_prot < 0)
  821. fs->write_prot = swim3_readbit(fs, WRITE_PROT);
  822. if (fs->write_prot)
  823. err = -EROFS;
  824. }
  825. if (err) {
  826. if (fs->ref_count == 0) {
  827. swim3_action(fs, MOTOR_OFF);
  828. out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE);
  829. swim3_select(fs, RELAX);
  830. }
  831. return err;
  832. }
  833. if (mode & FMODE_EXCL)
  834. fs->ref_count = -1;
  835. else
  836. ++fs->ref_count;
  837. return 0;
  838. }
  839. static int floppy_release(struct gendisk *disk, fmode_t mode)
  840. {
  841. struct floppy_state *fs = disk->private_data;
  842. struct swim3 __iomem *sw = fs->swim3;
  843. if (fs->ref_count > 0 && --fs->ref_count == 0) {
  844. swim3_action(fs, MOTOR_OFF);
  845. out_8(&sw->control_bic, 0xff);
  846. swim3_select(fs, RELAX);
  847. }
  848. return 0;
  849. }
  850. static int floppy_check_change(struct gendisk *disk)
  851. {
  852. struct floppy_state *fs = disk->private_data;
  853. return fs->ejected;
  854. }
  855. static int floppy_revalidate(struct gendisk *disk)
  856. {
  857. struct floppy_state *fs = disk->private_data;
  858. struct swim3 __iomem *sw;
  859. int ret, n;
  860. #ifdef CONFIG_PMAC_MEDIABAY
  861. if (fs->media_bay && check_media_bay(fs->media_bay, MB_FD))
  862. return -ENXIO;
  863. #endif
  864. sw = fs->swim3;
  865. grab_drive(fs, revalidating, 0);
  866. out_8(&sw->intr_enable, 0);
  867. out_8(&sw->control_bis, DRIVE_ENABLE);
  868. swim3_action(fs, MOTOR_ON); /* necessary? */
  869. fs->write_prot = -1;
  870. fs->cur_cyl = -1;
  871. mdelay(1);
  872. for (n = HZ; n > 0; --n) {
  873. if (swim3_readbit(fs, SEEK_COMPLETE))
  874. break;
  875. if (signal_pending(current))
  876. break;
  877. swim3_select(fs, RELAX);
  878. schedule_timeout_interruptible(1);
  879. }
  880. ret = swim3_readbit(fs, SEEK_COMPLETE) == 0
  881. || swim3_readbit(fs, DISK_IN) == 0;
  882. if (ret)
  883. swim3_action(fs, MOTOR_OFF);
  884. else {
  885. fs->ejected = 0;
  886. swim3_action(fs, SETMFM);
  887. }
  888. swim3_select(fs, RELAX);
  889. release_drive(fs);
  890. return ret;
  891. }
  892. static struct block_device_operations floppy_fops = {
  893. .open = floppy_open,
  894. .release = floppy_release,
  895. .locked_ioctl = floppy_ioctl,
  896. .media_changed = floppy_check_change,
  897. .revalidate_disk= floppy_revalidate,
  898. };
  899. static int swim3_add_device(struct macio_dev *mdev, int index)
  900. {
  901. struct device_node *swim = mdev->ofdev.node;
  902. struct device_node *mediabay;
  903. struct floppy_state *fs = &floppy_states[index];
  904. int rc = -EBUSY;
  905. /* Check & Request resources */
  906. if (macio_resource_count(mdev) < 2) {
  907. printk(KERN_WARNING "ifd%d: no address for %s\n",
  908. index, swim->full_name);
  909. return -ENXIO;
  910. }
  911. if (macio_irq_count(mdev) < 2) {
  912. printk(KERN_WARNING "fd%d: no intrs for device %s\n",
  913. index, swim->full_name);
  914. }
  915. if (macio_request_resource(mdev, 0, "swim3 (mmio)")) {
  916. printk(KERN_ERR "fd%d: can't request mmio resource for %s\n",
  917. index, swim->full_name);
  918. return -EBUSY;
  919. }
  920. if (macio_request_resource(mdev, 1, "swim3 (dma)")) {
  921. printk(KERN_ERR "fd%d: can't request dma resource for %s\n",
  922. index, swim->full_name);
  923. macio_release_resource(mdev, 0);
  924. return -EBUSY;
  925. }
  926. dev_set_drvdata(&mdev->ofdev.dev, fs);
  927. mediabay = (strcasecmp(swim->parent->type, "media-bay") == 0) ?
  928. swim->parent : NULL;
  929. if (mediabay == NULL)
  930. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1);
  931. memset(fs, 0, sizeof(*fs));
  932. spin_lock_init(&fs->lock);
  933. fs->state = idle;
  934. fs->swim3 = (struct swim3 __iomem *)
  935. ioremap(macio_resource_start(mdev, 0), 0x200);
  936. if (fs->swim3 == NULL) {
  937. printk("fd%d: couldn't map registers for %s\n",
  938. index, swim->full_name);
  939. rc = -ENOMEM;
  940. goto out_release;
  941. }
  942. fs->dma = (struct dbdma_regs __iomem *)
  943. ioremap(macio_resource_start(mdev, 1), 0x200);
  944. if (fs->dma == NULL) {
  945. printk("fd%d: couldn't map DMA for %s\n",
  946. index, swim->full_name);
  947. iounmap(fs->swim3);
  948. rc = -ENOMEM;
  949. goto out_release;
  950. }
  951. fs->swim3_intr = macio_irq(mdev, 0);
  952. fs->dma_intr = macio_irq(mdev, 1);;
  953. fs->cur_cyl = -1;
  954. fs->cur_sector = -1;
  955. fs->secpercyl = 36;
  956. fs->secpertrack = 18;
  957. fs->total_secs = 2880;
  958. fs->media_bay = mediabay;
  959. init_waitqueue_head(&fs->wait);
  960. fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space);
  961. memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd));
  962. st_le16(&fs->dma_cmd[1].command, DBDMA_STOP);
  963. if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) {
  964. printk(KERN_ERR "fd%d: couldn't request irq %d for %s\n",
  965. index, fs->swim3_intr, swim->full_name);
  966. pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0);
  967. goto out_unmap;
  968. return -EBUSY;
  969. }
  970. /*
  971. if (request_irq(fs->dma_intr, fd_dma_interrupt, 0, "SWIM3-dma", fs)) {
  972. printk(KERN_ERR "Couldn't get irq %d for SWIM3 DMA",
  973. fs->dma_intr);
  974. return -EBUSY;
  975. }
  976. */
  977. init_timer(&fs->timeout);
  978. printk(KERN_INFO "fd%d: SWIM3 floppy controller %s\n", floppy_count,
  979. mediabay ? "in media bay" : "");
  980. return 0;
  981. out_unmap:
  982. iounmap(fs->dma);
  983. iounmap(fs->swim3);
  984. out_release:
  985. macio_release_resource(mdev, 0);
  986. macio_release_resource(mdev, 1);
  987. return rc;
  988. }
  989. static int __devinit swim3_attach(struct macio_dev *mdev, const struct of_device_id *match)
  990. {
  991. int i, rc;
  992. struct gendisk *disk;
  993. /* Add the drive */
  994. rc = swim3_add_device(mdev, floppy_count);
  995. if (rc)
  996. return rc;
  997. /* Now create the queue if not there yet */
  998. if (swim3_queue == NULL) {
  999. /* If we failed, there isn't much we can do as the driver is still
  1000. * too dumb to remove the device, just bail out
  1001. */
  1002. if (register_blkdev(FLOPPY_MAJOR, "fd"))
  1003. return 0;
  1004. swim3_queue = blk_init_queue(do_fd_request, &swim3_lock);
  1005. if (swim3_queue == NULL) {
  1006. unregister_blkdev(FLOPPY_MAJOR, "fd");
  1007. return 0;
  1008. }
  1009. }
  1010. /* Now register that disk. Same comment about failure handling */
  1011. i = floppy_count++;
  1012. disk = disks[i] = alloc_disk(1);
  1013. if (disk == NULL)
  1014. return 0;
  1015. disk->major = FLOPPY_MAJOR;
  1016. disk->first_minor = i;
  1017. disk->fops = &floppy_fops;
  1018. disk->private_data = &floppy_states[i];
  1019. disk->queue = swim3_queue;
  1020. disk->flags |= GENHD_FL_REMOVABLE;
  1021. sprintf(disk->disk_name, "fd%d", i);
  1022. set_capacity(disk, 2880);
  1023. add_disk(disk);
  1024. return 0;
  1025. }
  1026. static struct of_device_id swim3_match[] =
  1027. {
  1028. {
  1029. .name = "swim3",
  1030. },
  1031. {
  1032. .compatible = "ohare-swim3"
  1033. },
  1034. {
  1035. .compatible = "swim3"
  1036. },
  1037. };
  1038. static struct macio_driver swim3_driver =
  1039. {
  1040. .name = "swim3",
  1041. .match_table = swim3_match,
  1042. .probe = swim3_attach,
  1043. #if 0
  1044. .suspend = swim3_suspend,
  1045. .resume = swim3_resume,
  1046. #endif
  1047. };
  1048. int swim3_init(void)
  1049. {
  1050. macio_register_driver(&swim3_driver);
  1051. return 0;
  1052. }
  1053. module_init(swim3_init)
  1054. MODULE_LICENSE("GPL");
  1055. MODULE_AUTHOR("Paul Mackerras");
  1056. MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR);