core.c 14 KB

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  1. /**
  2. * core.c - DesignWare USB3 DRD Controller Core file
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions, and the following disclaimer,
  14. * without modification.
  15. * 2. Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * 3. The names of the above-listed copyright holders may not be used
  19. * to endorse or promote products derived from this software without
  20. * specific prior written permission.
  21. *
  22. * ALTERNATIVELY, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2, as published by the Free
  24. * Software Foundation.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. */
  38. #include <linux/module.h>
  39. #include <linux/kernel.h>
  40. #include <linux/slab.h>
  41. #include <linux/spinlock.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/pm_runtime.h>
  44. #include <linux/interrupt.h>
  45. #include <linux/ioport.h>
  46. #include <linux/io.h>
  47. #include <linux/list.h>
  48. #include <linux/delay.h>
  49. #include <linux/dma-mapping.h>
  50. #include <linux/usb/ch9.h>
  51. #include <linux/usb/gadget.h>
  52. #include <linux/module.h>
  53. #include "core.h"
  54. #include "gadget.h"
  55. #include "io.h"
  56. #include "debug.h"
  57. static char *maximum_speed = "super";
  58. module_param(maximum_speed, charp, 0);
  59. MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
  60. /* -------------------------------------------------------------------------- */
  61. #define DWC3_DEVS_POSSIBLE 32
  62. static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE);
  63. int dwc3_get_device_id(void)
  64. {
  65. int id;
  66. again:
  67. id = find_first_zero_bit(dwc3_devs, DWC3_DEVS_POSSIBLE);
  68. if (id < DWC3_DEVS_POSSIBLE) {
  69. int old;
  70. old = test_and_set_bit(id, dwc3_devs);
  71. if (old)
  72. goto again;
  73. } else {
  74. pr_err("dwc3: no space for new device\n");
  75. id = -ENOMEM;
  76. }
  77. return 0;
  78. }
  79. EXPORT_SYMBOL_GPL(dwc3_get_device_id);
  80. void dwc3_put_device_id(int id)
  81. {
  82. int ret;
  83. if (id < 0)
  84. return;
  85. ret = test_bit(id, dwc3_devs);
  86. WARN(!ret, "dwc3: ID %d not in use\n", id);
  87. clear_bit(id, dwc3_devs);
  88. }
  89. EXPORT_SYMBOL_GPL(dwc3_put_device_id);
  90. /* -------------------------------------------------------------------------- */
  91. /**
  92. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  93. * @dwc: pointer to our context structure
  94. */
  95. static void dwc3_core_soft_reset(struct dwc3 *dwc)
  96. {
  97. u32 reg;
  98. /* Before Resetting PHY, put Core in Reset */
  99. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  100. reg |= DWC3_GCTL_CORESOFTRESET;
  101. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  102. /* Assert USB3 PHY reset */
  103. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  104. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  105. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  106. /* Assert USB2 PHY reset */
  107. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  108. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  109. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  110. mdelay(100);
  111. /* Clear USB3 PHY reset */
  112. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  113. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  114. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  115. /* Clear USB2 PHY reset */
  116. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  117. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  118. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  119. /* After PHYs are stable we can take Core out of reset state */
  120. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  121. reg &= ~DWC3_GCTL_CORESOFTRESET;
  122. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  123. }
  124. /**
  125. * dwc3_free_one_event_buffer - Frees one event buffer
  126. * @dwc: Pointer to our controller context structure
  127. * @evt: Pointer to event buffer to be freed
  128. */
  129. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  130. struct dwc3_event_buffer *evt)
  131. {
  132. dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
  133. kfree(evt);
  134. }
  135. /**
  136. * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
  137. * @dwc: Pointer to our controller context structure
  138. * @length: size of the event buffer
  139. *
  140. * Returns a pointer to the allocated event buffer structure on succes
  141. * otherwise ERR_PTR(errno).
  142. */
  143. static struct dwc3_event_buffer *__devinit
  144. dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
  145. {
  146. struct dwc3_event_buffer *evt;
  147. evt = kzalloc(sizeof(*evt), GFP_KERNEL);
  148. if (!evt)
  149. return ERR_PTR(-ENOMEM);
  150. evt->dwc = dwc;
  151. evt->length = length;
  152. evt->buf = dma_alloc_coherent(dwc->dev, length,
  153. &evt->dma, GFP_KERNEL);
  154. if (!evt->buf) {
  155. kfree(evt);
  156. return ERR_PTR(-ENOMEM);
  157. }
  158. return evt;
  159. }
  160. /**
  161. * dwc3_free_event_buffers - frees all allocated event buffers
  162. * @dwc: Pointer to our controller context structure
  163. */
  164. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  165. {
  166. struct dwc3_event_buffer *evt;
  167. int i;
  168. for (i = 0; i < dwc->num_event_buffers; i++) {
  169. evt = dwc->ev_buffs[i];
  170. if (evt) {
  171. dwc3_free_one_event_buffer(dwc, evt);
  172. dwc->ev_buffs[i] = NULL;
  173. }
  174. }
  175. }
  176. /**
  177. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  178. * @dwc: Pointer to out controller context structure
  179. * @length: size of event buffer
  180. *
  181. * Returns 0 on success otherwise negative errno. In error the case, dwc
  182. * may contain some buffers allocated but not all which were requested.
  183. */
  184. static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  185. {
  186. int num;
  187. int i;
  188. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  189. dwc->num_event_buffers = num;
  190. for (i = 0; i < num; i++) {
  191. struct dwc3_event_buffer *evt;
  192. evt = dwc3_alloc_one_event_buffer(dwc, length);
  193. if (IS_ERR(evt)) {
  194. dev_err(dwc->dev, "can't allocate event buffer\n");
  195. return PTR_ERR(evt);
  196. }
  197. dwc->ev_buffs[i] = evt;
  198. }
  199. return 0;
  200. }
  201. /**
  202. * dwc3_event_buffers_setup - setup our allocated event buffers
  203. * @dwc: Pointer to out controller context structure
  204. *
  205. * Returns 0 on success otherwise negative errno.
  206. */
  207. static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
  208. {
  209. struct dwc3_event_buffer *evt;
  210. int n;
  211. for (n = 0; n < dwc->num_event_buffers; n++) {
  212. evt = dwc->ev_buffs[n];
  213. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  214. evt->buf, (unsigned long long) evt->dma,
  215. evt->length);
  216. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  217. lower_32_bits(evt->dma));
  218. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  219. upper_32_bits(evt->dma));
  220. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  221. evt->length & 0xffff);
  222. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  223. }
  224. return 0;
  225. }
  226. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  227. {
  228. struct dwc3_event_buffer *evt;
  229. int n;
  230. for (n = 0; n < dwc->num_event_buffers; n++) {
  231. evt = dwc->ev_buffs[n];
  232. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  233. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  234. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
  235. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  236. }
  237. }
  238. static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
  239. {
  240. struct dwc3_hwparams *parms = &dwc->hwparams;
  241. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  242. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  243. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  244. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  245. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  246. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  247. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  248. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  249. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  250. }
  251. /**
  252. * dwc3_core_init - Low-level initialization of DWC3 Core
  253. * @dwc: Pointer to our controller context structure
  254. *
  255. * Returns 0 on success otherwise negative errno.
  256. */
  257. static int __devinit dwc3_core_init(struct dwc3 *dwc)
  258. {
  259. unsigned long timeout;
  260. u32 reg;
  261. int ret;
  262. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  263. /* This should read as U3 followed by revision number */
  264. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  265. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  266. ret = -ENODEV;
  267. goto err0;
  268. }
  269. dwc->revision = reg & DWC3_GSNPSREV_MASK;
  270. dwc3_core_soft_reset(dwc);
  271. /* issue device SoftReset too */
  272. timeout = jiffies + msecs_to_jiffies(500);
  273. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  274. do {
  275. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  276. if (!(reg & DWC3_DCTL_CSFTRST))
  277. break;
  278. if (time_after(jiffies, timeout)) {
  279. dev_err(dwc->dev, "Reset Timed Out\n");
  280. ret = -ETIMEDOUT;
  281. goto err0;
  282. }
  283. cpu_relax();
  284. } while (true);
  285. dwc3_cache_hwparams(dwc);
  286. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  287. if (ret) {
  288. dev_err(dwc->dev, "failed to allocate event buffers\n");
  289. ret = -ENOMEM;
  290. goto err1;
  291. }
  292. ret = dwc3_event_buffers_setup(dwc);
  293. if (ret) {
  294. dev_err(dwc->dev, "failed to setup event buffers\n");
  295. goto err1;
  296. }
  297. return 0;
  298. err1:
  299. dwc3_free_event_buffers(dwc);
  300. err0:
  301. return ret;
  302. }
  303. static void dwc3_core_exit(struct dwc3 *dwc)
  304. {
  305. dwc3_event_buffers_cleanup(dwc);
  306. dwc3_free_event_buffers(dwc);
  307. }
  308. #define DWC3_ALIGN_MASK (16 - 1)
  309. static int __devinit dwc3_probe(struct platform_device *pdev)
  310. {
  311. struct resource *res;
  312. struct dwc3 *dwc;
  313. int ret = -ENOMEM;
  314. int irq;
  315. void __iomem *regs;
  316. void *mem;
  317. u8 mode;
  318. mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  319. if (!mem) {
  320. dev_err(&pdev->dev, "not enough memory\n");
  321. goto err0;
  322. }
  323. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  324. dwc->mem = mem;
  325. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  326. if (!res) {
  327. dev_err(&pdev->dev, "missing resource\n");
  328. goto err1;
  329. }
  330. dwc->res = res;
  331. res = request_mem_region(res->start, resource_size(res),
  332. dev_name(&pdev->dev));
  333. if (!res) {
  334. dev_err(&pdev->dev, "can't request mem region\n");
  335. goto err1;
  336. }
  337. regs = ioremap(res->start, resource_size(res));
  338. if (!regs) {
  339. dev_err(&pdev->dev, "ioremap failed\n");
  340. goto err2;
  341. }
  342. irq = platform_get_irq(pdev, 0);
  343. if (irq < 0) {
  344. dev_err(&pdev->dev, "missing IRQ\n");
  345. goto err3;
  346. }
  347. spin_lock_init(&dwc->lock);
  348. platform_set_drvdata(pdev, dwc);
  349. dwc->regs = regs;
  350. dwc->regs_size = resource_size(res);
  351. dwc->dev = &pdev->dev;
  352. dwc->irq = irq;
  353. if (!strncmp("super", maximum_speed, 5))
  354. dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
  355. else if (!strncmp("high", maximum_speed, 4))
  356. dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
  357. else if (!strncmp("full", maximum_speed, 4))
  358. dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
  359. else if (!strncmp("low", maximum_speed, 3))
  360. dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
  361. else
  362. dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
  363. pm_runtime_enable(&pdev->dev);
  364. pm_runtime_get_sync(&pdev->dev);
  365. pm_runtime_forbid(&pdev->dev);
  366. ret = dwc3_core_init(dwc);
  367. if (ret) {
  368. dev_err(&pdev->dev, "failed to initialize core\n");
  369. goto err3;
  370. }
  371. mode = DWC3_MODE(dwc->hwparams.hwparams0);
  372. switch (mode) {
  373. case DWC3_MODE_DEVICE:
  374. ret = dwc3_gadget_init(dwc);
  375. if (ret) {
  376. dev_err(&pdev->dev, "failed to initialize gadget\n");
  377. goto err4;
  378. }
  379. break;
  380. case DWC3_MODE_HOST:
  381. ret = dwc3_host_init(dwc);
  382. if (ret) {
  383. dev_err(&pdev->dev, "failed to initialize host\n");
  384. goto err4;
  385. }
  386. break;
  387. case DWC3_MODE_DRD:
  388. ret = dwc3_host_init(dwc);
  389. if (ret) {
  390. dev_err(&pdev->dev, "failed to initialize host\n");
  391. goto err4;
  392. }
  393. ret = dwc3_gadget_init(dwc);
  394. if (ret) {
  395. dev_err(&pdev->dev, "failed to initialize gadget\n");
  396. goto err4;
  397. }
  398. break;
  399. default:
  400. dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode);
  401. goto err4;
  402. }
  403. dwc->mode = mode;
  404. ret = dwc3_debugfs_init(dwc);
  405. if (ret) {
  406. dev_err(&pdev->dev, "failed to initialize debugfs\n");
  407. goto err5;
  408. }
  409. pm_runtime_allow(&pdev->dev);
  410. return 0;
  411. err5:
  412. switch (mode) {
  413. case DWC3_MODE_DEVICE:
  414. dwc3_gadget_exit(dwc);
  415. break;
  416. case DWC3_MODE_HOST:
  417. dwc3_host_exit(dwc);
  418. break;
  419. case DWC3_MODE_DRD:
  420. dwc3_host_exit(dwc);
  421. dwc3_gadget_exit(dwc);
  422. break;
  423. default:
  424. /* do nothing */
  425. break;
  426. }
  427. err4:
  428. dwc3_core_exit(dwc);
  429. err3:
  430. iounmap(regs);
  431. err2:
  432. release_mem_region(res->start, resource_size(res));
  433. err1:
  434. kfree(dwc->mem);
  435. err0:
  436. return ret;
  437. }
  438. static int __devexit dwc3_remove(struct platform_device *pdev)
  439. {
  440. struct dwc3 *dwc = platform_get_drvdata(pdev);
  441. struct resource *res;
  442. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  443. pm_runtime_put(&pdev->dev);
  444. pm_runtime_disable(&pdev->dev);
  445. dwc3_debugfs_exit(dwc);
  446. switch (dwc->mode) {
  447. case DWC3_MODE_DEVICE:
  448. dwc3_gadget_exit(dwc);
  449. break;
  450. case DWC3_MODE_HOST:
  451. dwc3_host_exit(dwc);
  452. break;
  453. case DWC3_MODE_DRD:
  454. dwc3_host_exit(dwc);
  455. dwc3_gadget_exit(dwc);
  456. break;
  457. default:
  458. /* do nothing */
  459. break;
  460. }
  461. dwc3_core_exit(dwc);
  462. release_mem_region(res->start, resource_size(res));
  463. iounmap(dwc->regs);
  464. kfree(dwc->mem);
  465. return 0;
  466. }
  467. static struct platform_driver dwc3_driver = {
  468. .probe = dwc3_probe,
  469. .remove = __devexit_p(dwc3_remove),
  470. .driver = {
  471. .name = "dwc3",
  472. },
  473. };
  474. MODULE_ALIAS("platform:dwc3");
  475. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  476. MODULE_LICENSE("Dual BSD/GPL");
  477. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  478. static int __devinit dwc3_init(void)
  479. {
  480. return platform_driver_register(&dwc3_driver);
  481. }
  482. module_init(dwc3_init);
  483. static void __exit dwc3_exit(void)
  484. {
  485. platform_driver_unregister(&dwc3_driver);
  486. }
  487. module_exit(dwc3_exit);