jz4740.c 11 KB

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  1. /*
  2. * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * You should have received a copy of the GNU General Public License along
  9. * with this program; if not, write to the Free Software Foundation, Inc.,
  10. * 675 Mass Ave, Cambridge, MA 02139, USA.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/io.h>
  18. #include <linux/regmap.h>
  19. #include <linux/delay.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/initval.h>
  24. #include <sound/soc.h>
  25. #include <sound/tlv.h>
  26. #define JZ4740_REG_CODEC_1 0x0
  27. #define JZ4740_REG_CODEC_2 0x4
  28. #define JZ4740_CODEC_1_LINE_ENABLE BIT(29)
  29. #define JZ4740_CODEC_1_MIC_ENABLE BIT(28)
  30. #define JZ4740_CODEC_1_SW1_ENABLE BIT(27)
  31. #define JZ4740_CODEC_1_ADC_ENABLE BIT(26)
  32. #define JZ4740_CODEC_1_SW2_ENABLE BIT(25)
  33. #define JZ4740_CODEC_1_DAC_ENABLE BIT(24)
  34. #define JZ4740_CODEC_1_VREF_DISABLE BIT(20)
  35. #define JZ4740_CODEC_1_VREF_AMP_DISABLE BIT(19)
  36. #define JZ4740_CODEC_1_VREF_PULLDOWN BIT(18)
  37. #define JZ4740_CODEC_1_VREF_LOW_CURRENT BIT(17)
  38. #define JZ4740_CODEC_1_VREF_HIGH_CURRENT BIT(16)
  39. #define JZ4740_CODEC_1_HEADPHONE_DISABLE BIT(14)
  40. #define JZ4740_CODEC_1_HEADPHONE_AMP_CHANGE_ANY BIT(13)
  41. #define JZ4740_CODEC_1_HEADPHONE_CHARGE BIT(12)
  42. #define JZ4740_CODEC_1_HEADPHONE_PULLDOWN (BIT(11) | BIT(10))
  43. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M BIT(9)
  44. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN BIT(8)
  45. #define JZ4740_CODEC_1_SUSPEND BIT(1)
  46. #define JZ4740_CODEC_1_RESET BIT(0)
  47. #define JZ4740_CODEC_1_LINE_ENABLE_OFFSET 29
  48. #define JZ4740_CODEC_1_MIC_ENABLE_OFFSET 28
  49. #define JZ4740_CODEC_1_SW1_ENABLE_OFFSET 27
  50. #define JZ4740_CODEC_1_ADC_ENABLE_OFFSET 26
  51. #define JZ4740_CODEC_1_SW2_ENABLE_OFFSET 25
  52. #define JZ4740_CODEC_1_DAC_ENABLE_OFFSET 24
  53. #define JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET 14
  54. #define JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET 8
  55. #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
  56. #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
  57. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
  58. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
  59. #define JZ4740_CODEC_2_INPUT_VOLUME_OFFSET 16
  60. #define JZ4740_CODEC_2_SAMPLE_RATE_OFFSET 8
  61. #define JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET 4
  62. #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
  63. static const struct reg_default jz4740_codec_reg_defaults[] = {
  64. { JZ4740_REG_CODEC_1, 0x021b2302 },
  65. { JZ4740_REG_CODEC_2, 0x00170803 },
  66. };
  67. struct jz4740_codec {
  68. struct regmap *regmap;
  69. };
  70. static const unsigned int jz4740_mic_tlv[] = {
  71. TLV_DB_RANGE_HEAD(2),
  72. 0, 2, TLV_DB_SCALE_ITEM(0, 600, 0),
  73. 3, 3, TLV_DB_SCALE_ITEM(2000, 0, 0),
  74. };
  75. static const DECLARE_TLV_DB_SCALE(jz4740_out_tlv, 0, 200, 0);
  76. static const DECLARE_TLV_DB_SCALE(jz4740_in_tlv, -3450, 150, 0);
  77. static const struct snd_kcontrol_new jz4740_codec_controls[] = {
  78. SOC_SINGLE_TLV("Master Playback Volume", JZ4740_REG_CODEC_2,
  79. JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET, 3, 0,
  80. jz4740_out_tlv),
  81. SOC_SINGLE_TLV("Master Capture Volume", JZ4740_REG_CODEC_2,
  82. JZ4740_CODEC_2_INPUT_VOLUME_OFFSET, 31, 0,
  83. jz4740_in_tlv),
  84. SOC_SINGLE("Master Playback Switch", JZ4740_REG_CODEC_1,
  85. JZ4740_CODEC_1_HEADPHONE_DISABLE_OFFSET, 1, 1),
  86. SOC_SINGLE_TLV("Mic Capture Volume", JZ4740_REG_CODEC_2,
  87. JZ4740_CODEC_2_MIC_BOOST_GAIN_OFFSET, 3, 0,
  88. jz4740_mic_tlv),
  89. };
  90. static const struct snd_kcontrol_new jz4740_codec_output_controls[] = {
  91. SOC_DAPM_SINGLE("Bypass Switch", JZ4740_REG_CODEC_1,
  92. JZ4740_CODEC_1_SW1_ENABLE_OFFSET, 1, 0),
  93. SOC_DAPM_SINGLE("DAC Switch", JZ4740_REG_CODEC_1,
  94. JZ4740_CODEC_1_SW2_ENABLE_OFFSET, 1, 0),
  95. };
  96. static const struct snd_kcontrol_new jz4740_codec_input_controls[] = {
  97. SOC_DAPM_SINGLE("Line Capture Switch", JZ4740_REG_CODEC_1,
  98. JZ4740_CODEC_1_LINE_ENABLE_OFFSET, 1, 0),
  99. SOC_DAPM_SINGLE("Mic Capture Switch", JZ4740_REG_CODEC_1,
  100. JZ4740_CODEC_1_MIC_ENABLE_OFFSET, 1, 0),
  101. };
  102. static const struct snd_soc_dapm_widget jz4740_codec_dapm_widgets[] = {
  103. SND_SOC_DAPM_ADC("ADC", "Capture", JZ4740_REG_CODEC_1,
  104. JZ4740_CODEC_1_ADC_ENABLE_OFFSET, 0),
  105. SND_SOC_DAPM_DAC("DAC", "Playback", JZ4740_REG_CODEC_1,
  106. JZ4740_CODEC_1_DAC_ENABLE_OFFSET, 0),
  107. SND_SOC_DAPM_MIXER("Output Mixer", JZ4740_REG_CODEC_1,
  108. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_OFFSET, 1,
  109. jz4740_codec_output_controls,
  110. ARRAY_SIZE(jz4740_codec_output_controls)),
  111. SND_SOC_DAPM_MIXER_NAMED_CTL("Input Mixer", SND_SOC_NOPM, 0, 0,
  112. jz4740_codec_input_controls,
  113. ARRAY_SIZE(jz4740_codec_input_controls)),
  114. SND_SOC_DAPM_MIXER("Line Input", SND_SOC_NOPM, 0, 0, NULL, 0),
  115. SND_SOC_DAPM_OUTPUT("LOUT"),
  116. SND_SOC_DAPM_OUTPUT("ROUT"),
  117. SND_SOC_DAPM_INPUT("MIC"),
  118. SND_SOC_DAPM_INPUT("LIN"),
  119. SND_SOC_DAPM_INPUT("RIN"),
  120. };
  121. static const struct snd_soc_dapm_route jz4740_codec_dapm_routes[] = {
  122. {"Line Input", NULL, "LIN"},
  123. {"Line Input", NULL, "RIN"},
  124. {"Input Mixer", "Line Capture Switch", "Line Input"},
  125. {"Input Mixer", "Mic Capture Switch", "MIC"},
  126. {"ADC", NULL, "Input Mixer"},
  127. {"Output Mixer", "Bypass Switch", "Input Mixer"},
  128. {"Output Mixer", "DAC Switch", "DAC"},
  129. {"LOUT", NULL, "Output Mixer"},
  130. {"ROUT", NULL, "Output Mixer"},
  131. };
  132. static int jz4740_codec_hw_params(struct snd_pcm_substream *substream,
  133. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  134. {
  135. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(dai->codec);
  136. uint32_t val;
  137. switch (params_rate(params)) {
  138. case 8000:
  139. val = 0;
  140. break;
  141. case 11025:
  142. val = 1;
  143. break;
  144. case 12000:
  145. val = 2;
  146. break;
  147. case 16000:
  148. val = 3;
  149. break;
  150. case 22050:
  151. val = 4;
  152. break;
  153. case 24000:
  154. val = 5;
  155. break;
  156. case 32000:
  157. val = 6;
  158. break;
  159. case 44100:
  160. val = 7;
  161. break;
  162. case 48000:
  163. val = 8;
  164. break;
  165. default:
  166. return -EINVAL;
  167. }
  168. val <<= JZ4740_CODEC_2_SAMPLE_RATE_OFFSET;
  169. regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_2,
  170. JZ4740_CODEC_2_SAMPLE_RATE_MASK, val);
  171. return 0;
  172. }
  173. static const struct snd_soc_dai_ops jz4740_codec_dai_ops = {
  174. .hw_params = jz4740_codec_hw_params,
  175. };
  176. static struct snd_soc_dai_driver jz4740_codec_dai = {
  177. .name = "jz4740-hifi",
  178. .playback = {
  179. .stream_name = "Playback",
  180. .channels_min = 2,
  181. .channels_max = 2,
  182. .rates = SNDRV_PCM_RATE_8000_48000,
  183. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  184. },
  185. .capture = {
  186. .stream_name = "Capture",
  187. .channels_min = 2,
  188. .channels_max = 2,
  189. .rates = SNDRV_PCM_RATE_8000_48000,
  190. .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
  191. },
  192. .ops = &jz4740_codec_dai_ops,
  193. .symmetric_rates = 1,
  194. };
  195. static void jz4740_codec_wakeup(struct regmap *regmap)
  196. {
  197. regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
  198. JZ4740_CODEC_1_RESET, JZ4740_CODEC_1_RESET);
  199. udelay(2);
  200. regmap_update_bits(regmap, JZ4740_REG_CODEC_1,
  201. JZ4740_CODEC_1_SUSPEND | JZ4740_CODEC_1_RESET, 0);
  202. regcache_sync(regmap);
  203. }
  204. static int jz4740_codec_set_bias_level(struct snd_soc_codec *codec,
  205. enum snd_soc_bias_level level)
  206. {
  207. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
  208. struct regmap *regmap = jz4740_codec->regmap;
  209. unsigned int mask;
  210. unsigned int value;
  211. switch (level) {
  212. case SND_SOC_BIAS_ON:
  213. break;
  214. case SND_SOC_BIAS_PREPARE:
  215. mask = JZ4740_CODEC_1_VREF_DISABLE |
  216. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  217. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  218. value = 0;
  219. regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
  220. break;
  221. case SND_SOC_BIAS_STANDBY:
  222. /* The only way to clear the suspend flag is to reset the codec */
  223. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
  224. jz4740_codec_wakeup(regmap);
  225. mask = JZ4740_CODEC_1_VREF_DISABLE |
  226. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  227. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  228. value = JZ4740_CODEC_1_VREF_DISABLE |
  229. JZ4740_CODEC_1_VREF_AMP_DISABLE |
  230. JZ4740_CODEC_1_HEADPHONE_POWERDOWN_M;
  231. regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
  232. break;
  233. case SND_SOC_BIAS_OFF:
  234. mask = JZ4740_CODEC_1_SUSPEND;
  235. value = JZ4740_CODEC_1_SUSPEND;
  236. regmap_update_bits(regmap, JZ4740_REG_CODEC_1, mask, value);
  237. regcache_mark_dirty(regmap);
  238. break;
  239. default:
  240. break;
  241. }
  242. codec->dapm.bias_level = level;
  243. return 0;
  244. }
  245. static int jz4740_codec_dev_probe(struct snd_soc_codec *codec)
  246. {
  247. struct jz4740_codec *jz4740_codec = snd_soc_codec_get_drvdata(codec);
  248. regmap_update_bits(jz4740_codec->regmap, JZ4740_REG_CODEC_1,
  249. JZ4740_CODEC_1_SW2_ENABLE, JZ4740_CODEC_1_SW2_ENABLE);
  250. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  251. return 0;
  252. }
  253. static int jz4740_codec_dev_remove(struct snd_soc_codec *codec)
  254. {
  255. jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  256. return 0;
  257. }
  258. #ifdef CONFIG_PM_SLEEP
  259. static int jz4740_codec_suspend(struct snd_soc_codec *codec)
  260. {
  261. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_OFF);
  262. }
  263. static int jz4740_codec_resume(struct snd_soc_codec *codec)
  264. {
  265. return jz4740_codec_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  266. }
  267. #else
  268. #define jz4740_codec_suspend NULL
  269. #define jz4740_codec_resume NULL
  270. #endif
  271. static struct snd_soc_codec_driver soc_codec_dev_jz4740_codec = {
  272. .probe = jz4740_codec_dev_probe,
  273. .remove = jz4740_codec_dev_remove,
  274. .suspend = jz4740_codec_suspend,
  275. .resume = jz4740_codec_resume,
  276. .set_bias_level = jz4740_codec_set_bias_level,
  277. .controls = jz4740_codec_controls,
  278. .num_controls = ARRAY_SIZE(jz4740_codec_controls),
  279. .dapm_widgets = jz4740_codec_dapm_widgets,
  280. .num_dapm_widgets = ARRAY_SIZE(jz4740_codec_dapm_widgets),
  281. .dapm_routes = jz4740_codec_dapm_routes,
  282. .num_dapm_routes = ARRAY_SIZE(jz4740_codec_dapm_routes),
  283. };
  284. static const struct regmap_config jz4740_codec_regmap_config = {
  285. .reg_bits = 32,
  286. .reg_stride = 4,
  287. .val_bits = 32,
  288. .max_register = JZ4740_REG_CODEC_2,
  289. .reg_defaults = jz4740_codec_reg_defaults,
  290. .num_reg_defaults = ARRAY_SIZE(jz4740_codec_reg_defaults),
  291. .cache_type = REGCACHE_RBTREE,
  292. };
  293. static int jz4740_codec_probe(struct platform_device *pdev)
  294. {
  295. int ret;
  296. struct jz4740_codec *jz4740_codec;
  297. struct resource *mem;
  298. void __iomem *base;
  299. jz4740_codec = devm_kzalloc(&pdev->dev, sizeof(*jz4740_codec),
  300. GFP_KERNEL);
  301. if (!jz4740_codec)
  302. return -ENOMEM;
  303. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  304. base = devm_request_and_ioremap(&pdev->dev, mem);
  305. if (!base)
  306. return -EBUSY;
  307. jz4740_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
  308. &jz4740_codec_regmap_config);
  309. if (IS_ERR(jz4740_codec->regmap))
  310. return PTR_ERR(jz4740_codec->regmap);
  311. platform_set_drvdata(pdev, jz4740_codec);
  312. ret = snd_soc_register_codec(&pdev->dev,
  313. &soc_codec_dev_jz4740_codec, &jz4740_codec_dai, 1);
  314. if (ret)
  315. dev_err(&pdev->dev, "Failed to register codec\n");
  316. return ret;
  317. }
  318. static int jz4740_codec_remove(struct platform_device *pdev)
  319. {
  320. snd_soc_unregister_codec(&pdev->dev);
  321. platform_set_drvdata(pdev, NULL);
  322. return 0;
  323. }
  324. static struct platform_driver jz4740_codec_driver = {
  325. .probe = jz4740_codec_probe,
  326. .remove = jz4740_codec_remove,
  327. .driver = {
  328. .name = "jz4740-codec",
  329. .owner = THIS_MODULE,
  330. },
  331. };
  332. module_platform_driver(jz4740_codec_driver);
  333. MODULE_DESCRIPTION("JZ4740 SoC internal codec driver");
  334. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  335. MODULE_LICENSE("GPL v2");
  336. MODULE_ALIAS("platform:jz4740-codec");