omap_wdt.c 9.2 KB

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  1. /*
  2. * omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <linux/module.h>
  30. #include <linux/types.h>
  31. #include <linux/kernel.h>
  32. #include <linux/mm.h>
  33. #include <linux/watchdog.h>
  34. #include <linux/reboot.h>
  35. #include <linux/init.h>
  36. #include <linux/err.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/moduleparam.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/pm_runtime.h>
  42. #include <linux/platform_data/omap-wd-timer.h>
  43. #include "omap_wdt.h"
  44. static unsigned timer_margin;
  45. module_param(timer_margin, uint, 0);
  46. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  47. struct omap_wdt_dev {
  48. void __iomem *base; /* physical */
  49. struct device *dev;
  50. bool omap_wdt_users;
  51. struct resource *mem;
  52. int wdt_trgr_pattern;
  53. struct mutex lock; /* to avoid races with PM */
  54. };
  55. static void omap_wdt_reload(struct omap_wdt_dev *wdev)
  56. {
  57. void __iomem *base = wdev->base;
  58. /* wait for posted write to complete */
  59. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  60. cpu_relax();
  61. wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
  62. __raw_writel(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
  63. /* wait for posted write to complete */
  64. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
  65. cpu_relax();
  66. /* reloaded WCRR from WLDR */
  67. }
  68. static void omap_wdt_enable(struct omap_wdt_dev *wdev)
  69. {
  70. void __iomem *base = wdev->base;
  71. /* Sequence to enable the watchdog */
  72. __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
  73. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  74. cpu_relax();
  75. __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
  76. while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
  77. cpu_relax();
  78. }
  79. static void omap_wdt_disable(struct omap_wdt_dev *wdev)
  80. {
  81. void __iomem *base = wdev->base;
  82. /* sequence required to disable watchdog */
  83. __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  84. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  85. cpu_relax();
  86. __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  87. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
  88. cpu_relax();
  89. }
  90. static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
  91. unsigned int timeout)
  92. {
  93. u32 pre_margin = GET_WLDR_VAL(timeout);
  94. void __iomem *base = wdev->base;
  95. /* just count up at 32 KHz */
  96. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  97. cpu_relax();
  98. __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
  99. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
  100. cpu_relax();
  101. }
  102. static int omap_wdt_start(struct watchdog_device *wdog)
  103. {
  104. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  105. void __iomem *base = wdev->base;
  106. mutex_lock(&wdev->lock);
  107. wdev->omap_wdt_users = true;
  108. pm_runtime_get_sync(wdev->dev);
  109. /* initialize prescaler */
  110. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  111. cpu_relax();
  112. __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
  113. while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
  114. cpu_relax();
  115. omap_wdt_set_timer(wdev, wdog->timeout);
  116. omap_wdt_reload(wdev); /* trigger loading of new timeout value */
  117. omap_wdt_enable(wdev);
  118. mutex_unlock(&wdev->lock);
  119. return 0;
  120. }
  121. static int omap_wdt_stop(struct watchdog_device *wdog)
  122. {
  123. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  124. mutex_lock(&wdev->lock);
  125. omap_wdt_disable(wdev);
  126. pm_runtime_put_sync(wdev->dev);
  127. wdev->omap_wdt_users = false;
  128. mutex_unlock(&wdev->lock);
  129. return 0;
  130. }
  131. static int omap_wdt_ping(struct watchdog_device *wdog)
  132. {
  133. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  134. mutex_lock(&wdev->lock);
  135. omap_wdt_reload(wdev);
  136. mutex_unlock(&wdev->lock);
  137. return 0;
  138. }
  139. static int omap_wdt_set_timeout(struct watchdog_device *wdog,
  140. unsigned int timeout)
  141. {
  142. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  143. mutex_lock(&wdev->lock);
  144. omap_wdt_disable(wdev);
  145. omap_wdt_set_timer(wdev, timeout);
  146. omap_wdt_enable(wdev);
  147. omap_wdt_reload(wdev);
  148. wdog->timeout = timeout;
  149. mutex_unlock(&wdev->lock);
  150. return 0;
  151. }
  152. static const struct watchdog_info omap_wdt_info = {
  153. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  154. .identity = "OMAP Watchdog",
  155. };
  156. static const struct watchdog_ops omap_wdt_ops = {
  157. .owner = THIS_MODULE,
  158. .start = omap_wdt_start,
  159. .stop = omap_wdt_stop,
  160. .ping = omap_wdt_ping,
  161. .set_timeout = omap_wdt_set_timeout,
  162. };
  163. static int omap_wdt_probe(struct platform_device *pdev)
  164. {
  165. struct omap_wd_timer_platform_data *pdata = pdev->dev.platform_data;
  166. bool nowayout = WATCHDOG_NOWAYOUT;
  167. struct watchdog_device *omap_wdt;
  168. struct resource *res, *mem;
  169. struct omap_wdt_dev *wdev;
  170. u32 rs;
  171. int ret;
  172. omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL);
  173. if (!omap_wdt)
  174. return -ENOMEM;
  175. /* reserve static register mappings */
  176. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  177. if (!res)
  178. return -ENOENT;
  179. mem = devm_request_mem_region(&pdev->dev, res->start,
  180. resource_size(res), pdev->name);
  181. if (!mem)
  182. return -EBUSY;
  183. wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
  184. if (!wdev)
  185. return -ENOMEM;
  186. wdev->omap_wdt_users = false;
  187. wdev->mem = mem;
  188. wdev->dev = &pdev->dev;
  189. wdev->wdt_trgr_pattern = 0x1234;
  190. mutex_init(&wdev->lock);
  191. wdev->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
  192. if (!wdev->base)
  193. return -ENOMEM;
  194. omap_wdt->info = &omap_wdt_info;
  195. omap_wdt->ops = &omap_wdt_ops;
  196. omap_wdt->min_timeout = TIMER_MARGIN_MIN;
  197. omap_wdt->max_timeout = TIMER_MARGIN_MAX;
  198. if (timer_margin >= TIMER_MARGIN_MIN &&
  199. timer_margin <= TIMER_MARGIN_MAX)
  200. omap_wdt->timeout = timer_margin;
  201. else
  202. omap_wdt->timeout = TIMER_MARGIN_DEFAULT;
  203. watchdog_set_drvdata(omap_wdt, wdev);
  204. watchdog_set_nowayout(omap_wdt, nowayout);
  205. platform_set_drvdata(pdev, omap_wdt);
  206. pm_runtime_enable(wdev->dev);
  207. pm_runtime_get_sync(wdev->dev);
  208. if (pdata && pdata->read_reset_sources)
  209. rs = pdata->read_reset_sources();
  210. else
  211. rs = 0;
  212. omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ?
  213. WDIOF_CARDRESET : 0;
  214. omap_wdt_disable(wdev);
  215. ret = watchdog_register_device(omap_wdt);
  216. if (ret) {
  217. pm_runtime_disable(wdev->dev);
  218. return ret;
  219. }
  220. pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
  221. __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
  222. omap_wdt->timeout);
  223. pm_runtime_put_sync(wdev->dev);
  224. return 0;
  225. }
  226. static void omap_wdt_shutdown(struct platform_device *pdev)
  227. {
  228. struct watchdog_device *wdog = platform_get_drvdata(pdev);
  229. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  230. mutex_lock(&wdev->lock);
  231. if (wdev->omap_wdt_users) {
  232. omap_wdt_disable(wdev);
  233. pm_runtime_put_sync(wdev->dev);
  234. }
  235. mutex_unlock(&wdev->lock);
  236. }
  237. static int omap_wdt_remove(struct platform_device *pdev)
  238. {
  239. struct watchdog_device *wdog = platform_get_drvdata(pdev);
  240. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  241. pm_runtime_disable(wdev->dev);
  242. watchdog_unregister_device(wdog);
  243. return 0;
  244. }
  245. #ifdef CONFIG_PM
  246. /* REVISIT ... not clear this is the best way to handle system suspend; and
  247. * it's very inappropriate for selective device suspend (e.g. suspending this
  248. * through sysfs rather than by stopping the watchdog daemon). Also, this
  249. * may not play well enough with NOWAYOUT...
  250. */
  251. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  252. {
  253. struct watchdog_device *wdog = platform_get_drvdata(pdev);
  254. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  255. mutex_lock(&wdev->lock);
  256. if (wdev->omap_wdt_users) {
  257. omap_wdt_disable(wdev);
  258. pm_runtime_put_sync(wdev->dev);
  259. }
  260. mutex_unlock(&wdev->lock);
  261. return 0;
  262. }
  263. static int omap_wdt_resume(struct platform_device *pdev)
  264. {
  265. struct watchdog_device *wdog = platform_get_drvdata(pdev);
  266. struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
  267. mutex_lock(&wdev->lock);
  268. if (wdev->omap_wdt_users) {
  269. pm_runtime_get_sync(wdev->dev);
  270. omap_wdt_enable(wdev);
  271. omap_wdt_reload(wdev);
  272. }
  273. mutex_unlock(&wdev->lock);
  274. return 0;
  275. }
  276. #else
  277. #define omap_wdt_suspend NULL
  278. #define omap_wdt_resume NULL
  279. #endif
  280. static const struct of_device_id omap_wdt_of_match[] = {
  281. { .compatible = "ti,omap3-wdt", },
  282. {},
  283. };
  284. MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
  285. static struct platform_driver omap_wdt_driver = {
  286. .probe = omap_wdt_probe,
  287. .remove = omap_wdt_remove,
  288. .shutdown = omap_wdt_shutdown,
  289. .suspend = omap_wdt_suspend,
  290. .resume = omap_wdt_resume,
  291. .driver = {
  292. .owner = THIS_MODULE,
  293. .name = "omap_wdt",
  294. .of_match_table = omap_wdt_of_match,
  295. },
  296. };
  297. module_platform_driver(omap_wdt_driver);
  298. MODULE_AUTHOR("George G. Davis");
  299. MODULE_LICENSE("GPL");
  300. MODULE_ALIAS("platform:omap_wdt");