ehci-fsl.c 19 KB

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  1. /*
  2. * Copyright 2005-2009 MontaVista Software, Inc.
  3. * Copyright 2008,2012 Freescale Semiconductor, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software Foundation,
  17. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. *
  19. * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20. * by Hunter Wu.
  21. * Power Management support by Dave Liu <daveliu@freescale.com>,
  22. * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23. * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/types.h>
  27. #include <linux/delay.h>
  28. #include <linux/pm.h>
  29. #include <linux/err.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/fsl_devices.h>
  32. #include "ehci-fsl.h"
  33. /* configure so an HC device and id are always provided */
  34. /* always called with process context; sleeping is OK */
  35. /**
  36. * usb_hcd_fsl_probe - initialize FSL-based HCDs
  37. * @drvier: Driver to be used for this HCD
  38. * @pdev: USB Host Controller being probed
  39. * Context: !in_interrupt()
  40. *
  41. * Allocates basic resources for this USB host controller.
  42. *
  43. */
  44. static int usb_hcd_fsl_probe(const struct hc_driver *driver,
  45. struct platform_device *pdev)
  46. {
  47. struct fsl_usb2_platform_data *pdata;
  48. struct usb_hcd *hcd;
  49. struct resource *res;
  50. int irq;
  51. int retval;
  52. pr_debug("initializing FSL-SOC USB Controller\n");
  53. /* Need platform data for setup */
  54. pdata = (struct fsl_usb2_platform_data *)pdev->dev.platform_data;
  55. if (!pdata) {
  56. dev_err(&pdev->dev,
  57. "No platform data for %s.\n", dev_name(&pdev->dev));
  58. return -ENODEV;
  59. }
  60. /*
  61. * This is a host mode driver, verify that we're supposed to be
  62. * in host mode.
  63. */
  64. if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  65. (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  66. (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  67. dev_err(&pdev->dev,
  68. "Non Host Mode configured for %s. Wrong driver linked.\n",
  69. dev_name(&pdev->dev));
  70. return -ENODEV;
  71. }
  72. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  73. if (!res) {
  74. dev_err(&pdev->dev,
  75. "Found HC with no IRQ. Check %s setup!\n",
  76. dev_name(&pdev->dev));
  77. return -ENODEV;
  78. }
  79. irq = res->start;
  80. hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
  81. if (!hcd) {
  82. retval = -ENOMEM;
  83. goto err1;
  84. }
  85. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. if (!res) {
  87. dev_err(&pdev->dev,
  88. "Found HC with no register addr. Check %s setup!\n",
  89. dev_name(&pdev->dev));
  90. retval = -ENODEV;
  91. goto err2;
  92. }
  93. hcd->rsrc_start = res->start;
  94. hcd->rsrc_len = resource_size(res);
  95. if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
  96. driver->description)) {
  97. dev_dbg(&pdev->dev, "controller already in use\n");
  98. retval = -EBUSY;
  99. goto err2;
  100. }
  101. hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
  102. if (hcd->regs == NULL) {
  103. dev_dbg(&pdev->dev, "error mapping memory\n");
  104. retval = -EFAULT;
  105. goto err3;
  106. }
  107. pdata->regs = hcd->regs;
  108. if (pdata->power_budget)
  109. hcd->power_budget = pdata->power_budget;
  110. /*
  111. * do platform specific init: check the clock, grab/config pins, etc.
  112. */
  113. if (pdata->init && pdata->init(pdev)) {
  114. retval = -ENODEV;
  115. goto err4;
  116. }
  117. /* Enable USB controller, 83xx or 8536 */
  118. if (pdata->have_sysif_regs)
  119. setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
  120. /* Don't need to set host mode here. It will be done by tdi_reset() */
  121. retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
  122. if (retval != 0)
  123. goto err4;
  124. #ifdef CONFIG_USB_OTG
  125. if (pdata->operating_mode == FSL_USB2_DR_OTG) {
  126. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  127. hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
  128. dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
  129. hcd, ehci, hcd->phy);
  130. if (!IS_ERR_OR_NULL(hcd->phy)) {
  131. retval = otg_set_host(hcd->phy->otg,
  132. &ehci_to_hcd(ehci)->self);
  133. if (retval) {
  134. usb_put_phy(hcd->phy);
  135. goto err4;
  136. }
  137. } else {
  138. dev_err(&pdev->dev, "can't find phy\n");
  139. retval = -ENODEV;
  140. goto err4;
  141. }
  142. }
  143. #endif
  144. return retval;
  145. err4:
  146. iounmap(hcd->regs);
  147. err3:
  148. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  149. err2:
  150. usb_put_hcd(hcd);
  151. err1:
  152. dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
  153. if (pdata->exit)
  154. pdata->exit(pdev);
  155. return retval;
  156. }
  157. /* may be called without controller electrically present */
  158. /* may be called with controller, bus, and devices active */
  159. /**
  160. * usb_hcd_fsl_remove - shutdown processing for FSL-based HCDs
  161. * @dev: USB Host Controller being removed
  162. * Context: !in_interrupt()
  163. *
  164. * Reverses the effect of usb_hcd_fsl_probe().
  165. *
  166. */
  167. static void usb_hcd_fsl_remove(struct usb_hcd *hcd,
  168. struct platform_device *pdev)
  169. {
  170. struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
  171. if (!IS_ERR_OR_NULL(hcd->phy)) {
  172. otg_set_host(hcd->phy->otg, NULL);
  173. usb_put_phy(hcd->phy);
  174. }
  175. usb_remove_hcd(hcd);
  176. /*
  177. * do platform specific un-initialization:
  178. * release iomux pins, disable clock, etc.
  179. */
  180. if (pdata->exit)
  181. pdata->exit(pdev);
  182. iounmap(hcd->regs);
  183. release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  184. usb_put_hcd(hcd);
  185. }
  186. static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
  187. enum fsl_usb2_phy_modes phy_mode,
  188. unsigned int port_offset)
  189. {
  190. u32 portsc;
  191. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  192. void __iomem *non_ehci = hcd->regs;
  193. struct device *dev = hcd->self.controller;
  194. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  195. if (pdata->controller_ver < 0) {
  196. dev_warn(hcd->self.controller, "Could not get controller version\n");
  197. return -ENODEV;
  198. }
  199. portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
  200. portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
  201. switch (phy_mode) {
  202. case FSL_USB2_PHY_ULPI:
  203. if (pdata->controller_ver) {
  204. /* controller version 1.6 or above */
  205. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  206. ULPI_PHY_CLK_SEL);
  207. /*
  208. * Due to controller issue of PHY_CLK_VALID in ULPI
  209. * mode, we set USB_CTRL_USB_EN before checking
  210. * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
  211. */
  212. clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
  213. UTMI_PHY_EN, USB_CTRL_USB_EN);
  214. }
  215. portsc |= PORT_PTS_ULPI;
  216. break;
  217. case FSL_USB2_PHY_SERIAL:
  218. portsc |= PORT_PTS_SERIAL;
  219. break;
  220. case FSL_USB2_PHY_UTMI_WIDE:
  221. portsc |= PORT_PTS_PTW;
  222. /* fall through */
  223. case FSL_USB2_PHY_UTMI:
  224. if (pdata->controller_ver) {
  225. /* controller version 1.6 or above */
  226. setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
  227. mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
  228. become stable - 10ms*/
  229. }
  230. /* enable UTMI PHY */
  231. if (pdata->have_sysif_regs)
  232. setbits32(non_ehci + FSL_SOC_USB_CTRL,
  233. CTRL_UTMI_PHY_EN);
  234. portsc |= PORT_PTS_UTMI;
  235. break;
  236. case FSL_USB2_PHY_NONE:
  237. break;
  238. }
  239. if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) {
  240. /* check PHY_CLK_VALID to get phy clk valid */
  241. if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
  242. PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
  243. printk(KERN_WARNING "fsl-ehci: USB PHY clock invalid\n");
  244. return -EINVAL;
  245. }
  246. }
  247. ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
  248. if (phy_mode != FSL_USB2_PHY_ULPI)
  249. setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
  250. return 0;
  251. }
  252. static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
  253. {
  254. struct usb_hcd *hcd = ehci_to_hcd(ehci);
  255. struct fsl_usb2_platform_data *pdata;
  256. void __iomem *non_ehci = hcd->regs;
  257. pdata = hcd->self.controller->platform_data;
  258. if (pdata->have_sysif_regs) {
  259. /*
  260. * Turn on cache snooping hardware, since some PowerPC platforms
  261. * wholly rely on hardware to deal with cache coherent
  262. */
  263. /* Setup Snooping for all the 4GB space */
  264. /* SNOOP1 starts from 0x0, size 2G */
  265. out_be32(non_ehci + FSL_SOC_USB_SNOOP1, 0x0 | SNOOP_SIZE_2GB);
  266. /* SNOOP2 starts from 0x80000000, size 2G */
  267. out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
  268. }
  269. if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  270. (pdata->operating_mode == FSL_USB2_DR_OTG))
  271. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  272. return -EINVAL;
  273. if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
  274. unsigned int chip, rev, svr;
  275. svr = mfspr(SPRN_SVR);
  276. chip = svr >> 16;
  277. rev = (svr >> 4) & 0xf;
  278. /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
  279. if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
  280. ehci->has_fsl_port_bug = 1;
  281. if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
  282. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
  283. return -EINVAL;
  284. if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
  285. if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
  286. return -EINVAL;
  287. }
  288. if (pdata->have_sysif_regs) {
  289. #ifdef CONFIG_FSL_SOC_BOOKE
  290. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
  291. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000080);
  292. #else
  293. out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x0000000c);
  294. out_be32(non_ehci + FSL_SOC_USB_AGECNTTHRSH, 0x00000040);
  295. #endif
  296. out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
  297. }
  298. return 0;
  299. }
  300. /* called after powerup, by probe or system-pm "wakeup" */
  301. static int ehci_fsl_reinit(struct ehci_hcd *ehci)
  302. {
  303. if (ehci_fsl_usb_setup(ehci))
  304. return -EINVAL;
  305. return 0;
  306. }
  307. /* called during probe() after chip reset completes */
  308. static int ehci_fsl_setup(struct usb_hcd *hcd)
  309. {
  310. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  311. int retval;
  312. struct fsl_usb2_platform_data *pdata;
  313. struct device *dev;
  314. dev = hcd->self.controller;
  315. pdata = hcd->self.controller->platform_data;
  316. ehci->big_endian_desc = pdata->big_endian_desc;
  317. ehci->big_endian_mmio = pdata->big_endian_mmio;
  318. /* EHCI registers start at offset 0x100 */
  319. ehci->caps = hcd->regs + 0x100;
  320. hcd->has_tt = 1;
  321. retval = ehci_setup(hcd);
  322. if (retval)
  323. return retval;
  324. if (of_device_is_compatible(dev->parent->of_node,
  325. "fsl,mpc5121-usb2-dr")) {
  326. /*
  327. * set SBUSCFG:AHBBRST so that control msgs don't
  328. * fail when doing heavy PATA writes.
  329. */
  330. ehci_writel(ehci, SBUSCFG_INCR8,
  331. hcd->regs + FSL_SOC_USB_SBUSCFG);
  332. }
  333. retval = ehci_fsl_reinit(ehci);
  334. return retval;
  335. }
  336. struct ehci_fsl {
  337. struct ehci_hcd ehci;
  338. #ifdef CONFIG_PM
  339. /* Saved USB PHY settings, need to restore after deep sleep. */
  340. u32 usb_ctrl;
  341. #endif
  342. };
  343. #ifdef CONFIG_PM
  344. #ifdef CONFIG_PPC_MPC512x
  345. static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  346. {
  347. struct usb_hcd *hcd = dev_get_drvdata(dev);
  348. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  349. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  350. u32 tmp;
  351. #ifdef DEBUG
  352. u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
  353. mode &= USBMODE_CM_MASK;
  354. tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
  355. dev_dbg(dev, "suspend=%d already_suspended=%d "
  356. "mode=%d usbcmd %08x\n", pdata->suspended,
  357. pdata->already_suspended, mode, tmp);
  358. #endif
  359. /*
  360. * If the controller is already suspended, then this must be a
  361. * PM suspend. Remember this fact, so that we will leave the
  362. * controller suspended at PM resume time.
  363. */
  364. if (pdata->suspended) {
  365. dev_dbg(dev, "already suspended, leaving early\n");
  366. pdata->already_suspended = 1;
  367. return 0;
  368. }
  369. dev_dbg(dev, "suspending...\n");
  370. ehci->rh_state = EHCI_RH_SUSPENDED;
  371. dev->power.power_state = PMSG_SUSPEND;
  372. /* ignore non-host interrupts */
  373. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  374. /* stop the controller */
  375. tmp = ehci_readl(ehci, &ehci->regs->command);
  376. tmp &= ~CMD_RUN;
  377. ehci_writel(ehci, tmp, &ehci->regs->command);
  378. /* save EHCI registers */
  379. pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
  380. pdata->pm_command &= ~CMD_RUN;
  381. pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
  382. pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
  383. pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
  384. pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
  385. pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
  386. pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
  387. pdata->pm_configured_flag =
  388. ehci_readl(ehci, &ehci->regs->configured_flag);
  389. pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
  390. pdata->pm_usbgenctrl = ehci_readl(ehci,
  391. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  392. /* clear the W1C bits */
  393. pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
  394. pdata->suspended = 1;
  395. /* clear PP to cut power to the port */
  396. tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
  397. tmp &= ~PORT_POWER;
  398. ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
  399. return 0;
  400. }
  401. static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  402. {
  403. struct usb_hcd *hcd = dev_get_drvdata(dev);
  404. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  405. struct fsl_usb2_platform_data *pdata = dev->platform_data;
  406. u32 tmp;
  407. dev_dbg(dev, "suspend=%d already_suspended=%d\n",
  408. pdata->suspended, pdata->already_suspended);
  409. /*
  410. * If the controller was already suspended at suspend time,
  411. * then don't resume it now.
  412. */
  413. if (pdata->already_suspended) {
  414. dev_dbg(dev, "already suspended, leaving early\n");
  415. pdata->already_suspended = 0;
  416. return 0;
  417. }
  418. if (!pdata->suspended) {
  419. dev_dbg(dev, "not suspended, leaving early\n");
  420. return 0;
  421. }
  422. pdata->suspended = 0;
  423. dev_dbg(dev, "resuming...\n");
  424. /* set host mode */
  425. tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
  426. ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
  427. ehci_writel(ehci, pdata->pm_usbgenctrl,
  428. hcd->regs + FSL_SOC_USB_USBGENCTRL);
  429. ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
  430. hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
  431. ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
  432. /* restore EHCI registers */
  433. ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
  434. ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
  435. ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
  436. ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
  437. ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
  438. ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
  439. ehci_writel(ehci, pdata->pm_configured_flag,
  440. &ehci->regs->configured_flag);
  441. ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
  442. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  443. ehci->rh_state = EHCI_RH_RUNNING;
  444. dev->power.power_state = PMSG_ON;
  445. tmp = ehci_readl(ehci, &ehci->regs->command);
  446. tmp |= CMD_RUN;
  447. ehci_writel(ehci, tmp, &ehci->regs->command);
  448. usb_hcd_resume_root_hub(hcd);
  449. return 0;
  450. }
  451. #else
  452. static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
  453. {
  454. return 0;
  455. }
  456. static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
  457. {
  458. return 0;
  459. }
  460. #endif /* CONFIG_PPC_MPC512x */
  461. static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
  462. {
  463. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  464. return container_of(ehci, struct ehci_fsl, ehci);
  465. }
  466. static int ehci_fsl_drv_suspend(struct device *dev)
  467. {
  468. struct usb_hcd *hcd = dev_get_drvdata(dev);
  469. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  470. void __iomem *non_ehci = hcd->regs;
  471. if (of_device_is_compatible(dev->parent->of_node,
  472. "fsl,mpc5121-usb2-dr")) {
  473. return ehci_fsl_mpc512x_drv_suspend(dev);
  474. }
  475. ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
  476. device_may_wakeup(dev));
  477. if (!fsl_deep_sleep())
  478. return 0;
  479. ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
  480. return 0;
  481. }
  482. static int ehci_fsl_drv_resume(struct device *dev)
  483. {
  484. struct usb_hcd *hcd = dev_get_drvdata(dev);
  485. struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
  486. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  487. void __iomem *non_ehci = hcd->regs;
  488. if (of_device_is_compatible(dev->parent->of_node,
  489. "fsl,mpc5121-usb2-dr")) {
  490. return ehci_fsl_mpc512x_drv_resume(dev);
  491. }
  492. ehci_prepare_ports_for_controller_resume(ehci);
  493. if (!fsl_deep_sleep())
  494. return 0;
  495. usb_root_hub_lost_power(hcd->self.root_hub);
  496. /* Restore USB PHY settings and enable the controller. */
  497. out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
  498. ehci_reset(ehci);
  499. ehci_fsl_reinit(ehci);
  500. return 0;
  501. }
  502. static int ehci_fsl_drv_restore(struct device *dev)
  503. {
  504. struct usb_hcd *hcd = dev_get_drvdata(dev);
  505. usb_root_hub_lost_power(hcd->self.root_hub);
  506. return 0;
  507. }
  508. static struct dev_pm_ops ehci_fsl_pm_ops = {
  509. .suspend = ehci_fsl_drv_suspend,
  510. .resume = ehci_fsl_drv_resume,
  511. .restore = ehci_fsl_drv_restore,
  512. };
  513. #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops)
  514. #else
  515. #define EHCI_FSL_PM_OPS NULL
  516. #endif /* CONFIG_PM */
  517. #ifdef CONFIG_USB_OTG
  518. static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
  519. {
  520. struct ehci_hcd *ehci = hcd_to_ehci(hcd);
  521. u32 status;
  522. if (!port)
  523. return -EINVAL;
  524. port--;
  525. /* start port reset before HNP protocol time out */
  526. status = readl(&ehci->regs->port_status[port]);
  527. if (!(status & PORT_CONNECT))
  528. return -ENODEV;
  529. /* khubd will finish the reset later */
  530. if (ehci_is_TDI(ehci)) {
  531. writel(PORT_RESET |
  532. (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
  533. &ehci->regs->port_status[port]);
  534. } else {
  535. writel(PORT_RESET, &ehci->regs->port_status[port]);
  536. }
  537. return 0;
  538. }
  539. #else
  540. #define ehci_start_port_reset NULL
  541. #endif /* CONFIG_USB_OTG */
  542. static const struct hc_driver ehci_fsl_hc_driver = {
  543. .description = hcd_name,
  544. .product_desc = "Freescale On-Chip EHCI Host Controller",
  545. .hcd_priv_size = sizeof(struct ehci_fsl),
  546. /*
  547. * generic hardware linkage
  548. */
  549. .irq = ehci_irq,
  550. .flags = HCD_USB2 | HCD_MEMORY,
  551. /*
  552. * basic lifecycle operations
  553. */
  554. .reset = ehci_fsl_setup,
  555. .start = ehci_run,
  556. .stop = ehci_stop,
  557. .shutdown = ehci_shutdown,
  558. /*
  559. * managing i/o requests and associated device resources
  560. */
  561. .urb_enqueue = ehci_urb_enqueue,
  562. .urb_dequeue = ehci_urb_dequeue,
  563. .endpoint_disable = ehci_endpoint_disable,
  564. .endpoint_reset = ehci_endpoint_reset,
  565. /*
  566. * scheduling support
  567. */
  568. .get_frame_number = ehci_get_frame,
  569. /*
  570. * root hub support
  571. */
  572. .hub_status_data = ehci_hub_status_data,
  573. .hub_control = ehci_hub_control,
  574. .bus_suspend = ehci_bus_suspend,
  575. .bus_resume = ehci_bus_resume,
  576. .start_port_reset = ehci_start_port_reset,
  577. .relinquish_port = ehci_relinquish_port,
  578. .port_handed_over = ehci_port_handed_over,
  579. .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
  580. };
  581. static int ehci_fsl_drv_probe(struct platform_device *pdev)
  582. {
  583. if (usb_disabled())
  584. return -ENODEV;
  585. /* FIXME we only want one one probe() not two */
  586. return usb_hcd_fsl_probe(&ehci_fsl_hc_driver, pdev);
  587. }
  588. static int ehci_fsl_drv_remove(struct platform_device *pdev)
  589. {
  590. struct usb_hcd *hcd = platform_get_drvdata(pdev);
  591. /* FIXME we only want one one remove() not two */
  592. usb_hcd_fsl_remove(hcd, pdev);
  593. return 0;
  594. }
  595. MODULE_ALIAS("platform:fsl-ehci");
  596. static struct platform_driver ehci_fsl_driver = {
  597. .probe = ehci_fsl_drv_probe,
  598. .remove = ehci_fsl_drv_remove,
  599. .shutdown = usb_hcd_platform_shutdown,
  600. .driver = {
  601. .name = "fsl-ehci",
  602. .pm = EHCI_FSL_PM_OPS,
  603. },
  604. };