lpc32xx_hs.c 20 KB

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  1. /*
  2. * High Speed Serial Ports on NXP LPC32xx SoC
  3. *
  4. * Authors: Kevin Wells <kevin.wells@nxp.com>
  5. * Roland Stigge <stigge@antcom.de>
  6. *
  7. * Copyright (C) 2010 NXP Semiconductors
  8. * Copyright (C) 2012 Roland Stigge
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/ioport.h>
  22. #include <linux/init.h>
  23. #include <linux/console.h>
  24. #include <linux/sysrq.h>
  25. #include <linux/tty.h>
  26. #include <linux/tty_flip.h>
  27. #include <linux/serial_core.h>
  28. #include <linux/serial.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/delay.h>
  31. #include <linux/nmi.h>
  32. #include <linux/io.h>
  33. #include <linux/irq.h>
  34. #include <linux/gpio.h>
  35. #include <linux/of.h>
  36. #include <mach/platform.h>
  37. #include <mach/hardware.h>
  38. /*
  39. * High Speed UART register offsets
  40. */
  41. #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
  42. #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
  43. #define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
  44. #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
  45. #define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
  46. #define LPC32XX_HSU_BREAK_DATA (1 << 10)
  47. #define LPC32XX_HSU_ERROR_DATA (1 << 9)
  48. #define LPC32XX_HSU_RX_EMPTY (1 << 8)
  49. #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
  50. #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
  51. #define LPC32XX_HSU_TX_INT_SET (1 << 6)
  52. #define LPC32XX_HSU_RX_OE_INT (1 << 5)
  53. #define LPC32XX_HSU_BRK_INT (1 << 4)
  54. #define LPC32XX_HSU_FE_INT (1 << 3)
  55. #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
  56. #define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
  57. #define LPC32XX_HSU_TX_INT (1 << 0)
  58. #define LPC32XX_HSU_HRTS_INV (1 << 21)
  59. #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
  60. #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
  61. #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
  62. #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
  63. #define LPC32XX_HSU_HRTS_EN (1 << 18)
  64. #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
  65. #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
  66. #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
  67. #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
  68. #define LPC32XX_HSU_HCTS_INV (1 << 15)
  69. #define LPC32XX_HSU_HCTS_EN (1 << 14)
  70. #define LPC32XX_HSU_OFFSET(n) ((n) << 9)
  71. #define LPC32XX_HSU_BREAK (1 << 8)
  72. #define LPC32XX_HSU_ERR_INT_EN (1 << 7)
  73. #define LPC32XX_HSU_RX_INT_EN (1 << 6)
  74. #define LPC32XX_HSU_TX_INT_EN (1 << 5)
  75. #define LPC32XX_HSU_RX_TL1B (0x0 << 2)
  76. #define LPC32XX_HSU_RX_TL4B (0x1 << 2)
  77. #define LPC32XX_HSU_RX_TL8B (0x2 << 2)
  78. #define LPC32XX_HSU_RX_TL16B (0x3 << 2)
  79. #define LPC32XX_HSU_RX_TL32B (0x4 << 2)
  80. #define LPC32XX_HSU_RX_TL48B (0x5 << 2)
  81. #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
  82. #define LPC32XX_HSU_TX_TL0B (0x0 << 0)
  83. #define LPC32XX_HSU_TX_TL4B (0x1 << 0)
  84. #define LPC32XX_HSU_TX_TL8B (0x2 << 0)
  85. #define LPC32XX_HSU_TX_TL16B (0x3 << 0)
  86. #define MODNAME "lpc32xx_hsuart"
  87. struct lpc32xx_hsuart_port {
  88. struct uart_port port;
  89. };
  90. #define FIFO_READ_LIMIT 128
  91. #define MAX_PORTS 3
  92. #define LPC32XX_TTY_NAME "ttyTX"
  93. static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
  94. #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
  95. static void wait_for_xmit_empty(struct uart_port *port)
  96. {
  97. unsigned int timeout = 10000;
  98. do {
  99. if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
  100. port->membase))) == 0)
  101. break;
  102. if (--timeout == 0)
  103. break;
  104. udelay(1);
  105. } while (1);
  106. }
  107. static void wait_for_xmit_ready(struct uart_port *port)
  108. {
  109. unsigned int timeout = 10000;
  110. while (1) {
  111. if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
  112. port->membase))) < 32)
  113. break;
  114. if (--timeout == 0)
  115. break;
  116. udelay(1);
  117. }
  118. }
  119. static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
  120. {
  121. wait_for_xmit_ready(port);
  122. writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
  123. }
  124. static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
  125. unsigned int count)
  126. {
  127. struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
  128. unsigned long flags;
  129. int locked = 1;
  130. touch_nmi_watchdog();
  131. local_irq_save(flags);
  132. if (up->port.sysrq)
  133. locked = 0;
  134. else if (oops_in_progress)
  135. locked = spin_trylock(&up->port.lock);
  136. else
  137. spin_lock(&up->port.lock);
  138. uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
  139. wait_for_xmit_empty(&up->port);
  140. if (locked)
  141. spin_unlock(&up->port.lock);
  142. local_irq_restore(flags);
  143. }
  144. static int __init lpc32xx_hsuart_console_setup(struct console *co,
  145. char *options)
  146. {
  147. struct uart_port *port;
  148. int baud = 115200;
  149. int bits = 8;
  150. int parity = 'n';
  151. int flow = 'n';
  152. if (co->index >= MAX_PORTS)
  153. co->index = 0;
  154. port = &lpc32xx_hs_ports[co->index].port;
  155. if (!port->membase)
  156. return -ENODEV;
  157. if (options)
  158. uart_parse_options(options, &baud, &parity, &bits, &flow);
  159. return uart_set_options(port, co, baud, parity, bits, flow);
  160. }
  161. static struct uart_driver lpc32xx_hsuart_reg;
  162. static struct console lpc32xx_hsuart_console = {
  163. .name = LPC32XX_TTY_NAME,
  164. .write = lpc32xx_hsuart_console_write,
  165. .device = uart_console_device,
  166. .setup = lpc32xx_hsuart_console_setup,
  167. .flags = CON_PRINTBUFFER,
  168. .index = -1,
  169. .data = &lpc32xx_hsuart_reg,
  170. };
  171. static int __init lpc32xx_hsuart_console_init(void)
  172. {
  173. register_console(&lpc32xx_hsuart_console);
  174. return 0;
  175. }
  176. console_initcall(lpc32xx_hsuart_console_init);
  177. #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
  178. #else
  179. #define LPC32XX_HSUART_CONSOLE NULL
  180. #endif
  181. static struct uart_driver lpc32xx_hs_reg = {
  182. .owner = THIS_MODULE,
  183. .driver_name = MODNAME,
  184. .dev_name = LPC32XX_TTY_NAME,
  185. .nr = MAX_PORTS,
  186. .cons = LPC32XX_HSUART_CONSOLE,
  187. };
  188. static int uarts_registered;
  189. static unsigned int __serial_get_clock_div(unsigned long uartclk,
  190. unsigned long rate)
  191. {
  192. u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
  193. u32 rate_diff;
  194. /* Find the closest divider to get the desired clock rate */
  195. div = uartclk / rate;
  196. goodrate = hsu_rate = (div / 14) - 1;
  197. if (hsu_rate != 0)
  198. hsu_rate--;
  199. /* Tweak divider */
  200. l_hsu_rate = hsu_rate + 3;
  201. rate_diff = 0xFFFFFFFF;
  202. while (hsu_rate < l_hsu_rate) {
  203. comprate = uartclk / ((hsu_rate + 1) * 14);
  204. if (abs(comprate - rate) < rate_diff) {
  205. goodrate = hsu_rate;
  206. rate_diff = abs(comprate - rate);
  207. }
  208. hsu_rate++;
  209. }
  210. if (hsu_rate > 0xFF)
  211. hsu_rate = 0xFF;
  212. return goodrate;
  213. }
  214. static void __serial_uart_flush(struct uart_port *port)
  215. {
  216. u32 tmp;
  217. int cnt = 0;
  218. while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
  219. (cnt++ < FIFO_READ_LIMIT))
  220. tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
  221. }
  222. static void __serial_lpc32xx_rx(struct uart_port *port)
  223. {
  224. unsigned int tmp, flag;
  225. struct tty_struct *tty = tty_port_tty_get(&port->state->port);
  226. if (!tty) {
  227. /* Discard data: no tty available */
  228. while (!(readl(LPC32XX_HSUART_FIFO(port->membase)) &
  229. LPC32XX_HSU_RX_EMPTY))
  230. ;
  231. return;
  232. }
  233. /* Read data from FIFO and push into terminal */
  234. tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
  235. while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
  236. flag = TTY_NORMAL;
  237. port->icount.rx++;
  238. if (tmp & LPC32XX_HSU_ERROR_DATA) {
  239. /* Framing error */
  240. writel(LPC32XX_HSU_FE_INT,
  241. LPC32XX_HSUART_IIR(port->membase));
  242. port->icount.frame++;
  243. flag = TTY_FRAME;
  244. tty_insert_flip_char(tty, 0, TTY_FRAME);
  245. }
  246. tty_insert_flip_char(tty, (tmp & 0xFF), flag);
  247. tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
  248. }
  249. tty_flip_buffer_push(tty);
  250. tty_kref_put(tty);
  251. }
  252. static void __serial_lpc32xx_tx(struct uart_port *port)
  253. {
  254. struct circ_buf *xmit = &port->state->xmit;
  255. unsigned int tmp;
  256. if (port->x_char) {
  257. writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
  258. port->icount.tx++;
  259. port->x_char = 0;
  260. return;
  261. }
  262. if (uart_circ_empty(xmit) || uart_tx_stopped(port))
  263. goto exit_tx;
  264. /* Transfer data */
  265. while (LPC32XX_HSU_TX_LEV(readl(
  266. LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
  267. writel((u32) xmit->buf[xmit->tail],
  268. LPC32XX_HSUART_FIFO(port->membase));
  269. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  270. port->icount.tx++;
  271. if (uart_circ_empty(xmit))
  272. break;
  273. }
  274. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  275. uart_write_wakeup(port);
  276. exit_tx:
  277. if (uart_circ_empty(xmit)) {
  278. tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
  279. tmp &= ~LPC32XX_HSU_TX_INT_EN;
  280. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  281. }
  282. }
  283. static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
  284. {
  285. struct uart_port *port = dev_id;
  286. struct tty_struct *tty = tty_port_tty_get(&port->state->port);
  287. u32 status;
  288. spin_lock(&port->lock);
  289. /* Read UART status and clear latched interrupts */
  290. status = readl(LPC32XX_HSUART_IIR(port->membase));
  291. if (status & LPC32XX_HSU_BRK_INT) {
  292. /* Break received */
  293. writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
  294. port->icount.brk++;
  295. uart_handle_break(port);
  296. }
  297. /* Framing error */
  298. if (status & LPC32XX_HSU_FE_INT)
  299. writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
  300. if (status & LPC32XX_HSU_RX_OE_INT) {
  301. /* Receive FIFO overrun */
  302. writel(LPC32XX_HSU_RX_OE_INT,
  303. LPC32XX_HSUART_IIR(port->membase));
  304. port->icount.overrun++;
  305. if (tty) {
  306. tty_insert_flip_char(tty, 0, TTY_OVERRUN);
  307. tty_schedule_flip(tty);
  308. }
  309. }
  310. /* Data received? */
  311. if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
  312. __serial_lpc32xx_rx(port);
  313. if (tty)
  314. tty_flip_buffer_push(tty);
  315. }
  316. /* Transmit data request? */
  317. if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
  318. writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
  319. __serial_lpc32xx_tx(port);
  320. }
  321. spin_unlock(&port->lock);
  322. tty_kref_put(tty);
  323. return IRQ_HANDLED;
  324. }
  325. /* port->lock is not held. */
  326. static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
  327. {
  328. unsigned int ret = 0;
  329. if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
  330. ret = TIOCSER_TEMT;
  331. return ret;
  332. }
  333. /* port->lock held by caller. */
  334. static void serial_lpc32xx_set_mctrl(struct uart_port *port,
  335. unsigned int mctrl)
  336. {
  337. /* No signals are supported on HS UARTs */
  338. }
  339. /* port->lock is held by caller and interrupts are disabled. */
  340. static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
  341. {
  342. /* No signals are supported on HS UARTs */
  343. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  344. }
  345. /* port->lock held by caller. */
  346. static void serial_lpc32xx_stop_tx(struct uart_port *port)
  347. {
  348. u32 tmp;
  349. tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
  350. tmp &= ~LPC32XX_HSU_TX_INT_EN;
  351. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  352. }
  353. /* port->lock held by caller. */
  354. static void serial_lpc32xx_start_tx(struct uart_port *port)
  355. {
  356. u32 tmp;
  357. __serial_lpc32xx_tx(port);
  358. tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
  359. tmp |= LPC32XX_HSU_TX_INT_EN;
  360. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  361. }
  362. /* port->lock held by caller. */
  363. static void serial_lpc32xx_stop_rx(struct uart_port *port)
  364. {
  365. u32 tmp;
  366. tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
  367. tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
  368. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  369. writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
  370. LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
  371. }
  372. /* port->lock held by caller. */
  373. static void serial_lpc32xx_enable_ms(struct uart_port *port)
  374. {
  375. /* Modem status is not supported */
  376. }
  377. /* port->lock is not held. */
  378. static void serial_lpc32xx_break_ctl(struct uart_port *port,
  379. int break_state)
  380. {
  381. unsigned long flags;
  382. u32 tmp;
  383. spin_lock_irqsave(&port->lock, flags);
  384. tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
  385. if (break_state != 0)
  386. tmp |= LPC32XX_HSU_BREAK;
  387. else
  388. tmp &= ~LPC32XX_HSU_BREAK;
  389. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  390. spin_unlock_irqrestore(&port->lock, flags);
  391. }
  392. /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
  393. static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
  394. {
  395. int bit;
  396. u32 tmp;
  397. switch (mapbase) {
  398. case LPC32XX_HS_UART1_BASE:
  399. bit = 0;
  400. break;
  401. case LPC32XX_HS_UART2_BASE:
  402. bit = 1;
  403. break;
  404. case LPC32XX_HS_UART7_BASE:
  405. bit = 6;
  406. break;
  407. default:
  408. WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
  409. return;
  410. }
  411. tmp = readl(LPC32XX_UARTCTL_CLOOP);
  412. if (state)
  413. tmp |= (1 << bit);
  414. else
  415. tmp &= ~(1 << bit);
  416. writel(tmp, LPC32XX_UARTCTL_CLOOP);
  417. }
  418. /* port->lock is not held. */
  419. static int serial_lpc32xx_startup(struct uart_port *port)
  420. {
  421. int retval;
  422. unsigned long flags;
  423. u32 tmp;
  424. spin_lock_irqsave(&port->lock, flags);
  425. __serial_uart_flush(port);
  426. writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
  427. LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
  428. LPC32XX_HSUART_IIR(port->membase));
  429. writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
  430. /*
  431. * Set receiver timeout, HSU offset of 20, no break, no interrupts,
  432. * and default FIFO trigger levels
  433. */
  434. tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
  435. LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
  436. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  437. lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
  438. spin_unlock_irqrestore(&port->lock, flags);
  439. retval = request_irq(port->irq, serial_lpc32xx_interrupt,
  440. 0, MODNAME, port);
  441. if (!retval)
  442. writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
  443. LPC32XX_HSUART_CTRL(port->membase));
  444. return retval;
  445. }
  446. /* port->lock is not held. */
  447. static void serial_lpc32xx_shutdown(struct uart_port *port)
  448. {
  449. u32 tmp;
  450. unsigned long flags;
  451. spin_lock_irqsave(&port->lock, flags);
  452. tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
  453. LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
  454. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  455. lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
  456. spin_unlock_irqrestore(&port->lock, flags);
  457. free_irq(port->irq, port);
  458. }
  459. /* port->lock is not held. */
  460. static void serial_lpc32xx_set_termios(struct uart_port *port,
  461. struct ktermios *termios,
  462. struct ktermios *old)
  463. {
  464. unsigned long flags;
  465. unsigned int baud, quot;
  466. u32 tmp;
  467. /* Always 8-bit, no parity, 1 stop bit */
  468. termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
  469. termios->c_cflag |= CS8;
  470. termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
  471. baud = uart_get_baud_rate(port, termios, old, 0,
  472. port->uartclk / 14);
  473. quot = __serial_get_clock_div(port->uartclk, baud);
  474. spin_lock_irqsave(&port->lock, flags);
  475. /* Ignore characters? */
  476. tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
  477. if ((termios->c_cflag & CREAD) == 0)
  478. tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
  479. else
  480. tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
  481. writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
  482. writel(quot, LPC32XX_HSUART_RATE(port->membase));
  483. uart_update_timeout(port, termios->c_cflag, baud);
  484. spin_unlock_irqrestore(&port->lock, flags);
  485. /* Don't rewrite B0 */
  486. if (tty_termios_baud_rate(termios))
  487. tty_termios_encode_baud_rate(termios, baud, baud);
  488. }
  489. static const char *serial_lpc32xx_type(struct uart_port *port)
  490. {
  491. return MODNAME;
  492. }
  493. static void serial_lpc32xx_release_port(struct uart_port *port)
  494. {
  495. if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
  496. if (port->flags & UPF_IOREMAP) {
  497. iounmap(port->membase);
  498. port->membase = NULL;
  499. }
  500. release_mem_region(port->mapbase, SZ_4K);
  501. }
  502. }
  503. static int serial_lpc32xx_request_port(struct uart_port *port)
  504. {
  505. int ret = -ENODEV;
  506. if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
  507. ret = 0;
  508. if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
  509. ret = -EBUSY;
  510. else if (port->flags & UPF_IOREMAP) {
  511. port->membase = ioremap(port->mapbase, SZ_4K);
  512. if (!port->membase) {
  513. release_mem_region(port->mapbase, SZ_4K);
  514. ret = -ENOMEM;
  515. }
  516. }
  517. }
  518. return ret;
  519. }
  520. static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
  521. {
  522. int ret;
  523. ret = serial_lpc32xx_request_port(port);
  524. if (ret < 0)
  525. return;
  526. port->type = PORT_UART00;
  527. port->fifosize = 64;
  528. __serial_uart_flush(port);
  529. writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
  530. LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
  531. LPC32XX_HSUART_IIR(port->membase));
  532. writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
  533. /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
  534. and default FIFO trigger levels */
  535. writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
  536. LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
  537. LPC32XX_HSUART_CTRL(port->membase));
  538. }
  539. static int serial_lpc32xx_verify_port(struct uart_port *port,
  540. struct serial_struct *ser)
  541. {
  542. int ret = 0;
  543. if (ser->type != PORT_UART00)
  544. ret = -EINVAL;
  545. return ret;
  546. }
  547. static struct uart_ops serial_lpc32xx_pops = {
  548. .tx_empty = serial_lpc32xx_tx_empty,
  549. .set_mctrl = serial_lpc32xx_set_mctrl,
  550. .get_mctrl = serial_lpc32xx_get_mctrl,
  551. .stop_tx = serial_lpc32xx_stop_tx,
  552. .start_tx = serial_lpc32xx_start_tx,
  553. .stop_rx = serial_lpc32xx_stop_rx,
  554. .enable_ms = serial_lpc32xx_enable_ms,
  555. .break_ctl = serial_lpc32xx_break_ctl,
  556. .startup = serial_lpc32xx_startup,
  557. .shutdown = serial_lpc32xx_shutdown,
  558. .set_termios = serial_lpc32xx_set_termios,
  559. .type = serial_lpc32xx_type,
  560. .release_port = serial_lpc32xx_release_port,
  561. .request_port = serial_lpc32xx_request_port,
  562. .config_port = serial_lpc32xx_config_port,
  563. .verify_port = serial_lpc32xx_verify_port,
  564. };
  565. /*
  566. * Register a set of serial devices attached to a platform device
  567. */
  568. static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
  569. {
  570. struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
  571. int ret = 0;
  572. struct resource *res;
  573. if (uarts_registered >= MAX_PORTS) {
  574. dev_err(&pdev->dev,
  575. "Error: Number of possible ports exceeded (%d)!\n",
  576. uarts_registered + 1);
  577. return -ENXIO;
  578. }
  579. memset(p, 0, sizeof(*p));
  580. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  581. if (!res) {
  582. dev_err(&pdev->dev,
  583. "Error getting mem resource for HS UART port %d\n",
  584. uarts_registered);
  585. return -ENXIO;
  586. }
  587. p->port.mapbase = res->start;
  588. p->port.membase = NULL;
  589. p->port.irq = platform_get_irq(pdev, 0);
  590. if (p->port.irq < 0) {
  591. dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
  592. uarts_registered);
  593. return p->port.irq;
  594. }
  595. p->port.iotype = UPIO_MEM32;
  596. p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
  597. p->port.regshift = 2;
  598. p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
  599. p->port.dev = &pdev->dev;
  600. p->port.ops = &serial_lpc32xx_pops;
  601. p->port.line = uarts_registered++;
  602. spin_lock_init(&p->port.lock);
  603. /* send port to loopback mode by default */
  604. lpc32xx_loopback_set(p->port.mapbase, 1);
  605. ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
  606. platform_set_drvdata(pdev, p);
  607. return ret;
  608. }
  609. /*
  610. * Remove serial ports registered against a platform device.
  611. */
  612. static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
  613. {
  614. struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
  615. uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
  616. return 0;
  617. }
  618. #ifdef CONFIG_PM
  619. static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
  620. pm_message_t state)
  621. {
  622. struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
  623. uart_suspend_port(&lpc32xx_hs_reg, &p->port);
  624. return 0;
  625. }
  626. static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
  627. {
  628. struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
  629. uart_resume_port(&lpc32xx_hs_reg, &p->port);
  630. return 0;
  631. }
  632. #else
  633. #define serial_hs_lpc32xx_suspend NULL
  634. #define serial_hs_lpc32xx_resume NULL
  635. #endif
  636. static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
  637. { .compatible = "nxp,lpc3220-hsuart" },
  638. { /* sentinel */ }
  639. };
  640. MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
  641. static struct platform_driver serial_hs_lpc32xx_driver = {
  642. .probe = serial_hs_lpc32xx_probe,
  643. .remove = serial_hs_lpc32xx_remove,
  644. .suspend = serial_hs_lpc32xx_suspend,
  645. .resume = serial_hs_lpc32xx_resume,
  646. .driver = {
  647. .name = MODNAME,
  648. .owner = THIS_MODULE,
  649. .of_match_table = serial_hs_lpc32xx_dt_ids,
  650. },
  651. };
  652. static int __init lpc32xx_hsuart_init(void)
  653. {
  654. int ret;
  655. ret = uart_register_driver(&lpc32xx_hs_reg);
  656. if (ret)
  657. return ret;
  658. ret = platform_driver_register(&serial_hs_lpc32xx_driver);
  659. if (ret)
  660. uart_unregister_driver(&lpc32xx_hs_reg);
  661. return ret;
  662. }
  663. static void __exit lpc32xx_hsuart_exit(void)
  664. {
  665. platform_driver_unregister(&serial_hs_lpc32xx_driver);
  666. uart_unregister_driver(&lpc32xx_hs_reg);
  667. }
  668. module_init(lpc32xx_hsuart_init);
  669. module_exit(lpc32xx_hsuart_exit);
  670. MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
  671. MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
  672. MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
  673. MODULE_LICENSE("GPL");