bnx2fc_hwi.c 62 KB

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  1. /* bnx2fc_hwi.c: Broadcom NetXtreme II Linux FCoE offload driver.
  2. * This file contains the code that low level functions that interact
  3. * with 57712 FCoE firmware.
  4. *
  5. * Copyright (c) 2008 - 2011 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation.
  10. *
  11. * Written by: Bhanu Prakash Gollapudi (bprakash@broadcom.com)
  12. */
  13. #include "bnx2fc.h"
  14. DECLARE_PER_CPU(struct bnx2fc_percpu_s, bnx2fc_percpu);
  15. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  16. struct fcoe_kcqe *new_cqe_kcqe);
  17. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  18. struct fcoe_kcqe *ofld_kcqe);
  19. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  20. struct fcoe_kcqe *ofld_kcqe);
  21. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code);
  22. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  23. struct fcoe_kcqe *destroy_kcqe);
  24. int bnx2fc_send_stat_req(struct bnx2fc_hba *hba)
  25. {
  26. struct fcoe_kwqe_stat stat_req;
  27. struct kwqe *kwqe_arr[2];
  28. int num_kwqes = 1;
  29. int rc = 0;
  30. memset(&stat_req, 0x00, sizeof(struct fcoe_kwqe_stat));
  31. stat_req.hdr.op_code = FCOE_KWQE_OPCODE_STAT;
  32. stat_req.hdr.flags =
  33. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  34. stat_req.stat_params_addr_lo = (u32) hba->stats_buf_dma;
  35. stat_req.stat_params_addr_hi = (u32) ((u64)hba->stats_buf_dma >> 32);
  36. kwqe_arr[0] = (struct kwqe *) &stat_req;
  37. if (hba->cnic && hba->cnic->submit_kwqes)
  38. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  39. return rc;
  40. }
  41. /**
  42. * bnx2fc_send_fw_fcoe_init_msg - initiates initial handshake with FCoE f/w
  43. *
  44. * @hba: adapter structure pointer
  45. *
  46. * Send down FCoE firmware init KWQEs which initiates the initial handshake
  47. * with the f/w.
  48. *
  49. */
  50. int bnx2fc_send_fw_fcoe_init_msg(struct bnx2fc_hba *hba)
  51. {
  52. struct fcoe_kwqe_init1 fcoe_init1;
  53. struct fcoe_kwqe_init2 fcoe_init2;
  54. struct fcoe_kwqe_init3 fcoe_init3;
  55. struct kwqe *kwqe_arr[3];
  56. int num_kwqes = 3;
  57. int rc = 0;
  58. if (!hba->cnic) {
  59. printk(KERN_ERR PFX "hba->cnic NULL during fcoe fw init\n");
  60. return -ENODEV;
  61. }
  62. /* fill init1 KWQE */
  63. memset(&fcoe_init1, 0x00, sizeof(struct fcoe_kwqe_init1));
  64. fcoe_init1.hdr.op_code = FCOE_KWQE_OPCODE_INIT1;
  65. fcoe_init1.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  66. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  67. fcoe_init1.num_tasks = BNX2FC_MAX_TASKS;
  68. fcoe_init1.sq_num_wqes = BNX2FC_SQ_WQES_MAX;
  69. fcoe_init1.rq_num_wqes = BNX2FC_RQ_WQES_MAX;
  70. fcoe_init1.rq_buffer_log_size = BNX2FC_RQ_BUF_LOG_SZ;
  71. fcoe_init1.cq_num_wqes = BNX2FC_CQ_WQES_MAX;
  72. fcoe_init1.dummy_buffer_addr_lo = (u32) hba->dummy_buf_dma;
  73. fcoe_init1.dummy_buffer_addr_hi = (u32) ((u64)hba->dummy_buf_dma >> 32);
  74. fcoe_init1.task_list_pbl_addr_lo = (u32) hba->task_ctx_bd_dma;
  75. fcoe_init1.task_list_pbl_addr_hi =
  76. (u32) ((u64) hba->task_ctx_bd_dma >> 32);
  77. fcoe_init1.mtu = BNX2FC_MINI_JUMBO_MTU;
  78. fcoe_init1.flags = (PAGE_SHIFT <<
  79. FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT);
  80. fcoe_init1.num_sessions_log = BNX2FC_NUM_MAX_SESS_LOG;
  81. /* fill init2 KWQE */
  82. memset(&fcoe_init2, 0x00, sizeof(struct fcoe_kwqe_init2));
  83. fcoe_init2.hdr.op_code = FCOE_KWQE_OPCODE_INIT2;
  84. fcoe_init2.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  85. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  86. fcoe_init2.hsi_major_version = FCOE_HSI_MAJOR_VERSION;
  87. fcoe_init2.hsi_minor_version = FCOE_HSI_MINOR_VERSION;
  88. fcoe_init2.hash_tbl_pbl_addr_lo = (u32) hba->hash_tbl_pbl_dma;
  89. fcoe_init2.hash_tbl_pbl_addr_hi = (u32)
  90. ((u64) hba->hash_tbl_pbl_dma >> 32);
  91. fcoe_init2.t2_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_dma;
  92. fcoe_init2.t2_hash_tbl_addr_hi = (u32)
  93. ((u64) hba->t2_hash_tbl_dma >> 32);
  94. fcoe_init2.t2_ptr_hash_tbl_addr_lo = (u32) hba->t2_hash_tbl_ptr_dma;
  95. fcoe_init2.t2_ptr_hash_tbl_addr_hi = (u32)
  96. ((u64) hba->t2_hash_tbl_ptr_dma >> 32);
  97. fcoe_init2.free_list_count = BNX2FC_NUM_MAX_SESS;
  98. /* fill init3 KWQE */
  99. memset(&fcoe_init3, 0x00, sizeof(struct fcoe_kwqe_init3));
  100. fcoe_init3.hdr.op_code = FCOE_KWQE_OPCODE_INIT3;
  101. fcoe_init3.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  102. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  103. fcoe_init3.error_bit_map_lo = 0xffffffff;
  104. fcoe_init3.error_bit_map_hi = 0xffffffff;
  105. fcoe_init3.perf_config = 1;
  106. kwqe_arr[0] = (struct kwqe *) &fcoe_init1;
  107. kwqe_arr[1] = (struct kwqe *) &fcoe_init2;
  108. kwqe_arr[2] = (struct kwqe *) &fcoe_init3;
  109. if (hba->cnic && hba->cnic->submit_kwqes)
  110. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  111. return rc;
  112. }
  113. int bnx2fc_send_fw_fcoe_destroy_msg(struct bnx2fc_hba *hba)
  114. {
  115. struct fcoe_kwqe_destroy fcoe_destroy;
  116. struct kwqe *kwqe_arr[2];
  117. int num_kwqes = 1;
  118. int rc = -1;
  119. /* fill destroy KWQE */
  120. memset(&fcoe_destroy, 0x00, sizeof(struct fcoe_kwqe_destroy));
  121. fcoe_destroy.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY;
  122. fcoe_destroy.hdr.flags = (FCOE_KWQE_LAYER_CODE <<
  123. FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  124. kwqe_arr[0] = (struct kwqe *) &fcoe_destroy;
  125. if (hba->cnic && hba->cnic->submit_kwqes)
  126. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  127. return rc;
  128. }
  129. /**
  130. * bnx2fc_send_session_ofld_req - initiates FCoE Session offload process
  131. *
  132. * @port: port structure pointer
  133. * @tgt: bnx2fc_rport structure pointer
  134. */
  135. int bnx2fc_send_session_ofld_req(struct fcoe_port *port,
  136. struct bnx2fc_rport *tgt)
  137. {
  138. struct fc_lport *lport = port->lport;
  139. struct bnx2fc_interface *interface = port->priv;
  140. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  141. struct bnx2fc_hba *hba = interface->hba;
  142. struct kwqe *kwqe_arr[4];
  143. struct fcoe_kwqe_conn_offload1 ofld_req1;
  144. struct fcoe_kwqe_conn_offload2 ofld_req2;
  145. struct fcoe_kwqe_conn_offload3 ofld_req3;
  146. struct fcoe_kwqe_conn_offload4 ofld_req4;
  147. struct fc_rport_priv *rdata = tgt->rdata;
  148. struct fc_rport *rport = tgt->rport;
  149. int num_kwqes = 4;
  150. u32 port_id;
  151. int rc = 0;
  152. u16 conn_id;
  153. /* Initialize offload request 1 structure */
  154. memset(&ofld_req1, 0x00, sizeof(struct fcoe_kwqe_conn_offload1));
  155. ofld_req1.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN1;
  156. ofld_req1.hdr.flags =
  157. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  158. conn_id = (u16)tgt->fcoe_conn_id;
  159. ofld_req1.fcoe_conn_id = conn_id;
  160. ofld_req1.sq_addr_lo = (u32) tgt->sq_dma;
  161. ofld_req1.sq_addr_hi = (u32)((u64) tgt->sq_dma >> 32);
  162. ofld_req1.rq_pbl_addr_lo = (u32) tgt->rq_pbl_dma;
  163. ofld_req1.rq_pbl_addr_hi = (u32)((u64) tgt->rq_pbl_dma >> 32);
  164. ofld_req1.rq_first_pbe_addr_lo = (u32) tgt->rq_dma;
  165. ofld_req1.rq_first_pbe_addr_hi =
  166. (u32)((u64) tgt->rq_dma >> 32);
  167. ofld_req1.rq_prod = 0x8000;
  168. /* Initialize offload request 2 structure */
  169. memset(&ofld_req2, 0x00, sizeof(struct fcoe_kwqe_conn_offload2));
  170. ofld_req2.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN2;
  171. ofld_req2.hdr.flags =
  172. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  173. ofld_req2.tx_max_fc_pay_len = rdata->maxframe_size;
  174. ofld_req2.cq_addr_lo = (u32) tgt->cq_dma;
  175. ofld_req2.cq_addr_hi = (u32)((u64)tgt->cq_dma >> 32);
  176. ofld_req2.xferq_addr_lo = (u32) tgt->xferq_dma;
  177. ofld_req2.xferq_addr_hi = (u32)((u64)tgt->xferq_dma >> 32);
  178. ofld_req2.conn_db_addr_lo = (u32)tgt->conn_db_dma;
  179. ofld_req2.conn_db_addr_hi = (u32)((u64)tgt->conn_db_dma >> 32);
  180. /* Initialize offload request 3 structure */
  181. memset(&ofld_req3, 0x00, sizeof(struct fcoe_kwqe_conn_offload3));
  182. ofld_req3.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN3;
  183. ofld_req3.hdr.flags =
  184. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  185. ofld_req3.vlan_tag = interface->vlan_id <<
  186. FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT;
  187. ofld_req3.vlan_tag |= 3 << FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT;
  188. port_id = fc_host_port_id(lport->host);
  189. if (port_id == 0) {
  190. BNX2FC_HBA_DBG(lport, "ofld_req: port_id = 0, link down?\n");
  191. return -EINVAL;
  192. }
  193. /*
  194. * Store s_id of the initiator for further reference. This will
  195. * be used during disable/destroy during linkdown processing as
  196. * when the lport is reset, the port_id also is reset to 0
  197. */
  198. tgt->sid = port_id;
  199. ofld_req3.s_id[0] = (port_id & 0x000000FF);
  200. ofld_req3.s_id[1] = (port_id & 0x0000FF00) >> 8;
  201. ofld_req3.s_id[2] = (port_id & 0x00FF0000) >> 16;
  202. port_id = rport->port_id;
  203. ofld_req3.d_id[0] = (port_id & 0x000000FF);
  204. ofld_req3.d_id[1] = (port_id & 0x0000FF00) >> 8;
  205. ofld_req3.d_id[2] = (port_id & 0x00FF0000) >> 16;
  206. ofld_req3.tx_total_conc_seqs = rdata->max_seq;
  207. ofld_req3.tx_max_conc_seqs_c3 = rdata->max_seq;
  208. ofld_req3.rx_max_fc_pay_len = lport->mfs;
  209. ofld_req3.rx_total_conc_seqs = BNX2FC_MAX_SEQS;
  210. ofld_req3.rx_max_conc_seqs_c3 = BNX2FC_MAX_SEQS;
  211. ofld_req3.rx_open_seqs_exch_c3 = 1;
  212. ofld_req3.confq_first_pbe_addr_lo = tgt->confq_dma;
  213. ofld_req3.confq_first_pbe_addr_hi = (u32)((u64) tgt->confq_dma >> 32);
  214. /* set mul_n_port_ids supported flag to 0, until it is supported */
  215. ofld_req3.flags = 0;
  216. /*
  217. ofld_req3.flags |= (((lport->send_sp_features & FC_SP_FT_MNA) ? 1:0) <<
  218. FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT);
  219. */
  220. /* Info from PLOGI response */
  221. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_EDTR) ? 1 : 0) <<
  222. FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT);
  223. ofld_req3.flags |= (((rdata->sp_features & FC_SP_FT_SEQC) ? 1 : 0) <<
  224. FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT);
  225. /*
  226. * Info from PRLI response, this info is used for sequence level error
  227. * recovery support
  228. */
  229. if (tgt->dev_type == TYPE_TAPE) {
  230. ofld_req3.flags |= 1 <<
  231. FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT;
  232. ofld_req3.flags |= (((rdata->flags & FC_RP_FLAGS_REC_SUPPORTED)
  233. ? 1 : 0) <<
  234. FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT);
  235. }
  236. /* vlan flag */
  237. ofld_req3.flags |= (interface->vlan_enabled <<
  238. FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT);
  239. /* C2_VALID and ACK flags are not set as they are not supported */
  240. /* Initialize offload request 4 structure */
  241. memset(&ofld_req4, 0x00, sizeof(struct fcoe_kwqe_conn_offload4));
  242. ofld_req4.hdr.op_code = FCOE_KWQE_OPCODE_OFFLOAD_CONN4;
  243. ofld_req4.hdr.flags =
  244. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  245. ofld_req4.e_d_tov_timer_val = lport->e_d_tov / 20;
  246. ofld_req4.src_mac_addr_lo[0] = port->data_src_addr[5];
  247. /* local mac */
  248. ofld_req4.src_mac_addr_lo[1] = port->data_src_addr[4];
  249. ofld_req4.src_mac_addr_mid[0] = port->data_src_addr[3];
  250. ofld_req4.src_mac_addr_mid[1] = port->data_src_addr[2];
  251. ofld_req4.src_mac_addr_hi[0] = port->data_src_addr[1];
  252. ofld_req4.src_mac_addr_hi[1] = port->data_src_addr[0];
  253. ofld_req4.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  254. /* fcf mac */
  255. ofld_req4.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  256. ofld_req4.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  257. ofld_req4.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  258. ofld_req4.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  259. ofld_req4.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  260. ofld_req4.lcq_addr_lo = (u32) tgt->lcq_dma;
  261. ofld_req4.lcq_addr_hi = (u32)((u64) tgt->lcq_dma >> 32);
  262. ofld_req4.confq_pbl_base_addr_lo = (u32) tgt->confq_pbl_dma;
  263. ofld_req4.confq_pbl_base_addr_hi =
  264. (u32)((u64) tgt->confq_pbl_dma >> 32);
  265. kwqe_arr[0] = (struct kwqe *) &ofld_req1;
  266. kwqe_arr[1] = (struct kwqe *) &ofld_req2;
  267. kwqe_arr[2] = (struct kwqe *) &ofld_req3;
  268. kwqe_arr[3] = (struct kwqe *) &ofld_req4;
  269. if (hba->cnic && hba->cnic->submit_kwqes)
  270. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  271. return rc;
  272. }
  273. /**
  274. * bnx2fc_send_session_enable_req - initiates FCoE Session enablement
  275. *
  276. * @port: port structure pointer
  277. * @tgt: bnx2fc_rport structure pointer
  278. */
  279. static int bnx2fc_send_session_enable_req(struct fcoe_port *port,
  280. struct bnx2fc_rport *tgt)
  281. {
  282. struct kwqe *kwqe_arr[2];
  283. struct bnx2fc_interface *interface = port->priv;
  284. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  285. struct bnx2fc_hba *hba = interface->hba;
  286. struct fcoe_kwqe_conn_enable_disable enbl_req;
  287. struct fc_lport *lport = port->lport;
  288. struct fc_rport *rport = tgt->rport;
  289. int num_kwqes = 1;
  290. int rc = 0;
  291. u32 port_id;
  292. memset(&enbl_req, 0x00,
  293. sizeof(struct fcoe_kwqe_conn_enable_disable));
  294. enbl_req.hdr.op_code = FCOE_KWQE_OPCODE_ENABLE_CONN;
  295. enbl_req.hdr.flags =
  296. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  297. enbl_req.src_mac_addr_lo[0] = port->data_src_addr[5];
  298. /* local mac */
  299. enbl_req.src_mac_addr_lo[1] = port->data_src_addr[4];
  300. enbl_req.src_mac_addr_mid[0] = port->data_src_addr[3];
  301. enbl_req.src_mac_addr_mid[1] = port->data_src_addr[2];
  302. enbl_req.src_mac_addr_hi[0] = port->data_src_addr[1];
  303. enbl_req.src_mac_addr_hi[1] = port->data_src_addr[0];
  304. memcpy(tgt->src_addr, port->data_src_addr, ETH_ALEN);
  305. enbl_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  306. enbl_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  307. enbl_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  308. enbl_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  309. enbl_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  310. enbl_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  311. port_id = fc_host_port_id(lport->host);
  312. if (port_id != tgt->sid) {
  313. printk(KERN_ERR PFX "WARN: enable_req port_id = 0x%x,"
  314. "sid = 0x%x\n", port_id, tgt->sid);
  315. port_id = tgt->sid;
  316. }
  317. enbl_req.s_id[0] = (port_id & 0x000000FF);
  318. enbl_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  319. enbl_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  320. port_id = rport->port_id;
  321. enbl_req.d_id[0] = (port_id & 0x000000FF);
  322. enbl_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  323. enbl_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  324. enbl_req.vlan_tag = interface->vlan_id <<
  325. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  326. enbl_req.vlan_tag |= 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  327. enbl_req.vlan_flag = interface->vlan_enabled;
  328. enbl_req.context_id = tgt->context_id;
  329. enbl_req.conn_id = tgt->fcoe_conn_id;
  330. kwqe_arr[0] = (struct kwqe *) &enbl_req;
  331. if (hba->cnic && hba->cnic->submit_kwqes)
  332. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  333. return rc;
  334. }
  335. /**
  336. * bnx2fc_send_session_disable_req - initiates FCoE Session disable
  337. *
  338. * @port: port structure pointer
  339. * @tgt: bnx2fc_rport structure pointer
  340. */
  341. int bnx2fc_send_session_disable_req(struct fcoe_port *port,
  342. struct bnx2fc_rport *tgt)
  343. {
  344. struct bnx2fc_interface *interface = port->priv;
  345. struct fcoe_ctlr *ctlr = bnx2fc_to_ctlr(interface);
  346. struct bnx2fc_hba *hba = interface->hba;
  347. struct fcoe_kwqe_conn_enable_disable disable_req;
  348. struct kwqe *kwqe_arr[2];
  349. struct fc_rport *rport = tgt->rport;
  350. int num_kwqes = 1;
  351. int rc = 0;
  352. u32 port_id;
  353. memset(&disable_req, 0x00,
  354. sizeof(struct fcoe_kwqe_conn_enable_disable));
  355. disable_req.hdr.op_code = FCOE_KWQE_OPCODE_DISABLE_CONN;
  356. disable_req.hdr.flags =
  357. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  358. disable_req.src_mac_addr_lo[0] = tgt->src_addr[5];
  359. disable_req.src_mac_addr_lo[1] = tgt->src_addr[4];
  360. disable_req.src_mac_addr_mid[0] = tgt->src_addr[3];
  361. disable_req.src_mac_addr_mid[1] = tgt->src_addr[2];
  362. disable_req.src_mac_addr_hi[0] = tgt->src_addr[1];
  363. disable_req.src_mac_addr_hi[1] = tgt->src_addr[0];
  364. disable_req.dst_mac_addr_lo[0] = ctlr->dest_addr[5];
  365. disable_req.dst_mac_addr_lo[1] = ctlr->dest_addr[4];
  366. disable_req.dst_mac_addr_mid[0] = ctlr->dest_addr[3];
  367. disable_req.dst_mac_addr_mid[1] = ctlr->dest_addr[2];
  368. disable_req.dst_mac_addr_hi[0] = ctlr->dest_addr[1];
  369. disable_req.dst_mac_addr_hi[1] = ctlr->dest_addr[0];
  370. port_id = tgt->sid;
  371. disable_req.s_id[0] = (port_id & 0x000000FF);
  372. disable_req.s_id[1] = (port_id & 0x0000FF00) >> 8;
  373. disable_req.s_id[2] = (port_id & 0x00FF0000) >> 16;
  374. port_id = rport->port_id;
  375. disable_req.d_id[0] = (port_id & 0x000000FF);
  376. disable_req.d_id[1] = (port_id & 0x0000FF00) >> 8;
  377. disable_req.d_id[2] = (port_id & 0x00FF0000) >> 16;
  378. disable_req.context_id = tgt->context_id;
  379. disable_req.conn_id = tgt->fcoe_conn_id;
  380. disable_req.vlan_tag = interface->vlan_id <<
  381. FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT;
  382. disable_req.vlan_tag |=
  383. 3 << FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT;
  384. disable_req.vlan_flag = interface->vlan_enabled;
  385. kwqe_arr[0] = (struct kwqe *) &disable_req;
  386. if (hba->cnic && hba->cnic->submit_kwqes)
  387. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  388. return rc;
  389. }
  390. /**
  391. * bnx2fc_send_session_destroy_req - initiates FCoE Session destroy
  392. *
  393. * @port: port structure pointer
  394. * @tgt: bnx2fc_rport structure pointer
  395. */
  396. int bnx2fc_send_session_destroy_req(struct bnx2fc_hba *hba,
  397. struct bnx2fc_rport *tgt)
  398. {
  399. struct fcoe_kwqe_conn_destroy destroy_req;
  400. struct kwqe *kwqe_arr[2];
  401. int num_kwqes = 1;
  402. int rc = 0;
  403. memset(&destroy_req, 0x00, sizeof(struct fcoe_kwqe_conn_destroy));
  404. destroy_req.hdr.op_code = FCOE_KWQE_OPCODE_DESTROY_CONN;
  405. destroy_req.hdr.flags =
  406. (FCOE_KWQE_LAYER_CODE << FCOE_KWQE_HEADER_LAYER_CODE_SHIFT);
  407. destroy_req.context_id = tgt->context_id;
  408. destroy_req.conn_id = tgt->fcoe_conn_id;
  409. kwqe_arr[0] = (struct kwqe *) &destroy_req;
  410. if (hba->cnic && hba->cnic->submit_kwqes)
  411. rc = hba->cnic->submit_kwqes(hba->cnic, kwqe_arr, num_kwqes);
  412. return rc;
  413. }
  414. static bool is_valid_lport(struct bnx2fc_hba *hba, struct fc_lport *lport)
  415. {
  416. struct bnx2fc_lport *blport;
  417. spin_lock_bh(&hba->hba_lock);
  418. list_for_each_entry(blport, &hba->vports, list) {
  419. if (blport->lport == lport) {
  420. spin_unlock_bh(&hba->hba_lock);
  421. return true;
  422. }
  423. }
  424. spin_unlock_bh(&hba->hba_lock);
  425. return false;
  426. }
  427. static void bnx2fc_unsol_els_work(struct work_struct *work)
  428. {
  429. struct bnx2fc_unsol_els *unsol_els;
  430. struct fc_lport *lport;
  431. struct bnx2fc_hba *hba;
  432. struct fc_frame *fp;
  433. unsol_els = container_of(work, struct bnx2fc_unsol_els, unsol_els_work);
  434. lport = unsol_els->lport;
  435. fp = unsol_els->fp;
  436. hba = unsol_els->hba;
  437. if (is_valid_lport(hba, lport))
  438. fc_exch_recv(lport, fp);
  439. kfree(unsol_els);
  440. }
  441. void bnx2fc_process_l2_frame_compl(struct bnx2fc_rport *tgt,
  442. unsigned char *buf,
  443. u32 frame_len, u16 l2_oxid)
  444. {
  445. struct fcoe_port *port = tgt->port;
  446. struct fc_lport *lport = port->lport;
  447. struct bnx2fc_interface *interface = port->priv;
  448. struct bnx2fc_unsol_els *unsol_els;
  449. struct fc_frame_header *fh;
  450. struct fc_frame *fp;
  451. struct sk_buff *skb;
  452. u32 payload_len;
  453. u32 crc;
  454. u8 op;
  455. unsol_els = kzalloc(sizeof(*unsol_els), GFP_ATOMIC);
  456. if (!unsol_els) {
  457. BNX2FC_TGT_DBG(tgt, "Unable to allocate unsol_work\n");
  458. return;
  459. }
  460. BNX2FC_TGT_DBG(tgt, "l2_frame_compl l2_oxid = 0x%x, frame_len = %d\n",
  461. l2_oxid, frame_len);
  462. payload_len = frame_len - sizeof(struct fc_frame_header);
  463. fp = fc_frame_alloc(lport, payload_len);
  464. if (!fp) {
  465. printk(KERN_ERR PFX "fc_frame_alloc failure\n");
  466. kfree(unsol_els);
  467. return;
  468. }
  469. fh = (struct fc_frame_header *) fc_frame_header_get(fp);
  470. /* Copy FC Frame header and payload into the frame */
  471. memcpy(fh, buf, frame_len);
  472. if (l2_oxid != FC_XID_UNKNOWN)
  473. fh->fh_ox_id = htons(l2_oxid);
  474. skb = fp_skb(fp);
  475. if ((fh->fh_r_ctl == FC_RCTL_ELS_REQ) ||
  476. (fh->fh_r_ctl == FC_RCTL_ELS_REP)) {
  477. if (fh->fh_type == FC_TYPE_ELS) {
  478. op = fc_frame_payload_op(fp);
  479. if ((op == ELS_TEST) || (op == ELS_ESTC) ||
  480. (op == ELS_FAN) || (op == ELS_CSU)) {
  481. /*
  482. * No need to reply for these
  483. * ELS requests
  484. */
  485. printk(KERN_ERR PFX "dropping ELS 0x%x\n", op);
  486. kfree_skb(skb);
  487. kfree(unsol_els);
  488. return;
  489. }
  490. }
  491. crc = fcoe_fc_crc(fp);
  492. fc_frame_init(fp);
  493. fr_dev(fp) = lport;
  494. fr_sof(fp) = FC_SOF_I3;
  495. fr_eof(fp) = FC_EOF_T;
  496. fr_crc(fp) = cpu_to_le32(~crc);
  497. unsol_els->lport = lport;
  498. unsol_els->hba = interface->hba;
  499. unsol_els->fp = fp;
  500. INIT_WORK(&unsol_els->unsol_els_work, bnx2fc_unsol_els_work);
  501. queue_work(bnx2fc_wq, &unsol_els->unsol_els_work);
  502. } else {
  503. BNX2FC_HBA_DBG(lport, "fh_r_ctl = 0x%x\n", fh->fh_r_ctl);
  504. kfree_skb(skb);
  505. kfree(unsol_els);
  506. }
  507. }
  508. static void bnx2fc_process_unsol_compl(struct bnx2fc_rport *tgt, u16 wqe)
  509. {
  510. u8 num_rq;
  511. struct fcoe_err_report_entry *err_entry;
  512. unsigned char *rq_data;
  513. unsigned char *buf = NULL, *buf1;
  514. int i;
  515. u16 xid;
  516. u32 frame_len, len;
  517. struct bnx2fc_cmd *io_req = NULL;
  518. struct fcoe_task_ctx_entry *task, *task_page;
  519. struct bnx2fc_interface *interface = tgt->port->priv;
  520. struct bnx2fc_hba *hba = interface->hba;
  521. int task_idx, index;
  522. int rc = 0;
  523. u64 err_warn_bit_map;
  524. u8 err_warn = 0xff;
  525. BNX2FC_TGT_DBG(tgt, "Entered UNSOL COMPLETION wqe = 0x%x\n", wqe);
  526. switch (wqe & FCOE_UNSOLICITED_CQE_SUBTYPE) {
  527. case FCOE_UNSOLICITED_FRAME_CQE_TYPE:
  528. frame_len = (wqe & FCOE_UNSOLICITED_CQE_PKT_LEN) >>
  529. FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT;
  530. num_rq = (frame_len + BNX2FC_RQ_BUF_SZ - 1) / BNX2FC_RQ_BUF_SZ;
  531. spin_lock_bh(&tgt->tgt_lock);
  532. rq_data = (unsigned char *)bnx2fc_get_next_rqe(tgt, num_rq);
  533. spin_unlock_bh(&tgt->tgt_lock);
  534. if (rq_data) {
  535. buf = rq_data;
  536. } else {
  537. buf1 = buf = kmalloc((num_rq * BNX2FC_RQ_BUF_SZ),
  538. GFP_ATOMIC);
  539. if (!buf1) {
  540. BNX2FC_TGT_DBG(tgt, "Memory alloc failure\n");
  541. break;
  542. }
  543. for (i = 0; i < num_rq; i++) {
  544. spin_lock_bh(&tgt->tgt_lock);
  545. rq_data = (unsigned char *)
  546. bnx2fc_get_next_rqe(tgt, 1);
  547. spin_unlock_bh(&tgt->tgt_lock);
  548. len = BNX2FC_RQ_BUF_SZ;
  549. memcpy(buf1, rq_data, len);
  550. buf1 += len;
  551. }
  552. }
  553. bnx2fc_process_l2_frame_compl(tgt, buf, frame_len,
  554. FC_XID_UNKNOWN);
  555. if (buf != rq_data)
  556. kfree(buf);
  557. spin_lock_bh(&tgt->tgt_lock);
  558. bnx2fc_return_rqe(tgt, num_rq);
  559. spin_unlock_bh(&tgt->tgt_lock);
  560. break;
  561. case FCOE_ERROR_DETECTION_CQE_TYPE:
  562. /*
  563. * In case of error reporting CQE a single RQ entry
  564. * is consumed.
  565. */
  566. spin_lock_bh(&tgt->tgt_lock);
  567. num_rq = 1;
  568. err_entry = (struct fcoe_err_report_entry *)
  569. bnx2fc_get_next_rqe(tgt, 1);
  570. xid = err_entry->fc_hdr.ox_id;
  571. BNX2FC_TGT_DBG(tgt, "Unsol Error Frame OX_ID = 0x%x\n", xid);
  572. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x\n",
  573. err_entry->data.err_warn_bitmap_hi,
  574. err_entry->data.err_warn_bitmap_lo);
  575. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x\n",
  576. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  577. if (xid > BNX2FC_MAX_XID) {
  578. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n",
  579. xid);
  580. goto ret_err_rqe;
  581. }
  582. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  583. index = xid % BNX2FC_TASKS_PER_PAGE;
  584. task_page = (struct fcoe_task_ctx_entry *)
  585. hba->task_ctx[task_idx];
  586. task = &(task_page[index]);
  587. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  588. if (!io_req)
  589. goto ret_err_rqe;
  590. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  591. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  592. goto ret_err_rqe;
  593. }
  594. if (test_and_clear_bit(BNX2FC_FLAG_IO_CLEANUP,
  595. &io_req->req_flags)) {
  596. BNX2FC_IO_DBG(io_req, "unsol_err: cleanup in "
  597. "progress.. ignore unsol err\n");
  598. goto ret_err_rqe;
  599. }
  600. err_warn_bit_map = (u64)
  601. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  602. (u64)err_entry->data.err_warn_bitmap_lo;
  603. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  604. if (err_warn_bit_map & (u64)((u64)1 << i)) {
  605. err_warn = i;
  606. break;
  607. }
  608. }
  609. /*
  610. * If ABTS is already in progress, and FW error is
  611. * received after that, do not cancel the timeout_work
  612. * and let the error recovery continue by explicitly
  613. * logging out the target, when the ABTS eventually
  614. * times out.
  615. */
  616. if (test_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags)) {
  617. printk(KERN_ERR PFX "err_warn: io_req (0x%x) already "
  618. "in ABTS processing\n", xid);
  619. goto ret_err_rqe;
  620. }
  621. BNX2FC_TGT_DBG(tgt, "err = 0x%x\n", err_warn);
  622. if (tgt->dev_type != TYPE_TAPE)
  623. goto skip_rec;
  624. switch (err_warn) {
  625. case FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION:
  626. case FCOE_ERROR_CODE_DATA_OOO_RO:
  627. case FCOE_ERROR_CODE_COMMON_INCORRECT_SEQ_CNT:
  628. case FCOE_ERROR_CODE_DATA_SOFI3_SEQ_ACTIVE_SET:
  629. case FCOE_ERROR_CODE_FCP_RSP_OPENED_SEQ:
  630. case FCOE_ERROR_CODE_DATA_SOFN_SEQ_ACTIVE_RESET:
  631. BNX2FC_TGT_DBG(tgt, "REC TOV popped for xid - 0x%x\n",
  632. xid);
  633. memset(&io_req->err_entry, 0,
  634. sizeof(struct fcoe_err_report_entry));
  635. memcpy(&io_req->err_entry, err_entry,
  636. sizeof(struct fcoe_err_report_entry));
  637. if (!test_bit(BNX2FC_FLAG_SRR_SENT,
  638. &io_req->req_flags)) {
  639. spin_unlock_bh(&tgt->tgt_lock);
  640. rc = bnx2fc_send_rec(io_req);
  641. spin_lock_bh(&tgt->tgt_lock);
  642. if (rc)
  643. goto skip_rec;
  644. } else
  645. printk(KERN_ERR PFX "SRR in progress\n");
  646. goto ret_err_rqe;
  647. break;
  648. default:
  649. break;
  650. }
  651. skip_rec:
  652. set_bit(BNX2FC_FLAG_ISSUE_ABTS, &io_req->req_flags);
  653. /*
  654. * Cancel the timeout_work, as we received IO
  655. * completion with FW error.
  656. */
  657. if (cancel_delayed_work(&io_req->timeout_work))
  658. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  659. rc = bnx2fc_initiate_abts(io_req);
  660. if (rc != SUCCESS) {
  661. printk(KERN_ERR PFX "err_warn: initiate_abts "
  662. "failed xid = 0x%x. issue cleanup\n",
  663. io_req->xid);
  664. bnx2fc_initiate_cleanup(io_req);
  665. }
  666. ret_err_rqe:
  667. bnx2fc_return_rqe(tgt, 1);
  668. spin_unlock_bh(&tgt->tgt_lock);
  669. break;
  670. case FCOE_WARNING_DETECTION_CQE_TYPE:
  671. /*
  672. *In case of warning reporting CQE a single RQ entry
  673. * is consumes.
  674. */
  675. spin_lock_bh(&tgt->tgt_lock);
  676. num_rq = 1;
  677. err_entry = (struct fcoe_err_report_entry *)
  678. bnx2fc_get_next_rqe(tgt, 1);
  679. xid = cpu_to_be16(err_entry->fc_hdr.ox_id);
  680. BNX2FC_TGT_DBG(tgt, "Unsol Warning Frame OX_ID = 0x%x\n", xid);
  681. BNX2FC_TGT_DBG(tgt, "err_warn_bitmap = %08x:%08x",
  682. err_entry->data.err_warn_bitmap_hi,
  683. err_entry->data.err_warn_bitmap_lo);
  684. BNX2FC_TGT_DBG(tgt, "buf_offsets - tx = 0x%x, rx = 0x%x",
  685. err_entry->data.tx_buf_off, err_entry->data.rx_buf_off);
  686. if (xid > BNX2FC_MAX_XID) {
  687. BNX2FC_TGT_DBG(tgt, "xid(0x%x) out of FW range\n", xid);
  688. goto ret_warn_rqe;
  689. }
  690. err_warn_bit_map = (u64)
  691. ((u64)err_entry->data.err_warn_bitmap_hi << 32) |
  692. (u64)err_entry->data.err_warn_bitmap_lo;
  693. for (i = 0; i < BNX2FC_NUM_ERR_BITS; i++) {
  694. if (err_warn_bit_map & (u64) (1 << i)) {
  695. err_warn = i;
  696. break;
  697. }
  698. }
  699. BNX2FC_TGT_DBG(tgt, "warn = 0x%x\n", err_warn);
  700. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  701. index = xid % BNX2FC_TASKS_PER_PAGE;
  702. task_page = (struct fcoe_task_ctx_entry *)
  703. interface->hba->task_ctx[task_idx];
  704. task = &(task_page[index]);
  705. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  706. if (!io_req)
  707. goto ret_warn_rqe;
  708. if (io_req->cmd_type != BNX2FC_SCSI_CMD) {
  709. printk(KERN_ERR PFX "err_warn: Not a SCSI cmd\n");
  710. goto ret_warn_rqe;
  711. }
  712. memset(&io_req->err_entry, 0,
  713. sizeof(struct fcoe_err_report_entry));
  714. memcpy(&io_req->err_entry, err_entry,
  715. sizeof(struct fcoe_err_report_entry));
  716. if (err_warn == FCOE_ERROR_CODE_REC_TOV_TIMER_EXPIRATION)
  717. /* REC_TOV is not a warning code */
  718. BUG_ON(1);
  719. else
  720. BNX2FC_TGT_DBG(tgt, "Unsolicited warning\n");
  721. ret_warn_rqe:
  722. bnx2fc_return_rqe(tgt, 1);
  723. spin_unlock_bh(&tgt->tgt_lock);
  724. break;
  725. default:
  726. printk(KERN_ERR PFX "Unsol Compl: Invalid CQE Subtype\n");
  727. break;
  728. }
  729. }
  730. void bnx2fc_process_cq_compl(struct bnx2fc_rport *tgt, u16 wqe)
  731. {
  732. struct fcoe_task_ctx_entry *task;
  733. struct fcoe_task_ctx_entry *task_page;
  734. struct fcoe_port *port = tgt->port;
  735. struct bnx2fc_interface *interface = port->priv;
  736. struct bnx2fc_hba *hba = interface->hba;
  737. struct bnx2fc_cmd *io_req;
  738. int task_idx, index;
  739. u16 xid;
  740. u8 cmd_type;
  741. u8 rx_state = 0;
  742. u8 num_rq;
  743. spin_lock_bh(&tgt->tgt_lock);
  744. xid = wqe & FCOE_PEND_WQ_CQE_TASK_ID;
  745. if (xid >= BNX2FC_MAX_TASKS) {
  746. printk(KERN_ERR PFX "ERROR:xid out of range\n");
  747. spin_unlock_bh(&tgt->tgt_lock);
  748. return;
  749. }
  750. task_idx = xid / BNX2FC_TASKS_PER_PAGE;
  751. index = xid % BNX2FC_TASKS_PER_PAGE;
  752. task_page = (struct fcoe_task_ctx_entry *)hba->task_ctx[task_idx];
  753. task = &(task_page[index]);
  754. num_rq = ((task->rxwr_txrd.var_ctx.rx_flags &
  755. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE) >>
  756. FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT);
  757. io_req = (struct bnx2fc_cmd *)hba->cmd_mgr->cmds[xid];
  758. if (io_req == NULL) {
  759. printk(KERN_ERR PFX "ERROR? cq_compl - io_req is NULL\n");
  760. spin_unlock_bh(&tgt->tgt_lock);
  761. return;
  762. }
  763. /* Timestamp IO completion time */
  764. cmd_type = io_req->cmd_type;
  765. rx_state = ((task->rxwr_txrd.var_ctx.rx_flags &
  766. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE) >>
  767. FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT);
  768. /* Process other IO completion types */
  769. switch (cmd_type) {
  770. case BNX2FC_SCSI_CMD:
  771. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED) {
  772. bnx2fc_process_scsi_cmd_compl(io_req, task, num_rq);
  773. spin_unlock_bh(&tgt->tgt_lock);
  774. return;
  775. }
  776. if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  777. bnx2fc_process_abts_compl(io_req, task, num_rq);
  778. else if (rx_state ==
  779. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  780. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  781. else
  782. printk(KERN_ERR PFX "Invalid rx state - %d\n",
  783. rx_state);
  784. break;
  785. case BNX2FC_TASK_MGMT_CMD:
  786. BNX2FC_IO_DBG(io_req, "Processing TM complete\n");
  787. bnx2fc_process_tm_compl(io_req, task, num_rq);
  788. break;
  789. case BNX2FC_ABTS:
  790. /*
  791. * ABTS request received by firmware. ABTS response
  792. * will be delivered to the task belonging to the IO
  793. * that was aborted
  794. */
  795. BNX2FC_IO_DBG(io_req, "cq_compl- ABTS sent out by fw\n");
  796. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  797. break;
  798. case BNX2FC_ELS:
  799. if (rx_state == FCOE_TASK_RX_STATE_COMPLETED)
  800. bnx2fc_process_els_compl(io_req, task, num_rq);
  801. else if (rx_state == FCOE_TASK_RX_STATE_ABTS_COMPLETED)
  802. bnx2fc_process_abts_compl(io_req, task, num_rq);
  803. else if (rx_state ==
  804. FCOE_TASK_RX_STATE_EXCHANGE_CLEANUP_COMPLETED)
  805. bnx2fc_process_cleanup_compl(io_req, task, num_rq);
  806. else
  807. printk(KERN_ERR PFX "Invalid rx state = %d\n",
  808. rx_state);
  809. break;
  810. case BNX2FC_CLEANUP:
  811. BNX2FC_IO_DBG(io_req, "cq_compl- cleanup resp rcvd\n");
  812. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  813. break;
  814. case BNX2FC_SEQ_CLEANUP:
  815. BNX2FC_IO_DBG(io_req, "cq_compl(0x%x) - seq cleanup resp\n",
  816. io_req->xid);
  817. bnx2fc_process_seq_cleanup_compl(io_req, task, rx_state);
  818. kref_put(&io_req->refcount, bnx2fc_cmd_release);
  819. break;
  820. default:
  821. printk(KERN_ERR PFX "Invalid cmd_type %d\n", cmd_type);
  822. break;
  823. }
  824. spin_unlock_bh(&tgt->tgt_lock);
  825. }
  826. void bnx2fc_arm_cq(struct bnx2fc_rport *tgt)
  827. {
  828. struct b577xx_fcoe_rx_doorbell *rx_db = &tgt->rx_db;
  829. u32 msg;
  830. wmb();
  831. rx_db->doorbell_cq_cons = tgt->cq_cons_idx | (tgt->cq_curr_toggle_bit <<
  832. FCOE_CQE_TOGGLE_BIT_SHIFT);
  833. msg = *((u32 *)rx_db);
  834. writel(cpu_to_le32(msg), tgt->ctx_base);
  835. mmiowb();
  836. }
  837. struct bnx2fc_work *bnx2fc_alloc_work(struct bnx2fc_rport *tgt, u16 wqe)
  838. {
  839. struct bnx2fc_work *work;
  840. work = kzalloc(sizeof(struct bnx2fc_work), GFP_ATOMIC);
  841. if (!work)
  842. return NULL;
  843. INIT_LIST_HEAD(&work->list);
  844. work->tgt = tgt;
  845. work->wqe = wqe;
  846. return work;
  847. }
  848. int bnx2fc_process_new_cqes(struct bnx2fc_rport *tgt)
  849. {
  850. struct fcoe_cqe *cq;
  851. u32 cq_cons;
  852. struct fcoe_cqe *cqe;
  853. u32 num_free_sqes = 0;
  854. u32 num_cqes = 0;
  855. u16 wqe;
  856. /*
  857. * cq_lock is a low contention lock used to protect
  858. * the CQ data structure from being freed up during
  859. * the upload operation
  860. */
  861. spin_lock_bh(&tgt->cq_lock);
  862. if (!tgt->cq) {
  863. printk(KERN_ERR PFX "process_new_cqes: cq is NULL\n");
  864. spin_unlock_bh(&tgt->cq_lock);
  865. return 0;
  866. }
  867. cq = tgt->cq;
  868. cq_cons = tgt->cq_cons_idx;
  869. cqe = &cq[cq_cons];
  870. while (((wqe = cqe->wqe) & FCOE_CQE_TOGGLE_BIT) ==
  871. (tgt->cq_curr_toggle_bit <<
  872. FCOE_CQE_TOGGLE_BIT_SHIFT)) {
  873. /* new entry on the cq */
  874. if (wqe & FCOE_CQE_CQE_TYPE) {
  875. /* Unsolicited event notification */
  876. bnx2fc_process_unsol_compl(tgt, wqe);
  877. } else {
  878. /* Pending work request completion */
  879. struct bnx2fc_work *work = NULL;
  880. struct bnx2fc_percpu_s *fps = NULL;
  881. unsigned int cpu = wqe % num_possible_cpus();
  882. fps = &per_cpu(bnx2fc_percpu, cpu);
  883. spin_lock_bh(&fps->fp_work_lock);
  884. if (unlikely(!fps->iothread))
  885. goto unlock;
  886. work = bnx2fc_alloc_work(tgt, wqe);
  887. if (work)
  888. list_add_tail(&work->list,
  889. &fps->work_list);
  890. unlock:
  891. spin_unlock_bh(&fps->fp_work_lock);
  892. /* Pending work request completion */
  893. if (fps->iothread && work)
  894. wake_up_process(fps->iothread);
  895. else
  896. bnx2fc_process_cq_compl(tgt, wqe);
  897. num_free_sqes++;
  898. }
  899. cqe++;
  900. tgt->cq_cons_idx++;
  901. num_cqes++;
  902. if (tgt->cq_cons_idx == BNX2FC_CQ_WQES_MAX) {
  903. tgt->cq_cons_idx = 0;
  904. cqe = cq;
  905. tgt->cq_curr_toggle_bit =
  906. 1 - tgt->cq_curr_toggle_bit;
  907. }
  908. }
  909. if (num_cqes) {
  910. /* Arm CQ only if doorbell is mapped */
  911. if (tgt->ctx_base)
  912. bnx2fc_arm_cq(tgt);
  913. atomic_add(num_free_sqes, &tgt->free_sqes);
  914. }
  915. spin_unlock_bh(&tgt->cq_lock);
  916. return 0;
  917. }
  918. /**
  919. * bnx2fc_fastpath_notification - process global event queue (KCQ)
  920. *
  921. * @hba: adapter structure pointer
  922. * @new_cqe_kcqe: pointer to newly DMA'd KCQ entry
  923. *
  924. * Fast path event notification handler
  925. */
  926. static void bnx2fc_fastpath_notification(struct bnx2fc_hba *hba,
  927. struct fcoe_kcqe *new_cqe_kcqe)
  928. {
  929. u32 conn_id = new_cqe_kcqe->fcoe_conn_id;
  930. struct bnx2fc_rport *tgt = hba->tgt_ofld_list[conn_id];
  931. if (!tgt) {
  932. printk(KERN_ERR PFX "conn_id 0x%x not valid\n", conn_id);
  933. return;
  934. }
  935. bnx2fc_process_new_cqes(tgt);
  936. }
  937. /**
  938. * bnx2fc_process_ofld_cmpl - process FCoE session offload completion
  939. *
  940. * @hba: adapter structure pointer
  941. * @ofld_kcqe: connection offload kcqe pointer
  942. *
  943. * handle session offload completion, enable the session if offload is
  944. * successful.
  945. */
  946. static void bnx2fc_process_ofld_cmpl(struct bnx2fc_hba *hba,
  947. struct fcoe_kcqe *ofld_kcqe)
  948. {
  949. struct bnx2fc_rport *tgt;
  950. struct fcoe_port *port;
  951. struct bnx2fc_interface *interface;
  952. u32 conn_id;
  953. u32 context_id;
  954. int rc;
  955. conn_id = ofld_kcqe->fcoe_conn_id;
  956. context_id = ofld_kcqe->fcoe_conn_context_id;
  957. tgt = hba->tgt_ofld_list[conn_id];
  958. if (!tgt) {
  959. printk(KERN_ALERT PFX "ERROR:ofld_cmpl: No pending ofld req\n");
  960. return;
  961. }
  962. BNX2FC_TGT_DBG(tgt, "Entered ofld compl - context_id = 0x%x\n",
  963. ofld_kcqe->fcoe_conn_context_id);
  964. port = tgt->port;
  965. interface = tgt->port->priv;
  966. if (hba != interface->hba) {
  967. printk(KERN_ERR PFX "ERROR:ofld_cmpl: HBA mis-match\n");
  968. goto ofld_cmpl_err;
  969. }
  970. /*
  971. * cnic has allocated a context_id for this session; use this
  972. * while enabling the session.
  973. */
  974. tgt->context_id = context_id;
  975. if (ofld_kcqe->completion_status) {
  976. if (ofld_kcqe->completion_status ==
  977. FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE) {
  978. printk(KERN_ERR PFX "unable to allocate FCoE context "
  979. "resources\n");
  980. set_bit(BNX2FC_FLAG_CTX_ALLOC_FAILURE, &tgt->flags);
  981. }
  982. goto ofld_cmpl_err;
  983. } else {
  984. /* now enable the session */
  985. rc = bnx2fc_send_session_enable_req(port, tgt);
  986. if (rc) {
  987. printk(KERN_ERR PFX "enable session failed\n");
  988. goto ofld_cmpl_err;
  989. }
  990. }
  991. return;
  992. ofld_cmpl_err:
  993. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  994. wake_up_interruptible(&tgt->ofld_wait);
  995. }
  996. /**
  997. * bnx2fc_process_enable_conn_cmpl - process FCoE session enable completion
  998. *
  999. * @hba: adapter structure pointer
  1000. * @ofld_kcqe: connection offload kcqe pointer
  1001. *
  1002. * handle session enable completion, mark the rport as ready
  1003. */
  1004. static void bnx2fc_process_enable_conn_cmpl(struct bnx2fc_hba *hba,
  1005. struct fcoe_kcqe *ofld_kcqe)
  1006. {
  1007. struct bnx2fc_rport *tgt;
  1008. struct bnx2fc_interface *interface;
  1009. u32 conn_id;
  1010. u32 context_id;
  1011. context_id = ofld_kcqe->fcoe_conn_context_id;
  1012. conn_id = ofld_kcqe->fcoe_conn_id;
  1013. tgt = hba->tgt_ofld_list[conn_id];
  1014. if (!tgt) {
  1015. printk(KERN_ERR PFX "ERROR:enbl_cmpl: No pending ofld req\n");
  1016. return;
  1017. }
  1018. BNX2FC_TGT_DBG(tgt, "Enable compl - context_id = 0x%x\n",
  1019. ofld_kcqe->fcoe_conn_context_id);
  1020. /*
  1021. * context_id should be the same for this target during offload
  1022. * and enable
  1023. */
  1024. if (tgt->context_id != context_id) {
  1025. printk(KERN_ERR PFX "context id mis-match\n");
  1026. return;
  1027. }
  1028. interface = tgt->port->priv;
  1029. if (hba != interface->hba) {
  1030. printk(KERN_ERR PFX "bnx2fc-enbl_cmpl: HBA mis-match\n");
  1031. goto enbl_cmpl_err;
  1032. }
  1033. if (ofld_kcqe->completion_status)
  1034. goto enbl_cmpl_err;
  1035. else {
  1036. /* enable successful - rport ready for issuing IOs */
  1037. set_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  1038. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  1039. wake_up_interruptible(&tgt->ofld_wait);
  1040. }
  1041. return;
  1042. enbl_cmpl_err:
  1043. set_bit(BNX2FC_FLAG_OFLD_REQ_CMPL, &tgt->flags);
  1044. wake_up_interruptible(&tgt->ofld_wait);
  1045. }
  1046. static void bnx2fc_process_conn_disable_cmpl(struct bnx2fc_hba *hba,
  1047. struct fcoe_kcqe *disable_kcqe)
  1048. {
  1049. struct bnx2fc_rport *tgt;
  1050. u32 conn_id;
  1051. conn_id = disable_kcqe->fcoe_conn_id;
  1052. tgt = hba->tgt_ofld_list[conn_id];
  1053. if (!tgt) {
  1054. printk(KERN_ERR PFX "ERROR: disable_cmpl: No disable req\n");
  1055. return;
  1056. }
  1057. BNX2FC_TGT_DBG(tgt, PFX "disable_cmpl: conn_id %d\n", conn_id);
  1058. if (disable_kcqe->completion_status) {
  1059. printk(KERN_ERR PFX "Disable failed with cmpl status %d\n",
  1060. disable_kcqe->completion_status);
  1061. set_bit(BNX2FC_FLAG_DISABLE_FAILED, &tgt->flags);
  1062. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1063. wake_up_interruptible(&tgt->upld_wait);
  1064. } else {
  1065. /* disable successful */
  1066. BNX2FC_TGT_DBG(tgt, "disable successful\n");
  1067. clear_bit(BNX2FC_FLAG_OFFLOADED, &tgt->flags);
  1068. set_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1069. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1070. wake_up_interruptible(&tgt->upld_wait);
  1071. }
  1072. }
  1073. static void bnx2fc_process_conn_destroy_cmpl(struct bnx2fc_hba *hba,
  1074. struct fcoe_kcqe *destroy_kcqe)
  1075. {
  1076. struct bnx2fc_rport *tgt;
  1077. u32 conn_id;
  1078. conn_id = destroy_kcqe->fcoe_conn_id;
  1079. tgt = hba->tgt_ofld_list[conn_id];
  1080. if (!tgt) {
  1081. printk(KERN_ERR PFX "destroy_cmpl: No destroy req\n");
  1082. return;
  1083. }
  1084. BNX2FC_TGT_DBG(tgt, "destroy_cmpl: conn_id %d\n", conn_id);
  1085. if (destroy_kcqe->completion_status) {
  1086. printk(KERN_ERR PFX "Destroy conn failed, cmpl status %d\n",
  1087. destroy_kcqe->completion_status);
  1088. return;
  1089. } else {
  1090. /* destroy successful */
  1091. BNX2FC_TGT_DBG(tgt, "upload successful\n");
  1092. clear_bit(BNX2FC_FLAG_DISABLED, &tgt->flags);
  1093. set_bit(BNX2FC_FLAG_DESTROYED, &tgt->flags);
  1094. set_bit(BNX2FC_FLAG_UPLD_REQ_COMPL, &tgt->flags);
  1095. wake_up_interruptible(&tgt->upld_wait);
  1096. }
  1097. }
  1098. static void bnx2fc_init_failure(struct bnx2fc_hba *hba, u32 err_code)
  1099. {
  1100. switch (err_code) {
  1101. case FCOE_KCQE_COMPLETION_STATUS_INVALID_OPCODE:
  1102. printk(KERN_ERR PFX "init_failure due to invalid opcode\n");
  1103. break;
  1104. case FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE:
  1105. printk(KERN_ERR PFX "init failed due to ctx alloc failure\n");
  1106. break;
  1107. case FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR:
  1108. printk(KERN_ERR PFX "init_failure due to NIC error\n");
  1109. break;
  1110. case FCOE_KCQE_COMPLETION_STATUS_ERROR:
  1111. printk(KERN_ERR PFX "init failure due to compl status err\n");
  1112. break;
  1113. case FCOE_KCQE_COMPLETION_STATUS_WRONG_HSI_VERSION:
  1114. printk(KERN_ERR PFX "init failure due to HSI mismatch\n");
  1115. break;
  1116. default:
  1117. printk(KERN_ERR PFX "Unknown Error code %d\n", err_code);
  1118. }
  1119. }
  1120. /**
  1121. * bnx2fc_indicae_kcqe - process KCQE
  1122. *
  1123. * @hba: adapter structure pointer
  1124. * @kcqe: kcqe pointer
  1125. * @num_cqe: Number of completion queue elements
  1126. *
  1127. * Generic KCQ event handler
  1128. */
  1129. void bnx2fc_indicate_kcqe(void *context, struct kcqe *kcq[],
  1130. u32 num_cqe)
  1131. {
  1132. struct bnx2fc_hba *hba = (struct bnx2fc_hba *)context;
  1133. int i = 0;
  1134. struct fcoe_kcqe *kcqe = NULL;
  1135. while (i < num_cqe) {
  1136. kcqe = (struct fcoe_kcqe *) kcq[i++];
  1137. switch (kcqe->op_code) {
  1138. case FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION:
  1139. bnx2fc_fastpath_notification(hba, kcqe);
  1140. break;
  1141. case FCOE_KCQE_OPCODE_OFFLOAD_CONN:
  1142. bnx2fc_process_ofld_cmpl(hba, kcqe);
  1143. break;
  1144. case FCOE_KCQE_OPCODE_ENABLE_CONN:
  1145. bnx2fc_process_enable_conn_cmpl(hba, kcqe);
  1146. break;
  1147. case FCOE_KCQE_OPCODE_INIT_FUNC:
  1148. if (kcqe->completion_status !=
  1149. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1150. bnx2fc_init_failure(hba,
  1151. kcqe->completion_status);
  1152. } else {
  1153. set_bit(ADAPTER_STATE_UP, &hba->adapter_state);
  1154. bnx2fc_get_link_state(hba);
  1155. printk(KERN_INFO PFX "[%.2x]: FCOE_INIT passed\n",
  1156. (u8)hba->pcidev->bus->number);
  1157. }
  1158. break;
  1159. case FCOE_KCQE_OPCODE_DESTROY_FUNC:
  1160. if (kcqe->completion_status !=
  1161. FCOE_KCQE_COMPLETION_STATUS_SUCCESS) {
  1162. printk(KERN_ERR PFX "DESTROY failed\n");
  1163. } else {
  1164. printk(KERN_ERR PFX "DESTROY success\n");
  1165. }
  1166. set_bit(BNX2FC_FLAG_DESTROY_CMPL, &hba->flags);
  1167. wake_up_interruptible(&hba->destroy_wait);
  1168. break;
  1169. case FCOE_KCQE_OPCODE_DISABLE_CONN:
  1170. bnx2fc_process_conn_disable_cmpl(hba, kcqe);
  1171. break;
  1172. case FCOE_KCQE_OPCODE_DESTROY_CONN:
  1173. bnx2fc_process_conn_destroy_cmpl(hba, kcqe);
  1174. break;
  1175. case FCOE_KCQE_OPCODE_STAT_FUNC:
  1176. if (kcqe->completion_status !=
  1177. FCOE_KCQE_COMPLETION_STATUS_SUCCESS)
  1178. printk(KERN_ERR PFX "STAT failed\n");
  1179. complete(&hba->stat_req_done);
  1180. break;
  1181. case FCOE_KCQE_OPCODE_FCOE_ERROR:
  1182. /* fall thru */
  1183. default:
  1184. printk(KERN_ERR PFX "unknown opcode 0x%x\n",
  1185. kcqe->op_code);
  1186. }
  1187. }
  1188. }
  1189. void bnx2fc_add_2_sq(struct bnx2fc_rport *tgt, u16 xid)
  1190. {
  1191. struct fcoe_sqe *sqe;
  1192. sqe = &tgt->sq[tgt->sq_prod_idx];
  1193. /* Fill SQ WQE */
  1194. sqe->wqe = xid << FCOE_SQE_TASK_ID_SHIFT;
  1195. sqe->wqe |= tgt->sq_curr_toggle_bit << FCOE_SQE_TOGGLE_BIT_SHIFT;
  1196. /* Advance SQ Prod Idx */
  1197. if (++tgt->sq_prod_idx == BNX2FC_SQ_WQES_MAX) {
  1198. tgt->sq_prod_idx = 0;
  1199. tgt->sq_curr_toggle_bit = 1 - tgt->sq_curr_toggle_bit;
  1200. }
  1201. }
  1202. void bnx2fc_ring_doorbell(struct bnx2fc_rport *tgt)
  1203. {
  1204. struct b577xx_doorbell_set_prod *sq_db = &tgt->sq_db;
  1205. u32 msg;
  1206. wmb();
  1207. sq_db->prod = tgt->sq_prod_idx |
  1208. (tgt->sq_curr_toggle_bit << 15);
  1209. msg = *((u32 *)sq_db);
  1210. writel(cpu_to_le32(msg), tgt->ctx_base);
  1211. mmiowb();
  1212. }
  1213. int bnx2fc_map_doorbell(struct bnx2fc_rport *tgt)
  1214. {
  1215. u32 context_id = tgt->context_id;
  1216. struct fcoe_port *port = tgt->port;
  1217. u32 reg_off;
  1218. resource_size_t reg_base;
  1219. struct bnx2fc_interface *interface = port->priv;
  1220. struct bnx2fc_hba *hba = interface->hba;
  1221. reg_base = pci_resource_start(hba->pcidev,
  1222. BNX2X_DOORBELL_PCI_BAR);
  1223. reg_off = BNX2FC_5771X_DB_PAGE_SIZE *
  1224. (context_id & 0x1FFFF) + DPM_TRIGER_TYPE;
  1225. tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);
  1226. if (!tgt->ctx_base)
  1227. return -ENOMEM;
  1228. return 0;
  1229. }
  1230. char *bnx2fc_get_next_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1231. {
  1232. char *buf = (char *)tgt->rq + (tgt->rq_cons_idx * BNX2FC_RQ_BUF_SZ);
  1233. if (tgt->rq_cons_idx + num_items > BNX2FC_RQ_WQES_MAX)
  1234. return NULL;
  1235. tgt->rq_cons_idx += num_items;
  1236. if (tgt->rq_cons_idx >= BNX2FC_RQ_WQES_MAX)
  1237. tgt->rq_cons_idx -= BNX2FC_RQ_WQES_MAX;
  1238. return buf;
  1239. }
  1240. void bnx2fc_return_rqe(struct bnx2fc_rport *tgt, u8 num_items)
  1241. {
  1242. /* return the rq buffer */
  1243. u32 next_prod_idx = tgt->rq_prod_idx + num_items;
  1244. if ((next_prod_idx & 0x7fff) == BNX2FC_RQ_WQES_MAX) {
  1245. /* Wrap around RQ */
  1246. next_prod_idx += 0x8000 - BNX2FC_RQ_WQES_MAX;
  1247. }
  1248. tgt->rq_prod_idx = next_prod_idx;
  1249. tgt->conn_db->rq_prod = tgt->rq_prod_idx;
  1250. }
  1251. void bnx2fc_init_seq_cleanup_task(struct bnx2fc_cmd *seq_clnp_req,
  1252. struct fcoe_task_ctx_entry *task,
  1253. struct bnx2fc_cmd *orig_io_req,
  1254. u32 offset)
  1255. {
  1256. struct scsi_cmnd *sc_cmd = orig_io_req->sc_cmd;
  1257. struct bnx2fc_rport *tgt = seq_clnp_req->tgt;
  1258. struct bnx2fc_interface *interface = tgt->port->priv;
  1259. struct fcoe_bd_ctx *bd = orig_io_req->bd_tbl->bd_tbl;
  1260. struct fcoe_task_ctx_entry *orig_task;
  1261. struct fcoe_task_ctx_entry *task_page;
  1262. struct fcoe_ext_mul_sges_ctx *sgl;
  1263. u8 task_type = FCOE_TASK_TYPE_SEQUENCE_CLEANUP;
  1264. u8 orig_task_type;
  1265. u16 orig_xid = orig_io_req->xid;
  1266. u32 context_id = tgt->context_id;
  1267. u64 phys_addr = (u64)orig_io_req->bd_tbl->bd_tbl_dma;
  1268. u32 orig_offset = offset;
  1269. int bd_count;
  1270. int orig_task_idx, index;
  1271. int i;
  1272. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1273. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1274. orig_task_type = FCOE_TASK_TYPE_WRITE;
  1275. else
  1276. orig_task_type = FCOE_TASK_TYPE_READ;
  1277. /* Tx flags */
  1278. task->txwr_rxrd.const_ctx.tx_flags =
  1279. FCOE_TASK_TX_STATE_SEQUENCE_CLEANUP <<
  1280. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1281. /* init flags */
  1282. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1283. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1284. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1285. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1286. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1287. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1288. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1289. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1290. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1291. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_seq_cnt = 0;
  1292. task->txwr_rxrd.union_ctx.cleanup.ctx.rolled_tx_data_offset = offset;
  1293. bd_count = orig_io_req->bd_tbl->bd_valid;
  1294. /* obtain the appropriate bd entry from relative offset */
  1295. for (i = 0; i < bd_count; i++) {
  1296. if (offset < bd[i].buf_len)
  1297. break;
  1298. offset -= bd[i].buf_len;
  1299. }
  1300. phys_addr += (i * sizeof(struct fcoe_bd_ctx));
  1301. if (orig_task_type == FCOE_TASK_TYPE_WRITE) {
  1302. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1303. (u32)phys_addr;
  1304. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1305. (u32)((u64)phys_addr >> 32);
  1306. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1307. bd_count;
  1308. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_off =
  1309. offset; /* adjusted offset */
  1310. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_idx = i;
  1311. } else {
  1312. orig_task_idx = orig_xid / BNX2FC_TASKS_PER_PAGE;
  1313. index = orig_xid % BNX2FC_TASKS_PER_PAGE;
  1314. task_page = (struct fcoe_task_ctx_entry *)
  1315. interface->hba->task_ctx[orig_task_idx];
  1316. orig_task = &(task_page[index]);
  1317. /* Multiple SGEs were used for this IO */
  1318. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1319. sgl->mul_sgl.cur_sge_addr.lo = (u32)phys_addr;
  1320. sgl->mul_sgl.cur_sge_addr.hi = (u32)((u64)phys_addr >> 32);
  1321. sgl->mul_sgl.sgl_size = bd_count;
  1322. sgl->mul_sgl.cur_sge_off = offset; /*adjusted offset */
  1323. sgl->mul_sgl.cur_sge_idx = i;
  1324. memset(&task->rxwr_only.rx_seq_ctx, 0,
  1325. sizeof(struct fcoe_rx_seq_ctx));
  1326. task->rxwr_only.rx_seq_ctx.low_exp_ro = orig_offset;
  1327. task->rxwr_only.rx_seq_ctx.high_exp_ro = orig_offset;
  1328. }
  1329. }
  1330. void bnx2fc_init_cleanup_task(struct bnx2fc_cmd *io_req,
  1331. struct fcoe_task_ctx_entry *task,
  1332. u16 orig_xid)
  1333. {
  1334. u8 task_type = FCOE_TASK_TYPE_EXCHANGE_CLEANUP;
  1335. struct bnx2fc_rport *tgt = io_req->tgt;
  1336. u32 context_id = tgt->context_id;
  1337. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1338. /* Tx Write Rx Read */
  1339. /* init flags */
  1340. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1341. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1342. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1343. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1344. if (tgt->dev_type == TYPE_TAPE)
  1345. task->txwr_rxrd.const_ctx.init_flags |=
  1346. FCOE_TASK_DEV_TYPE_TAPE <<
  1347. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1348. else
  1349. task->txwr_rxrd.const_ctx.init_flags |=
  1350. FCOE_TASK_DEV_TYPE_DISK <<
  1351. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1352. task->txwr_rxrd.union_ctx.cleanup.ctx.cleaned_task_id = orig_xid;
  1353. /* Tx flags */
  1354. task->txwr_rxrd.const_ctx.tx_flags =
  1355. FCOE_TASK_TX_STATE_EXCHANGE_CLEANUP <<
  1356. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1357. /* Rx Read Tx Write */
  1358. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1359. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1360. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1361. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1362. }
  1363. void bnx2fc_init_mp_task(struct bnx2fc_cmd *io_req,
  1364. struct fcoe_task_ctx_entry *task)
  1365. {
  1366. struct bnx2fc_mp_req *mp_req = &(io_req->mp_req);
  1367. struct bnx2fc_rport *tgt = io_req->tgt;
  1368. struct fc_frame_header *fc_hdr;
  1369. struct fcoe_ext_mul_sges_ctx *sgl;
  1370. u8 task_type = 0;
  1371. u64 *hdr;
  1372. u64 temp_hdr[3];
  1373. u32 context_id;
  1374. /* Obtain task_type */
  1375. if ((io_req->cmd_type == BNX2FC_TASK_MGMT_CMD) ||
  1376. (io_req->cmd_type == BNX2FC_ELS)) {
  1377. task_type = FCOE_TASK_TYPE_MIDPATH;
  1378. } else if (io_req->cmd_type == BNX2FC_ABTS) {
  1379. task_type = FCOE_TASK_TYPE_ABTS;
  1380. }
  1381. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1382. /* Setup the task from io_req for easy reference */
  1383. io_req->task = task;
  1384. BNX2FC_IO_DBG(io_req, "Init MP task for cmd_type = %d task_type = %d\n",
  1385. io_req->cmd_type, task_type);
  1386. /* Tx only */
  1387. if ((task_type == FCOE_TASK_TYPE_MIDPATH) ||
  1388. (task_type == FCOE_TASK_TYPE_UNSOLICITED)) {
  1389. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1390. (u32)mp_req->mp_req_bd_dma;
  1391. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1392. (u32)((u64)mp_req->mp_req_bd_dma >> 32);
  1393. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size = 1;
  1394. }
  1395. /* Tx Write Rx Read */
  1396. /* init flags */
  1397. task->txwr_rxrd.const_ctx.init_flags = task_type <<
  1398. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1399. if (tgt->dev_type == TYPE_TAPE)
  1400. task->txwr_rxrd.const_ctx.init_flags |=
  1401. FCOE_TASK_DEV_TYPE_TAPE <<
  1402. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1403. else
  1404. task->txwr_rxrd.const_ctx.init_flags |=
  1405. FCOE_TASK_DEV_TYPE_DISK <<
  1406. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1407. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1408. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1409. /* tx flags */
  1410. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_INIT <<
  1411. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1412. /* Rx Write Tx Read */
  1413. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1414. /* rx flags */
  1415. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1416. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1417. context_id = tgt->context_id;
  1418. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1419. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1420. fc_hdr = &(mp_req->req_fc_hdr);
  1421. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1422. fc_hdr->fh_ox_id = cpu_to_be16(io_req->xid);
  1423. fc_hdr->fh_rx_id = htons(0xffff);
  1424. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1425. } else if (task_type == FCOE_TASK_TYPE_UNSOLICITED) {
  1426. fc_hdr->fh_rx_id = cpu_to_be16(io_req->xid);
  1427. }
  1428. /* Fill FC Header into middle path buffer */
  1429. hdr = (u64 *) &task->txwr_rxrd.union_ctx.tx_frame.fc_hdr;
  1430. memcpy(temp_hdr, fc_hdr, sizeof(temp_hdr));
  1431. hdr[0] = cpu_to_be64(temp_hdr[0]);
  1432. hdr[1] = cpu_to_be64(temp_hdr[1]);
  1433. hdr[2] = cpu_to_be64(temp_hdr[2]);
  1434. /* Rx Only */
  1435. if (task_type == FCOE_TASK_TYPE_MIDPATH) {
  1436. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1437. sgl->mul_sgl.cur_sge_addr.lo = (u32)mp_req->mp_resp_bd_dma;
  1438. sgl->mul_sgl.cur_sge_addr.hi =
  1439. (u32)((u64)mp_req->mp_resp_bd_dma >> 32);
  1440. sgl->mul_sgl.sgl_size = 1;
  1441. }
  1442. }
  1443. void bnx2fc_init_task(struct bnx2fc_cmd *io_req,
  1444. struct fcoe_task_ctx_entry *task)
  1445. {
  1446. u8 task_type;
  1447. struct scsi_cmnd *sc_cmd = io_req->sc_cmd;
  1448. struct io_bdt *bd_tbl = io_req->bd_tbl;
  1449. struct bnx2fc_rport *tgt = io_req->tgt;
  1450. struct fcoe_cached_sge_ctx *cached_sge;
  1451. struct fcoe_ext_mul_sges_ctx *sgl;
  1452. int dev_type = tgt->dev_type;
  1453. u64 *fcp_cmnd;
  1454. u64 tmp_fcp_cmnd[4];
  1455. u32 context_id;
  1456. int cnt, i;
  1457. int bd_count;
  1458. memset(task, 0, sizeof(struct fcoe_task_ctx_entry));
  1459. /* Setup the task from io_req for easy reference */
  1460. io_req->task = task;
  1461. if (sc_cmd->sc_data_direction == DMA_TO_DEVICE)
  1462. task_type = FCOE_TASK_TYPE_WRITE;
  1463. else
  1464. task_type = FCOE_TASK_TYPE_READ;
  1465. /* Tx only */
  1466. bd_count = bd_tbl->bd_valid;
  1467. cached_sge = &task->rxwr_only.union_ctx.read_info.sgl_ctx.cached_sge;
  1468. if (task_type == FCOE_TASK_TYPE_WRITE) {
  1469. if ((dev_type == TYPE_DISK) && (bd_count == 1)) {
  1470. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1471. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.lo =
  1472. cached_sge->cur_buf_addr.lo =
  1473. fcoe_bd_tbl->buf_addr_lo;
  1474. task->txwr_only.sgl_ctx.cached_sge.cur_buf_addr.hi =
  1475. cached_sge->cur_buf_addr.hi =
  1476. fcoe_bd_tbl->buf_addr_hi;
  1477. task->txwr_only.sgl_ctx.cached_sge.cur_buf_rem =
  1478. cached_sge->cur_buf_rem =
  1479. fcoe_bd_tbl->buf_len;
  1480. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1481. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1482. } else {
  1483. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.lo =
  1484. (u32)bd_tbl->bd_tbl_dma;
  1485. task->txwr_only.sgl_ctx.sgl.mul_sgl.cur_sge_addr.hi =
  1486. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1487. task->txwr_only.sgl_ctx.sgl.mul_sgl.sgl_size =
  1488. bd_tbl->bd_valid;
  1489. }
  1490. }
  1491. /*Tx Write Rx Read */
  1492. /* Init state to NORMAL */
  1493. task->txwr_rxrd.const_ctx.init_flags |= task_type <<
  1494. FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT;
  1495. if (dev_type == TYPE_TAPE) {
  1496. task->txwr_rxrd.const_ctx.init_flags |=
  1497. FCOE_TASK_DEV_TYPE_TAPE <<
  1498. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1499. io_req->rec_retry = 0;
  1500. io_req->rec_retry = 0;
  1501. } else
  1502. task->txwr_rxrd.const_ctx.init_flags |=
  1503. FCOE_TASK_DEV_TYPE_DISK <<
  1504. FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT;
  1505. task->txwr_rxrd.const_ctx.init_flags |= FCOE_TASK_CLASS_TYPE_3 <<
  1506. FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT;
  1507. /* tx flags */
  1508. task->txwr_rxrd.const_ctx.tx_flags = FCOE_TASK_TX_STATE_NORMAL <<
  1509. FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT;
  1510. /* Set initial seq counter */
  1511. task->txwr_rxrd.union_ctx.tx_seq.ctx.seq_cnt = 1;
  1512. /* Fill FCP_CMND IU */
  1513. fcp_cmnd = (u64 *)
  1514. task->txwr_rxrd.union_ctx.fcp_cmd.opaque;
  1515. bnx2fc_build_fcp_cmnd(io_req, (struct fcp_cmnd *)&tmp_fcp_cmnd);
  1516. /* swap fcp_cmnd */
  1517. cnt = sizeof(struct fcp_cmnd) / sizeof(u64);
  1518. for (i = 0; i < cnt; i++) {
  1519. *fcp_cmnd = cpu_to_be64(tmp_fcp_cmnd[i]);
  1520. fcp_cmnd++;
  1521. }
  1522. /* Rx Write Tx Read */
  1523. task->rxwr_txrd.const_ctx.data_2_trns = io_req->data_xfer_len;
  1524. context_id = tgt->context_id;
  1525. task->rxwr_txrd.const_ctx.init_flags = context_id <<
  1526. FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT;
  1527. /* rx flags */
  1528. /* Set state to "waiting for the first packet" */
  1529. task->rxwr_txrd.var_ctx.rx_flags |= 1 <<
  1530. FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT;
  1531. task->rxwr_txrd.var_ctx.rx_id = 0xffff;
  1532. /* Rx Only */
  1533. if (task_type != FCOE_TASK_TYPE_READ)
  1534. return;
  1535. sgl = &task->rxwr_only.union_ctx.read_info.sgl_ctx.sgl;
  1536. bd_count = bd_tbl->bd_valid;
  1537. if (dev_type == TYPE_DISK) {
  1538. if (bd_count == 1) {
  1539. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1540. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1541. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1542. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1543. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1544. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1545. } else if (bd_count == 2) {
  1546. struct fcoe_bd_ctx *fcoe_bd_tbl = bd_tbl->bd_tbl;
  1547. cached_sge->cur_buf_addr.lo = fcoe_bd_tbl->buf_addr_lo;
  1548. cached_sge->cur_buf_addr.hi = fcoe_bd_tbl->buf_addr_hi;
  1549. cached_sge->cur_buf_rem = fcoe_bd_tbl->buf_len;
  1550. fcoe_bd_tbl++;
  1551. cached_sge->second_buf_addr.lo =
  1552. fcoe_bd_tbl->buf_addr_lo;
  1553. cached_sge->second_buf_addr.hi =
  1554. fcoe_bd_tbl->buf_addr_hi;
  1555. cached_sge->second_buf_rem = fcoe_bd_tbl->buf_len;
  1556. task->txwr_rxrd.const_ctx.init_flags |= 1 <<
  1557. FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT;
  1558. } else {
  1559. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1560. sgl->mul_sgl.cur_sge_addr.hi =
  1561. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1562. sgl->mul_sgl.sgl_size = bd_count;
  1563. }
  1564. } else {
  1565. sgl->mul_sgl.cur_sge_addr.lo = (u32)bd_tbl->bd_tbl_dma;
  1566. sgl->mul_sgl.cur_sge_addr.hi =
  1567. (u32)((u64)bd_tbl->bd_tbl_dma >> 32);
  1568. sgl->mul_sgl.sgl_size = bd_count;
  1569. }
  1570. }
  1571. /**
  1572. * bnx2fc_setup_task_ctx - allocate and map task context
  1573. *
  1574. * @hba: pointer to adapter structure
  1575. *
  1576. * allocate memory for task context, and associated BD table to be used
  1577. * by firmware
  1578. *
  1579. */
  1580. int bnx2fc_setup_task_ctx(struct bnx2fc_hba *hba)
  1581. {
  1582. int rc = 0;
  1583. struct regpair *task_ctx_bdt;
  1584. dma_addr_t addr;
  1585. int i;
  1586. /*
  1587. * Allocate task context bd table. A page size of bd table
  1588. * can map 256 buffers. Each buffer contains 32 task context
  1589. * entries. Hence the limit with one page is 8192 task context
  1590. * entries.
  1591. */
  1592. hba->task_ctx_bd_tbl = dma_alloc_coherent(&hba->pcidev->dev,
  1593. PAGE_SIZE,
  1594. &hba->task_ctx_bd_dma,
  1595. GFP_KERNEL);
  1596. if (!hba->task_ctx_bd_tbl) {
  1597. printk(KERN_ERR PFX "unable to allocate task context BDT\n");
  1598. rc = -1;
  1599. goto out;
  1600. }
  1601. memset(hba->task_ctx_bd_tbl, 0, PAGE_SIZE);
  1602. /*
  1603. * Allocate task_ctx which is an array of pointers pointing to
  1604. * a page containing 32 task contexts
  1605. */
  1606. hba->task_ctx = kzalloc((BNX2FC_TASK_CTX_ARR_SZ * sizeof(void *)),
  1607. GFP_KERNEL);
  1608. if (!hba->task_ctx) {
  1609. printk(KERN_ERR PFX "unable to allocate task context array\n");
  1610. rc = -1;
  1611. goto out1;
  1612. }
  1613. /*
  1614. * Allocate task_ctx_dma which is an array of dma addresses
  1615. */
  1616. hba->task_ctx_dma = kmalloc((BNX2FC_TASK_CTX_ARR_SZ *
  1617. sizeof(dma_addr_t)), GFP_KERNEL);
  1618. if (!hba->task_ctx_dma) {
  1619. printk(KERN_ERR PFX "unable to alloc context mapping array\n");
  1620. rc = -1;
  1621. goto out2;
  1622. }
  1623. task_ctx_bdt = (struct regpair *)hba->task_ctx_bd_tbl;
  1624. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1625. hba->task_ctx[i] = dma_alloc_coherent(&hba->pcidev->dev,
  1626. PAGE_SIZE,
  1627. &hba->task_ctx_dma[i],
  1628. GFP_KERNEL);
  1629. if (!hba->task_ctx[i]) {
  1630. printk(KERN_ERR PFX "unable to alloc task context\n");
  1631. rc = -1;
  1632. goto out3;
  1633. }
  1634. memset(hba->task_ctx[i], 0, PAGE_SIZE);
  1635. addr = (u64)hba->task_ctx_dma[i];
  1636. task_ctx_bdt->hi = cpu_to_le32((u64)addr >> 32);
  1637. task_ctx_bdt->lo = cpu_to_le32((u32)addr);
  1638. task_ctx_bdt++;
  1639. }
  1640. return 0;
  1641. out3:
  1642. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1643. if (hba->task_ctx[i]) {
  1644. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1645. hba->task_ctx[i], hba->task_ctx_dma[i]);
  1646. hba->task_ctx[i] = NULL;
  1647. }
  1648. }
  1649. kfree(hba->task_ctx_dma);
  1650. hba->task_ctx_dma = NULL;
  1651. out2:
  1652. kfree(hba->task_ctx);
  1653. hba->task_ctx = NULL;
  1654. out1:
  1655. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1656. hba->task_ctx_bd_tbl, hba->task_ctx_bd_dma);
  1657. hba->task_ctx_bd_tbl = NULL;
  1658. out:
  1659. return rc;
  1660. }
  1661. void bnx2fc_free_task_ctx(struct bnx2fc_hba *hba)
  1662. {
  1663. int i;
  1664. if (hba->task_ctx_bd_tbl) {
  1665. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1666. hba->task_ctx_bd_tbl,
  1667. hba->task_ctx_bd_dma);
  1668. hba->task_ctx_bd_tbl = NULL;
  1669. }
  1670. if (hba->task_ctx) {
  1671. for (i = 0; i < BNX2FC_TASK_CTX_ARR_SZ; i++) {
  1672. if (hba->task_ctx[i]) {
  1673. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1674. hba->task_ctx[i],
  1675. hba->task_ctx_dma[i]);
  1676. hba->task_ctx[i] = NULL;
  1677. }
  1678. }
  1679. kfree(hba->task_ctx);
  1680. hba->task_ctx = NULL;
  1681. }
  1682. kfree(hba->task_ctx_dma);
  1683. hba->task_ctx_dma = NULL;
  1684. }
  1685. static void bnx2fc_free_hash_table(struct bnx2fc_hba *hba)
  1686. {
  1687. int i;
  1688. int segment_count;
  1689. int hash_table_size;
  1690. u32 *pbl;
  1691. segment_count = hba->hash_tbl_segment_count;
  1692. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1693. sizeof(struct fcoe_hash_table_entry);
  1694. pbl = hba->hash_tbl_pbl;
  1695. for (i = 0; i < segment_count; ++i) {
  1696. dma_addr_t dma_address;
  1697. dma_address = le32_to_cpu(*pbl);
  1698. ++pbl;
  1699. dma_address += ((u64)le32_to_cpu(*pbl)) << 32;
  1700. ++pbl;
  1701. dma_free_coherent(&hba->pcidev->dev,
  1702. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1703. hba->hash_tbl_segments[i],
  1704. dma_address);
  1705. }
  1706. if (hba->hash_tbl_pbl) {
  1707. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1708. hba->hash_tbl_pbl,
  1709. hba->hash_tbl_pbl_dma);
  1710. hba->hash_tbl_pbl = NULL;
  1711. }
  1712. }
  1713. static int bnx2fc_allocate_hash_table(struct bnx2fc_hba *hba)
  1714. {
  1715. int i;
  1716. int hash_table_size;
  1717. int segment_count;
  1718. int segment_array_size;
  1719. int dma_segment_array_size;
  1720. dma_addr_t *dma_segment_array;
  1721. u32 *pbl;
  1722. hash_table_size = BNX2FC_NUM_MAX_SESS * BNX2FC_MAX_ROWS_IN_HASH_TBL *
  1723. sizeof(struct fcoe_hash_table_entry);
  1724. segment_count = hash_table_size + BNX2FC_HASH_TBL_CHUNK_SIZE - 1;
  1725. segment_count /= BNX2FC_HASH_TBL_CHUNK_SIZE;
  1726. hba->hash_tbl_segment_count = segment_count;
  1727. segment_array_size = segment_count * sizeof(*hba->hash_tbl_segments);
  1728. hba->hash_tbl_segments = kzalloc(segment_array_size, GFP_KERNEL);
  1729. if (!hba->hash_tbl_segments) {
  1730. printk(KERN_ERR PFX "hash table pointers alloc failed\n");
  1731. return -ENOMEM;
  1732. }
  1733. dma_segment_array_size = segment_count * sizeof(*dma_segment_array);
  1734. dma_segment_array = kzalloc(dma_segment_array_size, GFP_KERNEL);
  1735. if (!dma_segment_array) {
  1736. printk(KERN_ERR PFX "hash table pointers (dma) alloc failed\n");
  1737. return -ENOMEM;
  1738. }
  1739. for (i = 0; i < segment_count; ++i) {
  1740. hba->hash_tbl_segments[i] =
  1741. dma_alloc_coherent(&hba->pcidev->dev,
  1742. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1743. &dma_segment_array[i],
  1744. GFP_KERNEL);
  1745. if (!hba->hash_tbl_segments[i]) {
  1746. printk(KERN_ERR PFX "hash segment alloc failed\n");
  1747. while (--i >= 0) {
  1748. dma_free_coherent(&hba->pcidev->dev,
  1749. BNX2FC_HASH_TBL_CHUNK_SIZE,
  1750. hba->hash_tbl_segments[i],
  1751. dma_segment_array[i]);
  1752. hba->hash_tbl_segments[i] = NULL;
  1753. }
  1754. kfree(dma_segment_array);
  1755. return -ENOMEM;
  1756. }
  1757. memset(hba->hash_tbl_segments[i], 0,
  1758. BNX2FC_HASH_TBL_CHUNK_SIZE);
  1759. }
  1760. hba->hash_tbl_pbl = dma_alloc_coherent(&hba->pcidev->dev,
  1761. PAGE_SIZE,
  1762. &hba->hash_tbl_pbl_dma,
  1763. GFP_KERNEL);
  1764. if (!hba->hash_tbl_pbl) {
  1765. printk(KERN_ERR PFX "hash table pbl alloc failed\n");
  1766. kfree(dma_segment_array);
  1767. return -ENOMEM;
  1768. }
  1769. memset(hba->hash_tbl_pbl, 0, PAGE_SIZE);
  1770. pbl = hba->hash_tbl_pbl;
  1771. for (i = 0; i < segment_count; ++i) {
  1772. u64 paddr = dma_segment_array[i];
  1773. *pbl = cpu_to_le32((u32) paddr);
  1774. ++pbl;
  1775. *pbl = cpu_to_le32((u32) (paddr >> 32));
  1776. ++pbl;
  1777. }
  1778. pbl = hba->hash_tbl_pbl;
  1779. i = 0;
  1780. while (*pbl && *(pbl + 1)) {
  1781. u32 lo;
  1782. u32 hi;
  1783. lo = *pbl;
  1784. ++pbl;
  1785. hi = *pbl;
  1786. ++pbl;
  1787. ++i;
  1788. }
  1789. kfree(dma_segment_array);
  1790. return 0;
  1791. }
  1792. /**
  1793. * bnx2fc_setup_fw_resc - Allocate and map hash table and dummy buffer
  1794. *
  1795. * @hba: Pointer to adapter structure
  1796. *
  1797. */
  1798. int bnx2fc_setup_fw_resc(struct bnx2fc_hba *hba)
  1799. {
  1800. u64 addr;
  1801. u32 mem_size;
  1802. int i;
  1803. if (bnx2fc_allocate_hash_table(hba))
  1804. return -ENOMEM;
  1805. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1806. hba->t2_hash_tbl_ptr = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1807. &hba->t2_hash_tbl_ptr_dma,
  1808. GFP_KERNEL);
  1809. if (!hba->t2_hash_tbl_ptr) {
  1810. printk(KERN_ERR PFX "unable to allocate t2 hash table ptr\n");
  1811. bnx2fc_free_fw_resc(hba);
  1812. return -ENOMEM;
  1813. }
  1814. memset(hba->t2_hash_tbl_ptr, 0x00, mem_size);
  1815. mem_size = BNX2FC_NUM_MAX_SESS *
  1816. sizeof(struct fcoe_t2_hash_table_entry);
  1817. hba->t2_hash_tbl = dma_alloc_coherent(&hba->pcidev->dev, mem_size,
  1818. &hba->t2_hash_tbl_dma,
  1819. GFP_KERNEL);
  1820. if (!hba->t2_hash_tbl) {
  1821. printk(KERN_ERR PFX "unable to allocate t2 hash table\n");
  1822. bnx2fc_free_fw_resc(hba);
  1823. return -ENOMEM;
  1824. }
  1825. memset(hba->t2_hash_tbl, 0x00, mem_size);
  1826. for (i = 0; i < BNX2FC_NUM_MAX_SESS; i++) {
  1827. addr = (unsigned long) hba->t2_hash_tbl_dma +
  1828. ((i+1) * sizeof(struct fcoe_t2_hash_table_entry));
  1829. hba->t2_hash_tbl[i].next.lo = addr & 0xffffffff;
  1830. hba->t2_hash_tbl[i].next.hi = addr >> 32;
  1831. }
  1832. hba->dummy_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1833. PAGE_SIZE, &hba->dummy_buf_dma,
  1834. GFP_KERNEL);
  1835. if (!hba->dummy_buffer) {
  1836. printk(KERN_ERR PFX "unable to alloc MP Dummy Buffer\n");
  1837. bnx2fc_free_fw_resc(hba);
  1838. return -ENOMEM;
  1839. }
  1840. hba->stats_buffer = dma_alloc_coherent(&hba->pcidev->dev,
  1841. PAGE_SIZE,
  1842. &hba->stats_buf_dma,
  1843. GFP_KERNEL);
  1844. if (!hba->stats_buffer) {
  1845. printk(KERN_ERR PFX "unable to alloc Stats Buffer\n");
  1846. bnx2fc_free_fw_resc(hba);
  1847. return -ENOMEM;
  1848. }
  1849. memset(hba->stats_buffer, 0x00, PAGE_SIZE);
  1850. return 0;
  1851. }
  1852. void bnx2fc_free_fw_resc(struct bnx2fc_hba *hba)
  1853. {
  1854. u32 mem_size;
  1855. if (hba->stats_buffer) {
  1856. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1857. hba->stats_buffer, hba->stats_buf_dma);
  1858. hba->stats_buffer = NULL;
  1859. }
  1860. if (hba->dummy_buffer) {
  1861. dma_free_coherent(&hba->pcidev->dev, PAGE_SIZE,
  1862. hba->dummy_buffer, hba->dummy_buf_dma);
  1863. hba->dummy_buffer = NULL;
  1864. }
  1865. if (hba->t2_hash_tbl_ptr) {
  1866. mem_size = BNX2FC_NUM_MAX_SESS * sizeof(struct regpair);
  1867. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1868. hba->t2_hash_tbl_ptr,
  1869. hba->t2_hash_tbl_ptr_dma);
  1870. hba->t2_hash_tbl_ptr = NULL;
  1871. }
  1872. if (hba->t2_hash_tbl) {
  1873. mem_size = BNX2FC_NUM_MAX_SESS *
  1874. sizeof(struct fcoe_t2_hash_table_entry);
  1875. dma_free_coherent(&hba->pcidev->dev, mem_size,
  1876. hba->t2_hash_tbl, hba->t2_hash_tbl_dma);
  1877. hba->t2_hash_tbl = NULL;
  1878. }
  1879. bnx2fc_free_hash_table(hba);
  1880. }