rtc-ds1307.c 25 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/slab.h>
  15. #include <linux/i2c.h>
  16. #include <linux/string.h>
  17. #include <linux/rtc.h>
  18. #include <linux/bcd.h>
  19. #include <linux/rtc/ds1307.h>
  20. /*
  21. * We can't determine type by probing, but if we expect pre-Linux code
  22. * to have set the chip up as a clock (turning on the oscillator and
  23. * setting the date and time), Linux can ignore the non-clock features.
  24. * That's a natural job for a factory or repair bench.
  25. */
  26. enum ds_type {
  27. ds_1307,
  28. ds_1337,
  29. ds_1338,
  30. ds_1339,
  31. ds_1340,
  32. ds_1388,
  33. ds_3231,
  34. m41t00,
  35. mcp7941x,
  36. rx_8025,
  37. last_ds_type /* always last */
  38. /* rs5c372 too? different address... */
  39. };
  40. /* RTC registers don't differ much, except for the century flag */
  41. #define DS1307_REG_SECS 0x00 /* 00-59 */
  42. # define DS1307_BIT_CH 0x80
  43. # define DS1340_BIT_nEOSC 0x80
  44. # define MCP7941X_BIT_ST 0x80
  45. #define DS1307_REG_MIN 0x01 /* 00-59 */
  46. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  47. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  48. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  49. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  51. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  52. # define MCP7941X_BIT_VBATEN 0x08
  53. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  54. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  55. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  56. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  57. /*
  58. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  59. * start at 7, and they differ a LOT. Only control and status matter for
  60. * basic RTC date and time functionality; be careful using them.
  61. */
  62. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  63. # define DS1307_BIT_OUT 0x80
  64. # define DS1338_BIT_OSF 0x20
  65. # define DS1307_BIT_SQWE 0x10
  66. # define DS1307_BIT_RS1 0x02
  67. # define DS1307_BIT_RS0 0x01
  68. #define DS1337_REG_CONTROL 0x0e
  69. # define DS1337_BIT_nEOSC 0x80
  70. # define DS1339_BIT_BBSQI 0x20
  71. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  72. # define DS1337_BIT_RS2 0x10
  73. # define DS1337_BIT_RS1 0x08
  74. # define DS1337_BIT_INTCN 0x04
  75. # define DS1337_BIT_A2IE 0x02
  76. # define DS1337_BIT_A1IE 0x01
  77. #define DS1340_REG_CONTROL 0x07
  78. # define DS1340_BIT_OUT 0x80
  79. # define DS1340_BIT_FT 0x40
  80. # define DS1340_BIT_CALIB_SIGN 0x20
  81. # define DS1340_M_CALIBRATION 0x1f
  82. #define DS1340_REG_FLAG 0x09
  83. # define DS1340_BIT_OSF 0x80
  84. #define DS1337_REG_STATUS 0x0f
  85. # define DS1337_BIT_OSF 0x80
  86. # define DS1337_BIT_A2I 0x02
  87. # define DS1337_BIT_A1I 0x01
  88. #define DS1339_REG_ALARM1_SECS 0x07
  89. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  90. #define RX8025_REG_CTRL1 0x0e
  91. # define RX8025_BIT_2412 0x20
  92. #define RX8025_REG_CTRL2 0x0f
  93. # define RX8025_BIT_PON 0x10
  94. # define RX8025_BIT_VDET 0x40
  95. # define RX8025_BIT_XST 0x20
  96. struct ds1307 {
  97. u8 offset; /* register's offset */
  98. u8 regs[11];
  99. u16 nvram_offset;
  100. struct bin_attribute *nvram;
  101. enum ds_type type;
  102. unsigned long flags;
  103. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  104. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  105. struct i2c_client *client;
  106. struct rtc_device *rtc;
  107. struct work_struct work;
  108. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  109. u8 length, u8 *values);
  110. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  111. u8 length, const u8 *values);
  112. };
  113. struct chip_desc {
  114. unsigned alarm:1;
  115. u16 nvram_offset;
  116. u16 nvram_size;
  117. u16 trickle_charger_reg;
  118. };
  119. static const struct chip_desc chips[last_ds_type] = {
  120. [ds_1307] = {
  121. .nvram_offset = 8,
  122. .nvram_size = 56,
  123. },
  124. [ds_1337] = {
  125. .alarm = 1,
  126. },
  127. [ds_1338] = {
  128. .nvram_offset = 8,
  129. .nvram_size = 56,
  130. },
  131. [ds_1339] = {
  132. .alarm = 1,
  133. .trickle_charger_reg = 0x10,
  134. },
  135. [ds_1340] = {
  136. .trickle_charger_reg = 0x08,
  137. },
  138. [ds_1388] = {
  139. .trickle_charger_reg = 0x0a,
  140. },
  141. [ds_3231] = {
  142. .alarm = 1,
  143. },
  144. [mcp7941x] = {
  145. /* this is battery backed SRAM */
  146. .nvram_offset = 0x20,
  147. .nvram_size = 0x40,
  148. },
  149. };
  150. static const struct i2c_device_id ds1307_id[] = {
  151. { "ds1307", ds_1307 },
  152. { "ds1337", ds_1337 },
  153. { "ds1338", ds_1338 },
  154. { "ds1339", ds_1339 },
  155. { "ds1388", ds_1388 },
  156. { "ds1340", ds_1340 },
  157. { "ds3231", ds_3231 },
  158. { "m41t00", m41t00 },
  159. { "mcp7941x", mcp7941x },
  160. { "pt7c4338", ds_1307 },
  161. { "rx8025", rx_8025 },
  162. { }
  163. };
  164. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  165. /*----------------------------------------------------------------------*/
  166. #define BLOCK_DATA_MAX_TRIES 10
  167. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  168. u8 command, u8 length, u8 *values)
  169. {
  170. s32 i, data;
  171. for (i = 0; i < length; i++) {
  172. data = i2c_smbus_read_byte_data(client, command + i);
  173. if (data < 0)
  174. return data;
  175. values[i] = data;
  176. }
  177. return i;
  178. }
  179. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  180. u8 length, u8 *values)
  181. {
  182. u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
  183. s32 ret;
  184. int tries = 0;
  185. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  186. ret = ds1307_read_block_data_once(client, command, length, values);
  187. if (ret < 0)
  188. return ret;
  189. do {
  190. if (++tries > BLOCK_DATA_MAX_TRIES) {
  191. dev_err(&client->dev,
  192. "ds1307_read_block_data failed\n");
  193. return -EIO;
  194. }
  195. memcpy(oldvalues, values, length);
  196. ret = ds1307_read_block_data_once(client, command, length,
  197. values);
  198. if (ret < 0)
  199. return ret;
  200. } while (memcmp(oldvalues, values, length));
  201. return length;
  202. }
  203. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  204. u8 length, const u8 *values)
  205. {
  206. u8 currvalues[I2C_SMBUS_BLOCK_MAX];
  207. int tries = 0;
  208. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  209. do {
  210. s32 i, ret;
  211. if (++tries > BLOCK_DATA_MAX_TRIES) {
  212. dev_err(&client->dev,
  213. "ds1307_write_block_data failed\n");
  214. return -EIO;
  215. }
  216. for (i = 0; i < length; i++) {
  217. ret = i2c_smbus_write_byte_data(client, command + i,
  218. values[i]);
  219. if (ret < 0)
  220. return ret;
  221. }
  222. ret = ds1307_read_block_data_once(client, command, length,
  223. currvalues);
  224. if (ret < 0)
  225. return ret;
  226. } while (memcmp(currvalues, values, length));
  227. return length;
  228. }
  229. /*----------------------------------------------------------------------*/
  230. /*
  231. * The IRQ logic includes a "real" handler running in IRQ context just
  232. * long enough to schedule this workqueue entry. We need a task context
  233. * to talk to the RTC, since I2C I/O calls require that; and disable the
  234. * IRQ until we clear its status on the chip, so that this handler can
  235. * work with any type of triggering (not just falling edge).
  236. *
  237. * The ds1337 and ds1339 both have two alarms, but we only use the first
  238. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  239. * signal; ds1339 chips have only one alarm signal.
  240. */
  241. static void ds1307_work(struct work_struct *work)
  242. {
  243. struct ds1307 *ds1307;
  244. struct i2c_client *client;
  245. struct mutex *lock;
  246. int stat, control;
  247. ds1307 = container_of(work, struct ds1307, work);
  248. client = ds1307->client;
  249. lock = &ds1307->rtc->ops_lock;
  250. mutex_lock(lock);
  251. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  252. if (stat < 0)
  253. goto out;
  254. if (stat & DS1337_BIT_A1I) {
  255. stat &= ~DS1337_BIT_A1I;
  256. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  257. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  258. if (control < 0)
  259. goto out;
  260. control &= ~DS1337_BIT_A1IE;
  261. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  262. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  263. }
  264. out:
  265. if (test_bit(HAS_ALARM, &ds1307->flags))
  266. enable_irq(client->irq);
  267. mutex_unlock(lock);
  268. }
  269. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  270. {
  271. struct i2c_client *client = dev_id;
  272. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  273. disable_irq_nosync(irq);
  274. schedule_work(&ds1307->work);
  275. return IRQ_HANDLED;
  276. }
  277. /*----------------------------------------------------------------------*/
  278. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  279. {
  280. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  281. int tmp;
  282. /* read the RTC date and time registers all at once */
  283. tmp = ds1307->read_block_data(ds1307->client,
  284. ds1307->offset, 7, ds1307->regs);
  285. if (tmp != 7) {
  286. dev_err(dev, "%s error %d\n", "read", tmp);
  287. return -EIO;
  288. }
  289. dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
  290. "read",
  291. ds1307->regs[0], ds1307->regs[1],
  292. ds1307->regs[2], ds1307->regs[3],
  293. ds1307->regs[4], ds1307->regs[5],
  294. ds1307->regs[6]);
  295. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  296. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  297. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  298. t->tm_hour = bcd2bin(tmp);
  299. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  300. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  301. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  302. t->tm_mon = bcd2bin(tmp) - 1;
  303. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  304. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  305. dev_dbg(dev, "%s secs=%d, mins=%d, "
  306. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  307. "read", t->tm_sec, t->tm_min,
  308. t->tm_hour, t->tm_mday,
  309. t->tm_mon, t->tm_year, t->tm_wday);
  310. /* initial clock setting can be undefined */
  311. return rtc_valid_tm(t);
  312. }
  313. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  314. {
  315. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  316. int result;
  317. int tmp;
  318. u8 *buf = ds1307->regs;
  319. dev_dbg(dev, "%s secs=%d, mins=%d, "
  320. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  321. "write", t->tm_sec, t->tm_min,
  322. t->tm_hour, t->tm_mday,
  323. t->tm_mon, t->tm_year, t->tm_wday);
  324. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  325. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  326. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  327. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  328. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  329. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  330. /* assume 20YY not 19YY */
  331. tmp = t->tm_year - 100;
  332. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  333. switch (ds1307->type) {
  334. case ds_1337:
  335. case ds_1339:
  336. case ds_3231:
  337. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  338. break;
  339. case ds_1340:
  340. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  341. | DS1340_BIT_CENTURY;
  342. break;
  343. case mcp7941x:
  344. /*
  345. * these bits were cleared when preparing the date/time
  346. * values and need to be set again before writing the
  347. * buffer out to the device.
  348. */
  349. buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
  350. buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
  351. break;
  352. default:
  353. break;
  354. }
  355. dev_dbg(dev, "%s: %02x %02x %02x %02x %02x %02x %02x\n",
  356. "write", buf[0], buf[1], buf[2], buf[3],
  357. buf[4], buf[5], buf[6]);
  358. result = ds1307->write_block_data(ds1307->client,
  359. ds1307->offset, 7, buf);
  360. if (result < 0) {
  361. dev_err(dev, "%s error %d\n", "write", result);
  362. return result;
  363. }
  364. return 0;
  365. }
  366. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  367. {
  368. struct i2c_client *client = to_i2c_client(dev);
  369. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  370. int ret;
  371. if (!test_bit(HAS_ALARM, &ds1307->flags))
  372. return -EINVAL;
  373. /* read all ALARM1, ALARM2, and status registers at once */
  374. ret = ds1307->read_block_data(client,
  375. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  376. if (ret != 9) {
  377. dev_err(dev, "%s error %d\n", "alarm read", ret);
  378. return -EIO;
  379. }
  380. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  381. "alarm read",
  382. ds1307->regs[0], ds1307->regs[1],
  383. ds1307->regs[2], ds1307->regs[3],
  384. ds1307->regs[4], ds1307->regs[5],
  385. ds1307->regs[6], ds1307->regs[7],
  386. ds1307->regs[8]);
  387. /*
  388. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  389. * and that all four fields are checked matches
  390. */
  391. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  392. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  393. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  394. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  395. t->time.tm_mon = -1;
  396. t->time.tm_year = -1;
  397. t->time.tm_wday = -1;
  398. t->time.tm_yday = -1;
  399. t->time.tm_isdst = -1;
  400. /* ... and status */
  401. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  402. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  403. dev_dbg(dev, "%s secs=%d, mins=%d, "
  404. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  405. "alarm read", t->time.tm_sec, t->time.tm_min,
  406. t->time.tm_hour, t->time.tm_mday,
  407. t->enabled, t->pending);
  408. return 0;
  409. }
  410. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  411. {
  412. struct i2c_client *client = to_i2c_client(dev);
  413. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  414. unsigned char *buf = ds1307->regs;
  415. u8 control, status;
  416. int ret;
  417. if (!test_bit(HAS_ALARM, &ds1307->flags))
  418. return -EINVAL;
  419. dev_dbg(dev, "%s secs=%d, mins=%d, "
  420. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  421. "alarm set", t->time.tm_sec, t->time.tm_min,
  422. t->time.tm_hour, t->time.tm_mday,
  423. t->enabled, t->pending);
  424. /* read current status of both alarms and the chip */
  425. ret = ds1307->read_block_data(client,
  426. DS1339_REG_ALARM1_SECS, 9, buf);
  427. if (ret != 9) {
  428. dev_err(dev, "%s error %d\n", "alarm write", ret);
  429. return -EIO;
  430. }
  431. control = ds1307->regs[7];
  432. status = ds1307->regs[8];
  433. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  434. "alarm set (old status)",
  435. ds1307->regs[0], ds1307->regs[1],
  436. ds1307->regs[2], ds1307->regs[3],
  437. ds1307->regs[4], ds1307->regs[5],
  438. ds1307->regs[6], control, status);
  439. /* set ALARM1, using 24 hour and day-of-month modes */
  440. buf[0] = bin2bcd(t->time.tm_sec);
  441. buf[1] = bin2bcd(t->time.tm_min);
  442. buf[2] = bin2bcd(t->time.tm_hour);
  443. buf[3] = bin2bcd(t->time.tm_mday);
  444. /* set ALARM2 to non-garbage */
  445. buf[4] = 0;
  446. buf[5] = 0;
  447. buf[6] = 0;
  448. /* optionally enable ALARM1 */
  449. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  450. if (t->enabled) {
  451. dev_dbg(dev, "alarm IRQ armed\n");
  452. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  453. }
  454. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  455. ret = ds1307->write_block_data(client,
  456. DS1339_REG_ALARM1_SECS, 9, buf);
  457. if (ret < 0) {
  458. dev_err(dev, "can't set alarm time\n");
  459. return ret;
  460. }
  461. return 0;
  462. }
  463. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  464. {
  465. struct i2c_client *client = to_i2c_client(dev);
  466. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  467. int ret;
  468. if (!test_bit(HAS_ALARM, &ds1307->flags))
  469. return -ENOTTY;
  470. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  471. if (ret < 0)
  472. return ret;
  473. if (enabled)
  474. ret |= DS1337_BIT_A1IE;
  475. else
  476. ret &= ~DS1337_BIT_A1IE;
  477. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  478. if (ret < 0)
  479. return ret;
  480. return 0;
  481. }
  482. static const struct rtc_class_ops ds13xx_rtc_ops = {
  483. .read_time = ds1307_get_time,
  484. .set_time = ds1307_set_time,
  485. .read_alarm = ds1337_read_alarm,
  486. .set_alarm = ds1337_set_alarm,
  487. .alarm_irq_enable = ds1307_alarm_irq_enable,
  488. };
  489. /*----------------------------------------------------------------------*/
  490. static ssize_t
  491. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  492. struct bin_attribute *attr,
  493. char *buf, loff_t off, size_t count)
  494. {
  495. struct i2c_client *client;
  496. struct ds1307 *ds1307;
  497. int result;
  498. client = kobj_to_i2c_client(kobj);
  499. ds1307 = i2c_get_clientdata(client);
  500. if (unlikely(off >= ds1307->nvram->size))
  501. return 0;
  502. if ((off + count) > ds1307->nvram->size)
  503. count = ds1307->nvram->size - off;
  504. if (unlikely(!count))
  505. return count;
  506. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  507. count, buf);
  508. if (result < 0)
  509. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  510. return result;
  511. }
  512. static ssize_t
  513. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  514. struct bin_attribute *attr,
  515. char *buf, loff_t off, size_t count)
  516. {
  517. struct i2c_client *client;
  518. struct ds1307 *ds1307;
  519. int result;
  520. client = kobj_to_i2c_client(kobj);
  521. ds1307 = i2c_get_clientdata(client);
  522. if (unlikely(off >= ds1307->nvram->size))
  523. return -EFBIG;
  524. if ((off + count) > ds1307->nvram->size)
  525. count = ds1307->nvram->size - off;
  526. if (unlikely(!count))
  527. return count;
  528. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  529. count, buf);
  530. if (result < 0) {
  531. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  532. return result;
  533. }
  534. return count;
  535. }
  536. /*----------------------------------------------------------------------*/
  537. static int ds1307_probe(struct i2c_client *client,
  538. const struct i2c_device_id *id)
  539. {
  540. struct ds1307 *ds1307;
  541. int err = -ENODEV;
  542. int tmp;
  543. const struct chip_desc *chip = &chips[id->driver_data];
  544. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  545. int want_irq = false;
  546. unsigned char *buf;
  547. struct ds1307_platform_data *pdata = client->dev.platform_data;
  548. static const int bbsqi_bitpos[] = {
  549. [ds_1337] = 0,
  550. [ds_1339] = DS1339_BIT_BBSQI,
  551. [ds_3231] = DS3231_BIT_BBSQW,
  552. };
  553. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  554. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  555. return -EIO;
  556. ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL);
  557. if (!ds1307)
  558. return -ENOMEM;
  559. i2c_set_clientdata(client, ds1307);
  560. ds1307->client = client;
  561. ds1307->type = id->driver_data;
  562. if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg)
  563. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  564. DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup);
  565. buf = ds1307->regs;
  566. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  567. ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
  568. ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
  569. } else {
  570. ds1307->read_block_data = ds1307_read_block_data;
  571. ds1307->write_block_data = ds1307_write_block_data;
  572. }
  573. switch (ds1307->type) {
  574. case ds_1337:
  575. case ds_1339:
  576. case ds_3231:
  577. /* get registers that the "rtc" read below won't read... */
  578. tmp = ds1307->read_block_data(ds1307->client,
  579. DS1337_REG_CONTROL, 2, buf);
  580. if (tmp != 2) {
  581. pr_debug("read error %d\n", tmp);
  582. err = -EIO;
  583. goto exit_free;
  584. }
  585. /* oscillator off? turn it on, so clock can tick. */
  586. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  587. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  588. /*
  589. * Using IRQ? Disable the square wave and both alarms.
  590. * For some variants, be sure alarms can trigger when we're
  591. * running on Vbackup (BBSQI/BBSQW)
  592. */
  593. if (ds1307->client->irq > 0 && chip->alarm) {
  594. INIT_WORK(&ds1307->work, ds1307_work);
  595. ds1307->regs[0] |= DS1337_BIT_INTCN
  596. | bbsqi_bitpos[ds1307->type];
  597. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  598. want_irq = true;
  599. }
  600. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  601. ds1307->regs[0]);
  602. /* oscillator fault? clear flag, and warn */
  603. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  604. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  605. ds1307->regs[1] & ~DS1337_BIT_OSF);
  606. dev_warn(&client->dev, "SET TIME!\n");
  607. }
  608. break;
  609. case rx_8025:
  610. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  611. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  612. if (tmp != 2) {
  613. pr_debug("read error %d\n", tmp);
  614. err = -EIO;
  615. goto exit_free;
  616. }
  617. /* oscillator off? turn it on, so clock can tick. */
  618. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  619. ds1307->regs[1] |= RX8025_BIT_XST;
  620. i2c_smbus_write_byte_data(client,
  621. RX8025_REG_CTRL2 << 4 | 0x08,
  622. ds1307->regs[1]);
  623. dev_warn(&client->dev,
  624. "oscillator stop detected - SET TIME!\n");
  625. }
  626. if (ds1307->regs[1] & RX8025_BIT_PON) {
  627. ds1307->regs[1] &= ~RX8025_BIT_PON;
  628. i2c_smbus_write_byte_data(client,
  629. RX8025_REG_CTRL2 << 4 | 0x08,
  630. ds1307->regs[1]);
  631. dev_warn(&client->dev, "power-on detected\n");
  632. }
  633. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  634. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  635. i2c_smbus_write_byte_data(client,
  636. RX8025_REG_CTRL2 << 4 | 0x08,
  637. ds1307->regs[1]);
  638. dev_warn(&client->dev, "voltage drop detected\n");
  639. }
  640. /* make sure we are running in 24hour mode */
  641. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  642. u8 hour;
  643. /* switch to 24 hour mode */
  644. i2c_smbus_write_byte_data(client,
  645. RX8025_REG_CTRL1 << 4 | 0x08,
  646. ds1307->regs[0] |
  647. RX8025_BIT_2412);
  648. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  649. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  650. if (tmp != 2) {
  651. pr_debug("read error %d\n", tmp);
  652. err = -EIO;
  653. goto exit_free;
  654. }
  655. /* correct hour */
  656. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  657. if (hour == 12)
  658. hour = 0;
  659. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  660. hour += 12;
  661. i2c_smbus_write_byte_data(client,
  662. DS1307_REG_HOUR << 4 | 0x08,
  663. hour);
  664. }
  665. break;
  666. case ds_1388:
  667. ds1307->offset = 1; /* Seconds starts at 1 */
  668. break;
  669. default:
  670. break;
  671. }
  672. read_rtc:
  673. /* read RTC registers */
  674. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  675. if (tmp != 8) {
  676. pr_debug("read error %d\n", tmp);
  677. err = -EIO;
  678. goto exit_free;
  679. }
  680. /*
  681. * minimal sanity checking; some chips (like DS1340) don't
  682. * specify the extra bits as must-be-zero, but there are
  683. * still a few values that are clearly out-of-range.
  684. */
  685. tmp = ds1307->regs[DS1307_REG_SECS];
  686. switch (ds1307->type) {
  687. case ds_1307:
  688. case m41t00:
  689. /* clock halted? turn it on, so clock can tick. */
  690. if (tmp & DS1307_BIT_CH) {
  691. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  692. dev_warn(&client->dev, "SET TIME!\n");
  693. goto read_rtc;
  694. }
  695. break;
  696. case ds_1338:
  697. /* clock halted? turn it on, so clock can tick. */
  698. if (tmp & DS1307_BIT_CH)
  699. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  700. /* oscillator fault? clear flag, and warn */
  701. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  702. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  703. ds1307->regs[DS1307_REG_CONTROL]
  704. & ~DS1338_BIT_OSF);
  705. dev_warn(&client->dev, "SET TIME!\n");
  706. goto read_rtc;
  707. }
  708. break;
  709. case ds_1340:
  710. /* clock halted? turn it on, so clock can tick. */
  711. if (tmp & DS1340_BIT_nEOSC)
  712. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  713. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  714. if (tmp < 0) {
  715. pr_debug("read error %d\n", tmp);
  716. err = -EIO;
  717. goto exit_free;
  718. }
  719. /* oscillator fault? clear flag, and warn */
  720. if (tmp & DS1340_BIT_OSF) {
  721. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  722. dev_warn(&client->dev, "SET TIME!\n");
  723. }
  724. break;
  725. case mcp7941x:
  726. /* make sure that the backup battery is enabled */
  727. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
  728. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  729. ds1307->regs[DS1307_REG_WDAY]
  730. | MCP7941X_BIT_VBATEN);
  731. }
  732. /* clock halted? turn it on, so clock can tick. */
  733. if (!(tmp & MCP7941X_BIT_ST)) {
  734. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  735. MCP7941X_BIT_ST);
  736. dev_warn(&client->dev, "SET TIME!\n");
  737. goto read_rtc;
  738. }
  739. break;
  740. default:
  741. break;
  742. }
  743. tmp = ds1307->regs[DS1307_REG_HOUR];
  744. switch (ds1307->type) {
  745. case ds_1340:
  746. case m41t00:
  747. /*
  748. * NOTE: ignores century bits; fix before deploying
  749. * systems that will run through year 2100.
  750. */
  751. break;
  752. case rx_8025:
  753. break;
  754. default:
  755. if (!(tmp & DS1307_BIT_12HR))
  756. break;
  757. /*
  758. * Be sure we're in 24 hour mode. Multi-master systems
  759. * take note...
  760. */
  761. tmp = bcd2bin(tmp & 0x1f);
  762. if (tmp == 12)
  763. tmp = 0;
  764. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  765. tmp += 12;
  766. i2c_smbus_write_byte_data(client,
  767. ds1307->offset + DS1307_REG_HOUR,
  768. bin2bcd(tmp));
  769. }
  770. ds1307->rtc = rtc_device_register(client->name, &client->dev,
  771. &ds13xx_rtc_ops, THIS_MODULE);
  772. if (IS_ERR(ds1307->rtc)) {
  773. err = PTR_ERR(ds1307->rtc);
  774. dev_err(&client->dev,
  775. "unable to register the class device\n");
  776. goto exit_free;
  777. }
  778. if (want_irq) {
  779. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  780. ds1307->rtc->name, client);
  781. if (err) {
  782. dev_err(&client->dev,
  783. "unable to request IRQ!\n");
  784. goto exit_irq;
  785. }
  786. device_set_wakeup_capable(&client->dev, 1);
  787. set_bit(HAS_ALARM, &ds1307->flags);
  788. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  789. }
  790. if (chip->nvram_size) {
  791. ds1307->nvram = kzalloc(sizeof(struct bin_attribute),
  792. GFP_KERNEL);
  793. if (!ds1307->nvram) {
  794. err = -ENOMEM;
  795. goto exit_nvram;
  796. }
  797. ds1307->nvram->attr.name = "nvram";
  798. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  799. sysfs_bin_attr_init(ds1307->nvram);
  800. ds1307->nvram->read = ds1307_nvram_read,
  801. ds1307->nvram->write = ds1307_nvram_write,
  802. ds1307->nvram->size = chip->nvram_size;
  803. ds1307->nvram_offset = chip->nvram_offset;
  804. err = sysfs_create_bin_file(&client->dev.kobj, ds1307->nvram);
  805. if (err) {
  806. kfree(ds1307->nvram);
  807. goto exit_nvram;
  808. }
  809. set_bit(HAS_NVRAM, &ds1307->flags);
  810. dev_info(&client->dev, "%zu bytes nvram\n", ds1307->nvram->size);
  811. }
  812. return 0;
  813. exit_nvram:
  814. exit_irq:
  815. rtc_device_unregister(ds1307->rtc);
  816. exit_free:
  817. kfree(ds1307);
  818. return err;
  819. }
  820. static int ds1307_remove(struct i2c_client *client)
  821. {
  822. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  823. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  824. free_irq(client->irq, client);
  825. cancel_work_sync(&ds1307->work);
  826. }
  827. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) {
  828. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  829. kfree(ds1307->nvram);
  830. }
  831. rtc_device_unregister(ds1307->rtc);
  832. kfree(ds1307);
  833. return 0;
  834. }
  835. static struct i2c_driver ds1307_driver = {
  836. .driver = {
  837. .name = "rtc-ds1307",
  838. .owner = THIS_MODULE,
  839. },
  840. .probe = ds1307_probe,
  841. .remove = ds1307_remove,
  842. .id_table = ds1307_id,
  843. };
  844. module_i2c_driver(ds1307_driver);
  845. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  846. MODULE_LICENSE("GPL");