pinctrl-lantiq.h 3.4 KB

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  1. /*
  2. * linux/drivers/pinctrl/pinctrl-lantiq.h
  3. * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * publishhed by the Free Software Foundation.
  8. *
  9. * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
  10. */
  11. #ifndef __PINCTRL_LANTIQ_H
  12. #include <linux/clkdev.h>
  13. #include <linux/pinctrl/pinctrl.h>
  14. #include <linux/pinctrl/pinconf.h>
  15. #include <linux/pinctrl/pinmux.h>
  16. #include <linux/pinctrl/consumer.h>
  17. #include <linux/pinctrl/machine.h>
  18. #include "core.h"
  19. #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
  20. #define LTQ_MAX_MUX 4
  21. #define MFPR_FUNC_MASK 0x3
  22. #define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))
  23. #define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
  24. #define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
  25. enum ltq_pinconf_param {
  26. LTQ_PINCONF_PARAM_PULL,
  27. LTQ_PINCONF_PARAM_OPEN_DRAIN,
  28. LTQ_PINCONF_PARAM_DRIVE_CURRENT,
  29. LTQ_PINCONF_PARAM_SLEW_RATE,
  30. };
  31. struct ltq_cfg_param {
  32. const char *property;
  33. enum ltq_pinconf_param param;
  34. };
  35. struct ltq_mfp_pin {
  36. const char *name;
  37. const unsigned int pin;
  38. const unsigned short func[LTQ_MAX_MUX];
  39. };
  40. struct ltq_pin_group {
  41. const char *name;
  42. const unsigned mux;
  43. const unsigned *pins;
  44. const unsigned npins;
  45. };
  46. struct ltq_pmx_func {
  47. const char *name;
  48. const char * const *groups;
  49. const unsigned num_groups;
  50. };
  51. struct ltq_pinmux_info {
  52. struct device *dev;
  53. struct pinctrl_dev *pctrl;
  54. /* we need to manage up to 5 pad controllers */
  55. void __iomem *membase[5];
  56. /* the descriptor for the subsystem */
  57. struct pinctrl_desc *desc;
  58. /* we expose our pads to the subsystem */
  59. struct pinctrl_pin_desc *pads;
  60. /* the number of pads. this varies between socs */
  61. unsigned int num_pads;
  62. /* these are our multifunction pins */
  63. const struct ltq_mfp_pin *mfp;
  64. unsigned int num_mfp;
  65. /* a number of multifunction pins can be grouped together */
  66. const struct ltq_pin_group *grps;
  67. unsigned int num_grps;
  68. /* a mapping between function string and id */
  69. const struct ltq_pmx_func *funcs;
  70. unsigned int num_funcs;
  71. /* the pinconf options that we are able to read from the DT */
  72. const struct ltq_cfg_param *params;
  73. unsigned int num_params;
  74. /* the pad controller can have a irq mapping */
  75. const unsigned *exin;
  76. unsigned int num_exin;
  77. /* we need 5 clocks max */
  78. struct clk *clk[5];
  79. /* soc specific callback used to apply muxing */
  80. int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
  81. };
  82. enum ltq_pin {
  83. GPIO0 = 0,
  84. GPIO1,
  85. GPIO2,
  86. GPIO3,
  87. GPIO4,
  88. GPIO5,
  89. GPIO6,
  90. GPIO7,
  91. GPIO8,
  92. GPIO9,
  93. GPIO10, /* 10 */
  94. GPIO11,
  95. GPIO12,
  96. GPIO13,
  97. GPIO14,
  98. GPIO15,
  99. GPIO16,
  100. GPIO17,
  101. GPIO18,
  102. GPIO19,
  103. GPIO20, /* 20 */
  104. GPIO21,
  105. GPIO22,
  106. GPIO23,
  107. GPIO24,
  108. GPIO25,
  109. GPIO26,
  110. GPIO27,
  111. GPIO28,
  112. GPIO29,
  113. GPIO30, /* 30 */
  114. GPIO31,
  115. GPIO32,
  116. GPIO33,
  117. GPIO34,
  118. GPIO35,
  119. GPIO36,
  120. GPIO37,
  121. GPIO38,
  122. GPIO39,
  123. GPIO40, /* 40 */
  124. GPIO41,
  125. GPIO42,
  126. GPIO43,
  127. GPIO44,
  128. GPIO45,
  129. GPIO46,
  130. GPIO47,
  131. GPIO48,
  132. GPIO49,
  133. GPIO50, /* 50 */
  134. GPIO51,
  135. GPIO52,
  136. GPIO53,
  137. GPIO54,
  138. GPIO55,
  139. GPIO64,
  140. GPIO65,
  141. GPIO66,
  142. GPIO67,
  143. GPIO68,
  144. GPIO69,
  145. GPIO70,
  146. GPIO71,
  147. GPIO72,
  148. GPIO73,
  149. GPIO74,
  150. GPIO75,
  151. GPIO76,
  152. GPIO77,
  153. GPIO78,
  154. GPIO79,
  155. GPIO80,
  156. GPIO81,
  157. GPIO82,
  158. GPIO83,
  159. GPIO84,
  160. GPIO85,
  161. GPIO86,
  162. GPIO87,
  163. GPIO88,
  164. };
  165. extern int ltq_pinctrl_register(struct platform_device *pdev,
  166. struct ltq_pinmux_info *info);
  167. extern int ltq_pinctrl_unregister(struct platform_device *pdev);
  168. #endif /* __PINCTRL_PXA3XX_H */