pci.h 10 KB

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  1. #ifndef DRIVERS_PCI_H
  2. #define DRIVERS_PCI_H
  3. #include <linux/workqueue.h>
  4. #define PCI_CFG_SPACE_SIZE 256
  5. #define PCI_CFG_SPACE_EXP_SIZE 4096
  6. /* Functions internal to the PCI core code */
  7. extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  8. extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  9. #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  10. static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  11. { return; }
  12. static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  13. { return; }
  14. #else
  15. extern void pci_create_firmware_label_files(struct pci_dev *pdev);
  16. extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
  17. #endif
  18. extern void pci_cleanup_rom(struct pci_dev *dev);
  19. #ifdef HAVE_PCI_MMAP
  20. enum pci_mmap_api {
  21. PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  22. PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  23. };
  24. extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
  25. struct vm_area_struct *vmai,
  26. enum pci_mmap_api mmap_api);
  27. #endif
  28. int pci_probe_reset_function(struct pci_dev *dev);
  29. /**
  30. * struct pci_platform_pm_ops - Firmware PM callbacks
  31. *
  32. * @is_manageable: returns 'true' if given device is power manageable by the
  33. * platform firmware
  34. *
  35. * @set_state: invokes the platform firmware to set the device's power state
  36. *
  37. * @choose_state: returns PCI power state of given device preferred by the
  38. * platform; to be used during system-wide transitions from a
  39. * sleeping state to the working state and vice versa
  40. *
  41. * @can_wakeup: returns 'true' if given device is capable of waking up the
  42. * system from a sleeping state
  43. *
  44. * @sleep_wake: enables/disables the system wake up capability of given device
  45. *
  46. * @run_wake: enables/disables the platform to generate run-time wake-up events
  47. * for given device (the device's wake-up capability has to be
  48. * enabled by @sleep_wake for this feature to work)
  49. *
  50. * If given platform is generally capable of power managing PCI devices, all of
  51. * these callbacks are mandatory.
  52. */
  53. struct pci_platform_pm_ops {
  54. bool (*is_manageable)(struct pci_dev *dev);
  55. int (*set_state)(struct pci_dev *dev, pci_power_t state);
  56. pci_power_t (*choose_state)(struct pci_dev *dev);
  57. bool (*can_wakeup)(struct pci_dev *dev);
  58. int (*sleep_wake)(struct pci_dev *dev, bool enable);
  59. int (*run_wake)(struct pci_dev *dev, bool enable);
  60. };
  61. extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
  62. extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  63. extern void pci_power_up(struct pci_dev *dev);
  64. extern void pci_disable_enabled_device(struct pci_dev *dev);
  65. extern int pci_finish_runtime_suspend(struct pci_dev *dev);
  66. extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  67. extern void pci_wakeup_bus(struct pci_bus *bus);
  68. extern void pci_config_pm_runtime_get(struct pci_dev *dev);
  69. extern void pci_config_pm_runtime_put(struct pci_dev *dev);
  70. extern void pci_pm_init(struct pci_dev *dev);
  71. extern void platform_pci_wakeup_init(struct pci_dev *dev);
  72. extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  73. void pci_free_cap_save_buffers(struct pci_dev *dev);
  74. static inline void pci_wakeup_event(struct pci_dev *dev)
  75. {
  76. /* Wait 100 ms before the system can be put into a sleep state. */
  77. pm_wakeup_event(&dev->dev, 100);
  78. }
  79. static inline bool pci_is_bridge(struct pci_dev *pci_dev)
  80. {
  81. return !!(pci_dev->subordinate);
  82. }
  83. struct pci_vpd_ops {
  84. ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
  85. ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
  86. void (*release)(struct pci_dev *dev);
  87. };
  88. struct pci_vpd {
  89. unsigned int len;
  90. const struct pci_vpd_ops *ops;
  91. struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
  92. };
  93. extern int pci_vpd_pci22_init(struct pci_dev *dev);
  94. static inline void pci_vpd_release(struct pci_dev *dev)
  95. {
  96. if (dev->vpd)
  97. dev->vpd->ops->release(dev);
  98. }
  99. /* PCI /proc functions */
  100. #ifdef CONFIG_PROC_FS
  101. extern int pci_proc_attach_device(struct pci_dev *dev);
  102. extern int pci_proc_detach_device(struct pci_dev *dev);
  103. extern int pci_proc_detach_bus(struct pci_bus *bus);
  104. #else
  105. static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
  106. static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
  107. static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
  108. #endif
  109. /* Functions for PCI Hotplug drivers to use */
  110. int pci_hp_add_bridge(struct pci_dev *dev);
  111. #ifdef HAVE_PCI_LEGACY
  112. extern void pci_create_legacy_files(struct pci_bus *bus);
  113. extern void pci_remove_legacy_files(struct pci_bus *bus);
  114. #else
  115. static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
  116. static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
  117. #endif
  118. /* Lock for read/write access to pci device and bus lists */
  119. extern struct rw_semaphore pci_bus_sem;
  120. extern raw_spinlock_t pci_lock;
  121. extern unsigned int pci_pm_d3_delay;
  122. #ifdef CONFIG_PCI_MSI
  123. void pci_no_msi(void);
  124. extern void pci_msi_init_pci_dev(struct pci_dev *dev);
  125. #else
  126. static inline void pci_no_msi(void) { }
  127. static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
  128. #endif
  129. void pci_realloc_get_opt(char *);
  130. static inline int pci_no_d1d2(struct pci_dev *dev)
  131. {
  132. unsigned int parent_dstates = 0;
  133. if (dev->bus->self)
  134. parent_dstates = dev->bus->self->no_d1d2;
  135. return (dev->no_d1d2 || parent_dstates);
  136. }
  137. extern struct device_attribute pci_dev_attrs[];
  138. extern struct device_attribute pcibus_dev_attrs[];
  139. extern struct device_type pci_dev_type;
  140. extern struct bus_attribute pci_bus_attrs[];
  141. /**
  142. * pci_match_one_device - Tell if a PCI device structure has a matching
  143. * PCI device id structure
  144. * @id: single PCI device id structure to match
  145. * @dev: the PCI device structure to match against
  146. *
  147. * Returns the matching pci_device_id structure or %NULL if there is no match.
  148. */
  149. static inline const struct pci_device_id *
  150. pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
  151. {
  152. if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
  153. (id->device == PCI_ANY_ID || id->device == dev->device) &&
  154. (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
  155. (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
  156. !((id->class ^ dev->class) & id->class_mask))
  157. return id;
  158. return NULL;
  159. }
  160. /* PCI slot sysfs helper code */
  161. #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
  162. extern struct kset *pci_slots_kset;
  163. struct pci_slot_attribute {
  164. struct attribute attr;
  165. ssize_t (*show)(struct pci_slot *, char *);
  166. ssize_t (*store)(struct pci_slot *, const char *, size_t);
  167. };
  168. #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
  169. enum pci_bar_type {
  170. pci_bar_unknown, /* Standard PCI BAR probe */
  171. pci_bar_io, /* An io port BAR */
  172. pci_bar_mem32, /* A 32-bit memory BAR */
  173. pci_bar_mem64, /* A 64-bit memory BAR */
  174. };
  175. bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
  176. int crs_timeout);
  177. extern int pci_setup_device(struct pci_dev *dev);
  178. extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
  179. struct resource *res, unsigned int reg);
  180. extern int pci_resource_bar(struct pci_dev *dev, int resno,
  181. enum pci_bar_type *type);
  182. extern int pci_bus_add_child(struct pci_bus *bus);
  183. extern void pci_enable_ari(struct pci_dev *dev);
  184. /**
  185. * pci_ari_enabled - query ARI forwarding status
  186. * @bus: the PCI bus
  187. *
  188. * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
  189. */
  190. static inline int pci_ari_enabled(struct pci_bus *bus)
  191. {
  192. return bus->self && bus->self->ari_enabled;
  193. }
  194. void pci_reassigndev_resource_alignment(struct pci_dev *dev);
  195. extern void pci_disable_bridge_window(struct pci_dev *dev);
  196. /* Single Root I/O Virtualization */
  197. struct pci_sriov {
  198. int pos; /* capability position */
  199. int nres; /* number of resources */
  200. u32 cap; /* SR-IOV Capabilities */
  201. u16 ctrl; /* SR-IOV Control */
  202. u16 total_VFs; /* total VFs associated with the PF */
  203. u16 initial_VFs; /* initial VFs associated with the PF */
  204. u16 num_VFs; /* number of VFs available */
  205. u16 offset; /* first VF Routing ID offset */
  206. u16 stride; /* following VF stride */
  207. u32 pgsz; /* page size for BAR alignment */
  208. u8 link; /* Function Dependency Link */
  209. u16 driver_max_VFs; /* max num VFs driver supports */
  210. struct pci_dev *dev; /* lowest numbered PF */
  211. struct pci_dev *self; /* this PF */
  212. struct mutex lock; /* lock for VF bus */
  213. struct work_struct mtask; /* VF Migration task */
  214. u8 __iomem *mstate; /* VF Migration State Array */
  215. };
  216. #ifdef CONFIG_PCI_ATS
  217. extern void pci_restore_ats_state(struct pci_dev *dev);
  218. #else
  219. static inline void pci_restore_ats_state(struct pci_dev *dev)
  220. {
  221. }
  222. #endif /* CONFIG_PCI_ATS */
  223. #ifdef CONFIG_PCI_IOV
  224. extern int pci_iov_init(struct pci_dev *dev);
  225. extern void pci_iov_release(struct pci_dev *dev);
  226. extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
  227. enum pci_bar_type *type);
  228. extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
  229. int resno);
  230. extern void pci_restore_iov_state(struct pci_dev *dev);
  231. extern int pci_iov_bus_range(struct pci_bus *bus);
  232. #else
  233. static inline int pci_iov_init(struct pci_dev *dev)
  234. {
  235. return -ENODEV;
  236. }
  237. static inline void pci_iov_release(struct pci_dev *dev)
  238. {
  239. }
  240. static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
  241. enum pci_bar_type *type)
  242. {
  243. return 0;
  244. }
  245. static inline void pci_restore_iov_state(struct pci_dev *dev)
  246. {
  247. }
  248. static inline int pci_iov_bus_range(struct pci_bus *bus)
  249. {
  250. return 0;
  251. }
  252. #endif /* CONFIG_PCI_IOV */
  253. extern unsigned long pci_cardbus_resource_alignment(struct resource *);
  254. static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
  255. struct resource *res)
  256. {
  257. #ifdef CONFIG_PCI_IOV
  258. int resno = res - dev->resource;
  259. if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
  260. return pci_sriov_resource_alignment(dev, resno);
  261. #endif
  262. if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
  263. return pci_cardbus_resource_alignment(res);
  264. return resource_alignment(res);
  265. }
  266. extern void pci_enable_acs(struct pci_dev *dev);
  267. struct pci_dev_reset_methods {
  268. u16 vendor;
  269. u16 device;
  270. int (*reset)(struct pci_dev *dev, int probe);
  271. };
  272. #ifdef CONFIG_PCI_QUIRKS
  273. extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
  274. #else
  275. static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
  276. {
  277. return -ENOTTY;
  278. }
  279. #endif
  280. #endif /* DRIVERS_PCI_H */