main.c 55 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_stoprecv(sc))
  168. ret = false;
  169. if (!ath_drain_all_txq(sc, retry_tx))
  170. ret = false;
  171. if (!flush) {
  172. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  173. ath_rx_tasklet(sc, 1, true);
  174. ath_rx_tasklet(sc, 1, false);
  175. } else {
  176. ath_flushrecv(sc);
  177. }
  178. return ret;
  179. }
  180. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  181. {
  182. struct ath_hw *ah = sc->sc_ah;
  183. struct ath_common *common = ath9k_hw_common(ah);
  184. unsigned long flags;
  185. if (ath_startrecv(sc) != 0) {
  186. ath_err(common, "Unable to restart recv logic\n");
  187. return false;
  188. }
  189. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  190. sc->config.txpowlimit, &sc->curtxpow);
  191. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  192. ath9k_hw_set_interrupts(ah);
  193. ath9k_hw_enable_interrupts(ah);
  194. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  195. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  196. goto work;
  197. ath9k_set_beacon(sc);
  198. if (ah->opmode == NL80211_IFTYPE_STATION &&
  199. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  200. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  201. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  202. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  203. }
  204. work:
  205. ath_restart_work(sc);
  206. }
  207. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  208. ath_ant_comb_update(sc);
  209. ieee80211_wake_queues(sc->hw);
  210. return true;
  211. }
  212. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  213. bool retry_tx)
  214. {
  215. struct ath_hw *ah = sc->sc_ah;
  216. struct ath_common *common = ath9k_hw_common(ah);
  217. struct ath9k_hw_cal_data *caldata = NULL;
  218. bool fastcc = true;
  219. bool flush = false;
  220. int r;
  221. __ath_cancel_work(sc);
  222. spin_lock_bh(&sc->sc_pcu_lock);
  223. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  224. fastcc = false;
  225. caldata = &sc->caldata;
  226. }
  227. if (!hchan) {
  228. fastcc = false;
  229. flush = true;
  230. hchan = ah->curchan;
  231. }
  232. if (!ath_prepare_reset(sc, retry_tx, flush))
  233. fastcc = false;
  234. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  235. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  236. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  237. if (r) {
  238. ath_err(common,
  239. "Unable to reset channel, reset status %d\n", r);
  240. goto out;
  241. }
  242. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  243. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  244. ath9k_mci_set_txpower(sc, true, false);
  245. if (!ath_complete_reset(sc, true))
  246. r = -EIO;
  247. out:
  248. spin_unlock_bh(&sc->sc_pcu_lock);
  249. return r;
  250. }
  251. /*
  252. * Set/change channels. If the channel is really being changed, it's done
  253. * by reseting the chip. To accomplish this we must first cleanup any pending
  254. * DMA, then restart stuff.
  255. */
  256. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  257. struct ath9k_channel *hchan)
  258. {
  259. int r;
  260. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  261. return -EIO;
  262. r = ath_reset_internal(sc, hchan, false);
  263. return r;
  264. }
  265. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  266. struct ieee80211_vif *vif)
  267. {
  268. struct ath_node *an;
  269. u8 density;
  270. an = (struct ath_node *)sta->drv_priv;
  271. an->sc = sc;
  272. an->sta = sta;
  273. an->vif = vif;
  274. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  275. ath_tx_node_init(sc, an);
  276. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  277. sta->ht_cap.ampdu_factor);
  278. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  279. an->mpdudensity = density;
  280. }
  281. }
  282. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  283. {
  284. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  285. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  286. ath_tx_node_cleanup(sc, an);
  287. }
  288. void ath9k_tasklet(unsigned long data)
  289. {
  290. struct ath_softc *sc = (struct ath_softc *)data;
  291. struct ath_hw *ah = sc->sc_ah;
  292. struct ath_common *common = ath9k_hw_common(ah);
  293. enum ath_reset_type type;
  294. unsigned long flags;
  295. u32 status = sc->intrstatus;
  296. u32 rxmask;
  297. ath9k_ps_wakeup(sc);
  298. spin_lock(&sc->sc_pcu_lock);
  299. if ((status & ATH9K_INT_FATAL) ||
  300. (status & ATH9K_INT_BB_WATCHDOG)) {
  301. if (status & ATH9K_INT_FATAL)
  302. type = RESET_TYPE_FATAL_INT;
  303. else
  304. type = RESET_TYPE_BB_WATCHDOG;
  305. ath9k_queue_reset(sc, type);
  306. goto out;
  307. }
  308. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  309. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  310. /*
  311. * TSF sync does not look correct; remain awake to sync with
  312. * the next Beacon.
  313. */
  314. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  315. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  316. }
  317. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  318. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  319. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  320. ATH9K_INT_RXORN);
  321. else
  322. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  323. if (status & rxmask) {
  324. /* Check for high priority Rx first */
  325. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  326. (status & ATH9K_INT_RXHP))
  327. ath_rx_tasklet(sc, 0, true);
  328. ath_rx_tasklet(sc, 0, false);
  329. }
  330. if (status & ATH9K_INT_TX) {
  331. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  332. ath_tx_edma_tasklet(sc);
  333. else
  334. ath_tx_tasklet(sc);
  335. }
  336. ath9k_btcoex_handle_interrupt(sc, status);
  337. out:
  338. /* re-enable hardware interrupt */
  339. ath9k_hw_enable_interrupts(ah);
  340. spin_unlock(&sc->sc_pcu_lock);
  341. ath9k_ps_restore(sc);
  342. }
  343. irqreturn_t ath_isr(int irq, void *dev)
  344. {
  345. #define SCHED_INTR ( \
  346. ATH9K_INT_FATAL | \
  347. ATH9K_INT_BB_WATCHDOG | \
  348. ATH9K_INT_RXORN | \
  349. ATH9K_INT_RXEOL | \
  350. ATH9K_INT_RX | \
  351. ATH9K_INT_RXLP | \
  352. ATH9K_INT_RXHP | \
  353. ATH9K_INT_TX | \
  354. ATH9K_INT_BMISS | \
  355. ATH9K_INT_CST | \
  356. ATH9K_INT_TSFOOR | \
  357. ATH9K_INT_GENTIMER | \
  358. ATH9K_INT_MCI)
  359. struct ath_softc *sc = dev;
  360. struct ath_hw *ah = sc->sc_ah;
  361. struct ath_common *common = ath9k_hw_common(ah);
  362. enum ath9k_int status;
  363. bool sched = false;
  364. /*
  365. * The hardware is not ready/present, don't
  366. * touch anything. Note this can happen early
  367. * on if the IRQ is shared.
  368. */
  369. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  370. return IRQ_NONE;
  371. /* shared irq, not for us */
  372. if (!ath9k_hw_intrpend(ah))
  373. return IRQ_NONE;
  374. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  375. ath9k_hw_kill_interrupts(ah);
  376. return IRQ_HANDLED;
  377. }
  378. /*
  379. * Figure out the reason(s) for the interrupt. Note
  380. * that the hal returns a pseudo-ISR that may include
  381. * bits we haven't explicitly enabled so we mask the
  382. * value to insure we only process bits we requested.
  383. */
  384. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  385. status &= ah->imask; /* discard unasked-for bits */
  386. /*
  387. * If there are no status bits set, then this interrupt was not
  388. * for me (should have been caught above).
  389. */
  390. if (!status)
  391. return IRQ_NONE;
  392. /* Cache the status */
  393. sc->intrstatus = status;
  394. if (status & SCHED_INTR)
  395. sched = true;
  396. /*
  397. * If a FATAL or RXORN interrupt is received, we have to reset the
  398. * chip immediately.
  399. */
  400. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  401. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  402. goto chip_reset;
  403. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  404. (status & ATH9K_INT_BB_WATCHDOG)) {
  405. spin_lock(&common->cc_lock);
  406. ath_hw_cycle_counters_update(common);
  407. ar9003_hw_bb_watchdog_dbg_info(ah);
  408. spin_unlock(&common->cc_lock);
  409. goto chip_reset;
  410. }
  411. #ifdef CONFIG_PM_SLEEP
  412. if (status & ATH9K_INT_BMISS) {
  413. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  414. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  415. atomic_inc(&sc->wow_got_bmiss_intr);
  416. atomic_dec(&sc->wow_sleep_proc_intr);
  417. }
  418. }
  419. #endif
  420. if (status & ATH9K_INT_SWBA)
  421. tasklet_schedule(&sc->bcon_tasklet);
  422. if (status & ATH9K_INT_TXURN)
  423. ath9k_hw_updatetxtriglevel(ah, true);
  424. if (status & ATH9K_INT_RXEOL) {
  425. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  426. ath9k_hw_set_interrupts(ah);
  427. }
  428. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  429. if (status & ATH9K_INT_TIM_TIMER) {
  430. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  431. goto chip_reset;
  432. /* Clear RxAbort bit so that we can
  433. * receive frames */
  434. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  435. spin_lock(&sc->sc_pm_lock);
  436. ath9k_hw_setrxabort(sc->sc_ah, 0);
  437. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  438. spin_unlock(&sc->sc_pm_lock);
  439. }
  440. chip_reset:
  441. ath_debug_stat_interrupt(sc, status);
  442. if (sched) {
  443. /* turn off every interrupt */
  444. ath9k_hw_disable_interrupts(ah);
  445. tasklet_schedule(&sc->intr_tq);
  446. }
  447. return IRQ_HANDLED;
  448. #undef SCHED_INTR
  449. }
  450. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  451. {
  452. int r;
  453. ath9k_ps_wakeup(sc);
  454. r = ath_reset_internal(sc, NULL, retry_tx);
  455. if (retry_tx) {
  456. int i;
  457. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  458. if (ATH_TXQ_SETUP(sc, i)) {
  459. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  460. ath_txq_schedule(sc, &sc->tx.txq[i]);
  461. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  462. }
  463. }
  464. }
  465. ath9k_ps_restore(sc);
  466. return r;
  467. }
  468. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  469. {
  470. #ifdef CONFIG_ATH9K_DEBUGFS
  471. RESET_STAT_INC(sc, type);
  472. #endif
  473. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  474. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  475. }
  476. void ath_reset_work(struct work_struct *work)
  477. {
  478. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  479. ath_reset(sc, true);
  480. }
  481. /**********************/
  482. /* mac80211 callbacks */
  483. /**********************/
  484. static int ath9k_start(struct ieee80211_hw *hw)
  485. {
  486. struct ath_softc *sc = hw->priv;
  487. struct ath_hw *ah = sc->sc_ah;
  488. struct ath_common *common = ath9k_hw_common(ah);
  489. struct ieee80211_channel *curchan = hw->conf.channel;
  490. struct ath9k_channel *init_channel;
  491. int r;
  492. ath_dbg(common, CONFIG,
  493. "Starting driver with initial channel: %d MHz\n",
  494. curchan->center_freq);
  495. ath9k_ps_wakeup(sc);
  496. mutex_lock(&sc->mutex);
  497. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  498. /* Reset SERDES registers */
  499. ath9k_hw_configpcipowersave(ah, false);
  500. /*
  501. * The basic interface to setting the hardware in a good
  502. * state is ``reset''. On return the hardware is known to
  503. * be powered up and with interrupts disabled. This must
  504. * be followed by initialization of the appropriate bits
  505. * and then setup of the interrupt mask.
  506. */
  507. spin_lock_bh(&sc->sc_pcu_lock);
  508. atomic_set(&ah->intr_ref_cnt, -1);
  509. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  510. if (r) {
  511. ath_err(common,
  512. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  513. r, curchan->center_freq);
  514. ah->reset_power_on = false;
  515. }
  516. /* Setup our intr mask. */
  517. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  518. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  519. ATH9K_INT_GLOBAL;
  520. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  521. ah->imask |= ATH9K_INT_RXHP |
  522. ATH9K_INT_RXLP |
  523. ATH9K_INT_BB_WATCHDOG;
  524. else
  525. ah->imask |= ATH9K_INT_RX;
  526. ah->imask |= ATH9K_INT_GTT;
  527. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  528. ah->imask |= ATH9K_INT_CST;
  529. ath_mci_enable(sc);
  530. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  531. sc->sc_ah->is_monitoring = false;
  532. if (!ath_complete_reset(sc, false))
  533. ah->reset_power_on = false;
  534. if (ah->led_pin >= 0) {
  535. ath9k_hw_cfg_output(ah, ah->led_pin,
  536. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  537. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  538. }
  539. /*
  540. * Reset key cache to sane defaults (all entries cleared) instead of
  541. * semi-random values after suspend/resume.
  542. */
  543. ath9k_cmn_init_crypto(sc->sc_ah);
  544. spin_unlock_bh(&sc->sc_pcu_lock);
  545. mutex_unlock(&sc->mutex);
  546. ath9k_ps_restore(sc);
  547. return 0;
  548. }
  549. static void ath9k_tx(struct ieee80211_hw *hw,
  550. struct ieee80211_tx_control *control,
  551. struct sk_buff *skb)
  552. {
  553. struct ath_softc *sc = hw->priv;
  554. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  555. struct ath_tx_control txctl;
  556. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  557. unsigned long flags;
  558. if (sc->ps_enabled) {
  559. /*
  560. * mac80211 does not set PM field for normal data frames, so we
  561. * need to update that based on the current PS mode.
  562. */
  563. if (ieee80211_is_data(hdr->frame_control) &&
  564. !ieee80211_is_nullfunc(hdr->frame_control) &&
  565. !ieee80211_has_pm(hdr->frame_control)) {
  566. ath_dbg(common, PS,
  567. "Add PM=1 for a TX frame while in PS mode\n");
  568. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  569. }
  570. }
  571. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  572. /*
  573. * We are using PS-Poll and mac80211 can request TX while in
  574. * power save mode. Need to wake up hardware for the TX to be
  575. * completed and if needed, also for RX of buffered frames.
  576. */
  577. ath9k_ps_wakeup(sc);
  578. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  579. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  580. ath9k_hw_setrxabort(sc->sc_ah, 0);
  581. if (ieee80211_is_pspoll(hdr->frame_control)) {
  582. ath_dbg(common, PS,
  583. "Sending PS-Poll to pick a buffered frame\n");
  584. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  585. } else {
  586. ath_dbg(common, PS, "Wake up to complete TX\n");
  587. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  588. }
  589. /*
  590. * The actual restore operation will happen only after
  591. * the ps_flags bit is cleared. We are just dropping
  592. * the ps_usecount here.
  593. */
  594. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  595. ath9k_ps_restore(sc);
  596. }
  597. /*
  598. * Cannot tx while the hardware is in full sleep, it first needs a full
  599. * chip reset to recover from that
  600. */
  601. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  602. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  603. goto exit;
  604. }
  605. memset(&txctl, 0, sizeof(struct ath_tx_control));
  606. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  607. txctl.sta = control->sta;
  608. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  609. if (ath_tx_start(hw, skb, &txctl) != 0) {
  610. ath_dbg(common, XMIT, "TX failed\n");
  611. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  612. goto exit;
  613. }
  614. return;
  615. exit:
  616. ieee80211_free_txskb(hw, skb);
  617. }
  618. static void ath9k_stop(struct ieee80211_hw *hw)
  619. {
  620. struct ath_softc *sc = hw->priv;
  621. struct ath_hw *ah = sc->sc_ah;
  622. struct ath_common *common = ath9k_hw_common(ah);
  623. bool prev_idle;
  624. mutex_lock(&sc->mutex);
  625. ath_cancel_work(sc);
  626. del_timer_sync(&sc->rx_poll_timer);
  627. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  628. ath_dbg(common, ANY, "Device not present\n");
  629. mutex_unlock(&sc->mutex);
  630. return;
  631. }
  632. /* Ensure HW is awake when we try to shut it down. */
  633. ath9k_ps_wakeup(sc);
  634. spin_lock_bh(&sc->sc_pcu_lock);
  635. /* prevent tasklets to enable interrupts once we disable them */
  636. ah->imask &= ~ATH9K_INT_GLOBAL;
  637. /* make sure h/w will not generate any interrupt
  638. * before setting the invalid flag. */
  639. ath9k_hw_disable_interrupts(ah);
  640. spin_unlock_bh(&sc->sc_pcu_lock);
  641. /* we can now sync irq and kill any running tasklets, since we already
  642. * disabled interrupts and not holding a spin lock */
  643. synchronize_irq(sc->irq);
  644. tasklet_kill(&sc->intr_tq);
  645. tasklet_kill(&sc->bcon_tasklet);
  646. prev_idle = sc->ps_idle;
  647. sc->ps_idle = true;
  648. spin_lock_bh(&sc->sc_pcu_lock);
  649. if (ah->led_pin >= 0) {
  650. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  651. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  652. }
  653. ath_prepare_reset(sc, false, true);
  654. if (sc->rx.frag) {
  655. dev_kfree_skb_any(sc->rx.frag);
  656. sc->rx.frag = NULL;
  657. }
  658. if (!ah->curchan)
  659. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  660. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  661. ath9k_hw_phy_disable(ah);
  662. ath9k_hw_configpcipowersave(ah, true);
  663. spin_unlock_bh(&sc->sc_pcu_lock);
  664. ath9k_ps_restore(sc);
  665. set_bit(SC_OP_INVALID, &sc->sc_flags);
  666. sc->ps_idle = prev_idle;
  667. mutex_unlock(&sc->mutex);
  668. ath_dbg(common, CONFIG, "Driver halt\n");
  669. }
  670. bool ath9k_uses_beacons(int type)
  671. {
  672. switch (type) {
  673. case NL80211_IFTYPE_AP:
  674. case NL80211_IFTYPE_ADHOC:
  675. case NL80211_IFTYPE_MESH_POINT:
  676. return true;
  677. default:
  678. return false;
  679. }
  680. }
  681. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  682. {
  683. struct ath9k_vif_iter_data *iter_data = data;
  684. int i;
  685. if (iter_data->hw_macaddr)
  686. for (i = 0; i < ETH_ALEN; i++)
  687. iter_data->mask[i] &=
  688. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  689. switch (vif->type) {
  690. case NL80211_IFTYPE_AP:
  691. iter_data->naps++;
  692. break;
  693. case NL80211_IFTYPE_STATION:
  694. iter_data->nstations++;
  695. break;
  696. case NL80211_IFTYPE_ADHOC:
  697. iter_data->nadhocs++;
  698. break;
  699. case NL80211_IFTYPE_MESH_POINT:
  700. iter_data->nmeshes++;
  701. break;
  702. case NL80211_IFTYPE_WDS:
  703. iter_data->nwds++;
  704. break;
  705. default:
  706. break;
  707. }
  708. }
  709. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  710. {
  711. struct ath_softc *sc = data;
  712. struct ath_vif *avp = (void *)vif->drv_priv;
  713. if (vif->type != NL80211_IFTYPE_STATION)
  714. return;
  715. if (avp->primary_sta_vif)
  716. ath9k_set_assoc_state(sc, vif);
  717. }
  718. /* Called with sc->mutex held. */
  719. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  720. struct ieee80211_vif *vif,
  721. struct ath9k_vif_iter_data *iter_data)
  722. {
  723. struct ath_softc *sc = hw->priv;
  724. struct ath_hw *ah = sc->sc_ah;
  725. struct ath_common *common = ath9k_hw_common(ah);
  726. /*
  727. * Use the hardware MAC address as reference, the hardware uses it
  728. * together with the BSSID mask when matching addresses.
  729. */
  730. memset(iter_data, 0, sizeof(*iter_data));
  731. iter_data->hw_macaddr = common->macaddr;
  732. memset(&iter_data->mask, 0xff, ETH_ALEN);
  733. if (vif)
  734. ath9k_vif_iter(iter_data, vif->addr, vif);
  735. /* Get list of all active MAC addresses */
  736. ieee80211_iterate_active_interfaces_atomic(
  737. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  738. ath9k_vif_iter, iter_data);
  739. }
  740. /* Called with sc->mutex held. */
  741. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  742. struct ieee80211_vif *vif)
  743. {
  744. struct ath_softc *sc = hw->priv;
  745. struct ath_hw *ah = sc->sc_ah;
  746. struct ath_common *common = ath9k_hw_common(ah);
  747. struct ath9k_vif_iter_data iter_data;
  748. enum nl80211_iftype old_opmode = ah->opmode;
  749. ath9k_calculate_iter_data(hw, vif, &iter_data);
  750. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  751. ath_hw_setbssidmask(common);
  752. if (iter_data.naps > 0) {
  753. ath9k_hw_set_tsfadjust(ah, true);
  754. ah->opmode = NL80211_IFTYPE_AP;
  755. } else {
  756. ath9k_hw_set_tsfadjust(ah, false);
  757. if (iter_data.nmeshes)
  758. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  759. else if (iter_data.nwds)
  760. ah->opmode = NL80211_IFTYPE_AP;
  761. else if (iter_data.nadhocs)
  762. ah->opmode = NL80211_IFTYPE_ADHOC;
  763. else
  764. ah->opmode = NL80211_IFTYPE_STATION;
  765. }
  766. ath9k_hw_setopmode(ah);
  767. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  768. ah->imask |= ATH9K_INT_TSFOOR;
  769. else
  770. ah->imask &= ~ATH9K_INT_TSFOOR;
  771. ath9k_hw_set_interrupts(ah);
  772. /*
  773. * If we are changing the opmode to STATION,
  774. * a beacon sync needs to be done.
  775. */
  776. if (ah->opmode == NL80211_IFTYPE_STATION &&
  777. old_opmode == NL80211_IFTYPE_AP &&
  778. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  779. ieee80211_iterate_active_interfaces_atomic(
  780. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  781. ath9k_sta_vif_iter, sc);
  782. }
  783. }
  784. static int ath9k_add_interface(struct ieee80211_hw *hw,
  785. struct ieee80211_vif *vif)
  786. {
  787. struct ath_softc *sc = hw->priv;
  788. struct ath_hw *ah = sc->sc_ah;
  789. struct ath_common *common = ath9k_hw_common(ah);
  790. mutex_lock(&sc->mutex);
  791. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  792. sc->nvifs++;
  793. ath9k_ps_wakeup(sc);
  794. ath9k_calculate_summary_state(hw, vif);
  795. ath9k_ps_restore(sc);
  796. if (ath9k_uses_beacons(vif->type))
  797. ath9k_beacon_assign_slot(sc, vif);
  798. mutex_unlock(&sc->mutex);
  799. return 0;
  800. }
  801. static int ath9k_change_interface(struct ieee80211_hw *hw,
  802. struct ieee80211_vif *vif,
  803. enum nl80211_iftype new_type,
  804. bool p2p)
  805. {
  806. struct ath_softc *sc = hw->priv;
  807. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  808. ath_dbg(common, CONFIG, "Change Interface\n");
  809. mutex_lock(&sc->mutex);
  810. if (ath9k_uses_beacons(vif->type))
  811. ath9k_beacon_remove_slot(sc, vif);
  812. vif->type = new_type;
  813. vif->p2p = p2p;
  814. ath9k_ps_wakeup(sc);
  815. ath9k_calculate_summary_state(hw, vif);
  816. ath9k_ps_restore(sc);
  817. if (ath9k_uses_beacons(vif->type))
  818. ath9k_beacon_assign_slot(sc, vif);
  819. mutex_unlock(&sc->mutex);
  820. return 0;
  821. }
  822. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  823. struct ieee80211_vif *vif)
  824. {
  825. struct ath_softc *sc = hw->priv;
  826. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  827. ath_dbg(common, CONFIG, "Detach Interface\n");
  828. mutex_lock(&sc->mutex);
  829. sc->nvifs--;
  830. if (ath9k_uses_beacons(vif->type))
  831. ath9k_beacon_remove_slot(sc, vif);
  832. ath9k_ps_wakeup(sc);
  833. ath9k_calculate_summary_state(hw, NULL);
  834. ath9k_ps_restore(sc);
  835. mutex_unlock(&sc->mutex);
  836. }
  837. static void ath9k_enable_ps(struct ath_softc *sc)
  838. {
  839. struct ath_hw *ah = sc->sc_ah;
  840. struct ath_common *common = ath9k_hw_common(ah);
  841. sc->ps_enabled = true;
  842. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  843. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  844. ah->imask |= ATH9K_INT_TIM_TIMER;
  845. ath9k_hw_set_interrupts(ah);
  846. }
  847. ath9k_hw_setrxabort(ah, 1);
  848. }
  849. ath_dbg(common, PS, "PowerSave enabled\n");
  850. }
  851. static void ath9k_disable_ps(struct ath_softc *sc)
  852. {
  853. struct ath_hw *ah = sc->sc_ah;
  854. struct ath_common *common = ath9k_hw_common(ah);
  855. sc->ps_enabled = false;
  856. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  857. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  858. ath9k_hw_setrxabort(ah, 0);
  859. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  860. PS_WAIT_FOR_CAB |
  861. PS_WAIT_FOR_PSPOLL_DATA |
  862. PS_WAIT_FOR_TX_ACK);
  863. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  864. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  865. ath9k_hw_set_interrupts(ah);
  866. }
  867. }
  868. ath_dbg(common, PS, "PowerSave disabled\n");
  869. }
  870. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  871. {
  872. struct ath_softc *sc = hw->priv;
  873. struct ath_hw *ah = sc->sc_ah;
  874. struct ath_common *common = ath9k_hw_common(ah);
  875. struct ieee80211_conf *conf = &hw->conf;
  876. bool reset_channel = false;
  877. ath9k_ps_wakeup(sc);
  878. mutex_lock(&sc->mutex);
  879. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  880. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  881. if (sc->ps_idle) {
  882. ath_cancel_work(sc);
  883. ath9k_stop_btcoex(sc);
  884. } else {
  885. ath9k_start_btcoex(sc);
  886. /*
  887. * The chip needs a reset to properly wake up from
  888. * full sleep
  889. */
  890. reset_channel = ah->chip_fullsleep;
  891. }
  892. }
  893. /*
  894. * We just prepare to enable PS. We have to wait until our AP has
  895. * ACK'd our null data frame to disable RX otherwise we'll ignore
  896. * those ACKs and end up retransmitting the same null data frames.
  897. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  898. */
  899. if (changed & IEEE80211_CONF_CHANGE_PS) {
  900. unsigned long flags;
  901. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  902. if (conf->flags & IEEE80211_CONF_PS)
  903. ath9k_enable_ps(sc);
  904. else
  905. ath9k_disable_ps(sc);
  906. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  907. }
  908. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  909. if (conf->flags & IEEE80211_CONF_MONITOR) {
  910. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  911. sc->sc_ah->is_monitoring = true;
  912. } else {
  913. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  914. sc->sc_ah->is_monitoring = false;
  915. }
  916. }
  917. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  918. struct ieee80211_channel *curchan = hw->conf.channel;
  919. int pos = curchan->hw_value;
  920. int old_pos = -1;
  921. unsigned long flags;
  922. if (ah->curchan)
  923. old_pos = ah->curchan - &ah->channels[0];
  924. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  925. curchan->center_freq, conf->channel_type);
  926. /* update survey stats for the old channel before switching */
  927. spin_lock_irqsave(&common->cc_lock, flags);
  928. ath_update_survey_stats(sc);
  929. spin_unlock_irqrestore(&common->cc_lock, flags);
  930. /*
  931. * Preserve the current channel values, before updating
  932. * the same channel
  933. */
  934. if (ah->curchan && (old_pos == pos))
  935. ath9k_hw_getnf(ah, ah->curchan);
  936. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  937. curchan, conf->channel_type);
  938. /*
  939. * If the operating channel changes, change the survey in-use flags
  940. * along with it.
  941. * Reset the survey data for the new channel, unless we're switching
  942. * back to the operating channel from an off-channel operation.
  943. */
  944. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  945. sc->cur_survey != &sc->survey[pos]) {
  946. if (sc->cur_survey)
  947. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  948. sc->cur_survey = &sc->survey[pos];
  949. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  950. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  951. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  952. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  953. }
  954. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  955. ath_err(common, "Unable to set channel\n");
  956. mutex_unlock(&sc->mutex);
  957. ath9k_ps_restore(sc);
  958. return -EINVAL;
  959. }
  960. /*
  961. * The most recent snapshot of channel->noisefloor for the old
  962. * channel is only available after the hardware reset. Copy it to
  963. * the survey stats now.
  964. */
  965. if (old_pos >= 0)
  966. ath_update_survey_nf(sc, old_pos);
  967. }
  968. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  969. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  970. sc->config.txpowlimit = 2 * conf->power_level;
  971. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  972. sc->config.txpowlimit, &sc->curtxpow);
  973. }
  974. mutex_unlock(&sc->mutex);
  975. ath9k_ps_restore(sc);
  976. return 0;
  977. }
  978. #define SUPPORTED_FILTERS \
  979. (FIF_PROMISC_IN_BSS | \
  980. FIF_ALLMULTI | \
  981. FIF_CONTROL | \
  982. FIF_PSPOLL | \
  983. FIF_OTHER_BSS | \
  984. FIF_BCN_PRBRESP_PROMISC | \
  985. FIF_PROBE_REQ | \
  986. FIF_FCSFAIL)
  987. /* FIXME: sc->sc_full_reset ? */
  988. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  989. unsigned int changed_flags,
  990. unsigned int *total_flags,
  991. u64 multicast)
  992. {
  993. struct ath_softc *sc = hw->priv;
  994. u32 rfilt;
  995. changed_flags &= SUPPORTED_FILTERS;
  996. *total_flags &= SUPPORTED_FILTERS;
  997. sc->rx.rxfilter = *total_flags;
  998. ath9k_ps_wakeup(sc);
  999. rfilt = ath_calcrxfilter(sc);
  1000. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1001. ath9k_ps_restore(sc);
  1002. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1003. rfilt);
  1004. }
  1005. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1006. struct ieee80211_vif *vif,
  1007. struct ieee80211_sta *sta)
  1008. {
  1009. struct ath_softc *sc = hw->priv;
  1010. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1011. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1012. struct ieee80211_key_conf ps_key = { };
  1013. ath_node_attach(sc, sta, vif);
  1014. if (vif->type != NL80211_IFTYPE_AP &&
  1015. vif->type != NL80211_IFTYPE_AP_VLAN)
  1016. return 0;
  1017. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1018. return 0;
  1019. }
  1020. static void ath9k_del_ps_key(struct ath_softc *sc,
  1021. struct ieee80211_vif *vif,
  1022. struct ieee80211_sta *sta)
  1023. {
  1024. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1025. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1026. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1027. if (!an->ps_key)
  1028. return;
  1029. ath_key_delete(common, &ps_key);
  1030. }
  1031. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1032. struct ieee80211_vif *vif,
  1033. struct ieee80211_sta *sta)
  1034. {
  1035. struct ath_softc *sc = hw->priv;
  1036. ath9k_del_ps_key(sc, vif, sta);
  1037. ath_node_detach(sc, sta);
  1038. return 0;
  1039. }
  1040. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1041. struct ieee80211_vif *vif,
  1042. enum sta_notify_cmd cmd,
  1043. struct ieee80211_sta *sta)
  1044. {
  1045. struct ath_softc *sc = hw->priv;
  1046. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1047. if (!sta->ht_cap.ht_supported)
  1048. return;
  1049. switch (cmd) {
  1050. case STA_NOTIFY_SLEEP:
  1051. an->sleeping = true;
  1052. ath_tx_aggr_sleep(sta, sc, an);
  1053. break;
  1054. case STA_NOTIFY_AWAKE:
  1055. an->sleeping = false;
  1056. ath_tx_aggr_wakeup(sc, an);
  1057. break;
  1058. }
  1059. }
  1060. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1061. struct ieee80211_vif *vif, u16 queue,
  1062. const struct ieee80211_tx_queue_params *params)
  1063. {
  1064. struct ath_softc *sc = hw->priv;
  1065. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1066. struct ath_txq *txq;
  1067. struct ath9k_tx_queue_info qi;
  1068. int ret = 0;
  1069. if (queue >= IEEE80211_NUM_ACS)
  1070. return 0;
  1071. txq = sc->tx.txq_map[queue];
  1072. ath9k_ps_wakeup(sc);
  1073. mutex_lock(&sc->mutex);
  1074. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1075. qi.tqi_aifs = params->aifs;
  1076. qi.tqi_cwmin = params->cw_min;
  1077. qi.tqi_cwmax = params->cw_max;
  1078. qi.tqi_burstTime = params->txop * 32;
  1079. ath_dbg(common, CONFIG,
  1080. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1081. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1082. params->cw_max, params->txop);
  1083. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1084. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1085. if (ret)
  1086. ath_err(common, "TXQ Update failed\n");
  1087. mutex_unlock(&sc->mutex);
  1088. ath9k_ps_restore(sc);
  1089. return ret;
  1090. }
  1091. static int ath9k_set_key(struct ieee80211_hw *hw,
  1092. enum set_key_cmd cmd,
  1093. struct ieee80211_vif *vif,
  1094. struct ieee80211_sta *sta,
  1095. struct ieee80211_key_conf *key)
  1096. {
  1097. struct ath_softc *sc = hw->priv;
  1098. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1099. int ret = 0;
  1100. if (ath9k_modparam_nohwcrypt)
  1101. return -ENOSPC;
  1102. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1103. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1104. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1105. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1106. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1107. /*
  1108. * For now, disable hw crypto for the RSN IBSS group keys. This
  1109. * could be optimized in the future to use a modified key cache
  1110. * design to support per-STA RX GTK, but until that gets
  1111. * implemented, use of software crypto for group addressed
  1112. * frames is a acceptable to allow RSN IBSS to be used.
  1113. */
  1114. return -EOPNOTSUPP;
  1115. }
  1116. mutex_lock(&sc->mutex);
  1117. ath9k_ps_wakeup(sc);
  1118. ath_dbg(common, CONFIG, "Set HW Key\n");
  1119. switch (cmd) {
  1120. case SET_KEY:
  1121. if (sta)
  1122. ath9k_del_ps_key(sc, vif, sta);
  1123. ret = ath_key_config(common, vif, sta, key);
  1124. if (ret >= 0) {
  1125. key->hw_key_idx = ret;
  1126. /* push IV and Michael MIC generation to stack */
  1127. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1128. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1129. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1130. if (sc->sc_ah->sw_mgmt_crypto &&
  1131. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1132. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1133. ret = 0;
  1134. }
  1135. break;
  1136. case DISABLE_KEY:
  1137. ath_key_delete(common, key);
  1138. break;
  1139. default:
  1140. ret = -EINVAL;
  1141. }
  1142. ath9k_ps_restore(sc);
  1143. mutex_unlock(&sc->mutex);
  1144. return ret;
  1145. }
  1146. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1147. struct ieee80211_vif *vif)
  1148. {
  1149. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1150. struct ath_vif *avp = (void *)vif->drv_priv;
  1151. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1152. unsigned long flags;
  1153. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1154. avp->primary_sta_vif = true;
  1155. /*
  1156. * Set the AID, BSSID and do beacon-sync only when
  1157. * the HW opmode is STATION.
  1158. *
  1159. * But the primary bit is set above in any case.
  1160. */
  1161. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1162. return;
  1163. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1164. common->curaid = bss_conf->aid;
  1165. ath9k_hw_write_associd(sc->sc_ah);
  1166. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1167. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1168. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1169. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1170. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1171. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1172. ath9k_mci_update_wlan_channels(sc, false);
  1173. ath_dbg(common, CONFIG,
  1174. "Primary Station interface: %pM, BSSID: %pM\n",
  1175. vif->addr, common->curbssid);
  1176. }
  1177. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1178. {
  1179. struct ath_softc *sc = data;
  1180. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1181. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1182. return;
  1183. if (bss_conf->assoc)
  1184. ath9k_set_assoc_state(sc, vif);
  1185. }
  1186. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1187. struct ieee80211_vif *vif,
  1188. struct ieee80211_bss_conf *bss_conf,
  1189. u32 changed)
  1190. {
  1191. #define CHECK_ANI \
  1192. (BSS_CHANGED_ASSOC | \
  1193. BSS_CHANGED_IBSS | \
  1194. BSS_CHANGED_BEACON_ENABLED)
  1195. struct ath_softc *sc = hw->priv;
  1196. struct ath_hw *ah = sc->sc_ah;
  1197. struct ath_common *common = ath9k_hw_common(ah);
  1198. struct ath_vif *avp = (void *)vif->drv_priv;
  1199. int slottime;
  1200. ath9k_ps_wakeup(sc);
  1201. mutex_lock(&sc->mutex);
  1202. if (changed & BSS_CHANGED_ASSOC) {
  1203. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1204. bss_conf->bssid, bss_conf->assoc);
  1205. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1206. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1207. avp->primary_sta_vif = false;
  1208. if (ah->opmode == NL80211_IFTYPE_STATION)
  1209. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1210. }
  1211. ieee80211_iterate_active_interfaces_atomic(
  1212. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1213. ath9k_bss_assoc_iter, sc);
  1214. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1215. ah->opmode == NL80211_IFTYPE_STATION) {
  1216. memset(common->curbssid, 0, ETH_ALEN);
  1217. common->curaid = 0;
  1218. ath9k_hw_write_associd(sc->sc_ah);
  1219. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1220. ath9k_mci_update_wlan_channels(sc, true);
  1221. }
  1222. }
  1223. if (changed & BSS_CHANGED_IBSS) {
  1224. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1225. common->curaid = bss_conf->aid;
  1226. ath9k_hw_write_associd(sc->sc_ah);
  1227. }
  1228. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1229. (changed & BSS_CHANGED_BEACON_INT)) {
  1230. if (ah->opmode == NL80211_IFTYPE_AP &&
  1231. bss_conf->enable_beacon)
  1232. ath9k_set_tsfadjust(sc, vif);
  1233. if (ath9k_allow_beacon_config(sc, vif))
  1234. ath9k_beacon_config(sc, vif, changed);
  1235. }
  1236. if (changed & BSS_CHANGED_ERP_SLOT) {
  1237. if (bss_conf->use_short_slot)
  1238. slottime = 9;
  1239. else
  1240. slottime = 20;
  1241. if (vif->type == NL80211_IFTYPE_AP) {
  1242. /*
  1243. * Defer update, so that connected stations can adjust
  1244. * their settings at the same time.
  1245. * See beacon.c for more details
  1246. */
  1247. sc->beacon.slottime = slottime;
  1248. sc->beacon.updateslot = UPDATE;
  1249. } else {
  1250. ah->slottime = slottime;
  1251. ath9k_hw_init_global_settings(ah);
  1252. }
  1253. }
  1254. if (changed & CHECK_ANI)
  1255. ath_check_ani(sc);
  1256. mutex_unlock(&sc->mutex);
  1257. ath9k_ps_restore(sc);
  1258. #undef CHECK_ANI
  1259. }
  1260. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1261. {
  1262. struct ath_softc *sc = hw->priv;
  1263. u64 tsf;
  1264. mutex_lock(&sc->mutex);
  1265. ath9k_ps_wakeup(sc);
  1266. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1267. ath9k_ps_restore(sc);
  1268. mutex_unlock(&sc->mutex);
  1269. return tsf;
  1270. }
  1271. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1272. struct ieee80211_vif *vif,
  1273. u64 tsf)
  1274. {
  1275. struct ath_softc *sc = hw->priv;
  1276. mutex_lock(&sc->mutex);
  1277. ath9k_ps_wakeup(sc);
  1278. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1279. ath9k_ps_restore(sc);
  1280. mutex_unlock(&sc->mutex);
  1281. }
  1282. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1283. {
  1284. struct ath_softc *sc = hw->priv;
  1285. mutex_lock(&sc->mutex);
  1286. ath9k_ps_wakeup(sc);
  1287. ath9k_hw_reset_tsf(sc->sc_ah);
  1288. ath9k_ps_restore(sc);
  1289. mutex_unlock(&sc->mutex);
  1290. }
  1291. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1292. struct ieee80211_vif *vif,
  1293. enum ieee80211_ampdu_mlme_action action,
  1294. struct ieee80211_sta *sta,
  1295. u16 tid, u16 *ssn, u8 buf_size)
  1296. {
  1297. struct ath_softc *sc = hw->priv;
  1298. int ret = 0;
  1299. local_bh_disable();
  1300. switch (action) {
  1301. case IEEE80211_AMPDU_RX_START:
  1302. break;
  1303. case IEEE80211_AMPDU_RX_STOP:
  1304. break;
  1305. case IEEE80211_AMPDU_TX_START:
  1306. ath9k_ps_wakeup(sc);
  1307. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1308. if (!ret)
  1309. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1310. ath9k_ps_restore(sc);
  1311. break;
  1312. case IEEE80211_AMPDU_TX_STOP:
  1313. ath9k_ps_wakeup(sc);
  1314. ath_tx_aggr_stop(sc, sta, tid);
  1315. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1316. ath9k_ps_restore(sc);
  1317. break;
  1318. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1319. ath9k_ps_wakeup(sc);
  1320. ath_tx_aggr_resume(sc, sta, tid);
  1321. ath9k_ps_restore(sc);
  1322. break;
  1323. default:
  1324. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1325. }
  1326. local_bh_enable();
  1327. return ret;
  1328. }
  1329. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1330. struct survey_info *survey)
  1331. {
  1332. struct ath_softc *sc = hw->priv;
  1333. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1334. struct ieee80211_supported_band *sband;
  1335. struct ieee80211_channel *chan;
  1336. unsigned long flags;
  1337. int pos;
  1338. spin_lock_irqsave(&common->cc_lock, flags);
  1339. if (idx == 0)
  1340. ath_update_survey_stats(sc);
  1341. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1342. if (sband && idx >= sband->n_channels) {
  1343. idx -= sband->n_channels;
  1344. sband = NULL;
  1345. }
  1346. if (!sband)
  1347. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1348. if (!sband || idx >= sband->n_channels) {
  1349. spin_unlock_irqrestore(&common->cc_lock, flags);
  1350. return -ENOENT;
  1351. }
  1352. chan = &sband->channels[idx];
  1353. pos = chan->hw_value;
  1354. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1355. survey->channel = chan;
  1356. spin_unlock_irqrestore(&common->cc_lock, flags);
  1357. return 0;
  1358. }
  1359. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1360. {
  1361. struct ath_softc *sc = hw->priv;
  1362. struct ath_hw *ah = sc->sc_ah;
  1363. mutex_lock(&sc->mutex);
  1364. ah->coverage_class = coverage_class;
  1365. ath9k_ps_wakeup(sc);
  1366. ath9k_hw_init_global_settings(ah);
  1367. ath9k_ps_restore(sc);
  1368. mutex_unlock(&sc->mutex);
  1369. }
  1370. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1371. {
  1372. struct ath_softc *sc = hw->priv;
  1373. struct ath_hw *ah = sc->sc_ah;
  1374. struct ath_common *common = ath9k_hw_common(ah);
  1375. int timeout = 200; /* ms */
  1376. int i, j;
  1377. bool drain_txq;
  1378. mutex_lock(&sc->mutex);
  1379. cancel_delayed_work_sync(&sc->tx_complete_work);
  1380. if (ah->ah_flags & AH_UNPLUGGED) {
  1381. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1382. mutex_unlock(&sc->mutex);
  1383. return;
  1384. }
  1385. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1386. ath_dbg(common, ANY, "Device not present\n");
  1387. mutex_unlock(&sc->mutex);
  1388. return;
  1389. }
  1390. for (j = 0; j < timeout; j++) {
  1391. bool npend = false;
  1392. if (j)
  1393. usleep_range(1000, 2000);
  1394. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1395. if (!ATH_TXQ_SETUP(sc, i))
  1396. continue;
  1397. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1398. if (npend)
  1399. break;
  1400. }
  1401. if (!npend)
  1402. break;
  1403. }
  1404. if (drop) {
  1405. ath9k_ps_wakeup(sc);
  1406. spin_lock_bh(&sc->sc_pcu_lock);
  1407. drain_txq = ath_drain_all_txq(sc, false);
  1408. spin_unlock_bh(&sc->sc_pcu_lock);
  1409. if (!drain_txq)
  1410. ath_reset(sc, false);
  1411. ath9k_ps_restore(sc);
  1412. ieee80211_wake_queues(hw);
  1413. }
  1414. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1415. mutex_unlock(&sc->mutex);
  1416. }
  1417. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1418. {
  1419. struct ath_softc *sc = hw->priv;
  1420. int i;
  1421. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1422. if (!ATH_TXQ_SETUP(sc, i))
  1423. continue;
  1424. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1425. return true;
  1426. }
  1427. return false;
  1428. }
  1429. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1430. {
  1431. struct ath_softc *sc = hw->priv;
  1432. struct ath_hw *ah = sc->sc_ah;
  1433. struct ieee80211_vif *vif;
  1434. struct ath_vif *avp;
  1435. struct ath_buf *bf;
  1436. struct ath_tx_status ts;
  1437. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1438. int status;
  1439. vif = sc->beacon.bslot[0];
  1440. if (!vif)
  1441. return 0;
  1442. if (!vif->bss_conf.enable_beacon)
  1443. return 0;
  1444. avp = (void *)vif->drv_priv;
  1445. if (!sc->beacon.tx_processed && !edma) {
  1446. tasklet_disable(&sc->bcon_tasklet);
  1447. bf = avp->av_bcbuf;
  1448. if (!bf || !bf->bf_mpdu)
  1449. goto skip;
  1450. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1451. if (status == -EINPROGRESS)
  1452. goto skip;
  1453. sc->beacon.tx_processed = true;
  1454. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1455. skip:
  1456. tasklet_enable(&sc->bcon_tasklet);
  1457. }
  1458. return sc->beacon.tx_last;
  1459. }
  1460. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1461. struct ieee80211_low_level_stats *stats)
  1462. {
  1463. struct ath_softc *sc = hw->priv;
  1464. struct ath_hw *ah = sc->sc_ah;
  1465. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1466. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1467. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1468. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1469. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1470. return 0;
  1471. }
  1472. static u32 fill_chainmask(u32 cap, u32 new)
  1473. {
  1474. u32 filled = 0;
  1475. int i;
  1476. for (i = 0; cap && new; i++, cap >>= 1) {
  1477. if (!(cap & BIT(0)))
  1478. continue;
  1479. if (new & BIT(0))
  1480. filled |= BIT(i);
  1481. new >>= 1;
  1482. }
  1483. return filled;
  1484. }
  1485. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1486. {
  1487. switch (val & 0x7) {
  1488. case 0x1:
  1489. case 0x3:
  1490. case 0x7:
  1491. return true;
  1492. case 0x2:
  1493. return (ah->caps.rx_chainmask == 1);
  1494. default:
  1495. return false;
  1496. }
  1497. }
  1498. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1499. {
  1500. struct ath_softc *sc = hw->priv;
  1501. struct ath_hw *ah = sc->sc_ah;
  1502. if (ah->caps.rx_chainmask != 1)
  1503. rx_ant |= tx_ant;
  1504. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1505. return -EINVAL;
  1506. sc->ant_rx = rx_ant;
  1507. sc->ant_tx = tx_ant;
  1508. if (ah->caps.rx_chainmask == 1)
  1509. return 0;
  1510. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1511. if (AR_SREV_9100(ah))
  1512. ah->rxchainmask = 0x7;
  1513. else
  1514. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1515. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1516. ath9k_reload_chainmask_settings(sc);
  1517. return 0;
  1518. }
  1519. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1520. {
  1521. struct ath_softc *sc = hw->priv;
  1522. *tx_ant = sc->ant_tx;
  1523. *rx_ant = sc->ant_rx;
  1524. return 0;
  1525. }
  1526. #ifdef CONFIG_PM_SLEEP
  1527. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1528. struct cfg80211_wowlan *wowlan,
  1529. u32 *wow_triggers)
  1530. {
  1531. if (wowlan->disconnect)
  1532. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1533. AH_WOW_BEACON_MISS;
  1534. if (wowlan->magic_pkt)
  1535. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1536. if (wowlan->n_patterns)
  1537. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1538. sc->wow_enabled = *wow_triggers;
  1539. }
  1540. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1541. {
  1542. struct ath_hw *ah = sc->sc_ah;
  1543. struct ath_common *common = ath9k_hw_common(ah);
  1544. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1545. int pattern_count = 0;
  1546. int i, byte_cnt;
  1547. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1548. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1549. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1550. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1551. /*
  1552. * Create Dissassociate / Deauthenticate packet filter
  1553. *
  1554. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1555. * +--------------+----------+---------+--------+--------+----
  1556. * + Frame Control+ Duration + DA + SA + BSSID +
  1557. * +--------------+----------+---------+--------+--------+----
  1558. *
  1559. * The above is the management frame format for disassociate/
  1560. * deauthenticate pattern, from this we need to match the first byte
  1561. * of 'Frame Control' and DA, SA, and BSSID fields
  1562. * (skipping 2nd byte of FC and Duration feild.
  1563. *
  1564. * Disassociate pattern
  1565. * --------------------
  1566. * Frame control = 00 00 1010
  1567. * DA, SA, BSSID = x:x:x:x:x:x
  1568. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1569. * | x:x:x:x:x:x -- 22 bytes
  1570. *
  1571. * Deauthenticate pattern
  1572. * ----------------------
  1573. * Frame control = 00 00 1100
  1574. * DA, SA, BSSID = x:x:x:x:x:x
  1575. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1576. * | x:x:x:x:x:x -- 22 bytes
  1577. */
  1578. /* Create Disassociate Pattern first */
  1579. byte_cnt = 0;
  1580. /* Fill out the mask with all FF's */
  1581. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1582. dis_deauth_mask[i] = 0xff;
  1583. /* copy the first byte of frame control field */
  1584. dis_deauth_pattern[byte_cnt] = 0xa0;
  1585. byte_cnt++;
  1586. /* skip 2nd byte of frame control and Duration field */
  1587. byte_cnt += 3;
  1588. /*
  1589. * need not match the destination mac address, it can be a broadcast
  1590. * mac address or an unicast to this station
  1591. */
  1592. byte_cnt += 6;
  1593. /* copy the source mac address */
  1594. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1595. byte_cnt += 6;
  1596. /* copy the bssid, its same as the source mac address */
  1597. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1598. /* Create Disassociate pattern mask */
  1599. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1600. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1601. /*
  1602. * for AR9280, because of hardware limitation, the
  1603. * first 4 bytes have to be matched for all patterns.
  1604. * the mask for disassociation and de-auth pattern
  1605. * matching need to enable the first 4 bytes.
  1606. * also the duration field needs to be filled.
  1607. */
  1608. dis_deauth_mask[0] = 0xf0;
  1609. /*
  1610. * fill in duration field
  1611. FIXME: what is the exact value ?
  1612. */
  1613. dis_deauth_pattern[2] = 0xff;
  1614. dis_deauth_pattern[3] = 0xff;
  1615. } else {
  1616. dis_deauth_mask[0] = 0xfe;
  1617. }
  1618. dis_deauth_mask[1] = 0x03;
  1619. dis_deauth_mask[2] = 0xc0;
  1620. } else {
  1621. dis_deauth_mask[0] = 0xef;
  1622. dis_deauth_mask[1] = 0x3f;
  1623. dis_deauth_mask[2] = 0x00;
  1624. dis_deauth_mask[3] = 0xfc;
  1625. }
  1626. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1627. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1628. pattern_count, byte_cnt);
  1629. pattern_count++;
  1630. /*
  1631. * for de-authenticate pattern, only the first byte of the frame
  1632. * control field gets changed from 0xA0 to 0xC0
  1633. */
  1634. dis_deauth_pattern[0] = 0xC0;
  1635. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1636. pattern_count, byte_cnt);
  1637. }
  1638. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1639. struct cfg80211_wowlan *wowlan)
  1640. {
  1641. struct ath_hw *ah = sc->sc_ah;
  1642. struct ath9k_wow_pattern *wow_pattern = NULL;
  1643. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1644. int mask_len;
  1645. s8 i = 0;
  1646. if (!wowlan->n_patterns)
  1647. return;
  1648. /*
  1649. * Add the new user configured patterns
  1650. */
  1651. for (i = 0; i < wowlan->n_patterns; i++) {
  1652. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1653. if (!wow_pattern)
  1654. return;
  1655. /*
  1656. * TODO: convert the generic user space pattern to
  1657. * appropriate chip specific/802.11 pattern.
  1658. */
  1659. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1660. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1661. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1662. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1663. patterns[i].pattern_len);
  1664. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1665. wow_pattern->pattern_len = patterns[i].pattern_len;
  1666. /*
  1667. * just need to take care of deauth and disssoc pattern,
  1668. * make sure we don't overwrite them.
  1669. */
  1670. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1671. wow_pattern->mask_bytes,
  1672. i + 2,
  1673. wow_pattern->pattern_len);
  1674. kfree(wow_pattern);
  1675. }
  1676. }
  1677. static int ath9k_suspend(struct ieee80211_hw *hw,
  1678. struct cfg80211_wowlan *wowlan)
  1679. {
  1680. struct ath_softc *sc = hw->priv;
  1681. struct ath_hw *ah = sc->sc_ah;
  1682. struct ath_common *common = ath9k_hw_common(ah);
  1683. u32 wow_triggers_enabled = 0;
  1684. int ret = 0;
  1685. mutex_lock(&sc->mutex);
  1686. ath_cancel_work(sc);
  1687. ath_stop_ani(sc);
  1688. del_timer_sync(&sc->rx_poll_timer);
  1689. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1690. ath_dbg(common, ANY, "Device not present\n");
  1691. ret = -EINVAL;
  1692. goto fail_wow;
  1693. }
  1694. if (WARN_ON(!wowlan)) {
  1695. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1696. ret = -EINVAL;
  1697. goto fail_wow;
  1698. }
  1699. if (!device_can_wakeup(sc->dev)) {
  1700. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1701. ret = 1;
  1702. goto fail_wow;
  1703. }
  1704. /*
  1705. * none of the sta vifs are associated
  1706. * and we are not currently handling multivif
  1707. * cases, for instance we have to seperately
  1708. * configure 'keep alive frame' for each
  1709. * STA.
  1710. */
  1711. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1712. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1713. ret = 1;
  1714. goto fail_wow;
  1715. }
  1716. if (sc->nvifs > 1) {
  1717. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1718. ret = 1;
  1719. goto fail_wow;
  1720. }
  1721. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1722. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1723. wow_triggers_enabled);
  1724. ath9k_ps_wakeup(sc);
  1725. ath9k_stop_btcoex(sc);
  1726. /*
  1727. * Enable wake up on recieving disassoc/deauth
  1728. * frame by default.
  1729. */
  1730. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1731. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1732. ath9k_wow_add_pattern(sc, wowlan);
  1733. spin_lock_bh(&sc->sc_pcu_lock);
  1734. /*
  1735. * To avoid false wake, we enable beacon miss interrupt only
  1736. * when we go to sleep. We save the current interrupt mask
  1737. * so we can restore it after the system wakes up
  1738. */
  1739. sc->wow_intr_before_sleep = ah->imask;
  1740. ah->imask &= ~ATH9K_INT_GLOBAL;
  1741. ath9k_hw_disable_interrupts(ah);
  1742. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1743. ath9k_hw_set_interrupts(ah);
  1744. ath9k_hw_enable_interrupts(ah);
  1745. spin_unlock_bh(&sc->sc_pcu_lock);
  1746. /*
  1747. * we can now sync irq and kill any running tasklets, since we already
  1748. * disabled interrupts and not holding a spin lock
  1749. */
  1750. synchronize_irq(sc->irq);
  1751. tasklet_kill(&sc->intr_tq);
  1752. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1753. ath9k_ps_restore(sc);
  1754. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1755. atomic_inc(&sc->wow_sleep_proc_intr);
  1756. fail_wow:
  1757. mutex_unlock(&sc->mutex);
  1758. return ret;
  1759. }
  1760. static int ath9k_resume(struct ieee80211_hw *hw)
  1761. {
  1762. struct ath_softc *sc = hw->priv;
  1763. struct ath_hw *ah = sc->sc_ah;
  1764. struct ath_common *common = ath9k_hw_common(ah);
  1765. u32 wow_status;
  1766. mutex_lock(&sc->mutex);
  1767. ath9k_ps_wakeup(sc);
  1768. spin_lock_bh(&sc->sc_pcu_lock);
  1769. ath9k_hw_disable_interrupts(ah);
  1770. ah->imask = sc->wow_intr_before_sleep;
  1771. ath9k_hw_set_interrupts(ah);
  1772. ath9k_hw_enable_interrupts(ah);
  1773. spin_unlock_bh(&sc->sc_pcu_lock);
  1774. wow_status = ath9k_hw_wow_wakeup(ah);
  1775. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1776. /*
  1777. * some devices may not pick beacon miss
  1778. * as the reason they woke up so we add
  1779. * that here for that shortcoming.
  1780. */
  1781. wow_status |= AH_WOW_BEACON_MISS;
  1782. atomic_dec(&sc->wow_got_bmiss_intr);
  1783. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1784. }
  1785. atomic_dec(&sc->wow_sleep_proc_intr);
  1786. if (wow_status) {
  1787. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1788. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1789. }
  1790. ath_restart_work(sc);
  1791. ath9k_start_btcoex(sc);
  1792. ath9k_ps_restore(sc);
  1793. mutex_unlock(&sc->mutex);
  1794. return 0;
  1795. }
  1796. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1797. {
  1798. struct ath_softc *sc = hw->priv;
  1799. mutex_lock(&sc->mutex);
  1800. device_init_wakeup(sc->dev, 1);
  1801. device_set_wakeup_enable(sc->dev, enabled);
  1802. mutex_unlock(&sc->mutex);
  1803. }
  1804. #endif
  1805. struct ieee80211_ops ath9k_ops = {
  1806. .tx = ath9k_tx,
  1807. .start = ath9k_start,
  1808. .stop = ath9k_stop,
  1809. .add_interface = ath9k_add_interface,
  1810. .change_interface = ath9k_change_interface,
  1811. .remove_interface = ath9k_remove_interface,
  1812. .config = ath9k_config,
  1813. .configure_filter = ath9k_configure_filter,
  1814. .sta_add = ath9k_sta_add,
  1815. .sta_remove = ath9k_sta_remove,
  1816. .sta_notify = ath9k_sta_notify,
  1817. .conf_tx = ath9k_conf_tx,
  1818. .bss_info_changed = ath9k_bss_info_changed,
  1819. .set_key = ath9k_set_key,
  1820. .get_tsf = ath9k_get_tsf,
  1821. .set_tsf = ath9k_set_tsf,
  1822. .reset_tsf = ath9k_reset_tsf,
  1823. .ampdu_action = ath9k_ampdu_action,
  1824. .get_survey = ath9k_get_survey,
  1825. .rfkill_poll = ath9k_rfkill_poll_state,
  1826. .set_coverage_class = ath9k_set_coverage_class,
  1827. .flush = ath9k_flush,
  1828. .tx_frames_pending = ath9k_tx_frames_pending,
  1829. .tx_last_beacon = ath9k_tx_last_beacon,
  1830. .get_stats = ath9k_get_stats,
  1831. .set_antenna = ath9k_set_antenna,
  1832. .get_antenna = ath9k_get_antenna,
  1833. #ifdef CONFIG_PM_SLEEP
  1834. .suspend = ath9k_suspend,
  1835. .resume = ath9k_resume,
  1836. .set_wakeup = ath9k_set_wakeup,
  1837. #endif
  1838. #ifdef CONFIG_ATH9K_DEBUGFS
  1839. .get_et_sset_count = ath9k_get_et_sset_count,
  1840. .get_et_stats = ath9k_get_et_stats,
  1841. .get_et_strings = ath9k_get_et_strings,
  1842. #endif
  1843. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  1844. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1845. .sta_remove_debugfs = ath9k_sta_remove_debugfs,
  1846. #endif
  1847. };