icplus.c 6.1 KB

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  1. /*
  2. * Driver for ICPlus PHYs
  3. *
  4. * Copyright (c) 2007 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. *
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/string.h>
  14. #include <linux/errno.h>
  15. #include <linux/unistd.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/skbuff.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/mm.h>
  24. #include <linux/module.h>
  25. #include <linux/mii.h>
  26. #include <linux/ethtool.h>
  27. #include <linux/phy.h>
  28. #include <asm/io.h>
  29. #include <asm/irq.h>
  30. #include <asm/uaccess.h>
  31. MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IP101G/IC1001 PHY drivers");
  32. MODULE_AUTHOR("Michael Barkowski");
  33. MODULE_LICENSE("GPL");
  34. /* IP101A/G - IP1001 */
  35. #define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
  36. #define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
  37. #define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
  38. #define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
  39. #define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
  40. #define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
  41. #define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
  42. #define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
  43. static int ip175c_config_init(struct phy_device *phydev)
  44. {
  45. int err, i;
  46. static int full_reset_performed = 0;
  47. if (full_reset_performed == 0) {
  48. /* master reset */
  49. err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
  50. if (err < 0)
  51. return err;
  52. /* ensure no bus delays overlap reset period */
  53. err = mdiobus_read(phydev->bus, 30, 0);
  54. /* data sheet specifies reset period is 2 msec */
  55. mdelay(2);
  56. /* enable IP175C mode */
  57. err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
  58. if (err < 0)
  59. return err;
  60. /* Set MII0 speed and duplex (in PHY mode) */
  61. err = mdiobus_write(phydev->bus, 29, 22, 0x420);
  62. if (err < 0)
  63. return err;
  64. /* reset switch ports */
  65. for (i = 0; i < 5; i++) {
  66. err = mdiobus_write(phydev->bus, i,
  67. MII_BMCR, BMCR_RESET);
  68. if (err < 0)
  69. return err;
  70. }
  71. for (i = 0; i < 5; i++)
  72. err = mdiobus_read(phydev->bus, i, MII_BMCR);
  73. mdelay(2);
  74. full_reset_performed = 1;
  75. }
  76. if (phydev->addr != 4) {
  77. phydev->state = PHY_RUNNING;
  78. phydev->speed = SPEED_100;
  79. phydev->duplex = DUPLEX_FULL;
  80. phydev->link = 1;
  81. netif_carrier_on(phydev->attached_dev);
  82. }
  83. return 0;
  84. }
  85. static int ip1xx_reset(struct phy_device *phydev)
  86. {
  87. int bmcr;
  88. /* Software Reset PHY */
  89. bmcr = phy_read(phydev, MII_BMCR);
  90. if (bmcr < 0)
  91. return bmcr;
  92. bmcr |= BMCR_RESET;
  93. bmcr = phy_write(phydev, MII_BMCR, bmcr);
  94. if (bmcr < 0)
  95. return bmcr;
  96. do {
  97. bmcr = phy_read(phydev, MII_BMCR);
  98. if (bmcr < 0)
  99. return bmcr;
  100. } while (bmcr & BMCR_RESET);
  101. return 0;
  102. }
  103. static int ip1001_config_init(struct phy_device *phydev)
  104. {
  105. int c;
  106. c = ip1xx_reset(phydev);
  107. if (c < 0)
  108. return c;
  109. /* Enable Auto Power Saving mode */
  110. c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
  111. if (c < 0)
  112. return c;
  113. c |= IP1001_APS_ON;
  114. c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c);
  115. if (c < 0)
  116. return c;
  117. /* INTR pin used: speed/link/duplex will cause an interrupt */
  118. c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT);
  119. if (c < 0)
  120. return c;
  121. if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
  122. /* Additional delay (2ns) used to adjust RX clock phase
  123. * at RGMII interface */
  124. c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
  125. if (c < 0)
  126. return c;
  127. c |= IP1001_PHASE_SEL_MASK;
  128. c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
  129. if (c < 0)
  130. return c;
  131. }
  132. return 0;
  133. }
  134. static int ip101a_g_config_init(struct phy_device *phydev)
  135. {
  136. int c;
  137. c = ip1xx_reset(phydev);
  138. if (c < 0)
  139. return c;
  140. /* Enable Auto Power Saving mode */
  141. c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
  142. c |= IP101A_G_APS_ON;
  143. return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
  144. }
  145. static int ip175c_read_status(struct phy_device *phydev)
  146. {
  147. if (phydev->addr == 4) /* WAN port */
  148. genphy_read_status(phydev);
  149. else
  150. /* Don't need to read status for switch ports */
  151. phydev->irq = PHY_IGNORE_INTERRUPT;
  152. return 0;
  153. }
  154. static int ip175c_config_aneg(struct phy_device *phydev)
  155. {
  156. if (phydev->addr == 4) /* WAN port */
  157. genphy_config_aneg(phydev);
  158. return 0;
  159. }
  160. static int ip101a_g_ack_interrupt(struct phy_device *phydev)
  161. {
  162. int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
  163. if (err < 0)
  164. return err;
  165. return 0;
  166. }
  167. static struct phy_driver icplus_driver[] = {
  168. {
  169. .phy_id = 0x02430d80,
  170. .name = "ICPlus IP175C",
  171. .phy_id_mask = 0x0ffffff0,
  172. .features = PHY_BASIC_FEATURES,
  173. .config_init = &ip175c_config_init,
  174. .config_aneg = &ip175c_config_aneg,
  175. .read_status = &ip175c_read_status,
  176. .suspend = genphy_suspend,
  177. .resume = genphy_resume,
  178. .driver = { .owner = THIS_MODULE,},
  179. }, {
  180. .phy_id = 0x02430d90,
  181. .name = "ICPlus IP1001",
  182. .phy_id_mask = 0x0ffffff0,
  183. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
  184. SUPPORTED_Asym_Pause,
  185. .config_init = &ip1001_config_init,
  186. .config_aneg = &genphy_config_aneg,
  187. .read_status = &genphy_read_status,
  188. .suspend = genphy_suspend,
  189. .resume = genphy_resume,
  190. .driver = { .owner = THIS_MODULE,},
  191. }, {
  192. .phy_id = 0x02430c54,
  193. .name = "ICPlus IP101A/G",
  194. .phy_id_mask = 0x0ffffff0,
  195. .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
  196. SUPPORTED_Asym_Pause,
  197. .flags = PHY_HAS_INTERRUPT,
  198. .ack_interrupt = ip101a_g_ack_interrupt,
  199. .config_init = &ip101a_g_config_init,
  200. .config_aneg = &genphy_config_aneg,
  201. .read_status = &genphy_read_status,
  202. .suspend = genphy_suspend,
  203. .resume = genphy_resume,
  204. .driver = { .owner = THIS_MODULE,},
  205. } };
  206. static int __init icplus_init(void)
  207. {
  208. return phy_drivers_register(icplus_driver,
  209. ARRAY_SIZE(icplus_driver));
  210. }
  211. static void __exit icplus_exit(void)
  212. {
  213. phy_drivers_unregister(icplus_driver,
  214. ARRAY_SIZE(icplus_driver));
  215. }
  216. module_init(icplus_init);
  217. module_exit(icplus_exit);
  218. static struct mdio_device_id __maybe_unused icplus_tbl[] = {
  219. { 0x02430d80, 0x0ffffff0 },
  220. { 0x02430d90, 0x0ffffff0 },
  221. { 0x02430c54, 0x0ffffff0 },
  222. { }
  223. };
  224. MODULE_DEVICE_TABLE(mdio, icplus_tbl);