rrunner.c 41 KB

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  1. /*
  2. * rrunner.c: Linux driver for the Essential RoadRunner HIPPI board.
  3. *
  4. * Copyright (C) 1998-2002 by Jes Sorensen, <jes@wildopensource.com>.
  5. *
  6. * Thanks to Essential Communication for providing us with hardware
  7. * and very comprehensive documentation without which I would not have
  8. * been able to write this driver. A special thank you to John Gibbon
  9. * for sorting out the legal issues, with the NDA, allowing the code to
  10. * be released under the GPL.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * Thanks to Jayaram Bhat from ODS/Essential for fixing some of the
  18. * stupid bugs in my code.
  19. *
  20. * Softnet support and various other patches from Val Henson of
  21. * ODS/Essential.
  22. *
  23. * PCI DMA mapping code partly based on work by Francois Romieu.
  24. */
  25. #define DEBUG 1
  26. #define RX_DMA_SKBUFF 1
  27. #define PKT_COPY_THRESHOLD 512
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/errno.h>
  31. #include <linux/ioport.h>
  32. #include <linux/pci.h>
  33. #include <linux/kernel.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/hippidevice.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/init.h>
  38. #include <linux/delay.h>
  39. #include <linux/mm.h>
  40. #include <linux/slab.h>
  41. #include <net/sock.h>
  42. #include <asm/cache.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/uaccess.h>
  47. #define rr_if_busy(dev) netif_queue_stopped(dev)
  48. #define rr_if_running(dev) netif_running(dev)
  49. #include "rrunner.h"
  50. #define RUN_AT(x) (jiffies + (x))
  51. MODULE_AUTHOR("Jes Sorensen <jes@wildopensource.com>");
  52. MODULE_DESCRIPTION("Essential RoadRunner HIPPI driver");
  53. MODULE_LICENSE("GPL");
  54. static char version[] = "rrunner.c: v0.50 11/11/2002 Jes Sorensen (jes@wildopensource.com)\n";
  55. static const struct net_device_ops rr_netdev_ops = {
  56. .ndo_open = rr_open,
  57. .ndo_stop = rr_close,
  58. .ndo_do_ioctl = rr_ioctl,
  59. .ndo_start_xmit = rr_start_xmit,
  60. .ndo_change_mtu = hippi_change_mtu,
  61. .ndo_set_mac_address = hippi_mac_addr,
  62. };
  63. /*
  64. * Implementation notes:
  65. *
  66. * The DMA engine only allows for DMA within physical 64KB chunks of
  67. * memory. The current approach of the driver (and stack) is to use
  68. * linear blocks of memory for the skbuffs. However, as the data block
  69. * is always the first part of the skb and skbs are 2^n aligned so we
  70. * are guarantted to get the whole block within one 64KB align 64KB
  71. * chunk.
  72. *
  73. * On the long term, relying on being able to allocate 64KB linear
  74. * chunks of memory is not feasible and the skb handling code and the
  75. * stack will need to know about I/O vectors or something similar.
  76. */
  77. static int rr_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  78. {
  79. struct net_device *dev;
  80. static int version_disp;
  81. u8 pci_latency;
  82. struct rr_private *rrpriv;
  83. void *tmpptr;
  84. dma_addr_t ring_dma;
  85. int ret = -ENOMEM;
  86. dev = alloc_hippi_dev(sizeof(struct rr_private));
  87. if (!dev)
  88. goto out3;
  89. ret = pci_enable_device(pdev);
  90. if (ret) {
  91. ret = -ENODEV;
  92. goto out2;
  93. }
  94. rrpriv = netdev_priv(dev);
  95. SET_NETDEV_DEV(dev, &pdev->dev);
  96. ret = pci_request_regions(pdev, "rrunner");
  97. if (ret < 0)
  98. goto out;
  99. pci_set_drvdata(pdev, dev);
  100. rrpriv->pci_dev = pdev;
  101. spin_lock_init(&rrpriv->lock);
  102. dev->netdev_ops = &rr_netdev_ops;
  103. /* display version info if adapter is found */
  104. if (!version_disp) {
  105. /* set display flag to TRUE so that */
  106. /* we only display this string ONCE */
  107. version_disp = 1;
  108. printk(version);
  109. }
  110. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
  111. if (pci_latency <= 0x58){
  112. pci_latency = 0x58;
  113. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, pci_latency);
  114. }
  115. pci_set_master(pdev);
  116. printk(KERN_INFO "%s: Essential RoadRunner serial HIPPI "
  117. "at 0x%llx, irq %i, PCI latency %i\n", dev->name,
  118. (unsigned long long)pci_resource_start(pdev, 0),
  119. pdev->irq, pci_latency);
  120. /*
  121. * Remap the MMIO regs into kernel space.
  122. */
  123. rrpriv->regs = pci_iomap(pdev, 0, 0x1000);
  124. if (!rrpriv->regs) {
  125. printk(KERN_ERR "%s: Unable to map I/O register, "
  126. "RoadRunner will be disabled.\n", dev->name);
  127. ret = -EIO;
  128. goto out;
  129. }
  130. tmpptr = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
  131. rrpriv->tx_ring = tmpptr;
  132. rrpriv->tx_ring_dma = ring_dma;
  133. if (!tmpptr) {
  134. ret = -ENOMEM;
  135. goto out;
  136. }
  137. tmpptr = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
  138. rrpriv->rx_ring = tmpptr;
  139. rrpriv->rx_ring_dma = ring_dma;
  140. if (!tmpptr) {
  141. ret = -ENOMEM;
  142. goto out;
  143. }
  144. tmpptr = pci_alloc_consistent(pdev, EVT_RING_SIZE, &ring_dma);
  145. rrpriv->evt_ring = tmpptr;
  146. rrpriv->evt_ring_dma = ring_dma;
  147. if (!tmpptr) {
  148. ret = -ENOMEM;
  149. goto out;
  150. }
  151. /*
  152. * Don't access any register before this point!
  153. */
  154. #ifdef __BIG_ENDIAN
  155. writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
  156. &rrpriv->regs->HostCtrl);
  157. #endif
  158. /*
  159. * Need to add a case for little-endian 64-bit hosts here.
  160. */
  161. rr_init(dev);
  162. ret = register_netdev(dev);
  163. if (ret)
  164. goto out;
  165. return 0;
  166. out:
  167. if (rrpriv->rx_ring)
  168. pci_free_consistent(pdev, RX_TOTAL_SIZE, rrpriv->rx_ring,
  169. rrpriv->rx_ring_dma);
  170. if (rrpriv->tx_ring)
  171. pci_free_consistent(pdev, TX_TOTAL_SIZE, rrpriv->tx_ring,
  172. rrpriv->tx_ring_dma);
  173. if (rrpriv->regs)
  174. pci_iounmap(pdev, rrpriv->regs);
  175. if (pdev) {
  176. pci_release_regions(pdev);
  177. pci_set_drvdata(pdev, NULL);
  178. }
  179. out2:
  180. free_netdev(dev);
  181. out3:
  182. return ret;
  183. }
  184. static void rr_remove_one(struct pci_dev *pdev)
  185. {
  186. struct net_device *dev = pci_get_drvdata(pdev);
  187. struct rr_private *rr = netdev_priv(dev);
  188. if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)) {
  189. printk(KERN_ERR "%s: trying to unload running NIC\n",
  190. dev->name);
  191. writel(HALT_NIC, &rr->regs->HostCtrl);
  192. }
  193. unregister_netdev(dev);
  194. pci_free_consistent(pdev, EVT_RING_SIZE, rr->evt_ring,
  195. rr->evt_ring_dma);
  196. pci_free_consistent(pdev, RX_TOTAL_SIZE, rr->rx_ring,
  197. rr->rx_ring_dma);
  198. pci_free_consistent(pdev, TX_TOTAL_SIZE, rr->tx_ring,
  199. rr->tx_ring_dma);
  200. pci_iounmap(pdev, rr->regs);
  201. pci_release_regions(pdev);
  202. pci_disable_device(pdev);
  203. pci_set_drvdata(pdev, NULL);
  204. free_netdev(dev);
  205. }
  206. /*
  207. * Commands are considered to be slow, thus there is no reason to
  208. * inline this.
  209. */
  210. static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
  211. {
  212. struct rr_regs __iomem *regs;
  213. u32 idx;
  214. regs = rrpriv->regs;
  215. /*
  216. * This is temporary - it will go away in the final version.
  217. * We probably also want to make this function inline.
  218. */
  219. if (readl(&regs->HostCtrl) & NIC_HALTED){
  220. printk("issuing command for halted NIC, code 0x%x, "
  221. "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));
  222. if (readl(&regs->Mode) & FATAL_ERR)
  223. printk("error codes Fail1 %02x, Fail2 %02x\n",
  224. readl(&regs->Fail1), readl(&regs->Fail2));
  225. }
  226. idx = rrpriv->info->cmd_ctrl.pi;
  227. writel(*(u32*)(cmd), &regs->CmdRing[idx]);
  228. wmb();
  229. idx = (idx - 1) % CMD_RING_ENTRIES;
  230. rrpriv->info->cmd_ctrl.pi = idx;
  231. wmb();
  232. if (readl(&regs->Mode) & FATAL_ERR)
  233. printk("error code %02x\n", readl(&regs->Fail1));
  234. }
  235. /*
  236. * Reset the board in a sensible manner. The NIC is already halted
  237. * when we get here and a spin-lock is held.
  238. */
  239. static int rr_reset(struct net_device *dev)
  240. {
  241. struct rr_private *rrpriv;
  242. struct rr_regs __iomem *regs;
  243. u32 start_pc;
  244. int i;
  245. rrpriv = netdev_priv(dev);
  246. regs = rrpriv->regs;
  247. rr_load_firmware(dev);
  248. writel(0x01000000, &regs->TX_state);
  249. writel(0xff800000, &regs->RX_state);
  250. writel(0, &regs->AssistState);
  251. writel(CLEAR_INTA, &regs->LocalCtrl);
  252. writel(0x01, &regs->BrkPt);
  253. writel(0, &regs->Timer);
  254. writel(0, &regs->TimerRef);
  255. writel(RESET_DMA, &regs->DmaReadState);
  256. writel(RESET_DMA, &regs->DmaWriteState);
  257. writel(0, &regs->DmaWriteHostHi);
  258. writel(0, &regs->DmaWriteHostLo);
  259. writel(0, &regs->DmaReadHostHi);
  260. writel(0, &regs->DmaReadHostLo);
  261. writel(0, &regs->DmaReadLen);
  262. writel(0, &regs->DmaWriteLen);
  263. writel(0, &regs->DmaWriteLcl);
  264. writel(0, &regs->DmaWriteIPchecksum);
  265. writel(0, &regs->DmaReadLcl);
  266. writel(0, &regs->DmaReadIPchecksum);
  267. writel(0, &regs->PciState);
  268. #if (BITS_PER_LONG == 64) && defined __LITTLE_ENDIAN
  269. writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);
  270. #elif (BITS_PER_LONG == 64)
  271. writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);
  272. #else
  273. writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);
  274. #endif
  275. #if 0
  276. /*
  277. * Don't worry, this is just black magic.
  278. */
  279. writel(0xdf000, &regs->RxBase);
  280. writel(0xdf000, &regs->RxPrd);
  281. writel(0xdf000, &regs->RxCon);
  282. writel(0xce000, &regs->TxBase);
  283. writel(0xce000, &regs->TxPrd);
  284. writel(0xce000, &regs->TxCon);
  285. writel(0, &regs->RxIndPro);
  286. writel(0, &regs->RxIndCon);
  287. writel(0, &regs->RxIndRef);
  288. writel(0, &regs->TxIndPro);
  289. writel(0, &regs->TxIndCon);
  290. writel(0, &regs->TxIndRef);
  291. writel(0xcc000, &regs->pad10[0]);
  292. writel(0, &regs->DrCmndPro);
  293. writel(0, &regs->DrCmndCon);
  294. writel(0, &regs->DwCmndPro);
  295. writel(0, &regs->DwCmndCon);
  296. writel(0, &regs->DwCmndRef);
  297. writel(0, &regs->DrDataPro);
  298. writel(0, &regs->DrDataCon);
  299. writel(0, &regs->DrDataRef);
  300. writel(0, &regs->DwDataPro);
  301. writel(0, &regs->DwDataCon);
  302. writel(0, &regs->DwDataRef);
  303. #endif
  304. writel(0xffffffff, &regs->MbEvent);
  305. writel(0, &regs->Event);
  306. writel(0, &regs->TxPi);
  307. writel(0, &regs->IpRxPi);
  308. writel(0, &regs->EvtCon);
  309. writel(0, &regs->EvtPrd);
  310. rrpriv->info->evt_ctrl.pi = 0;
  311. for (i = 0; i < CMD_RING_ENTRIES; i++)
  312. writel(0, &regs->CmdRing[i]);
  313. /*
  314. * Why 32 ? is this not cache line size dependent?
  315. */
  316. writel(RBURST_64|WBURST_64, &regs->PciState);
  317. wmb();
  318. start_pc = rr_read_eeprom_word(rrpriv,
  319. offsetof(struct eeprom, rncd_info.FwStart));
  320. #if (DEBUG > 1)
  321. printk("%s: Executing firmware at address 0x%06x\n",
  322. dev->name, start_pc);
  323. #endif
  324. writel(start_pc + 0x800, &regs->Pc);
  325. wmb();
  326. udelay(5);
  327. writel(start_pc, &regs->Pc);
  328. wmb();
  329. return 0;
  330. }
  331. /*
  332. * Read a string from the EEPROM.
  333. */
  334. static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
  335. unsigned long offset,
  336. unsigned char *buf,
  337. unsigned long length)
  338. {
  339. struct rr_regs __iomem *regs = rrpriv->regs;
  340. u32 misc, io, host, i;
  341. io = readl(&regs->ExtIo);
  342. writel(0, &regs->ExtIo);
  343. misc = readl(&regs->LocalCtrl);
  344. writel(0, &regs->LocalCtrl);
  345. host = readl(&regs->HostCtrl);
  346. writel(host | HALT_NIC, &regs->HostCtrl);
  347. mb();
  348. for (i = 0; i < length; i++){
  349. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  350. mb();
  351. buf[i] = (readl(&regs->WinData) >> 24) & 0xff;
  352. mb();
  353. }
  354. writel(host, &regs->HostCtrl);
  355. writel(misc, &regs->LocalCtrl);
  356. writel(io, &regs->ExtIo);
  357. mb();
  358. return i;
  359. }
  360. /*
  361. * Shortcut to read one word (4 bytes) out of the EEPROM and convert
  362. * it to our CPU byte-order.
  363. */
  364. static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
  365. size_t offset)
  366. {
  367. __be32 word;
  368. if ((rr_read_eeprom(rrpriv, offset,
  369. (unsigned char *)&word, 4) == 4))
  370. return be32_to_cpu(word);
  371. return 0;
  372. }
  373. /*
  374. * Write a string to the EEPROM.
  375. *
  376. * This is only called when the firmware is not running.
  377. */
  378. static unsigned int write_eeprom(struct rr_private *rrpriv,
  379. unsigned long offset,
  380. unsigned char *buf,
  381. unsigned long length)
  382. {
  383. struct rr_regs __iomem *regs = rrpriv->regs;
  384. u32 misc, io, data, i, j, ready, error = 0;
  385. io = readl(&regs->ExtIo);
  386. writel(0, &regs->ExtIo);
  387. misc = readl(&regs->LocalCtrl);
  388. writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);
  389. mb();
  390. for (i = 0; i < length; i++){
  391. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  392. mb();
  393. data = buf[i] << 24;
  394. /*
  395. * Only try to write the data if it is not the same
  396. * value already.
  397. */
  398. if ((readl(&regs->WinData) & 0xff000000) != data){
  399. writel(data, &regs->WinData);
  400. ready = 0;
  401. j = 0;
  402. mb();
  403. while(!ready){
  404. udelay(20);
  405. if ((readl(&regs->WinData) & 0xff000000) ==
  406. data)
  407. ready = 1;
  408. mb();
  409. if (j++ > 5000){
  410. printk("data mismatch: %08x, "
  411. "WinData %08x\n", data,
  412. readl(&regs->WinData));
  413. ready = 1;
  414. error = 1;
  415. }
  416. }
  417. }
  418. }
  419. writel(misc, &regs->LocalCtrl);
  420. writel(io, &regs->ExtIo);
  421. mb();
  422. return error;
  423. }
  424. static int rr_init(struct net_device *dev)
  425. {
  426. struct rr_private *rrpriv;
  427. struct rr_regs __iomem *regs;
  428. u32 sram_size, rev;
  429. rrpriv = netdev_priv(dev);
  430. regs = rrpriv->regs;
  431. rev = readl(&regs->FwRev);
  432. rrpriv->fw_rev = rev;
  433. if (rev > 0x00020024)
  434. printk(" Firmware revision: %i.%i.%i\n", (rev >> 16),
  435. ((rev >> 8) & 0xff), (rev & 0xff));
  436. else if (rev >= 0x00020000) {
  437. printk(" Firmware revision: %i.%i.%i (2.0.37 or "
  438. "later is recommended)\n", (rev >> 16),
  439. ((rev >> 8) & 0xff), (rev & 0xff));
  440. }else{
  441. printk(" Firmware revision too old: %i.%i.%i, please "
  442. "upgrade to 2.0.37 or later.\n",
  443. (rev >> 16), ((rev >> 8) & 0xff), (rev & 0xff));
  444. }
  445. #if (DEBUG > 2)
  446. printk(" Maximum receive rings %i\n", readl(&regs->MaxRxRng));
  447. #endif
  448. /*
  449. * Read the hardware address from the eeprom. The HW address
  450. * is not really necessary for HIPPI but awfully convenient.
  451. * The pointer arithmetic to put it in dev_addr is ugly, but
  452. * Donald Becker does it this way for the GigE version of this
  453. * card and it's shorter and more portable than any
  454. * other method I've seen. -VAL
  455. */
  456. *(__be16 *)(dev->dev_addr) =
  457. htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
  458. *(__be32 *)(dev->dev_addr+2) =
  459. htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
  460. printk(" MAC: %pM\n", dev->dev_addr);
  461. sram_size = rr_read_eeprom_word(rrpriv, 8);
  462. printk(" SRAM size 0x%06x\n", sram_size);
  463. return 0;
  464. }
  465. static int rr_init1(struct net_device *dev)
  466. {
  467. struct rr_private *rrpriv;
  468. struct rr_regs __iomem *regs;
  469. unsigned long myjif, flags;
  470. struct cmd cmd;
  471. u32 hostctrl;
  472. int ecode = 0;
  473. short i;
  474. rrpriv = netdev_priv(dev);
  475. regs = rrpriv->regs;
  476. spin_lock_irqsave(&rrpriv->lock, flags);
  477. hostctrl = readl(&regs->HostCtrl);
  478. writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);
  479. wmb();
  480. if (hostctrl & PARITY_ERR){
  481. printk("%s: Parity error halting NIC - this is serious!\n",
  482. dev->name);
  483. spin_unlock_irqrestore(&rrpriv->lock, flags);
  484. ecode = -EFAULT;
  485. goto error;
  486. }
  487. set_rxaddr(regs, rrpriv->rx_ctrl_dma);
  488. set_infoaddr(regs, rrpriv->info_dma);
  489. rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
  490. rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
  491. rrpriv->info->evt_ctrl.mode = 0;
  492. rrpriv->info->evt_ctrl.pi = 0;
  493. set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
  494. rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
  495. rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
  496. rrpriv->info->cmd_ctrl.mode = 0;
  497. rrpriv->info->cmd_ctrl.pi = 15;
  498. for (i = 0; i < CMD_RING_ENTRIES; i++) {
  499. writel(0, &regs->CmdRing[i]);
  500. }
  501. for (i = 0; i < TX_RING_ENTRIES; i++) {
  502. rrpriv->tx_ring[i].size = 0;
  503. set_rraddr(&rrpriv->tx_ring[i].addr, 0);
  504. rrpriv->tx_skbuff[i] = NULL;
  505. }
  506. rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
  507. rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
  508. rrpriv->info->tx_ctrl.mode = 0;
  509. rrpriv->info->tx_ctrl.pi = 0;
  510. set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
  511. /*
  512. * Set dirty_tx before we start receiving interrupts, otherwise
  513. * the interrupt handler might think it is supposed to process
  514. * tx ints before we are up and running, which may cause a null
  515. * pointer access in the int handler.
  516. */
  517. rrpriv->tx_full = 0;
  518. rrpriv->cur_rx = 0;
  519. rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
  520. rr_reset(dev);
  521. /* Tuning values */
  522. writel(0x5000, &regs->ConRetry);
  523. writel(0x100, &regs->ConRetryTmr);
  524. writel(0x500000, &regs->ConTmout);
  525. writel(0x60, &regs->IntrTmr);
  526. writel(0x500000, &regs->TxDataMvTimeout);
  527. writel(0x200000, &regs->RxDataMvTimeout);
  528. writel(0x80, &regs->WriteDmaThresh);
  529. writel(0x80, &regs->ReadDmaThresh);
  530. rrpriv->fw_running = 0;
  531. wmb();
  532. hostctrl &= ~(HALT_NIC | INVALID_INST_B | PARITY_ERR);
  533. writel(hostctrl, &regs->HostCtrl);
  534. wmb();
  535. spin_unlock_irqrestore(&rrpriv->lock, flags);
  536. for (i = 0; i < RX_RING_ENTRIES; i++) {
  537. struct sk_buff *skb;
  538. dma_addr_t addr;
  539. rrpriv->rx_ring[i].mode = 0;
  540. skb = alloc_skb(dev->mtu + HIPPI_HLEN, GFP_ATOMIC);
  541. if (!skb) {
  542. printk(KERN_WARNING "%s: Unable to allocate memory "
  543. "for receive ring - halting NIC\n", dev->name);
  544. ecode = -ENOMEM;
  545. goto error;
  546. }
  547. rrpriv->rx_skbuff[i] = skb;
  548. addr = pci_map_single(rrpriv->pci_dev, skb->data,
  549. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  550. /*
  551. * Sanity test to see if we conflict with the DMA
  552. * limitations of the Roadrunner.
  553. */
  554. if ((((unsigned long)skb->data) & 0xfff) > ~65320)
  555. printk("skb alloc error\n");
  556. set_rraddr(&rrpriv->rx_ring[i].addr, addr);
  557. rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
  558. }
  559. rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
  560. rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
  561. rrpriv->rx_ctrl[4].mode = 8;
  562. rrpriv->rx_ctrl[4].pi = 0;
  563. wmb();
  564. set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
  565. udelay(1000);
  566. /*
  567. * Now start the FirmWare.
  568. */
  569. cmd.code = C_START_FW;
  570. cmd.ring = 0;
  571. cmd.index = 0;
  572. rr_issue_cmd(rrpriv, &cmd);
  573. /*
  574. * Give the FirmWare time to chew on the `get running' command.
  575. */
  576. myjif = jiffies + 5 * HZ;
  577. while (time_before(jiffies, myjif) && !rrpriv->fw_running)
  578. cpu_relax();
  579. netif_start_queue(dev);
  580. return ecode;
  581. error:
  582. /*
  583. * We might have gotten here because we are out of memory,
  584. * make sure we release everything we allocated before failing
  585. */
  586. for (i = 0; i < RX_RING_ENTRIES; i++) {
  587. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  588. if (skb) {
  589. pci_unmap_single(rrpriv->pci_dev,
  590. rrpriv->rx_ring[i].addr.addrlo,
  591. dev->mtu + HIPPI_HLEN,
  592. PCI_DMA_FROMDEVICE);
  593. rrpriv->rx_ring[i].size = 0;
  594. set_rraddr(&rrpriv->rx_ring[i].addr, 0);
  595. dev_kfree_skb(skb);
  596. rrpriv->rx_skbuff[i] = NULL;
  597. }
  598. }
  599. return ecode;
  600. }
  601. /*
  602. * All events are considered to be slow (RX/TX ints do not generate
  603. * events) and are handled here, outside the main interrupt handler,
  604. * to reduce the size of the handler.
  605. */
  606. static u32 rr_handle_event(struct net_device *dev, u32 prodidx, u32 eidx)
  607. {
  608. struct rr_private *rrpriv;
  609. struct rr_regs __iomem *regs;
  610. u32 tmp;
  611. rrpriv = netdev_priv(dev);
  612. regs = rrpriv->regs;
  613. while (prodidx != eidx){
  614. switch (rrpriv->evt_ring[eidx].code){
  615. case E_NIC_UP:
  616. tmp = readl(&regs->FwRev);
  617. printk(KERN_INFO "%s: Firmware revision %i.%i.%i "
  618. "up and running\n", dev->name,
  619. (tmp >> 16), ((tmp >> 8) & 0xff), (tmp & 0xff));
  620. rrpriv->fw_running = 1;
  621. writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);
  622. wmb();
  623. break;
  624. case E_LINK_ON:
  625. printk(KERN_INFO "%s: Optical link ON\n", dev->name);
  626. break;
  627. case E_LINK_OFF:
  628. printk(KERN_INFO "%s: Optical link OFF\n", dev->name);
  629. break;
  630. case E_RX_IDLE:
  631. printk(KERN_WARNING "%s: RX data not moving\n",
  632. dev->name);
  633. goto drop;
  634. case E_WATCHDOG:
  635. printk(KERN_INFO "%s: The watchdog is here to see "
  636. "us\n", dev->name);
  637. break;
  638. case E_INTERN_ERR:
  639. printk(KERN_ERR "%s: HIPPI Internal NIC error\n",
  640. dev->name);
  641. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  642. &regs->HostCtrl);
  643. wmb();
  644. break;
  645. case E_HOST_ERR:
  646. printk(KERN_ERR "%s: Host software error\n",
  647. dev->name);
  648. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  649. &regs->HostCtrl);
  650. wmb();
  651. break;
  652. /*
  653. * TX events.
  654. */
  655. case E_CON_REJ:
  656. printk(KERN_WARNING "%s: Connection rejected\n",
  657. dev->name);
  658. dev->stats.tx_aborted_errors++;
  659. break;
  660. case E_CON_TMOUT:
  661. printk(KERN_WARNING "%s: Connection timeout\n",
  662. dev->name);
  663. break;
  664. case E_DISC_ERR:
  665. printk(KERN_WARNING "%s: HIPPI disconnect error\n",
  666. dev->name);
  667. dev->stats.tx_aborted_errors++;
  668. break;
  669. case E_INT_PRTY:
  670. printk(KERN_ERR "%s: HIPPI Internal Parity error\n",
  671. dev->name);
  672. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  673. &regs->HostCtrl);
  674. wmb();
  675. break;
  676. case E_TX_IDLE:
  677. printk(KERN_WARNING "%s: Transmitter idle\n",
  678. dev->name);
  679. break;
  680. case E_TX_LINK_DROP:
  681. printk(KERN_WARNING "%s: Link lost during transmit\n",
  682. dev->name);
  683. dev->stats.tx_aborted_errors++;
  684. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  685. &regs->HostCtrl);
  686. wmb();
  687. break;
  688. case E_TX_INV_RNG:
  689. printk(KERN_ERR "%s: Invalid send ring block\n",
  690. dev->name);
  691. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  692. &regs->HostCtrl);
  693. wmb();
  694. break;
  695. case E_TX_INV_BUF:
  696. printk(KERN_ERR "%s: Invalid send buffer address\n",
  697. dev->name);
  698. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  699. &regs->HostCtrl);
  700. wmb();
  701. break;
  702. case E_TX_INV_DSC:
  703. printk(KERN_ERR "%s: Invalid descriptor address\n",
  704. dev->name);
  705. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  706. &regs->HostCtrl);
  707. wmb();
  708. break;
  709. /*
  710. * RX events.
  711. */
  712. case E_RX_RNG_OUT:
  713. printk(KERN_INFO "%s: Receive ring full\n", dev->name);
  714. break;
  715. case E_RX_PAR_ERR:
  716. printk(KERN_WARNING "%s: Receive parity error\n",
  717. dev->name);
  718. goto drop;
  719. case E_RX_LLRC_ERR:
  720. printk(KERN_WARNING "%s: Receive LLRC error\n",
  721. dev->name);
  722. goto drop;
  723. case E_PKT_LN_ERR:
  724. printk(KERN_WARNING "%s: Receive packet length "
  725. "error\n", dev->name);
  726. goto drop;
  727. case E_DTA_CKSM_ERR:
  728. printk(KERN_WARNING "%s: Data checksum error\n",
  729. dev->name);
  730. goto drop;
  731. case E_SHT_BST:
  732. printk(KERN_WARNING "%s: Unexpected short burst "
  733. "error\n", dev->name);
  734. goto drop;
  735. case E_STATE_ERR:
  736. printk(KERN_WARNING "%s: Recv. state transition"
  737. " error\n", dev->name);
  738. goto drop;
  739. case E_UNEXP_DATA:
  740. printk(KERN_WARNING "%s: Unexpected data error\n",
  741. dev->name);
  742. goto drop;
  743. case E_LST_LNK_ERR:
  744. printk(KERN_WARNING "%s: Link lost error\n",
  745. dev->name);
  746. goto drop;
  747. case E_FRM_ERR:
  748. printk(KERN_WARNING "%s: Framming Error\n",
  749. dev->name);
  750. goto drop;
  751. case E_FLG_SYN_ERR:
  752. printk(KERN_WARNING "%s: Flag sync. lost during "
  753. "packet\n", dev->name);
  754. goto drop;
  755. case E_RX_INV_BUF:
  756. printk(KERN_ERR "%s: Invalid receive buffer "
  757. "address\n", dev->name);
  758. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  759. &regs->HostCtrl);
  760. wmb();
  761. break;
  762. case E_RX_INV_DSC:
  763. printk(KERN_ERR "%s: Invalid receive descriptor "
  764. "address\n", dev->name);
  765. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  766. &regs->HostCtrl);
  767. wmb();
  768. break;
  769. case E_RNG_BLK:
  770. printk(KERN_ERR "%s: Invalid ring block\n",
  771. dev->name);
  772. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  773. &regs->HostCtrl);
  774. wmb();
  775. break;
  776. drop:
  777. /* Label packet to be dropped.
  778. * Actual dropping occurs in rx
  779. * handling.
  780. *
  781. * The index of packet we get to drop is
  782. * the index of the packet following
  783. * the bad packet. -kbf
  784. */
  785. {
  786. u16 index = rrpriv->evt_ring[eidx].index;
  787. index = (index + (RX_RING_ENTRIES - 1)) %
  788. RX_RING_ENTRIES;
  789. rrpriv->rx_ring[index].mode |=
  790. (PACKET_BAD | PACKET_END);
  791. }
  792. break;
  793. default:
  794. printk(KERN_WARNING "%s: Unhandled event 0x%02x\n",
  795. dev->name, rrpriv->evt_ring[eidx].code);
  796. }
  797. eidx = (eidx + 1) % EVT_RING_ENTRIES;
  798. }
  799. rrpriv->info->evt_ctrl.pi = eidx;
  800. wmb();
  801. return eidx;
  802. }
  803. static void rx_int(struct net_device *dev, u32 rxlimit, u32 index)
  804. {
  805. struct rr_private *rrpriv = netdev_priv(dev);
  806. struct rr_regs __iomem *regs = rrpriv->regs;
  807. do {
  808. struct rx_desc *desc;
  809. u32 pkt_len;
  810. desc = &(rrpriv->rx_ring[index]);
  811. pkt_len = desc->size;
  812. #if (DEBUG > 2)
  813. printk("index %i, rxlimit %i\n", index, rxlimit);
  814. printk("len %x, mode %x\n", pkt_len, desc->mode);
  815. #endif
  816. if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
  817. dev->stats.rx_dropped++;
  818. goto defer;
  819. }
  820. if (pkt_len > 0){
  821. struct sk_buff *skb, *rx_skb;
  822. rx_skb = rrpriv->rx_skbuff[index];
  823. if (pkt_len < PKT_COPY_THRESHOLD) {
  824. skb = alloc_skb(pkt_len, GFP_ATOMIC);
  825. if (skb == NULL){
  826. printk(KERN_WARNING "%s: Unable to allocate skb (%i bytes), deferring packet\n", dev->name, pkt_len);
  827. dev->stats.rx_dropped++;
  828. goto defer;
  829. } else {
  830. pci_dma_sync_single_for_cpu(rrpriv->pci_dev,
  831. desc->addr.addrlo,
  832. pkt_len,
  833. PCI_DMA_FROMDEVICE);
  834. memcpy(skb_put(skb, pkt_len),
  835. rx_skb->data, pkt_len);
  836. pci_dma_sync_single_for_device(rrpriv->pci_dev,
  837. desc->addr.addrlo,
  838. pkt_len,
  839. PCI_DMA_FROMDEVICE);
  840. }
  841. }else{
  842. struct sk_buff *newskb;
  843. newskb = alloc_skb(dev->mtu + HIPPI_HLEN,
  844. GFP_ATOMIC);
  845. if (newskb){
  846. dma_addr_t addr;
  847. pci_unmap_single(rrpriv->pci_dev,
  848. desc->addr.addrlo, dev->mtu +
  849. HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  850. skb = rx_skb;
  851. skb_put(skb, pkt_len);
  852. rrpriv->rx_skbuff[index] = newskb;
  853. addr = pci_map_single(rrpriv->pci_dev,
  854. newskb->data,
  855. dev->mtu + HIPPI_HLEN,
  856. PCI_DMA_FROMDEVICE);
  857. set_rraddr(&desc->addr, addr);
  858. } else {
  859. printk("%s: Out of memory, deferring "
  860. "packet\n", dev->name);
  861. dev->stats.rx_dropped++;
  862. goto defer;
  863. }
  864. }
  865. skb->protocol = hippi_type_trans(skb, dev);
  866. netif_rx(skb); /* send it up */
  867. dev->stats.rx_packets++;
  868. dev->stats.rx_bytes += pkt_len;
  869. }
  870. defer:
  871. desc->mode = 0;
  872. desc->size = dev->mtu + HIPPI_HLEN;
  873. if ((index & 7) == 7)
  874. writel(index, &regs->IpRxPi);
  875. index = (index + 1) % RX_RING_ENTRIES;
  876. } while(index != rxlimit);
  877. rrpriv->cur_rx = index;
  878. wmb();
  879. }
  880. static irqreturn_t rr_interrupt(int irq, void *dev_id)
  881. {
  882. struct rr_private *rrpriv;
  883. struct rr_regs __iomem *regs;
  884. struct net_device *dev = (struct net_device *)dev_id;
  885. u32 prodidx, rxindex, eidx, txcsmr, rxlimit, txcon;
  886. rrpriv = netdev_priv(dev);
  887. regs = rrpriv->regs;
  888. if (!(readl(&regs->HostCtrl) & RR_INT))
  889. return IRQ_NONE;
  890. spin_lock(&rrpriv->lock);
  891. prodidx = readl(&regs->EvtPrd);
  892. txcsmr = (prodidx >> 8) & 0xff;
  893. rxlimit = (prodidx >> 16) & 0xff;
  894. prodidx &= 0xff;
  895. #if (DEBUG > 2)
  896. printk("%s: interrupt, prodidx = %i, eidx = %i\n", dev->name,
  897. prodidx, rrpriv->info->evt_ctrl.pi);
  898. #endif
  899. /*
  900. * Order here is important. We must handle events
  901. * before doing anything else in order to catch
  902. * such things as LLRC errors, etc -kbf
  903. */
  904. eidx = rrpriv->info->evt_ctrl.pi;
  905. if (prodidx != eidx)
  906. eidx = rr_handle_event(dev, prodidx, eidx);
  907. rxindex = rrpriv->cur_rx;
  908. if (rxindex != rxlimit)
  909. rx_int(dev, rxlimit, rxindex);
  910. txcon = rrpriv->dirty_tx;
  911. if (txcsmr != txcon) {
  912. do {
  913. /* Due to occational firmware TX producer/consumer out
  914. * of sync. error need to check entry in ring -kbf
  915. */
  916. if(rrpriv->tx_skbuff[txcon]){
  917. struct tx_desc *desc;
  918. struct sk_buff *skb;
  919. desc = &(rrpriv->tx_ring[txcon]);
  920. skb = rrpriv->tx_skbuff[txcon];
  921. dev->stats.tx_packets++;
  922. dev->stats.tx_bytes += skb->len;
  923. pci_unmap_single(rrpriv->pci_dev,
  924. desc->addr.addrlo, skb->len,
  925. PCI_DMA_TODEVICE);
  926. dev_kfree_skb_irq(skb);
  927. rrpriv->tx_skbuff[txcon] = NULL;
  928. desc->size = 0;
  929. set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
  930. desc->mode = 0;
  931. }
  932. txcon = (txcon + 1) % TX_RING_ENTRIES;
  933. } while (txcsmr != txcon);
  934. wmb();
  935. rrpriv->dirty_tx = txcon;
  936. if (rrpriv->tx_full && rr_if_busy(dev) &&
  937. (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
  938. != rrpriv->dirty_tx)){
  939. rrpriv->tx_full = 0;
  940. netif_wake_queue(dev);
  941. }
  942. }
  943. eidx |= ((txcsmr << 8) | (rxlimit << 16));
  944. writel(eidx, &regs->EvtCon);
  945. wmb();
  946. spin_unlock(&rrpriv->lock);
  947. return IRQ_HANDLED;
  948. }
  949. static inline void rr_raz_tx(struct rr_private *rrpriv,
  950. struct net_device *dev)
  951. {
  952. int i;
  953. for (i = 0; i < TX_RING_ENTRIES; i++) {
  954. struct sk_buff *skb = rrpriv->tx_skbuff[i];
  955. if (skb) {
  956. struct tx_desc *desc = &(rrpriv->tx_ring[i]);
  957. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  958. skb->len, PCI_DMA_TODEVICE);
  959. desc->size = 0;
  960. set_rraddr(&desc->addr, 0);
  961. dev_kfree_skb(skb);
  962. rrpriv->tx_skbuff[i] = NULL;
  963. }
  964. }
  965. }
  966. static inline void rr_raz_rx(struct rr_private *rrpriv,
  967. struct net_device *dev)
  968. {
  969. int i;
  970. for (i = 0; i < RX_RING_ENTRIES; i++) {
  971. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  972. if (skb) {
  973. struct rx_desc *desc = &(rrpriv->rx_ring[i]);
  974. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  975. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  976. desc->size = 0;
  977. set_rraddr(&desc->addr, 0);
  978. dev_kfree_skb(skb);
  979. rrpriv->rx_skbuff[i] = NULL;
  980. }
  981. }
  982. }
  983. static void rr_timer(unsigned long data)
  984. {
  985. struct net_device *dev = (struct net_device *)data;
  986. struct rr_private *rrpriv = netdev_priv(dev);
  987. struct rr_regs __iomem *regs = rrpriv->regs;
  988. unsigned long flags;
  989. if (readl(&regs->HostCtrl) & NIC_HALTED){
  990. printk("%s: Restarting nic\n", dev->name);
  991. memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
  992. memset(rrpriv->info, 0, sizeof(struct rr_info));
  993. wmb();
  994. rr_raz_tx(rrpriv, dev);
  995. rr_raz_rx(rrpriv, dev);
  996. if (rr_init1(dev)) {
  997. spin_lock_irqsave(&rrpriv->lock, flags);
  998. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  999. &regs->HostCtrl);
  1000. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1001. }
  1002. }
  1003. rrpriv->timer.expires = RUN_AT(5*HZ);
  1004. add_timer(&rrpriv->timer);
  1005. }
  1006. static int rr_open(struct net_device *dev)
  1007. {
  1008. struct rr_private *rrpriv = netdev_priv(dev);
  1009. struct pci_dev *pdev = rrpriv->pci_dev;
  1010. struct rr_regs __iomem *regs;
  1011. int ecode = 0;
  1012. unsigned long flags;
  1013. dma_addr_t dma_addr;
  1014. regs = rrpriv->regs;
  1015. if (rrpriv->fw_rev < 0x00020000) {
  1016. printk(KERN_WARNING "%s: trying to configure device with "
  1017. "obsolete firmware\n", dev->name);
  1018. ecode = -EBUSY;
  1019. goto error;
  1020. }
  1021. rrpriv->rx_ctrl = pci_alloc_consistent(pdev,
  1022. 256 * sizeof(struct ring_ctrl),
  1023. &dma_addr);
  1024. if (!rrpriv->rx_ctrl) {
  1025. ecode = -ENOMEM;
  1026. goto error;
  1027. }
  1028. rrpriv->rx_ctrl_dma = dma_addr;
  1029. memset(rrpriv->rx_ctrl, 0, 256*sizeof(struct ring_ctrl));
  1030. rrpriv->info = pci_alloc_consistent(pdev, sizeof(struct rr_info),
  1031. &dma_addr);
  1032. if (!rrpriv->info) {
  1033. ecode = -ENOMEM;
  1034. goto error;
  1035. }
  1036. rrpriv->info_dma = dma_addr;
  1037. memset(rrpriv->info, 0, sizeof(struct rr_info));
  1038. wmb();
  1039. spin_lock_irqsave(&rrpriv->lock, flags);
  1040. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1041. readl(&regs->HostCtrl);
  1042. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1043. if (request_irq(pdev->irq, rr_interrupt, IRQF_SHARED, dev->name, dev)) {
  1044. printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
  1045. dev->name, pdev->irq);
  1046. ecode = -EAGAIN;
  1047. goto error;
  1048. }
  1049. if ((ecode = rr_init1(dev)))
  1050. goto error;
  1051. /* Set the timer to switch to check for link beat and perhaps switch
  1052. to an alternate media type. */
  1053. init_timer(&rrpriv->timer);
  1054. rrpriv->timer.expires = RUN_AT(5*HZ); /* 5 sec. watchdog */
  1055. rrpriv->timer.data = (unsigned long)dev;
  1056. rrpriv->timer.function = rr_timer; /* timer handler */
  1057. add_timer(&rrpriv->timer);
  1058. netif_start_queue(dev);
  1059. return ecode;
  1060. error:
  1061. spin_lock_irqsave(&rrpriv->lock, flags);
  1062. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1063. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1064. if (rrpriv->info) {
  1065. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1066. rrpriv->info_dma);
  1067. rrpriv->info = NULL;
  1068. }
  1069. if (rrpriv->rx_ctrl) {
  1070. pci_free_consistent(pdev, sizeof(struct ring_ctrl),
  1071. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1072. rrpriv->rx_ctrl = NULL;
  1073. }
  1074. netif_stop_queue(dev);
  1075. return ecode;
  1076. }
  1077. static void rr_dump(struct net_device *dev)
  1078. {
  1079. struct rr_private *rrpriv;
  1080. struct rr_regs __iomem *regs;
  1081. u32 index, cons;
  1082. short i;
  1083. int len;
  1084. rrpriv = netdev_priv(dev);
  1085. regs = rrpriv->regs;
  1086. printk("%s: dumping NIC TX rings\n", dev->name);
  1087. printk("RxPrd %08x, TxPrd %02x, EvtPrd %08x, TxPi %02x, TxCtrlPi %02x\n",
  1088. readl(&regs->RxPrd), readl(&regs->TxPrd),
  1089. readl(&regs->EvtPrd), readl(&regs->TxPi),
  1090. rrpriv->info->tx_ctrl.pi);
  1091. printk("Error code 0x%x\n", readl(&regs->Fail1));
  1092. index = (((readl(&regs->EvtPrd) >> 8) & 0xff) - 1) % TX_RING_ENTRIES;
  1093. cons = rrpriv->dirty_tx;
  1094. printk("TX ring index %i, TX consumer %i\n",
  1095. index, cons);
  1096. if (rrpriv->tx_skbuff[index]){
  1097. len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
  1098. printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
  1099. for (i = 0; i < len; i++){
  1100. if (!(i & 7))
  1101. printk("\n");
  1102. printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
  1103. }
  1104. printk("\n");
  1105. }
  1106. if (rrpriv->tx_skbuff[cons]){
  1107. len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
  1108. printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
  1109. printk("mode 0x%x, size 0x%x,\n phys %08Lx, skbuff-addr %08lx, truesize 0x%x\n",
  1110. rrpriv->tx_ring[cons].mode,
  1111. rrpriv->tx_ring[cons].size,
  1112. (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
  1113. (unsigned long)rrpriv->tx_skbuff[cons]->data,
  1114. (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
  1115. for (i = 0; i < len; i++){
  1116. if (!(i & 7))
  1117. printk("\n");
  1118. printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
  1119. }
  1120. printk("\n");
  1121. }
  1122. printk("dumping TX ring info:\n");
  1123. for (i = 0; i < TX_RING_ENTRIES; i++)
  1124. printk("mode 0x%x, size 0x%x, phys-addr %08Lx\n",
  1125. rrpriv->tx_ring[i].mode,
  1126. rrpriv->tx_ring[i].size,
  1127. (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
  1128. }
  1129. static int rr_close(struct net_device *dev)
  1130. {
  1131. struct rr_private *rrpriv = netdev_priv(dev);
  1132. struct rr_regs __iomem *regs = rrpriv->regs;
  1133. struct pci_dev *pdev = rrpriv->pci_dev;
  1134. unsigned long flags;
  1135. u32 tmp;
  1136. short i;
  1137. netif_stop_queue(dev);
  1138. /*
  1139. * Lock to make sure we are not cleaning up while another CPU
  1140. * is handling interrupts.
  1141. */
  1142. spin_lock_irqsave(&rrpriv->lock, flags);
  1143. tmp = readl(&regs->HostCtrl);
  1144. if (tmp & NIC_HALTED){
  1145. printk("%s: NIC already halted\n", dev->name);
  1146. rr_dump(dev);
  1147. }else{
  1148. tmp |= HALT_NIC | RR_CLEAR_INT;
  1149. writel(tmp, &regs->HostCtrl);
  1150. readl(&regs->HostCtrl);
  1151. }
  1152. rrpriv->fw_running = 0;
  1153. del_timer_sync(&rrpriv->timer);
  1154. writel(0, &regs->TxPi);
  1155. writel(0, &regs->IpRxPi);
  1156. writel(0, &regs->EvtCon);
  1157. writel(0, &regs->EvtPrd);
  1158. for (i = 0; i < CMD_RING_ENTRIES; i++)
  1159. writel(0, &regs->CmdRing[i]);
  1160. rrpriv->info->tx_ctrl.entries = 0;
  1161. rrpriv->info->cmd_ctrl.pi = 0;
  1162. rrpriv->info->evt_ctrl.pi = 0;
  1163. rrpriv->rx_ctrl[4].entries = 0;
  1164. rr_raz_tx(rrpriv, dev);
  1165. rr_raz_rx(rrpriv, dev);
  1166. pci_free_consistent(pdev, 256 * sizeof(struct ring_ctrl),
  1167. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1168. rrpriv->rx_ctrl = NULL;
  1169. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1170. rrpriv->info_dma);
  1171. rrpriv->info = NULL;
  1172. free_irq(pdev->irq, dev);
  1173. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1174. return 0;
  1175. }
  1176. static netdev_tx_t rr_start_xmit(struct sk_buff *skb,
  1177. struct net_device *dev)
  1178. {
  1179. struct rr_private *rrpriv = netdev_priv(dev);
  1180. struct rr_regs __iomem *regs = rrpriv->regs;
  1181. struct hippi_cb *hcb = (struct hippi_cb *) skb->cb;
  1182. struct ring_ctrl *txctrl;
  1183. unsigned long flags;
  1184. u32 index, len = skb->len;
  1185. u32 *ifield;
  1186. struct sk_buff *new_skb;
  1187. if (readl(&regs->Mode) & FATAL_ERR)
  1188. printk("error codes Fail1 %02x, Fail2 %02x\n",
  1189. readl(&regs->Fail1), readl(&regs->Fail2));
  1190. /*
  1191. * We probably need to deal with tbusy here to prevent overruns.
  1192. */
  1193. if (skb_headroom(skb) < 8){
  1194. printk("incoming skb too small - reallocating\n");
  1195. if (!(new_skb = dev_alloc_skb(len + 8))) {
  1196. dev_kfree_skb(skb);
  1197. netif_wake_queue(dev);
  1198. return NETDEV_TX_OK;
  1199. }
  1200. skb_reserve(new_skb, 8);
  1201. skb_put(new_skb, len);
  1202. skb_copy_from_linear_data(skb, new_skb->data, len);
  1203. dev_kfree_skb(skb);
  1204. skb = new_skb;
  1205. }
  1206. ifield = (u32 *)skb_push(skb, 8);
  1207. ifield[0] = 0;
  1208. ifield[1] = hcb->ifield;
  1209. /*
  1210. * We don't need the lock before we are actually going to start
  1211. * fiddling with the control blocks.
  1212. */
  1213. spin_lock_irqsave(&rrpriv->lock, flags);
  1214. txctrl = &rrpriv->info->tx_ctrl;
  1215. index = txctrl->pi;
  1216. rrpriv->tx_skbuff[index] = skb;
  1217. set_rraddr(&rrpriv->tx_ring[index].addr, pci_map_single(
  1218. rrpriv->pci_dev, skb->data, len + 8, PCI_DMA_TODEVICE));
  1219. rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
  1220. rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
  1221. txctrl->pi = (index + 1) % TX_RING_ENTRIES;
  1222. wmb();
  1223. writel(txctrl->pi, &regs->TxPi);
  1224. if (txctrl->pi == rrpriv->dirty_tx){
  1225. rrpriv->tx_full = 1;
  1226. netif_stop_queue(dev);
  1227. }
  1228. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1229. return NETDEV_TX_OK;
  1230. }
  1231. /*
  1232. * Read the firmware out of the EEPROM and put it into the SRAM
  1233. * (or from user space - later)
  1234. *
  1235. * This operation requires the NIC to be halted and is performed with
  1236. * interrupts disabled and with the spinlock hold.
  1237. */
  1238. static int rr_load_firmware(struct net_device *dev)
  1239. {
  1240. struct rr_private *rrpriv;
  1241. struct rr_regs __iomem *regs;
  1242. size_t eptr, segptr;
  1243. int i, j;
  1244. u32 localctrl, sptr, len, tmp;
  1245. u32 p2len, p2size, nr_seg, revision, io, sram_size;
  1246. rrpriv = netdev_priv(dev);
  1247. regs = rrpriv->regs;
  1248. if (dev->flags & IFF_UP)
  1249. return -EBUSY;
  1250. if (!(readl(&regs->HostCtrl) & NIC_HALTED)){
  1251. printk("%s: Trying to load firmware to a running NIC.\n",
  1252. dev->name);
  1253. return -EBUSY;
  1254. }
  1255. localctrl = readl(&regs->LocalCtrl);
  1256. writel(0, &regs->LocalCtrl);
  1257. writel(0, &regs->EvtPrd);
  1258. writel(0, &regs->RxPrd);
  1259. writel(0, &regs->TxPrd);
  1260. /*
  1261. * First wipe the entire SRAM, otherwise we might run into all
  1262. * kinds of trouble ... sigh, this took almost all afternoon
  1263. * to track down ;-(
  1264. */
  1265. io = readl(&regs->ExtIo);
  1266. writel(0, &regs->ExtIo);
  1267. sram_size = rr_read_eeprom_word(rrpriv, 8);
  1268. for (i = 200; i < sram_size / 4; i++){
  1269. writel(i * 4, &regs->WinBase);
  1270. mb();
  1271. writel(0, &regs->WinData);
  1272. mb();
  1273. }
  1274. writel(io, &regs->ExtIo);
  1275. mb();
  1276. eptr = rr_read_eeprom_word(rrpriv,
  1277. offsetof(struct eeprom, rncd_info.AddrRunCodeSegs));
  1278. eptr = ((eptr & 0x1fffff) >> 3);
  1279. p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
  1280. p2len = (p2len << 2);
  1281. p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
  1282. p2size = ((p2size & 0x1fffff) >> 3);
  1283. if ((eptr < p2size) || (eptr > (p2size + p2len))){
  1284. printk("%s: eptr is invalid\n", dev->name);
  1285. goto out;
  1286. }
  1287. revision = rr_read_eeprom_word(rrpriv,
  1288. offsetof(struct eeprom, manf.HeaderFmt));
  1289. if (revision != 1){
  1290. printk("%s: invalid firmware format (%i)\n",
  1291. dev->name, revision);
  1292. goto out;
  1293. }
  1294. nr_seg = rr_read_eeprom_word(rrpriv, eptr);
  1295. eptr +=4;
  1296. #if (DEBUG > 1)
  1297. printk("%s: nr_seg %i\n", dev->name, nr_seg);
  1298. #endif
  1299. for (i = 0; i < nr_seg; i++){
  1300. sptr = rr_read_eeprom_word(rrpriv, eptr);
  1301. eptr += 4;
  1302. len = rr_read_eeprom_word(rrpriv, eptr);
  1303. eptr += 4;
  1304. segptr = rr_read_eeprom_word(rrpriv, eptr);
  1305. segptr = ((segptr & 0x1fffff) >> 3);
  1306. eptr += 4;
  1307. #if (DEBUG > 1)
  1308. printk("%s: segment %i, sram address %06x, length %04x, segptr %06x\n",
  1309. dev->name, i, sptr, len, segptr);
  1310. #endif
  1311. for (j = 0; j < len; j++){
  1312. tmp = rr_read_eeprom_word(rrpriv, segptr);
  1313. writel(sptr, &regs->WinBase);
  1314. mb();
  1315. writel(tmp, &regs->WinData);
  1316. mb();
  1317. segptr += 4;
  1318. sptr += 4;
  1319. }
  1320. }
  1321. out:
  1322. writel(localctrl, &regs->LocalCtrl);
  1323. mb();
  1324. return 0;
  1325. }
  1326. static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1327. {
  1328. struct rr_private *rrpriv;
  1329. unsigned char *image, *oldimage;
  1330. unsigned long flags;
  1331. unsigned int i;
  1332. int error = -EOPNOTSUPP;
  1333. rrpriv = netdev_priv(dev);
  1334. switch(cmd){
  1335. case SIOCRRGFW:
  1336. if (!capable(CAP_SYS_RAWIO)){
  1337. return -EPERM;
  1338. }
  1339. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1340. if (!image)
  1341. return -ENOMEM;
  1342. if (rrpriv->fw_running){
  1343. printk("%s: Firmware already running\n", dev->name);
  1344. error = -EPERM;
  1345. goto gf_out;
  1346. }
  1347. spin_lock_irqsave(&rrpriv->lock, flags);
  1348. i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1349. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1350. if (i != EEPROM_BYTES){
  1351. printk(KERN_ERR "%s: Error reading EEPROM\n",
  1352. dev->name);
  1353. error = -EFAULT;
  1354. goto gf_out;
  1355. }
  1356. error = copy_to_user(rq->ifr_data, image, EEPROM_BYTES);
  1357. if (error)
  1358. error = -EFAULT;
  1359. gf_out:
  1360. kfree(image);
  1361. return error;
  1362. case SIOCRRPFW:
  1363. if (!capable(CAP_SYS_RAWIO)){
  1364. return -EPERM;
  1365. }
  1366. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1367. oldimage = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1368. if (!image || !oldimage) {
  1369. error = -ENOMEM;
  1370. goto wf_out;
  1371. }
  1372. error = copy_from_user(image, rq->ifr_data, EEPROM_BYTES);
  1373. if (error) {
  1374. error = -EFAULT;
  1375. goto wf_out;
  1376. }
  1377. if (rrpriv->fw_running){
  1378. printk("%s: Firmware already running\n", dev->name);
  1379. error = -EPERM;
  1380. goto wf_out;
  1381. }
  1382. printk("%s: Updating EEPROM firmware\n", dev->name);
  1383. spin_lock_irqsave(&rrpriv->lock, flags);
  1384. error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1385. if (error)
  1386. printk(KERN_ERR "%s: Error writing EEPROM\n",
  1387. dev->name);
  1388. i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
  1389. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1390. if (i != EEPROM_BYTES)
  1391. printk(KERN_ERR "%s: Error reading back EEPROM "
  1392. "image\n", dev->name);
  1393. error = memcmp(image, oldimage, EEPROM_BYTES);
  1394. if (error){
  1395. printk(KERN_ERR "%s: Error verifying EEPROM image\n",
  1396. dev->name);
  1397. error = -EFAULT;
  1398. }
  1399. wf_out:
  1400. kfree(oldimage);
  1401. kfree(image);
  1402. return error;
  1403. case SIOCRRID:
  1404. return put_user(0x52523032, (int __user *)rq->ifr_data);
  1405. default:
  1406. return error;
  1407. }
  1408. }
  1409. static DEFINE_PCI_DEVICE_TABLE(rr_pci_tbl) = {
  1410. { PCI_VENDOR_ID_ESSENTIAL, PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER,
  1411. PCI_ANY_ID, PCI_ANY_ID, },
  1412. { 0,}
  1413. };
  1414. MODULE_DEVICE_TABLE(pci, rr_pci_tbl);
  1415. static struct pci_driver rr_driver = {
  1416. .name = "rrunner",
  1417. .id_table = rr_pci_tbl,
  1418. .probe = rr_init_one,
  1419. .remove = rr_remove_one,
  1420. };
  1421. static int __init rr_init_module(void)
  1422. {
  1423. return pci_register_driver(&rr_driver);
  1424. }
  1425. static void __exit rr_cleanup_module(void)
  1426. {
  1427. pci_unregister_driver(&rr_driver);
  1428. }
  1429. module_init(rr_init_module);
  1430. module_exit(rr_cleanup_module);