rx.c 22 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2011 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/socket.h>
  11. #include <linux/in.h>
  12. #include <linux/slab.h>
  13. #include <linux/ip.h>
  14. #include <linux/tcp.h>
  15. #include <linux/udp.h>
  16. #include <linux/prefetch.h>
  17. #include <linux/moduleparam.h>
  18. #include <net/ip.h>
  19. #include <net/checksum.h>
  20. #include "net_driver.h"
  21. #include "efx.h"
  22. #include "nic.h"
  23. #include "selftest.h"
  24. #include "workarounds.h"
  25. /* Number of RX descriptors pushed at once. */
  26. #define EFX_RX_BATCH 8
  27. /* Maximum size of a buffer sharing a page */
  28. #define EFX_RX_HALF_PAGE ((PAGE_SIZE >> 1) - sizeof(struct efx_rx_page_state))
  29. /* Size of buffer allocated for skb header area. */
  30. #define EFX_SKB_HEADERS 64u
  31. /*
  32. * rx_alloc_method - RX buffer allocation method
  33. *
  34. * This driver supports two methods for allocating and using RX buffers:
  35. * each RX buffer may be backed by an skb or by an order-n page.
  36. *
  37. * When GRO is in use then the second method has a lower overhead,
  38. * since we don't have to allocate then free skbs on reassembled frames.
  39. *
  40. * Values:
  41. * - RX_ALLOC_METHOD_AUTO = 0
  42. * - RX_ALLOC_METHOD_SKB = 1
  43. * - RX_ALLOC_METHOD_PAGE = 2
  44. *
  45. * The heuristic for %RX_ALLOC_METHOD_AUTO is a simple hysteresis count
  46. * controlled by the parameters below.
  47. *
  48. * - Since pushing and popping descriptors are separated by the rx_queue
  49. * size, so the watermarks should be ~rxd_size.
  50. * - The performance win by using page-based allocation for GRO is less
  51. * than the performance hit of using page-based allocation of non-GRO,
  52. * so the watermarks should reflect this.
  53. *
  54. * Per channel we maintain a single variable, updated by each channel:
  55. *
  56. * rx_alloc_level += (gro_performed ? RX_ALLOC_FACTOR_GRO :
  57. * RX_ALLOC_FACTOR_SKB)
  58. * Per NAPI poll interval, we constrain rx_alloc_level to 0..MAX (which
  59. * limits the hysteresis), and update the allocation strategy:
  60. *
  61. * rx_alloc_method = (rx_alloc_level > RX_ALLOC_LEVEL_GRO ?
  62. * RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB)
  63. */
  64. static int rx_alloc_method = RX_ALLOC_METHOD_AUTO;
  65. #define RX_ALLOC_LEVEL_GRO 0x2000
  66. #define RX_ALLOC_LEVEL_MAX 0x3000
  67. #define RX_ALLOC_FACTOR_GRO 1
  68. #define RX_ALLOC_FACTOR_SKB (-2)
  69. /* This is the percentage fill level below which new RX descriptors
  70. * will be added to the RX descriptor ring.
  71. */
  72. static unsigned int rx_refill_threshold;
  73. /*
  74. * RX maximum head room required.
  75. *
  76. * This must be at least 1 to prevent overflow and at least 2 to allow
  77. * pipelined receives.
  78. */
  79. #define EFX_RXD_HEAD_ROOM 2
  80. /* Offset of ethernet header within page */
  81. static inline unsigned int efx_rx_buf_offset(struct efx_nic *efx,
  82. struct efx_rx_buffer *buf)
  83. {
  84. /* Offset is always within one page, so we don't need to consider
  85. * the page order.
  86. */
  87. return ((unsigned int) buf->dma_addr & (PAGE_SIZE - 1)) +
  88. efx->type->rx_buffer_hash_size;
  89. }
  90. static inline unsigned int efx_rx_buf_size(struct efx_nic *efx)
  91. {
  92. return PAGE_SIZE << efx->rx_buffer_order;
  93. }
  94. static u8 *efx_rx_buf_eh(struct efx_nic *efx, struct efx_rx_buffer *buf)
  95. {
  96. if (buf->flags & EFX_RX_BUF_PAGE)
  97. return page_address(buf->u.page) + efx_rx_buf_offset(efx, buf);
  98. else
  99. return (u8 *)buf->u.skb->data + efx->type->rx_buffer_hash_size;
  100. }
  101. static inline u32 efx_rx_buf_hash(const u8 *eh)
  102. {
  103. /* The ethernet header is always directly after any hash. */
  104. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) || NET_IP_ALIGN % 4 == 0
  105. return __le32_to_cpup((const __le32 *)(eh - 4));
  106. #else
  107. const u8 *data = eh - 4;
  108. return (u32)data[0] |
  109. (u32)data[1] << 8 |
  110. (u32)data[2] << 16 |
  111. (u32)data[3] << 24;
  112. #endif
  113. }
  114. /**
  115. * efx_init_rx_buffers_skb - create EFX_RX_BATCH skb-based RX buffers
  116. *
  117. * @rx_queue: Efx RX queue
  118. *
  119. * This allocates EFX_RX_BATCH skbs, maps them for DMA, and populates a
  120. * struct efx_rx_buffer for each one. Return a negative error code or 0
  121. * on success. May fail having only inserted fewer than EFX_RX_BATCH
  122. * buffers.
  123. */
  124. static int efx_init_rx_buffers_skb(struct efx_rx_queue *rx_queue)
  125. {
  126. struct efx_nic *efx = rx_queue->efx;
  127. struct net_device *net_dev = efx->net_dev;
  128. struct efx_rx_buffer *rx_buf;
  129. struct sk_buff *skb;
  130. int skb_len = efx->rx_buffer_len;
  131. unsigned index, count;
  132. for (count = 0; count < EFX_RX_BATCH; ++count) {
  133. index = rx_queue->added_count & rx_queue->ptr_mask;
  134. rx_buf = efx_rx_buffer(rx_queue, index);
  135. rx_buf->u.skb = skb = netdev_alloc_skb(net_dev, skb_len);
  136. if (unlikely(!skb))
  137. return -ENOMEM;
  138. /* Adjust the SKB for padding */
  139. skb_reserve(skb, NET_IP_ALIGN);
  140. rx_buf->len = skb_len - NET_IP_ALIGN;
  141. rx_buf->flags = 0;
  142. rx_buf->dma_addr = dma_map_single(&efx->pci_dev->dev,
  143. skb->data, rx_buf->len,
  144. DMA_FROM_DEVICE);
  145. if (unlikely(dma_mapping_error(&efx->pci_dev->dev,
  146. rx_buf->dma_addr))) {
  147. dev_kfree_skb_any(skb);
  148. rx_buf->u.skb = NULL;
  149. return -EIO;
  150. }
  151. ++rx_queue->added_count;
  152. ++rx_queue->alloc_skb_count;
  153. }
  154. return 0;
  155. }
  156. /**
  157. * efx_init_rx_buffers_page - create EFX_RX_BATCH page-based RX buffers
  158. *
  159. * @rx_queue: Efx RX queue
  160. *
  161. * This allocates memory for EFX_RX_BATCH receive buffers, maps them for DMA,
  162. * and populates struct efx_rx_buffers for each one. Return a negative error
  163. * code or 0 on success. If a single page can be split between two buffers,
  164. * then the page will either be inserted fully, or not at at all.
  165. */
  166. static int efx_init_rx_buffers_page(struct efx_rx_queue *rx_queue)
  167. {
  168. struct efx_nic *efx = rx_queue->efx;
  169. struct efx_rx_buffer *rx_buf;
  170. struct page *page;
  171. struct efx_rx_page_state *state;
  172. dma_addr_t dma_addr;
  173. unsigned index, count;
  174. /* We can split a page between two buffers */
  175. BUILD_BUG_ON(EFX_RX_BATCH & 1);
  176. for (count = 0; count < EFX_RX_BATCH; ++count) {
  177. page = alloc_pages(__GFP_COLD | __GFP_COMP | GFP_ATOMIC,
  178. efx->rx_buffer_order);
  179. if (unlikely(page == NULL))
  180. return -ENOMEM;
  181. dma_addr = dma_map_page(&efx->pci_dev->dev, page, 0,
  182. efx_rx_buf_size(efx),
  183. DMA_FROM_DEVICE);
  184. if (unlikely(dma_mapping_error(&efx->pci_dev->dev, dma_addr))) {
  185. __free_pages(page, efx->rx_buffer_order);
  186. return -EIO;
  187. }
  188. state = page_address(page);
  189. state->refcnt = 0;
  190. state->dma_addr = dma_addr;
  191. dma_addr += sizeof(struct efx_rx_page_state);
  192. split:
  193. index = rx_queue->added_count & rx_queue->ptr_mask;
  194. rx_buf = efx_rx_buffer(rx_queue, index);
  195. rx_buf->dma_addr = dma_addr + EFX_PAGE_IP_ALIGN;
  196. rx_buf->u.page = page;
  197. rx_buf->len = efx->rx_buffer_len - EFX_PAGE_IP_ALIGN;
  198. rx_buf->flags = EFX_RX_BUF_PAGE;
  199. ++rx_queue->added_count;
  200. ++rx_queue->alloc_page_count;
  201. ++state->refcnt;
  202. if ((~count & 1) && (efx->rx_buffer_len <= EFX_RX_HALF_PAGE)) {
  203. /* Use the second half of the page */
  204. get_page(page);
  205. dma_addr += (PAGE_SIZE >> 1);
  206. ++count;
  207. goto split;
  208. }
  209. }
  210. return 0;
  211. }
  212. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  213. struct efx_rx_buffer *rx_buf)
  214. {
  215. if ((rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.page) {
  216. struct efx_rx_page_state *state;
  217. state = page_address(rx_buf->u.page);
  218. if (--state->refcnt == 0) {
  219. dma_unmap_page(&efx->pci_dev->dev,
  220. state->dma_addr,
  221. efx_rx_buf_size(efx),
  222. DMA_FROM_DEVICE);
  223. }
  224. } else if (!(rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.skb) {
  225. dma_unmap_single(&efx->pci_dev->dev, rx_buf->dma_addr,
  226. rx_buf->len, DMA_FROM_DEVICE);
  227. }
  228. }
  229. static void efx_free_rx_buffer(struct efx_nic *efx,
  230. struct efx_rx_buffer *rx_buf)
  231. {
  232. if ((rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.page) {
  233. __free_pages(rx_buf->u.page, efx->rx_buffer_order);
  234. rx_buf->u.page = NULL;
  235. } else if (!(rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.skb) {
  236. dev_kfree_skb_any(rx_buf->u.skb);
  237. rx_buf->u.skb = NULL;
  238. }
  239. }
  240. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  241. struct efx_rx_buffer *rx_buf)
  242. {
  243. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  244. efx_free_rx_buffer(rx_queue->efx, rx_buf);
  245. }
  246. /* Attempt to resurrect the other receive buffer that used to share this page,
  247. * which had previously been passed up to the kernel and freed. */
  248. static void efx_resurrect_rx_buffer(struct efx_rx_queue *rx_queue,
  249. struct efx_rx_buffer *rx_buf)
  250. {
  251. struct efx_rx_page_state *state = page_address(rx_buf->u.page);
  252. struct efx_rx_buffer *new_buf;
  253. unsigned fill_level, index;
  254. /* +1 because efx_rx_packet() incremented removed_count. +1 because
  255. * we'd like to insert an additional descriptor whilst leaving
  256. * EFX_RXD_HEAD_ROOM for the non-recycle path */
  257. fill_level = (rx_queue->added_count - rx_queue->removed_count + 2);
  258. if (unlikely(fill_level > rx_queue->max_fill)) {
  259. /* We could place "state" on a list, and drain the list in
  260. * efx_fast_push_rx_descriptors(). For now, this will do. */
  261. return;
  262. }
  263. ++state->refcnt;
  264. get_page(rx_buf->u.page);
  265. index = rx_queue->added_count & rx_queue->ptr_mask;
  266. new_buf = efx_rx_buffer(rx_queue, index);
  267. new_buf->dma_addr = rx_buf->dma_addr ^ (PAGE_SIZE >> 1);
  268. new_buf->u.page = rx_buf->u.page;
  269. new_buf->len = rx_buf->len;
  270. new_buf->flags = EFX_RX_BUF_PAGE;
  271. ++rx_queue->added_count;
  272. }
  273. /* Recycle the given rx buffer directly back into the rx_queue. There is
  274. * always room to add this buffer, because we've just popped a buffer. */
  275. static void efx_recycle_rx_buffer(struct efx_channel *channel,
  276. struct efx_rx_buffer *rx_buf)
  277. {
  278. struct efx_nic *efx = channel->efx;
  279. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  280. struct efx_rx_buffer *new_buf;
  281. unsigned index;
  282. rx_buf->flags &= EFX_RX_BUF_PAGE;
  283. if ((rx_buf->flags & EFX_RX_BUF_PAGE) &&
  284. efx->rx_buffer_len <= EFX_RX_HALF_PAGE &&
  285. page_count(rx_buf->u.page) == 1)
  286. efx_resurrect_rx_buffer(rx_queue, rx_buf);
  287. index = rx_queue->added_count & rx_queue->ptr_mask;
  288. new_buf = efx_rx_buffer(rx_queue, index);
  289. memcpy(new_buf, rx_buf, sizeof(*new_buf));
  290. rx_buf->u.page = NULL;
  291. ++rx_queue->added_count;
  292. }
  293. /**
  294. * efx_fast_push_rx_descriptors - push new RX descriptors quickly
  295. * @rx_queue: RX descriptor queue
  296. *
  297. * This will aim to fill the RX descriptor queue up to
  298. * @rx_queue->@max_fill. If there is insufficient atomic
  299. * memory to do so, a slow fill will be scheduled.
  300. *
  301. * The caller must provide serialisation (none is used here). In practise,
  302. * this means this function must run from the NAPI handler, or be called
  303. * when NAPI is disabled.
  304. */
  305. void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue)
  306. {
  307. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  308. unsigned fill_level;
  309. int space, rc = 0;
  310. /* Calculate current fill level, and exit if we don't need to fill */
  311. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  312. EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  313. if (fill_level >= rx_queue->fast_fill_trigger)
  314. goto out;
  315. /* Record minimum fill level */
  316. if (unlikely(fill_level < rx_queue->min_fill)) {
  317. if (fill_level)
  318. rx_queue->min_fill = fill_level;
  319. }
  320. space = rx_queue->max_fill - fill_level;
  321. EFX_BUG_ON_PARANOID(space < EFX_RX_BATCH);
  322. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  323. "RX queue %d fast-filling descriptor ring from"
  324. " level %d to level %d using %s allocation\n",
  325. efx_rx_queue_index(rx_queue), fill_level,
  326. rx_queue->max_fill,
  327. channel->rx_alloc_push_pages ? "page" : "skb");
  328. do {
  329. if (channel->rx_alloc_push_pages)
  330. rc = efx_init_rx_buffers_page(rx_queue);
  331. else
  332. rc = efx_init_rx_buffers_skb(rx_queue);
  333. if (unlikely(rc)) {
  334. /* Ensure that we don't leave the rx queue empty */
  335. if (rx_queue->added_count == rx_queue->removed_count)
  336. efx_schedule_slow_fill(rx_queue);
  337. goto out;
  338. }
  339. } while ((space -= EFX_RX_BATCH) >= EFX_RX_BATCH);
  340. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  341. "RX queue %d fast-filled descriptor ring "
  342. "to level %d\n", efx_rx_queue_index(rx_queue),
  343. rx_queue->added_count - rx_queue->removed_count);
  344. out:
  345. if (rx_queue->notified_count != rx_queue->added_count)
  346. efx_nic_notify_rx_desc(rx_queue);
  347. }
  348. void efx_rx_slow_fill(unsigned long context)
  349. {
  350. struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
  351. /* Post an event to cause NAPI to run and refill the queue */
  352. efx_nic_generate_fill_event(rx_queue);
  353. ++rx_queue->slow_fill_count;
  354. }
  355. static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  356. struct efx_rx_buffer *rx_buf,
  357. int len, bool *leak_packet)
  358. {
  359. struct efx_nic *efx = rx_queue->efx;
  360. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  361. if (likely(len <= max_len))
  362. return;
  363. /* The packet must be discarded, but this is only a fatal error
  364. * if the caller indicated it was
  365. */
  366. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  367. if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
  368. if (net_ratelimit())
  369. netif_err(efx, rx_err, efx->net_dev,
  370. " RX queue %d seriously overlength "
  371. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  372. efx_rx_queue_index(rx_queue), len, max_len,
  373. efx->type->rx_buffer_padding);
  374. /* If this buffer was skb-allocated, then the meta
  375. * data at the end of the skb will be trashed. So
  376. * we have no choice but to leak the fragment.
  377. */
  378. *leak_packet = !(rx_buf->flags & EFX_RX_BUF_PAGE);
  379. efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  380. } else {
  381. if (net_ratelimit())
  382. netif_err(efx, rx_err, efx->net_dev,
  383. " RX queue %d overlength RX event "
  384. "(0x%x > 0x%x)\n",
  385. efx_rx_queue_index(rx_queue), len, max_len);
  386. }
  387. efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
  388. }
  389. /* Pass a received packet up through GRO. GRO can handle pages
  390. * regardless of checksum state and skbs with a good checksum.
  391. */
  392. static void efx_rx_packet_gro(struct efx_channel *channel,
  393. struct efx_rx_buffer *rx_buf,
  394. const u8 *eh)
  395. {
  396. struct napi_struct *napi = &channel->napi_str;
  397. gro_result_t gro_result;
  398. if (rx_buf->flags & EFX_RX_BUF_PAGE) {
  399. struct efx_nic *efx = channel->efx;
  400. struct page *page = rx_buf->u.page;
  401. struct sk_buff *skb;
  402. rx_buf->u.page = NULL;
  403. skb = napi_get_frags(napi);
  404. if (!skb) {
  405. put_page(page);
  406. return;
  407. }
  408. if (efx->net_dev->features & NETIF_F_RXHASH)
  409. skb->rxhash = efx_rx_buf_hash(eh);
  410. skb_fill_page_desc(skb, 0, page,
  411. efx_rx_buf_offset(efx, rx_buf), rx_buf->len);
  412. skb->len = rx_buf->len;
  413. skb->data_len = rx_buf->len;
  414. skb->truesize += rx_buf->len;
  415. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  416. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  417. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  418. gro_result = napi_gro_frags(napi);
  419. } else {
  420. struct sk_buff *skb = rx_buf->u.skb;
  421. EFX_BUG_ON_PARANOID(!(rx_buf->flags & EFX_RX_PKT_CSUMMED));
  422. rx_buf->u.skb = NULL;
  423. skb->ip_summed = CHECKSUM_UNNECESSARY;
  424. gro_result = napi_gro_receive(napi, skb);
  425. }
  426. if (gro_result == GRO_NORMAL) {
  427. channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
  428. } else if (gro_result != GRO_DROP) {
  429. channel->rx_alloc_level += RX_ALLOC_FACTOR_GRO;
  430. channel->irq_mod_score += 2;
  431. }
  432. }
  433. void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
  434. unsigned int len, u16 flags)
  435. {
  436. struct efx_nic *efx = rx_queue->efx;
  437. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  438. struct efx_rx_buffer *rx_buf;
  439. bool leak_packet = false;
  440. rx_buf = efx_rx_buffer(rx_queue, index);
  441. rx_buf->flags |= flags;
  442. /* This allows the refill path to post another buffer.
  443. * EFX_RXD_HEAD_ROOM ensures that the slot we are using
  444. * isn't overwritten yet.
  445. */
  446. rx_queue->removed_count++;
  447. /* Validate the length encoded in the event vs the descriptor pushed */
  448. efx_rx_packet__check_len(rx_queue, rx_buf, len, &leak_packet);
  449. netif_vdbg(efx, rx_status, efx->net_dev,
  450. "RX queue %d received id %x at %llx+%x %s%s\n",
  451. efx_rx_queue_index(rx_queue), index,
  452. (unsigned long long)rx_buf->dma_addr, len,
  453. (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
  454. (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : "");
  455. /* Discard packet, if instructed to do so */
  456. if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) {
  457. if (unlikely(leak_packet))
  458. channel->n_skbuff_leaks++;
  459. else
  460. efx_recycle_rx_buffer(channel, rx_buf);
  461. /* Don't hold off the previous receive */
  462. rx_buf = NULL;
  463. goto out;
  464. }
  465. /* Release card resources - assumes all RX buffers consumed in-order
  466. * per RX queue
  467. */
  468. efx_unmap_rx_buffer(efx, rx_buf);
  469. /* Prefetch nice and early so data will (hopefully) be in cache by
  470. * the time we look at it.
  471. */
  472. prefetch(efx_rx_buf_eh(efx, rx_buf));
  473. /* Pipeline receives so that we give time for packet headers to be
  474. * prefetched into cache.
  475. */
  476. rx_buf->len = len - efx->type->rx_buffer_hash_size;
  477. out:
  478. if (channel->rx_pkt)
  479. __efx_rx_packet(channel, channel->rx_pkt);
  480. channel->rx_pkt = rx_buf;
  481. }
  482. static void efx_rx_deliver(struct efx_channel *channel,
  483. struct efx_rx_buffer *rx_buf)
  484. {
  485. struct sk_buff *skb;
  486. /* We now own the SKB */
  487. skb = rx_buf->u.skb;
  488. rx_buf->u.skb = NULL;
  489. /* Set the SKB flags */
  490. skb_checksum_none_assert(skb);
  491. /* Record the rx_queue */
  492. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  493. /* Pass the packet up */
  494. if (channel->type->receive_skb)
  495. channel->type->receive_skb(channel, skb);
  496. else
  497. netif_receive_skb(skb);
  498. /* Update allocation strategy method */
  499. channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
  500. }
  501. /* Handle a received packet. Second half: Touches packet payload. */
  502. void __efx_rx_packet(struct efx_channel *channel, struct efx_rx_buffer *rx_buf)
  503. {
  504. struct efx_nic *efx = channel->efx;
  505. u8 *eh = efx_rx_buf_eh(efx, rx_buf);
  506. /* If we're in loopback test, then pass the packet directly to the
  507. * loopback layer, and free the rx_buf here
  508. */
  509. if (unlikely(efx->loopback_selftest)) {
  510. efx_loopback_rx_packet(efx, eh, rx_buf->len);
  511. efx_free_rx_buffer(efx, rx_buf);
  512. return;
  513. }
  514. if (!(rx_buf->flags & EFX_RX_BUF_PAGE)) {
  515. struct sk_buff *skb = rx_buf->u.skb;
  516. prefetch(skb_shinfo(skb));
  517. skb_reserve(skb, efx->type->rx_buffer_hash_size);
  518. skb_put(skb, rx_buf->len);
  519. if (efx->net_dev->features & NETIF_F_RXHASH)
  520. skb->rxhash = efx_rx_buf_hash(eh);
  521. /* Move past the ethernet header. rx_buf->data still points
  522. * at the ethernet header */
  523. skb->protocol = eth_type_trans(skb, efx->net_dev);
  524. skb_record_rx_queue(skb, channel->rx_queue.core_index);
  525. }
  526. if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
  527. rx_buf->flags &= ~EFX_RX_PKT_CSUMMED;
  528. if (likely(rx_buf->flags & (EFX_RX_BUF_PAGE | EFX_RX_PKT_CSUMMED)) &&
  529. !channel->type->receive_skb)
  530. efx_rx_packet_gro(channel, rx_buf, eh);
  531. else
  532. efx_rx_deliver(channel, rx_buf);
  533. }
  534. void efx_rx_strategy(struct efx_channel *channel)
  535. {
  536. enum efx_rx_alloc_method method = rx_alloc_method;
  537. if (channel->type->receive_skb) {
  538. channel->rx_alloc_push_pages = false;
  539. return;
  540. }
  541. /* Only makes sense to use page based allocation if GRO is enabled */
  542. if (!(channel->efx->net_dev->features & NETIF_F_GRO)) {
  543. method = RX_ALLOC_METHOD_SKB;
  544. } else if (method == RX_ALLOC_METHOD_AUTO) {
  545. /* Constrain the rx_alloc_level */
  546. if (channel->rx_alloc_level < 0)
  547. channel->rx_alloc_level = 0;
  548. else if (channel->rx_alloc_level > RX_ALLOC_LEVEL_MAX)
  549. channel->rx_alloc_level = RX_ALLOC_LEVEL_MAX;
  550. /* Decide on the allocation method */
  551. method = ((channel->rx_alloc_level > RX_ALLOC_LEVEL_GRO) ?
  552. RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB);
  553. }
  554. /* Push the option */
  555. channel->rx_alloc_push_pages = (method == RX_ALLOC_METHOD_PAGE);
  556. }
  557. int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
  558. {
  559. struct efx_nic *efx = rx_queue->efx;
  560. unsigned int entries;
  561. int rc;
  562. /* Create the smallest power-of-two aligned ring */
  563. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  564. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  565. rx_queue->ptr_mask = entries - 1;
  566. netif_dbg(efx, probe, efx->net_dev,
  567. "creating RX queue %d size %#x mask %#x\n",
  568. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  569. rx_queue->ptr_mask);
  570. /* Allocate RX buffers */
  571. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  572. GFP_KERNEL);
  573. if (!rx_queue->buffer)
  574. return -ENOMEM;
  575. rc = efx_nic_probe_rx(rx_queue);
  576. if (rc) {
  577. kfree(rx_queue->buffer);
  578. rx_queue->buffer = NULL;
  579. }
  580. return rc;
  581. }
  582. void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
  583. {
  584. struct efx_nic *efx = rx_queue->efx;
  585. unsigned int max_fill, trigger, max_trigger;
  586. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  587. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  588. /* Initialise ptr fields */
  589. rx_queue->added_count = 0;
  590. rx_queue->notified_count = 0;
  591. rx_queue->removed_count = 0;
  592. rx_queue->min_fill = -1U;
  593. /* Initialise limit fields */
  594. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  595. max_trigger = max_fill - EFX_RX_BATCH;
  596. if (rx_refill_threshold != 0) {
  597. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  598. if (trigger > max_trigger)
  599. trigger = max_trigger;
  600. } else {
  601. trigger = max_trigger;
  602. }
  603. rx_queue->max_fill = max_fill;
  604. rx_queue->fast_fill_trigger = trigger;
  605. /* Set up RX descriptor ring */
  606. rx_queue->enabled = true;
  607. efx_nic_init_rx(rx_queue);
  608. }
  609. void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
  610. {
  611. int i;
  612. struct efx_rx_buffer *rx_buf;
  613. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  614. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  615. /* A flush failure might have left rx_queue->enabled */
  616. rx_queue->enabled = false;
  617. del_timer_sync(&rx_queue->slow_fill);
  618. efx_nic_fini_rx(rx_queue);
  619. /* Release RX buffers NB start at index 0 not current HW ptr */
  620. if (rx_queue->buffer) {
  621. for (i = 0; i <= rx_queue->ptr_mask; i++) {
  622. rx_buf = efx_rx_buffer(rx_queue, i);
  623. efx_fini_rx_buffer(rx_queue, rx_buf);
  624. }
  625. }
  626. }
  627. void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
  628. {
  629. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  630. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  631. efx_nic_remove_rx(rx_queue);
  632. kfree(rx_queue->buffer);
  633. rx_queue->buffer = NULL;
  634. }
  635. module_param(rx_alloc_method, int, 0644);
  636. MODULE_PARM_DESC(rx_alloc_method, "Allocation method used for RX buffers");
  637. module_param(rx_refill_threshold, uint, 0444);
  638. MODULE_PARM_DESC(rx_refill_threshold,
  639. "RX descriptor ring refill threshold (%)");