xgmac.c 55 KB

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  1. /*
  2. * Copyright 2010-2011 Calxeda, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/circ_buf.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/etherdevice.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/skbuff.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/if.h>
  26. #include <linux/crc32.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/slab.h>
  29. /* XGMAC Register definitions */
  30. #define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
  31. #define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */
  32. #define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */
  33. #define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */
  34. #define XGMAC_VERSION 0x00000020 /* Version */
  35. #define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */
  36. #define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */
  37. #define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */
  38. #define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */
  39. #define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */
  40. #define XGMAC_DEBUG 0x00000038 /* Debug */
  41. #define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */
  42. #define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8))
  43. #define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8))
  44. #define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */
  45. #define XGMAC_NUM_HASH 16
  46. #define XGMAC_OMR 0x00000400
  47. #define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
  48. #define XGMAC_PMT 0x00000704 /* PMT Control and Status */
  49. #define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
  50. #define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
  51. #define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
  52. #define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
  53. #define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
  54. /* Hardware TX Statistics Counters */
  55. #define XGMAC_MMC_TXOCTET_GB_LO 0x00000814
  56. #define XGMAC_MMC_TXOCTET_GB_HI 0x00000818
  57. #define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C
  58. #define XGMAC_MMC_TXFRAME_GB_HI 0x00000820
  59. #define XGMAC_MMC_TXBCFRAME_G 0x00000824
  60. #define XGMAC_MMC_TXMCFRAME_G 0x0000082C
  61. #define XGMAC_MMC_TXUCFRAME_GB 0x00000864
  62. #define XGMAC_MMC_TXMCFRAME_GB 0x0000086C
  63. #define XGMAC_MMC_TXBCFRAME_GB 0x00000874
  64. #define XGMAC_MMC_TXUNDERFLOW 0x0000087C
  65. #define XGMAC_MMC_TXOCTET_G_LO 0x00000884
  66. #define XGMAC_MMC_TXOCTET_G_HI 0x00000888
  67. #define XGMAC_MMC_TXFRAME_G_LO 0x0000088C
  68. #define XGMAC_MMC_TXFRAME_G_HI 0x00000890
  69. #define XGMAC_MMC_TXPAUSEFRAME 0x00000894
  70. #define XGMAC_MMC_TXVLANFRAME 0x0000089C
  71. /* Hardware RX Statistics Counters */
  72. #define XGMAC_MMC_RXFRAME_GB_LO 0x00000900
  73. #define XGMAC_MMC_RXFRAME_GB_HI 0x00000904
  74. #define XGMAC_MMC_RXOCTET_GB_LO 0x00000908
  75. #define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C
  76. #define XGMAC_MMC_RXOCTET_G_LO 0x00000910
  77. #define XGMAC_MMC_RXOCTET_G_HI 0x00000914
  78. #define XGMAC_MMC_RXBCFRAME_G 0x00000918
  79. #define XGMAC_MMC_RXMCFRAME_G 0x00000920
  80. #define XGMAC_MMC_RXCRCERR 0x00000928
  81. #define XGMAC_MMC_RXRUNT 0x00000930
  82. #define XGMAC_MMC_RXJABBER 0x00000934
  83. #define XGMAC_MMC_RXUCFRAME_G 0x00000970
  84. #define XGMAC_MMC_RXLENGTHERR 0x00000978
  85. #define XGMAC_MMC_RXPAUSEFRAME 0x00000988
  86. #define XGMAC_MMC_RXOVERFLOW 0x00000990
  87. #define XGMAC_MMC_RXVLANFRAME 0x00000998
  88. #define XGMAC_MMC_RXWATCHDOG 0x000009a0
  89. /* DMA Control and Status Registers */
  90. #define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */
  91. #define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */
  92. #define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */
  93. #define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */
  94. #define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */
  95. #define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */
  96. #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
  97. #define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
  98. #define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */
  99. #define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */
  100. #define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */
  101. #define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */
  102. #define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
  103. #define XGMAC_ADDR_AE 0x80000000
  104. #define XGMAC_MAX_FILTER_ADDR 31
  105. /* PMT Control and Status */
  106. #define XGMAC_PMT_POINTER_RESET 0x80000000
  107. #define XGMAC_PMT_GLBL_UNICAST 0x00000200
  108. #define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040
  109. #define XGMAC_PMT_MAGIC_PKT 0x00000020
  110. #define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004
  111. #define XGMAC_PMT_MAGIC_PKT_EN 0x00000002
  112. #define XGMAC_PMT_POWERDOWN 0x00000001
  113. #define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */
  114. #define XGMAC_CONTROL_SPD_MASK 0x60000000
  115. #define XGMAC_CONTROL_SPD_1G 0x60000000
  116. #define XGMAC_CONTROL_SPD_2_5G 0x40000000
  117. #define XGMAC_CONTROL_SPD_10G 0x00000000
  118. #define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */
  119. #define XGMAC_CONTROL_SARK_MASK 0x18000000
  120. #define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */
  121. #define XGMAC_CONTROL_CAR_MASK 0x06000000
  122. #define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */
  123. #define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */
  124. #define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */
  125. #define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
  126. #define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
  127. #define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
  128. #define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */
  129. #define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */
  130. #define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
  131. #define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
  132. /* XGMAC Frame Filter defines */
  133. #define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
  134. #define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
  135. #define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
  136. #define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
  137. #define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
  138. #define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
  139. #define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
  140. #define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
  141. #define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
  142. #define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */
  143. #define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */
  144. #define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
  145. /* XGMAC FLOW CTRL defines */
  146. #define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
  147. #define XGMAC_FLOW_CTRL_PT_SHIFT 16
  148. #define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
  149. #define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
  150. #define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
  151. #define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
  152. #define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
  153. #define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
  154. #define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
  155. /* XGMAC_INT_STAT reg */
  156. #define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */
  157. #define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */
  158. /* DMA Bus Mode register defines */
  159. #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
  160. #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
  161. #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
  162. #define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
  163. /* Programmable burst length */
  164. #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
  165. #define DMA_BUS_MODE_PBL_SHIFT 8
  166. #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
  167. #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
  168. #define DMA_BUS_MODE_RPBL_SHIFT 17
  169. #define DMA_BUS_MODE_USP 0x00800000
  170. #define DMA_BUS_MODE_8PBL 0x01000000
  171. #define DMA_BUS_MODE_AAL 0x02000000
  172. /* DMA Bus Mode register defines */
  173. #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
  174. #define DMA_BUS_PR_RATIO_SHIFT 14
  175. #define DMA_BUS_FB 0x00010000 /* Fixed Burst */
  176. /* DMA Control register defines */
  177. #define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
  178. #define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
  179. #define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
  180. #define DMA_CONTROL_OSF 0x00000004 /* Operate on 2nd tx frame */
  181. /* DMA Normal interrupt */
  182. #define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
  183. #define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
  184. #define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
  185. #define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
  186. #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
  187. #define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
  188. #define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
  189. #define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
  190. #define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
  191. #define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
  192. #define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
  193. #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
  194. #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */
  195. #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
  196. #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
  197. #define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
  198. DMA_INTR_ENA_TUE | DMA_INTR_ENA_TIE)
  199. #define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
  200. DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
  201. DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
  202. DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
  203. DMA_INTR_ENA_TSE)
  204. /* DMA default interrupt mask */
  205. #define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
  206. /* DMA Status register defines */
  207. #define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
  208. #define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
  209. #define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
  210. #define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
  211. #define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
  212. #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
  213. #define DMA_STATUS_TS_SHIFT 20
  214. #define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
  215. #define DMA_STATUS_RS_SHIFT 17
  216. #define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
  217. #define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
  218. #define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
  219. #define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
  220. #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
  221. #define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
  222. #define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
  223. #define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
  224. #define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
  225. #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
  226. #define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
  227. #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
  228. #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */
  229. #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
  230. #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
  231. /* Common MAC defines */
  232. #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
  233. #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
  234. /* XGMAC Operation Mode Register */
  235. #define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */
  236. #define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */
  237. #define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */
  238. #define XGMAC_OMR_TTC_MASK 0x00030000
  239. #define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */
  240. #define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */
  241. #define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */
  242. #define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */
  243. #define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */
  244. #define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */
  245. #define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */
  246. #define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */
  247. #define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */
  248. #define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */
  249. /* XGMAC HW Features Register */
  250. #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */
  251. #define XGMAC_MMC_CTRL_CNT_FRZ 0x00000008
  252. /* XGMAC Descriptor Defines */
  253. #define MAX_DESC_BUF_SZ (0x2000 - 8)
  254. #define RXDESC_EXT_STATUS 0x00000001
  255. #define RXDESC_CRC_ERR 0x00000002
  256. #define RXDESC_RX_ERR 0x00000008
  257. #define RXDESC_RX_WDOG 0x00000010
  258. #define RXDESC_FRAME_TYPE 0x00000020
  259. #define RXDESC_GIANT_FRAME 0x00000080
  260. #define RXDESC_LAST_SEG 0x00000100
  261. #define RXDESC_FIRST_SEG 0x00000200
  262. #define RXDESC_VLAN_FRAME 0x00000400
  263. #define RXDESC_OVERFLOW_ERR 0x00000800
  264. #define RXDESC_LENGTH_ERR 0x00001000
  265. #define RXDESC_SA_FILTER_FAIL 0x00002000
  266. #define RXDESC_DESCRIPTOR_ERR 0x00004000
  267. #define RXDESC_ERROR_SUMMARY 0x00008000
  268. #define RXDESC_FRAME_LEN_OFFSET 16
  269. #define RXDESC_FRAME_LEN_MASK 0x3fff0000
  270. #define RXDESC_DA_FILTER_FAIL 0x40000000
  271. #define RXDESC1_END_RING 0x00008000
  272. #define RXDESC_IP_PAYLOAD_MASK 0x00000003
  273. #define RXDESC_IP_PAYLOAD_UDP 0x00000001
  274. #define RXDESC_IP_PAYLOAD_TCP 0x00000002
  275. #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
  276. #define RXDESC_IP_HEADER_ERR 0x00000008
  277. #define RXDESC_IP_PAYLOAD_ERR 0x00000010
  278. #define RXDESC_IPV4_PACKET 0x00000040
  279. #define RXDESC_IPV6_PACKET 0x00000080
  280. #define TXDESC_UNDERFLOW_ERR 0x00000001
  281. #define TXDESC_JABBER_TIMEOUT 0x00000002
  282. #define TXDESC_LOCAL_FAULT 0x00000004
  283. #define TXDESC_REMOTE_FAULT 0x00000008
  284. #define TXDESC_VLAN_FRAME 0x00000010
  285. #define TXDESC_FRAME_FLUSHED 0x00000020
  286. #define TXDESC_IP_HEADER_ERR 0x00000040
  287. #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
  288. #define TXDESC_ERROR_SUMMARY 0x00008000
  289. #define TXDESC_SA_CTRL_INSERT 0x00040000
  290. #define TXDESC_SA_CTRL_REPLACE 0x00080000
  291. #define TXDESC_2ND_ADDR_CHAINED 0x00100000
  292. #define TXDESC_END_RING 0x00200000
  293. #define TXDESC_CSUM_IP 0x00400000
  294. #define TXDESC_CSUM_IP_PAYLD 0x00800000
  295. #define TXDESC_CSUM_ALL 0x00C00000
  296. #define TXDESC_CRC_EN_REPLACE 0x01000000
  297. #define TXDESC_CRC_EN_APPEND 0x02000000
  298. #define TXDESC_DISABLE_PAD 0x04000000
  299. #define TXDESC_FIRST_SEG 0x10000000
  300. #define TXDESC_LAST_SEG 0x20000000
  301. #define TXDESC_INTERRUPT 0x40000000
  302. #define DESC_OWN 0x80000000
  303. #define DESC_BUFFER1_SZ_MASK 0x00001fff
  304. #define DESC_BUFFER2_SZ_MASK 0x1fff0000
  305. #define DESC_BUFFER2_SZ_OFFSET 16
  306. struct xgmac_dma_desc {
  307. __le32 flags;
  308. __le32 buf_size;
  309. __le32 buf1_addr; /* Buffer 1 Address Pointer */
  310. __le32 buf2_addr; /* Buffer 2 Address Pointer */
  311. __le32 ext_status;
  312. __le32 res[3];
  313. };
  314. struct xgmac_extra_stats {
  315. /* Transmit errors */
  316. unsigned long tx_jabber;
  317. unsigned long tx_frame_flushed;
  318. unsigned long tx_payload_error;
  319. unsigned long tx_ip_header_error;
  320. unsigned long tx_local_fault;
  321. unsigned long tx_remote_fault;
  322. /* Receive errors */
  323. unsigned long rx_watchdog;
  324. unsigned long rx_da_filter_fail;
  325. unsigned long rx_sa_filter_fail;
  326. unsigned long rx_payload_error;
  327. unsigned long rx_ip_header_error;
  328. /* Tx/Rx IRQ errors */
  329. unsigned long tx_undeflow;
  330. unsigned long tx_process_stopped;
  331. unsigned long rx_buf_unav;
  332. unsigned long rx_process_stopped;
  333. unsigned long tx_early;
  334. unsigned long fatal_bus_error;
  335. };
  336. struct xgmac_priv {
  337. struct xgmac_dma_desc *dma_rx;
  338. struct sk_buff **rx_skbuff;
  339. unsigned int rx_tail;
  340. unsigned int rx_head;
  341. struct xgmac_dma_desc *dma_tx;
  342. struct sk_buff **tx_skbuff;
  343. unsigned int tx_head;
  344. unsigned int tx_tail;
  345. int tx_irq_cnt;
  346. void __iomem *base;
  347. unsigned int dma_buf_sz;
  348. dma_addr_t dma_rx_phy;
  349. dma_addr_t dma_tx_phy;
  350. struct net_device *dev;
  351. struct device *device;
  352. struct napi_struct napi;
  353. struct xgmac_extra_stats xstats;
  354. spinlock_t stats_lock;
  355. int pmt_irq;
  356. char rx_pause;
  357. char tx_pause;
  358. int wolopts;
  359. };
  360. /* XGMAC Configuration Settings */
  361. #define MAX_MTU 9000
  362. #define PAUSE_TIME 0x400
  363. #define DMA_RX_RING_SZ 256
  364. #define DMA_TX_RING_SZ 128
  365. /* minimum number of free TX descriptors required to wake up TX process */
  366. #define TX_THRESH (DMA_TX_RING_SZ/4)
  367. /* DMA descriptor ring helpers */
  368. #define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1))
  369. #define dma_ring_space(h, t, s) CIRC_SPACE(h, t, s)
  370. #define dma_ring_cnt(h, t, s) CIRC_CNT(h, t, s)
  371. /* XGMAC Descriptor Access Helpers */
  372. static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
  373. {
  374. if (buf_sz > MAX_DESC_BUF_SZ)
  375. p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
  376. (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
  377. else
  378. p->buf_size = cpu_to_le32(buf_sz);
  379. }
  380. static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
  381. {
  382. u32 len = cpu_to_le32(p->flags);
  383. return (len & DESC_BUFFER1_SZ_MASK) +
  384. ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
  385. }
  386. static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
  387. int buf_sz)
  388. {
  389. struct xgmac_dma_desc *end = p + ring_size - 1;
  390. memset(p, 0, sizeof(*p) * ring_size);
  391. for (; p <= end; p++)
  392. desc_set_buf_len(p, buf_sz);
  393. end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
  394. }
  395. static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
  396. {
  397. memset(p, 0, sizeof(*p) * ring_size);
  398. p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
  399. }
  400. static inline int desc_get_owner(struct xgmac_dma_desc *p)
  401. {
  402. return le32_to_cpu(p->flags) & DESC_OWN;
  403. }
  404. static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
  405. {
  406. /* Clear all fields and set the owner */
  407. p->flags = cpu_to_le32(DESC_OWN);
  408. }
  409. static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
  410. {
  411. u32 tmpflags = le32_to_cpu(p->flags);
  412. tmpflags &= TXDESC_END_RING;
  413. tmpflags |= flags | DESC_OWN;
  414. p->flags = cpu_to_le32(tmpflags);
  415. }
  416. static inline int desc_get_tx_ls(struct xgmac_dma_desc *p)
  417. {
  418. return le32_to_cpu(p->flags) & TXDESC_LAST_SEG;
  419. }
  420. static inline u32 desc_get_buf_addr(struct xgmac_dma_desc *p)
  421. {
  422. return le32_to_cpu(p->buf1_addr);
  423. }
  424. static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
  425. u32 paddr, int len)
  426. {
  427. p->buf1_addr = cpu_to_le32(paddr);
  428. if (len > MAX_DESC_BUF_SZ)
  429. p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
  430. }
  431. static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
  432. u32 paddr, int len)
  433. {
  434. desc_set_buf_len(p, len);
  435. desc_set_buf_addr(p, paddr, len);
  436. }
  437. static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
  438. {
  439. u32 data = le32_to_cpu(p->flags);
  440. u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
  441. if (data & RXDESC_FRAME_TYPE)
  442. len -= ETH_FCS_LEN;
  443. return len;
  444. }
  445. static void xgmac_dma_flush_tx_fifo(void __iomem *ioaddr)
  446. {
  447. int timeout = 1000;
  448. u32 reg = readl(ioaddr + XGMAC_OMR);
  449. writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR);
  450. while ((timeout-- > 0) && readl(ioaddr + XGMAC_OMR) & XGMAC_OMR_FTF)
  451. udelay(1);
  452. }
  453. static int desc_get_tx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p)
  454. {
  455. struct xgmac_extra_stats *x = &priv->xstats;
  456. u32 status = le32_to_cpu(p->flags);
  457. if (!(status & TXDESC_ERROR_SUMMARY))
  458. return 0;
  459. netdev_dbg(priv->dev, "tx desc error = 0x%08x\n", status);
  460. if (status & TXDESC_JABBER_TIMEOUT)
  461. x->tx_jabber++;
  462. if (status & TXDESC_FRAME_FLUSHED)
  463. x->tx_frame_flushed++;
  464. if (status & TXDESC_UNDERFLOW_ERR)
  465. xgmac_dma_flush_tx_fifo(priv->base);
  466. if (status & TXDESC_IP_HEADER_ERR)
  467. x->tx_ip_header_error++;
  468. if (status & TXDESC_LOCAL_FAULT)
  469. x->tx_local_fault++;
  470. if (status & TXDESC_REMOTE_FAULT)
  471. x->tx_remote_fault++;
  472. if (status & TXDESC_PAYLOAD_CSUM_ERR)
  473. x->tx_payload_error++;
  474. return -1;
  475. }
  476. static int desc_get_rx_status(struct xgmac_priv *priv, struct xgmac_dma_desc *p)
  477. {
  478. struct xgmac_extra_stats *x = &priv->xstats;
  479. int ret = CHECKSUM_UNNECESSARY;
  480. u32 status = le32_to_cpu(p->flags);
  481. u32 ext_status = le32_to_cpu(p->ext_status);
  482. if (status & RXDESC_DA_FILTER_FAIL) {
  483. netdev_dbg(priv->dev, "XGMAC RX : Dest Address filter fail\n");
  484. x->rx_da_filter_fail++;
  485. return -1;
  486. }
  487. /* Check if packet has checksum already */
  488. if ((status & RXDESC_FRAME_TYPE) && (status & RXDESC_EXT_STATUS) &&
  489. !(ext_status & RXDESC_IP_PAYLOAD_MASK))
  490. ret = CHECKSUM_NONE;
  491. netdev_dbg(priv->dev, "rx status - frame type=%d, csum = %d, ext stat %08x\n",
  492. (status & RXDESC_FRAME_TYPE) ? 1 : 0, ret, ext_status);
  493. if (!(status & RXDESC_ERROR_SUMMARY))
  494. return ret;
  495. /* Handle any errors */
  496. if (status & (RXDESC_DESCRIPTOR_ERR | RXDESC_OVERFLOW_ERR |
  497. RXDESC_GIANT_FRAME | RXDESC_LENGTH_ERR | RXDESC_CRC_ERR))
  498. return -1;
  499. if (status & RXDESC_EXT_STATUS) {
  500. if (ext_status & RXDESC_IP_HEADER_ERR)
  501. x->rx_ip_header_error++;
  502. if (ext_status & RXDESC_IP_PAYLOAD_ERR)
  503. x->rx_payload_error++;
  504. netdev_dbg(priv->dev, "IP checksum error - stat %08x\n",
  505. ext_status);
  506. return CHECKSUM_NONE;
  507. }
  508. return ret;
  509. }
  510. static inline void xgmac_mac_enable(void __iomem *ioaddr)
  511. {
  512. u32 value = readl(ioaddr + XGMAC_CONTROL);
  513. value |= MAC_ENABLE_RX | MAC_ENABLE_TX;
  514. writel(value, ioaddr + XGMAC_CONTROL);
  515. value = readl(ioaddr + XGMAC_DMA_CONTROL);
  516. value |= DMA_CONTROL_ST | DMA_CONTROL_SR;
  517. writel(value, ioaddr + XGMAC_DMA_CONTROL);
  518. }
  519. static inline void xgmac_mac_disable(void __iomem *ioaddr)
  520. {
  521. u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
  522. value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
  523. writel(value, ioaddr + XGMAC_DMA_CONTROL);
  524. value = readl(ioaddr + XGMAC_CONTROL);
  525. value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
  526. writel(value, ioaddr + XGMAC_CONTROL);
  527. }
  528. static void xgmac_set_mac_addr(void __iomem *ioaddr, unsigned char *addr,
  529. int num)
  530. {
  531. u32 data;
  532. data = (addr[5] << 8) | addr[4] | (num ? XGMAC_ADDR_AE : 0);
  533. writel(data, ioaddr + XGMAC_ADDR_HIGH(num));
  534. data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
  535. writel(data, ioaddr + XGMAC_ADDR_LOW(num));
  536. }
  537. static void xgmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
  538. int num)
  539. {
  540. u32 hi_addr, lo_addr;
  541. /* Read the MAC address from the hardware */
  542. hi_addr = readl(ioaddr + XGMAC_ADDR_HIGH(num));
  543. lo_addr = readl(ioaddr + XGMAC_ADDR_LOW(num));
  544. /* Extract the MAC address from the high and low words */
  545. addr[0] = lo_addr & 0xff;
  546. addr[1] = (lo_addr >> 8) & 0xff;
  547. addr[2] = (lo_addr >> 16) & 0xff;
  548. addr[3] = (lo_addr >> 24) & 0xff;
  549. addr[4] = hi_addr & 0xff;
  550. addr[5] = (hi_addr >> 8) & 0xff;
  551. }
  552. static int xgmac_set_flow_ctrl(struct xgmac_priv *priv, int rx, int tx)
  553. {
  554. u32 reg;
  555. unsigned int flow = 0;
  556. priv->rx_pause = rx;
  557. priv->tx_pause = tx;
  558. if (rx || tx) {
  559. if (rx)
  560. flow |= XGMAC_FLOW_CTRL_RFE;
  561. if (tx)
  562. flow |= XGMAC_FLOW_CTRL_TFE;
  563. flow |= XGMAC_FLOW_CTRL_PLT | XGMAC_FLOW_CTRL_UP;
  564. flow |= (PAUSE_TIME << XGMAC_FLOW_CTRL_PT_SHIFT);
  565. writel(flow, priv->base + XGMAC_FLOW_CTRL);
  566. reg = readl(priv->base + XGMAC_OMR);
  567. reg |= XGMAC_OMR_EFC;
  568. writel(reg, priv->base + XGMAC_OMR);
  569. } else {
  570. writel(0, priv->base + XGMAC_FLOW_CTRL);
  571. reg = readl(priv->base + XGMAC_OMR);
  572. reg &= ~XGMAC_OMR_EFC;
  573. writel(reg, priv->base + XGMAC_OMR);
  574. }
  575. return 0;
  576. }
  577. static void xgmac_rx_refill(struct xgmac_priv *priv)
  578. {
  579. struct xgmac_dma_desc *p;
  580. dma_addr_t paddr;
  581. int bufsz = priv->dev->mtu + ETH_HLEN + ETH_FCS_LEN;
  582. while (dma_ring_space(priv->rx_head, priv->rx_tail, DMA_RX_RING_SZ) > 1) {
  583. int entry = priv->rx_head;
  584. struct sk_buff *skb;
  585. p = priv->dma_rx + entry;
  586. if (priv->rx_skbuff[entry] == NULL) {
  587. skb = netdev_alloc_skb_ip_align(priv->dev, bufsz);
  588. if (unlikely(skb == NULL))
  589. break;
  590. priv->rx_skbuff[entry] = skb;
  591. paddr = dma_map_single(priv->device, skb->data,
  592. bufsz, DMA_FROM_DEVICE);
  593. desc_set_buf_addr(p, paddr, priv->dma_buf_sz);
  594. }
  595. netdev_dbg(priv->dev, "rx ring: head %d, tail %d\n",
  596. priv->rx_head, priv->rx_tail);
  597. priv->rx_head = dma_ring_incr(priv->rx_head, DMA_RX_RING_SZ);
  598. desc_set_rx_owner(p);
  599. }
  600. }
  601. /**
  602. * init_xgmac_dma_desc_rings - init the RX/TX descriptor rings
  603. * @dev: net device structure
  604. * Description: this function initializes the DMA RX/TX descriptors
  605. * and allocates the socket buffers.
  606. */
  607. static int xgmac_dma_desc_rings_init(struct net_device *dev)
  608. {
  609. struct xgmac_priv *priv = netdev_priv(dev);
  610. unsigned int bfsize;
  611. /* Set the Buffer size according to the MTU;
  612. * The total buffer size including any IP offset must be a multiple
  613. * of 8 bytes.
  614. */
  615. bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
  616. netdev_dbg(priv->dev, "mtu [%d] bfsize [%d]\n", dev->mtu, bfsize);
  617. priv->rx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_RX_RING_SZ,
  618. GFP_KERNEL);
  619. if (!priv->rx_skbuff)
  620. return -ENOMEM;
  621. priv->dma_rx = dma_alloc_coherent(priv->device,
  622. DMA_RX_RING_SZ *
  623. sizeof(struct xgmac_dma_desc),
  624. &priv->dma_rx_phy,
  625. GFP_KERNEL);
  626. if (!priv->dma_rx)
  627. goto err_dma_rx;
  628. priv->tx_skbuff = kzalloc(sizeof(struct sk_buff *) * DMA_TX_RING_SZ,
  629. GFP_KERNEL);
  630. if (!priv->tx_skbuff)
  631. goto err_tx_skb;
  632. priv->dma_tx = dma_alloc_coherent(priv->device,
  633. DMA_TX_RING_SZ *
  634. sizeof(struct xgmac_dma_desc),
  635. &priv->dma_tx_phy,
  636. GFP_KERNEL);
  637. if (!priv->dma_tx)
  638. goto err_dma_tx;
  639. netdev_dbg(priv->dev, "DMA desc rings: virt addr (Rx %p, "
  640. "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
  641. priv->dma_rx, priv->dma_tx,
  642. (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
  643. priv->rx_tail = 0;
  644. priv->rx_head = 0;
  645. priv->dma_buf_sz = bfsize;
  646. desc_init_rx_desc(priv->dma_rx, DMA_RX_RING_SZ, priv->dma_buf_sz);
  647. xgmac_rx_refill(priv);
  648. priv->tx_tail = 0;
  649. priv->tx_head = 0;
  650. desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ);
  651. writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
  652. writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR);
  653. return 0;
  654. err_dma_tx:
  655. kfree(priv->tx_skbuff);
  656. err_tx_skb:
  657. dma_free_coherent(priv->device,
  658. DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc),
  659. priv->dma_rx, priv->dma_rx_phy);
  660. err_dma_rx:
  661. kfree(priv->rx_skbuff);
  662. return -ENOMEM;
  663. }
  664. static void xgmac_free_rx_skbufs(struct xgmac_priv *priv)
  665. {
  666. int i;
  667. struct xgmac_dma_desc *p;
  668. if (!priv->rx_skbuff)
  669. return;
  670. for (i = 0; i < DMA_RX_RING_SZ; i++) {
  671. if (priv->rx_skbuff[i] == NULL)
  672. continue;
  673. p = priv->dma_rx + i;
  674. dma_unmap_single(priv->device, desc_get_buf_addr(p),
  675. priv->dma_buf_sz, DMA_FROM_DEVICE);
  676. dev_kfree_skb_any(priv->rx_skbuff[i]);
  677. priv->rx_skbuff[i] = NULL;
  678. }
  679. }
  680. static void xgmac_free_tx_skbufs(struct xgmac_priv *priv)
  681. {
  682. int i, f;
  683. struct xgmac_dma_desc *p;
  684. if (!priv->tx_skbuff)
  685. return;
  686. for (i = 0; i < DMA_TX_RING_SZ; i++) {
  687. if (priv->tx_skbuff[i] == NULL)
  688. continue;
  689. p = priv->dma_tx + i;
  690. dma_unmap_single(priv->device, desc_get_buf_addr(p),
  691. desc_get_buf_len(p), DMA_TO_DEVICE);
  692. for (f = 0; f < skb_shinfo(priv->tx_skbuff[i])->nr_frags; f++) {
  693. p = priv->dma_tx + i++;
  694. dma_unmap_page(priv->device, desc_get_buf_addr(p),
  695. desc_get_buf_len(p), DMA_TO_DEVICE);
  696. }
  697. dev_kfree_skb_any(priv->tx_skbuff[i]);
  698. priv->tx_skbuff[i] = NULL;
  699. }
  700. }
  701. static void xgmac_free_dma_desc_rings(struct xgmac_priv *priv)
  702. {
  703. /* Release the DMA TX/RX socket buffers */
  704. xgmac_free_rx_skbufs(priv);
  705. xgmac_free_tx_skbufs(priv);
  706. /* Free the consistent memory allocated for descriptor rings */
  707. if (priv->dma_tx) {
  708. dma_free_coherent(priv->device,
  709. DMA_TX_RING_SZ * sizeof(struct xgmac_dma_desc),
  710. priv->dma_tx, priv->dma_tx_phy);
  711. priv->dma_tx = NULL;
  712. }
  713. if (priv->dma_rx) {
  714. dma_free_coherent(priv->device,
  715. DMA_RX_RING_SZ * sizeof(struct xgmac_dma_desc),
  716. priv->dma_rx, priv->dma_rx_phy);
  717. priv->dma_rx = NULL;
  718. }
  719. kfree(priv->rx_skbuff);
  720. priv->rx_skbuff = NULL;
  721. kfree(priv->tx_skbuff);
  722. priv->tx_skbuff = NULL;
  723. }
  724. /**
  725. * xgmac_tx:
  726. * @priv: private driver structure
  727. * Description: it reclaims resources after transmission completes.
  728. */
  729. static void xgmac_tx_complete(struct xgmac_priv *priv)
  730. {
  731. int i;
  732. while (dma_ring_cnt(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ)) {
  733. unsigned int entry = priv->tx_tail;
  734. struct sk_buff *skb = priv->tx_skbuff[entry];
  735. struct xgmac_dma_desc *p = priv->dma_tx + entry;
  736. /* Check if the descriptor is owned by the DMA. */
  737. if (desc_get_owner(p))
  738. break;
  739. /* Verify tx error by looking at the last segment */
  740. if (desc_get_tx_ls(p))
  741. desc_get_tx_status(priv, p);
  742. netdev_dbg(priv->dev, "tx ring: curr %d, dirty %d\n",
  743. priv->tx_head, priv->tx_tail);
  744. dma_unmap_single(priv->device, desc_get_buf_addr(p),
  745. desc_get_buf_len(p), DMA_TO_DEVICE);
  746. priv->tx_skbuff[entry] = NULL;
  747. priv->tx_tail = dma_ring_incr(entry, DMA_TX_RING_SZ);
  748. if (!skb) {
  749. continue;
  750. }
  751. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  752. entry = priv->tx_tail = dma_ring_incr(priv->tx_tail,
  753. DMA_TX_RING_SZ);
  754. p = priv->dma_tx + priv->tx_tail;
  755. dma_unmap_page(priv->device, desc_get_buf_addr(p),
  756. desc_get_buf_len(p), DMA_TO_DEVICE);
  757. }
  758. dev_kfree_skb(skb);
  759. }
  760. if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) >
  761. MAX_SKB_FRAGS)
  762. netif_wake_queue(priv->dev);
  763. }
  764. /**
  765. * xgmac_tx_err:
  766. * @priv: pointer to the private device structure
  767. * Description: it cleans the descriptors and restarts the transmission
  768. * in case of errors.
  769. */
  770. static void xgmac_tx_err(struct xgmac_priv *priv)
  771. {
  772. u32 reg, value, inten;
  773. netif_stop_queue(priv->dev);
  774. inten = readl(priv->base + XGMAC_DMA_INTR_ENA);
  775. writel(0, priv->base + XGMAC_DMA_INTR_ENA);
  776. reg = readl(priv->base + XGMAC_DMA_CONTROL);
  777. writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
  778. do {
  779. value = readl(priv->base + XGMAC_DMA_STATUS) & 0x700000;
  780. } while (value && (value != 0x600000));
  781. xgmac_free_tx_skbufs(priv);
  782. desc_init_tx_desc(priv->dma_tx, DMA_TX_RING_SZ);
  783. priv->tx_tail = 0;
  784. priv->tx_head = 0;
  785. writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);
  786. writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);
  787. writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS,
  788. priv->base + XGMAC_DMA_STATUS);
  789. writel(inten, priv->base + XGMAC_DMA_INTR_ENA);
  790. netif_wake_queue(priv->dev);
  791. }
  792. static int xgmac_hw_init(struct net_device *dev)
  793. {
  794. u32 value, ctrl;
  795. int limit;
  796. struct xgmac_priv *priv = netdev_priv(dev);
  797. void __iomem *ioaddr = priv->base;
  798. /* Save the ctrl register value */
  799. ctrl = readl(ioaddr + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK;
  800. /* SW reset */
  801. value = DMA_BUS_MODE_SFT_RESET;
  802. writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
  803. limit = 15000;
  804. while (limit-- &&
  805. (readl(ioaddr + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
  806. cpu_relax();
  807. if (limit < 0)
  808. return -EBUSY;
  809. value = (0x10 << DMA_BUS_MODE_PBL_SHIFT) |
  810. (0x10 << DMA_BUS_MODE_RPBL_SHIFT) |
  811. DMA_BUS_MODE_FB | DMA_BUS_MODE_ATDS | DMA_BUS_MODE_AAL;
  812. writel(value, ioaddr + XGMAC_DMA_BUS_MODE);
  813. /* Enable interrupts */
  814. writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
  815. writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
  816. /* XGMAC requires AXI bus init. This is a 'magic number' for now */
  817. writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS);
  818. ctrl |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_JE | XGMAC_CONTROL_ACS |
  819. XGMAC_CONTROL_CAR;
  820. if (dev->features & NETIF_F_RXCSUM)
  821. ctrl |= XGMAC_CONTROL_IPC;
  822. writel(ctrl, ioaddr + XGMAC_CONTROL);
  823. writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL);
  824. /* Set the HW DMA mode and the COE */
  825. writel(XGMAC_OMR_TSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA |
  826. XGMAC_OMR_RTC_256,
  827. ioaddr + XGMAC_OMR);
  828. /* Reset the MMC counters */
  829. writel(1, ioaddr + XGMAC_MMC_CTRL);
  830. return 0;
  831. }
  832. /**
  833. * xgmac_open - open entry point of the driver
  834. * @dev : pointer to the device structure.
  835. * Description:
  836. * This function is the open entry point of the driver.
  837. * Return value:
  838. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  839. * file on failure.
  840. */
  841. static int xgmac_open(struct net_device *dev)
  842. {
  843. int ret;
  844. struct xgmac_priv *priv = netdev_priv(dev);
  845. void __iomem *ioaddr = priv->base;
  846. /* Check that the MAC address is valid. If its not, refuse
  847. * to bring the device up. The user must specify an
  848. * address using the following linux command:
  849. * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
  850. if (!is_valid_ether_addr(dev->dev_addr)) {
  851. eth_hw_addr_random(dev);
  852. netdev_dbg(priv->dev, "generated random MAC address %pM\n",
  853. dev->dev_addr);
  854. }
  855. memset(&priv->xstats, 0, sizeof(struct xgmac_extra_stats));
  856. /* Initialize the XGMAC and descriptors */
  857. xgmac_hw_init(dev);
  858. xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0);
  859. xgmac_set_flow_ctrl(priv, priv->rx_pause, priv->tx_pause);
  860. ret = xgmac_dma_desc_rings_init(dev);
  861. if (ret < 0)
  862. return ret;
  863. /* Enable the MAC Rx/Tx */
  864. xgmac_mac_enable(ioaddr);
  865. napi_enable(&priv->napi);
  866. netif_start_queue(dev);
  867. return 0;
  868. }
  869. /**
  870. * xgmac_release - close entry point of the driver
  871. * @dev : device pointer.
  872. * Description:
  873. * This is the stop entry point of the driver.
  874. */
  875. static int xgmac_stop(struct net_device *dev)
  876. {
  877. struct xgmac_priv *priv = netdev_priv(dev);
  878. netif_stop_queue(dev);
  879. if (readl(priv->base + XGMAC_DMA_INTR_ENA))
  880. napi_disable(&priv->napi);
  881. writel(0, priv->base + XGMAC_DMA_INTR_ENA);
  882. /* Disable the MAC core */
  883. xgmac_mac_disable(priv->base);
  884. /* Release and free the Rx/Tx resources */
  885. xgmac_free_dma_desc_rings(priv);
  886. return 0;
  887. }
  888. /**
  889. * xgmac_xmit:
  890. * @skb : the socket buffer
  891. * @dev : device pointer
  892. * Description : Tx entry point of the driver.
  893. */
  894. static netdev_tx_t xgmac_xmit(struct sk_buff *skb, struct net_device *dev)
  895. {
  896. struct xgmac_priv *priv = netdev_priv(dev);
  897. unsigned int entry;
  898. int i;
  899. u32 irq_flag;
  900. int nfrags = skb_shinfo(skb)->nr_frags;
  901. struct xgmac_dma_desc *desc, *first;
  902. unsigned int desc_flags;
  903. unsigned int len;
  904. dma_addr_t paddr;
  905. priv->tx_irq_cnt = (priv->tx_irq_cnt + 1) & (DMA_TX_RING_SZ/4 - 1);
  906. irq_flag = priv->tx_irq_cnt ? 0 : TXDESC_INTERRUPT;
  907. desc_flags = (skb->ip_summed == CHECKSUM_PARTIAL) ?
  908. TXDESC_CSUM_ALL : 0;
  909. entry = priv->tx_head;
  910. desc = priv->dma_tx + entry;
  911. first = desc;
  912. len = skb_headlen(skb);
  913. paddr = dma_map_single(priv->device, skb->data, len, DMA_TO_DEVICE);
  914. if (dma_mapping_error(priv->device, paddr)) {
  915. dev_kfree_skb(skb);
  916. return -EIO;
  917. }
  918. priv->tx_skbuff[entry] = skb;
  919. desc_set_buf_addr_and_size(desc, paddr, len);
  920. for (i = 0; i < nfrags; i++) {
  921. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  922. len = frag->size;
  923. paddr = skb_frag_dma_map(priv->device, frag, 0, len,
  924. DMA_TO_DEVICE);
  925. if (dma_mapping_error(priv->device, paddr)) {
  926. dev_kfree_skb(skb);
  927. return -EIO;
  928. }
  929. entry = dma_ring_incr(entry, DMA_TX_RING_SZ);
  930. desc = priv->dma_tx + entry;
  931. priv->tx_skbuff[entry] = NULL;
  932. desc_set_buf_addr_and_size(desc, paddr, len);
  933. if (i < (nfrags - 1))
  934. desc_set_tx_owner(desc, desc_flags);
  935. }
  936. /* Interrupt on completition only for the latest segment */
  937. if (desc != first)
  938. desc_set_tx_owner(desc, desc_flags |
  939. TXDESC_LAST_SEG | irq_flag);
  940. else
  941. desc_flags |= TXDESC_LAST_SEG | irq_flag;
  942. /* Set owner on first desc last to avoid race condition */
  943. wmb();
  944. desc_set_tx_owner(first, desc_flags | TXDESC_FIRST_SEG);
  945. priv->tx_head = dma_ring_incr(entry, DMA_TX_RING_SZ);
  946. writel(1, priv->base + XGMAC_DMA_TX_POLL);
  947. if (dma_ring_space(priv->tx_head, priv->tx_tail, DMA_TX_RING_SZ) <
  948. MAX_SKB_FRAGS)
  949. netif_stop_queue(dev);
  950. return NETDEV_TX_OK;
  951. }
  952. static int xgmac_rx(struct xgmac_priv *priv, int limit)
  953. {
  954. unsigned int entry;
  955. unsigned int count = 0;
  956. struct xgmac_dma_desc *p;
  957. while (count < limit) {
  958. int ip_checksum;
  959. struct sk_buff *skb;
  960. int frame_len;
  961. entry = priv->rx_tail;
  962. p = priv->dma_rx + entry;
  963. if (desc_get_owner(p))
  964. break;
  965. count++;
  966. priv->rx_tail = dma_ring_incr(priv->rx_tail, DMA_RX_RING_SZ);
  967. /* read the status of the incoming frame */
  968. ip_checksum = desc_get_rx_status(priv, p);
  969. if (ip_checksum < 0)
  970. continue;
  971. skb = priv->rx_skbuff[entry];
  972. if (unlikely(!skb)) {
  973. netdev_err(priv->dev, "Inconsistent Rx descriptor chain\n");
  974. break;
  975. }
  976. priv->rx_skbuff[entry] = NULL;
  977. frame_len = desc_get_rx_frame_len(p);
  978. netdev_dbg(priv->dev, "RX frame size %d, COE status: %d\n",
  979. frame_len, ip_checksum);
  980. skb_put(skb, frame_len);
  981. dma_unmap_single(priv->device, desc_get_buf_addr(p),
  982. frame_len, DMA_FROM_DEVICE);
  983. skb->protocol = eth_type_trans(skb, priv->dev);
  984. skb->ip_summed = ip_checksum;
  985. if (ip_checksum == CHECKSUM_NONE)
  986. netif_receive_skb(skb);
  987. else
  988. napi_gro_receive(&priv->napi, skb);
  989. }
  990. xgmac_rx_refill(priv);
  991. return count;
  992. }
  993. /**
  994. * xgmac_poll - xgmac poll method (NAPI)
  995. * @napi : pointer to the napi structure.
  996. * @budget : maximum number of packets that the current CPU can receive from
  997. * all interfaces.
  998. * Description :
  999. * This function implements the the reception process.
  1000. * Also it runs the TX completion thread
  1001. */
  1002. static int xgmac_poll(struct napi_struct *napi, int budget)
  1003. {
  1004. struct xgmac_priv *priv = container_of(napi,
  1005. struct xgmac_priv, napi);
  1006. int work_done = 0;
  1007. xgmac_tx_complete(priv);
  1008. work_done = xgmac_rx(priv, budget);
  1009. if (work_done < budget) {
  1010. napi_complete(napi);
  1011. __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);
  1012. }
  1013. return work_done;
  1014. }
  1015. /**
  1016. * xgmac_tx_timeout
  1017. * @dev : Pointer to net device structure
  1018. * Description: this function is called when a packet transmission fails to
  1019. * complete within a reasonable tmrate. The driver will mark the error in the
  1020. * netdev structure and arrange for the device to be reset to a sane state
  1021. * in order to transmit a new packet.
  1022. */
  1023. static void xgmac_tx_timeout(struct net_device *dev)
  1024. {
  1025. struct xgmac_priv *priv = netdev_priv(dev);
  1026. /* Clear Tx resources and restart transmitting again */
  1027. xgmac_tx_err(priv);
  1028. }
  1029. /**
  1030. * xgmac_set_rx_mode - entry point for multicast addressing
  1031. * @dev : pointer to the device structure
  1032. * Description:
  1033. * This function is a driver entry point which gets called by the kernel
  1034. * whenever multicast addresses must be enabled/disabled.
  1035. * Return value:
  1036. * void.
  1037. */
  1038. static void xgmac_set_rx_mode(struct net_device *dev)
  1039. {
  1040. int i;
  1041. struct xgmac_priv *priv = netdev_priv(dev);
  1042. void __iomem *ioaddr = priv->base;
  1043. unsigned int value = 0;
  1044. u32 hash_filter[XGMAC_NUM_HASH];
  1045. int reg = 1;
  1046. struct netdev_hw_addr *ha;
  1047. bool use_hash = false;
  1048. netdev_dbg(priv->dev, "# mcasts %d, # unicast %d\n",
  1049. netdev_mc_count(dev), netdev_uc_count(dev));
  1050. if (dev->flags & IFF_PROMISC) {
  1051. writel(XGMAC_FRAME_FILTER_PR, ioaddr + XGMAC_FRAME_FILTER);
  1052. return;
  1053. }
  1054. memset(hash_filter, 0, sizeof(hash_filter));
  1055. if (netdev_uc_count(dev) > XGMAC_MAX_FILTER_ADDR) {
  1056. use_hash = true;
  1057. value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF;
  1058. }
  1059. netdev_for_each_uc_addr(ha, dev) {
  1060. if (use_hash) {
  1061. u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23;
  1062. /* The most significant 4 bits determine the register to
  1063. * use (H/L) while the other 5 bits determine the bit
  1064. * within the register. */
  1065. hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1066. } else {
  1067. xgmac_set_mac_addr(ioaddr, ha->addr, reg);
  1068. reg++;
  1069. }
  1070. }
  1071. if (dev->flags & IFF_ALLMULTI) {
  1072. value |= XGMAC_FRAME_FILTER_PM;
  1073. goto out;
  1074. }
  1075. if ((netdev_mc_count(dev) + reg - 1) > XGMAC_MAX_FILTER_ADDR) {
  1076. use_hash = true;
  1077. value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF;
  1078. }
  1079. netdev_for_each_mc_addr(ha, dev) {
  1080. if (use_hash) {
  1081. u32 bit_nr = ~ether_crc(ETH_ALEN, ha->addr) >> 23;
  1082. /* The most significant 4 bits determine the register to
  1083. * use (H/L) while the other 5 bits determine the bit
  1084. * within the register. */
  1085. hash_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1086. } else {
  1087. xgmac_set_mac_addr(ioaddr, ha->addr, reg);
  1088. reg++;
  1089. }
  1090. }
  1091. out:
  1092. for (i = 0; i < XGMAC_NUM_HASH; i++)
  1093. writel(hash_filter[i], ioaddr + XGMAC_HASH(i));
  1094. writel(value, ioaddr + XGMAC_FRAME_FILTER);
  1095. }
  1096. /**
  1097. * xgmac_change_mtu - entry point to change MTU size for the device.
  1098. * @dev : device pointer.
  1099. * @new_mtu : the new MTU size for the device.
  1100. * Description: the Maximum Transfer Unit (MTU) is used by the network layer
  1101. * to drive packet transmission. Ethernet has an MTU of 1500 octets
  1102. * (ETH_DATA_LEN). This value can be changed with ifconfig.
  1103. * Return value:
  1104. * 0 on success and an appropriate (-)ve integer as defined in errno.h
  1105. * file on failure.
  1106. */
  1107. static int xgmac_change_mtu(struct net_device *dev, int new_mtu)
  1108. {
  1109. struct xgmac_priv *priv = netdev_priv(dev);
  1110. int old_mtu;
  1111. if ((new_mtu < 46) || (new_mtu > MAX_MTU)) {
  1112. netdev_err(priv->dev, "invalid MTU, max MTU is: %d\n", MAX_MTU);
  1113. return -EINVAL;
  1114. }
  1115. old_mtu = dev->mtu;
  1116. dev->mtu = new_mtu;
  1117. /* return early if the buffer sizes will not change */
  1118. if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
  1119. return 0;
  1120. if (old_mtu == new_mtu)
  1121. return 0;
  1122. /* Stop everything, get ready to change the MTU */
  1123. if (!netif_running(dev))
  1124. return 0;
  1125. /* Bring the interface down and then back up */
  1126. xgmac_stop(dev);
  1127. return xgmac_open(dev);
  1128. }
  1129. static irqreturn_t xgmac_pmt_interrupt(int irq, void *dev_id)
  1130. {
  1131. u32 intr_status;
  1132. struct net_device *dev = (struct net_device *)dev_id;
  1133. struct xgmac_priv *priv = netdev_priv(dev);
  1134. void __iomem *ioaddr = priv->base;
  1135. intr_status = __raw_readl(ioaddr + XGMAC_INT_STAT);
  1136. if (intr_status & XGMAC_INT_STAT_PMT) {
  1137. netdev_dbg(priv->dev, "received Magic frame\n");
  1138. /* clear the PMT bits 5 and 6 by reading the PMT */
  1139. readl(ioaddr + XGMAC_PMT);
  1140. }
  1141. return IRQ_HANDLED;
  1142. }
  1143. static irqreturn_t xgmac_interrupt(int irq, void *dev_id)
  1144. {
  1145. u32 intr_status;
  1146. bool tx_err = false;
  1147. struct net_device *dev = (struct net_device *)dev_id;
  1148. struct xgmac_priv *priv = netdev_priv(dev);
  1149. struct xgmac_extra_stats *x = &priv->xstats;
  1150. /* read the status register (CSR5) */
  1151. intr_status = __raw_readl(priv->base + XGMAC_DMA_STATUS);
  1152. intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA);
  1153. __raw_writel(intr_status, priv->base + XGMAC_DMA_STATUS);
  1154. /* It displays the DMA process states (CSR5 register) */
  1155. /* ABNORMAL interrupts */
  1156. if (unlikely(intr_status & DMA_STATUS_AIS)) {
  1157. if (intr_status & DMA_STATUS_TJT) {
  1158. netdev_err(priv->dev, "transmit jabber\n");
  1159. x->tx_jabber++;
  1160. }
  1161. if (intr_status & DMA_STATUS_RU)
  1162. x->rx_buf_unav++;
  1163. if (intr_status & DMA_STATUS_RPS) {
  1164. netdev_err(priv->dev, "receive process stopped\n");
  1165. x->rx_process_stopped++;
  1166. }
  1167. if (intr_status & DMA_STATUS_ETI) {
  1168. netdev_err(priv->dev, "transmit early interrupt\n");
  1169. x->tx_early++;
  1170. }
  1171. if (intr_status & DMA_STATUS_TPS) {
  1172. netdev_err(priv->dev, "transmit process stopped\n");
  1173. x->tx_process_stopped++;
  1174. tx_err = true;
  1175. }
  1176. if (intr_status & DMA_STATUS_FBI) {
  1177. netdev_err(priv->dev, "fatal bus error\n");
  1178. x->fatal_bus_error++;
  1179. tx_err = true;
  1180. }
  1181. if (tx_err)
  1182. xgmac_tx_err(priv);
  1183. }
  1184. /* TX/RX NORMAL interrupts */
  1185. if (intr_status & (DMA_STATUS_RI | DMA_STATUS_TU | DMA_STATUS_TI)) {
  1186. __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA);
  1187. napi_schedule(&priv->napi);
  1188. }
  1189. return IRQ_HANDLED;
  1190. }
  1191. #ifdef CONFIG_NET_POLL_CONTROLLER
  1192. /* Polling receive - used by NETCONSOLE and other diagnostic tools
  1193. * to allow network I/O with interrupts disabled. */
  1194. static void xgmac_poll_controller(struct net_device *dev)
  1195. {
  1196. disable_irq(dev->irq);
  1197. xgmac_interrupt(dev->irq, dev);
  1198. enable_irq(dev->irq);
  1199. }
  1200. #endif
  1201. static struct rtnl_link_stats64 *
  1202. xgmac_get_stats64(struct net_device *dev,
  1203. struct rtnl_link_stats64 *storage)
  1204. {
  1205. struct xgmac_priv *priv = netdev_priv(dev);
  1206. void __iomem *base = priv->base;
  1207. u32 count;
  1208. spin_lock_bh(&priv->stats_lock);
  1209. writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL);
  1210. storage->rx_bytes = readl(base + XGMAC_MMC_RXOCTET_G_LO);
  1211. storage->rx_bytes |= (u64)(readl(base + XGMAC_MMC_RXOCTET_G_HI)) << 32;
  1212. storage->rx_packets = readl(base + XGMAC_MMC_RXFRAME_GB_LO);
  1213. storage->multicast = readl(base + XGMAC_MMC_RXMCFRAME_G);
  1214. storage->rx_crc_errors = readl(base + XGMAC_MMC_RXCRCERR);
  1215. storage->rx_length_errors = readl(base + XGMAC_MMC_RXLENGTHERR);
  1216. storage->rx_missed_errors = readl(base + XGMAC_MMC_RXOVERFLOW);
  1217. storage->tx_bytes = readl(base + XGMAC_MMC_TXOCTET_G_LO);
  1218. storage->tx_bytes |= (u64)(readl(base + XGMAC_MMC_TXOCTET_G_HI)) << 32;
  1219. count = readl(base + XGMAC_MMC_TXFRAME_GB_LO);
  1220. storage->tx_errors = count - readl(base + XGMAC_MMC_TXFRAME_G_LO);
  1221. storage->tx_packets = count;
  1222. storage->tx_fifo_errors = readl(base + XGMAC_MMC_TXUNDERFLOW);
  1223. writel(0, base + XGMAC_MMC_CTRL);
  1224. spin_unlock_bh(&priv->stats_lock);
  1225. return storage;
  1226. }
  1227. static int xgmac_set_mac_address(struct net_device *dev, void *p)
  1228. {
  1229. struct xgmac_priv *priv = netdev_priv(dev);
  1230. void __iomem *ioaddr = priv->base;
  1231. struct sockaddr *addr = p;
  1232. if (!is_valid_ether_addr(addr->sa_data))
  1233. return -EADDRNOTAVAIL;
  1234. dev->addr_assign_type &= ~NET_ADDR_RANDOM;
  1235. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  1236. xgmac_set_mac_addr(ioaddr, dev->dev_addr, 0);
  1237. return 0;
  1238. }
  1239. static int xgmac_set_features(struct net_device *dev, netdev_features_t features)
  1240. {
  1241. u32 ctrl;
  1242. struct xgmac_priv *priv = netdev_priv(dev);
  1243. void __iomem *ioaddr = priv->base;
  1244. u32 changed = dev->features ^ features;
  1245. if (!(changed & NETIF_F_RXCSUM))
  1246. return 0;
  1247. ctrl = readl(ioaddr + XGMAC_CONTROL);
  1248. if (features & NETIF_F_RXCSUM)
  1249. ctrl |= XGMAC_CONTROL_IPC;
  1250. else
  1251. ctrl &= ~XGMAC_CONTROL_IPC;
  1252. writel(ctrl, ioaddr + XGMAC_CONTROL);
  1253. return 0;
  1254. }
  1255. static const struct net_device_ops xgmac_netdev_ops = {
  1256. .ndo_open = xgmac_open,
  1257. .ndo_start_xmit = xgmac_xmit,
  1258. .ndo_stop = xgmac_stop,
  1259. .ndo_change_mtu = xgmac_change_mtu,
  1260. .ndo_set_rx_mode = xgmac_set_rx_mode,
  1261. .ndo_tx_timeout = xgmac_tx_timeout,
  1262. .ndo_get_stats64 = xgmac_get_stats64,
  1263. #ifdef CONFIG_NET_POLL_CONTROLLER
  1264. .ndo_poll_controller = xgmac_poll_controller,
  1265. #endif
  1266. .ndo_set_mac_address = xgmac_set_mac_address,
  1267. .ndo_set_features = xgmac_set_features,
  1268. };
  1269. static int xgmac_ethtool_getsettings(struct net_device *dev,
  1270. struct ethtool_cmd *cmd)
  1271. {
  1272. cmd->autoneg = 0;
  1273. cmd->duplex = DUPLEX_FULL;
  1274. ethtool_cmd_speed_set(cmd, 10000);
  1275. cmd->supported = 0;
  1276. cmd->advertising = 0;
  1277. cmd->transceiver = XCVR_INTERNAL;
  1278. return 0;
  1279. }
  1280. static void xgmac_get_pauseparam(struct net_device *netdev,
  1281. struct ethtool_pauseparam *pause)
  1282. {
  1283. struct xgmac_priv *priv = netdev_priv(netdev);
  1284. pause->rx_pause = priv->rx_pause;
  1285. pause->tx_pause = priv->tx_pause;
  1286. }
  1287. static int xgmac_set_pauseparam(struct net_device *netdev,
  1288. struct ethtool_pauseparam *pause)
  1289. {
  1290. struct xgmac_priv *priv = netdev_priv(netdev);
  1291. if (pause->autoneg)
  1292. return -EINVAL;
  1293. return xgmac_set_flow_ctrl(priv, pause->rx_pause, pause->tx_pause);
  1294. }
  1295. struct xgmac_stats {
  1296. char stat_string[ETH_GSTRING_LEN];
  1297. int stat_offset;
  1298. bool is_reg;
  1299. };
  1300. #define XGMAC_STAT(m) \
  1301. { #m, offsetof(struct xgmac_priv, xstats.m), false }
  1302. #define XGMAC_HW_STAT(m, reg_offset) \
  1303. { #m, reg_offset, true }
  1304. static const struct xgmac_stats xgmac_gstrings_stats[] = {
  1305. XGMAC_STAT(tx_frame_flushed),
  1306. XGMAC_STAT(tx_payload_error),
  1307. XGMAC_STAT(tx_ip_header_error),
  1308. XGMAC_STAT(tx_local_fault),
  1309. XGMAC_STAT(tx_remote_fault),
  1310. XGMAC_STAT(tx_early),
  1311. XGMAC_STAT(tx_process_stopped),
  1312. XGMAC_STAT(tx_jabber),
  1313. XGMAC_STAT(rx_buf_unav),
  1314. XGMAC_STAT(rx_process_stopped),
  1315. XGMAC_STAT(rx_payload_error),
  1316. XGMAC_STAT(rx_ip_header_error),
  1317. XGMAC_STAT(rx_da_filter_fail),
  1318. XGMAC_STAT(rx_sa_filter_fail),
  1319. XGMAC_STAT(fatal_bus_error),
  1320. XGMAC_HW_STAT(rx_watchdog, XGMAC_MMC_RXWATCHDOG),
  1321. XGMAC_HW_STAT(tx_vlan, XGMAC_MMC_TXVLANFRAME),
  1322. XGMAC_HW_STAT(rx_vlan, XGMAC_MMC_RXVLANFRAME),
  1323. XGMAC_HW_STAT(tx_pause, XGMAC_MMC_TXPAUSEFRAME),
  1324. XGMAC_HW_STAT(rx_pause, XGMAC_MMC_RXPAUSEFRAME),
  1325. };
  1326. #define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats)
  1327. static void xgmac_get_ethtool_stats(struct net_device *dev,
  1328. struct ethtool_stats *dummy,
  1329. u64 *data)
  1330. {
  1331. struct xgmac_priv *priv = netdev_priv(dev);
  1332. void *p = priv;
  1333. int i;
  1334. for (i = 0; i < XGMAC_STATS_LEN; i++) {
  1335. if (xgmac_gstrings_stats[i].is_reg)
  1336. *data++ = readl(priv->base +
  1337. xgmac_gstrings_stats[i].stat_offset);
  1338. else
  1339. *data++ = *(u32 *)(p +
  1340. xgmac_gstrings_stats[i].stat_offset);
  1341. }
  1342. }
  1343. static int xgmac_get_sset_count(struct net_device *netdev, int sset)
  1344. {
  1345. switch (sset) {
  1346. case ETH_SS_STATS:
  1347. return XGMAC_STATS_LEN;
  1348. default:
  1349. return -EINVAL;
  1350. }
  1351. }
  1352. static void xgmac_get_strings(struct net_device *dev, u32 stringset,
  1353. u8 *data)
  1354. {
  1355. int i;
  1356. u8 *p = data;
  1357. switch (stringset) {
  1358. case ETH_SS_STATS:
  1359. for (i = 0; i < XGMAC_STATS_LEN; i++) {
  1360. memcpy(p, xgmac_gstrings_stats[i].stat_string,
  1361. ETH_GSTRING_LEN);
  1362. p += ETH_GSTRING_LEN;
  1363. }
  1364. break;
  1365. default:
  1366. WARN_ON(1);
  1367. break;
  1368. }
  1369. }
  1370. static void xgmac_get_wol(struct net_device *dev,
  1371. struct ethtool_wolinfo *wol)
  1372. {
  1373. struct xgmac_priv *priv = netdev_priv(dev);
  1374. if (device_can_wakeup(priv->device)) {
  1375. wol->supported = WAKE_MAGIC | WAKE_UCAST;
  1376. wol->wolopts = priv->wolopts;
  1377. }
  1378. }
  1379. static int xgmac_set_wol(struct net_device *dev,
  1380. struct ethtool_wolinfo *wol)
  1381. {
  1382. struct xgmac_priv *priv = netdev_priv(dev);
  1383. u32 support = WAKE_MAGIC | WAKE_UCAST;
  1384. if (!device_can_wakeup(priv->device))
  1385. return -ENOTSUPP;
  1386. if (wol->wolopts & ~support)
  1387. return -EINVAL;
  1388. priv->wolopts = wol->wolopts;
  1389. if (wol->wolopts) {
  1390. device_set_wakeup_enable(priv->device, 1);
  1391. enable_irq_wake(dev->irq);
  1392. } else {
  1393. device_set_wakeup_enable(priv->device, 0);
  1394. disable_irq_wake(dev->irq);
  1395. }
  1396. return 0;
  1397. }
  1398. static const struct ethtool_ops xgmac_ethtool_ops = {
  1399. .get_settings = xgmac_ethtool_getsettings,
  1400. .get_link = ethtool_op_get_link,
  1401. .get_pauseparam = xgmac_get_pauseparam,
  1402. .set_pauseparam = xgmac_set_pauseparam,
  1403. .get_ethtool_stats = xgmac_get_ethtool_stats,
  1404. .get_strings = xgmac_get_strings,
  1405. .get_wol = xgmac_get_wol,
  1406. .set_wol = xgmac_set_wol,
  1407. .get_sset_count = xgmac_get_sset_count,
  1408. };
  1409. /**
  1410. * xgmac_probe
  1411. * @pdev: platform device pointer
  1412. * Description: the driver is initialized through platform_device.
  1413. */
  1414. static int xgmac_probe(struct platform_device *pdev)
  1415. {
  1416. int ret = 0;
  1417. struct resource *res;
  1418. struct net_device *ndev = NULL;
  1419. struct xgmac_priv *priv = NULL;
  1420. u32 uid;
  1421. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1422. if (!res)
  1423. return -ENODEV;
  1424. if (!request_mem_region(res->start, resource_size(res), pdev->name))
  1425. return -EBUSY;
  1426. ndev = alloc_etherdev(sizeof(struct xgmac_priv));
  1427. if (!ndev) {
  1428. ret = -ENOMEM;
  1429. goto err_alloc;
  1430. }
  1431. SET_NETDEV_DEV(ndev, &pdev->dev);
  1432. priv = netdev_priv(ndev);
  1433. platform_set_drvdata(pdev, ndev);
  1434. ether_setup(ndev);
  1435. ndev->netdev_ops = &xgmac_netdev_ops;
  1436. SET_ETHTOOL_OPS(ndev, &xgmac_ethtool_ops);
  1437. spin_lock_init(&priv->stats_lock);
  1438. priv->device = &pdev->dev;
  1439. priv->dev = ndev;
  1440. priv->rx_pause = 1;
  1441. priv->tx_pause = 1;
  1442. priv->base = ioremap(res->start, resource_size(res));
  1443. if (!priv->base) {
  1444. netdev_err(ndev, "ioremap failed\n");
  1445. ret = -ENOMEM;
  1446. goto err_io;
  1447. }
  1448. uid = readl(priv->base + XGMAC_VERSION);
  1449. netdev_info(ndev, "h/w version is 0x%x\n", uid);
  1450. writel(0, priv->base + XGMAC_DMA_INTR_ENA);
  1451. ndev->irq = platform_get_irq(pdev, 0);
  1452. if (ndev->irq == -ENXIO) {
  1453. netdev_err(ndev, "No irq resource\n");
  1454. ret = ndev->irq;
  1455. goto err_irq;
  1456. }
  1457. ret = request_irq(ndev->irq, xgmac_interrupt, 0,
  1458. dev_name(&pdev->dev), ndev);
  1459. if (ret < 0) {
  1460. netdev_err(ndev, "Could not request irq %d - ret %d)\n",
  1461. ndev->irq, ret);
  1462. goto err_irq;
  1463. }
  1464. priv->pmt_irq = platform_get_irq(pdev, 1);
  1465. if (priv->pmt_irq == -ENXIO) {
  1466. netdev_err(ndev, "No pmt irq resource\n");
  1467. ret = priv->pmt_irq;
  1468. goto err_pmt_irq;
  1469. }
  1470. ret = request_irq(priv->pmt_irq, xgmac_pmt_interrupt, 0,
  1471. dev_name(&pdev->dev), ndev);
  1472. if (ret < 0) {
  1473. netdev_err(ndev, "Could not request irq %d - ret %d)\n",
  1474. priv->pmt_irq, ret);
  1475. goto err_pmt_irq;
  1476. }
  1477. device_set_wakeup_capable(&pdev->dev, 1);
  1478. if (device_can_wakeup(priv->device))
  1479. priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
  1480. ndev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_HIGHDMA;
  1481. if (readl(priv->base + XGMAC_DMA_HW_FEATURE) & DMA_HW_FEAT_TXCOESEL)
  1482. ndev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1483. NETIF_F_RXCSUM;
  1484. ndev->features |= ndev->hw_features;
  1485. ndev->priv_flags |= IFF_UNICAST_FLT;
  1486. /* Get the MAC address */
  1487. xgmac_get_mac_addr(priv->base, ndev->dev_addr, 0);
  1488. if (!is_valid_ether_addr(ndev->dev_addr))
  1489. netdev_warn(ndev, "MAC address %pM not valid",
  1490. ndev->dev_addr);
  1491. netif_napi_add(ndev, &priv->napi, xgmac_poll, 64);
  1492. ret = register_netdev(ndev);
  1493. if (ret)
  1494. goto err_reg;
  1495. return 0;
  1496. err_reg:
  1497. netif_napi_del(&priv->napi);
  1498. free_irq(priv->pmt_irq, ndev);
  1499. err_pmt_irq:
  1500. free_irq(ndev->irq, ndev);
  1501. err_irq:
  1502. iounmap(priv->base);
  1503. err_io:
  1504. free_netdev(ndev);
  1505. err_alloc:
  1506. release_mem_region(res->start, resource_size(res));
  1507. platform_set_drvdata(pdev, NULL);
  1508. return ret;
  1509. }
  1510. /**
  1511. * xgmac_dvr_remove
  1512. * @pdev: platform device pointer
  1513. * Description: this function resets the TX/RX processes, disables the MAC RX/TX
  1514. * changes the link status, releases the DMA descriptor rings,
  1515. * unregisters the MDIO bus and unmaps the allocated memory.
  1516. */
  1517. static int xgmac_remove(struct platform_device *pdev)
  1518. {
  1519. struct net_device *ndev = platform_get_drvdata(pdev);
  1520. struct xgmac_priv *priv = netdev_priv(ndev);
  1521. struct resource *res;
  1522. xgmac_mac_disable(priv->base);
  1523. /* Free the IRQ lines */
  1524. free_irq(ndev->irq, ndev);
  1525. free_irq(priv->pmt_irq, ndev);
  1526. platform_set_drvdata(pdev, NULL);
  1527. unregister_netdev(ndev);
  1528. netif_napi_del(&priv->napi);
  1529. iounmap(priv->base);
  1530. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1531. release_mem_region(res->start, resource_size(res));
  1532. free_netdev(ndev);
  1533. return 0;
  1534. }
  1535. #ifdef CONFIG_PM_SLEEP
  1536. static void xgmac_pmt(void __iomem *ioaddr, unsigned long mode)
  1537. {
  1538. unsigned int pmt = 0;
  1539. if (mode & WAKE_MAGIC)
  1540. pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_MAGIC_PKT;
  1541. if (mode & WAKE_UCAST)
  1542. pmt |= XGMAC_PMT_POWERDOWN | XGMAC_PMT_GLBL_UNICAST;
  1543. writel(pmt, ioaddr + XGMAC_PMT);
  1544. }
  1545. static int xgmac_suspend(struct device *dev)
  1546. {
  1547. struct net_device *ndev = platform_get_drvdata(to_platform_device(dev));
  1548. struct xgmac_priv *priv = netdev_priv(ndev);
  1549. u32 value;
  1550. if (!ndev || !netif_running(ndev))
  1551. return 0;
  1552. netif_device_detach(ndev);
  1553. napi_disable(&priv->napi);
  1554. writel(0, priv->base + XGMAC_DMA_INTR_ENA);
  1555. if (device_may_wakeup(priv->device)) {
  1556. /* Stop TX/RX DMA Only */
  1557. value = readl(priv->base + XGMAC_DMA_CONTROL);
  1558. value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
  1559. writel(value, priv->base + XGMAC_DMA_CONTROL);
  1560. xgmac_pmt(priv->base, priv->wolopts);
  1561. } else
  1562. xgmac_mac_disable(priv->base);
  1563. return 0;
  1564. }
  1565. static int xgmac_resume(struct device *dev)
  1566. {
  1567. struct net_device *ndev = platform_get_drvdata(to_platform_device(dev));
  1568. struct xgmac_priv *priv = netdev_priv(ndev);
  1569. void __iomem *ioaddr = priv->base;
  1570. if (!netif_running(ndev))
  1571. return 0;
  1572. xgmac_pmt(ioaddr, 0);
  1573. /* Enable the MAC and DMA */
  1574. xgmac_mac_enable(ioaddr);
  1575. writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);
  1576. writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);
  1577. netif_device_attach(ndev);
  1578. napi_enable(&priv->napi);
  1579. return 0;
  1580. }
  1581. static SIMPLE_DEV_PM_OPS(xgmac_pm_ops, xgmac_suspend, xgmac_resume);
  1582. #define XGMAC_PM_OPS (&xgmac_pm_ops)
  1583. #else
  1584. #define XGMAC_PM_OPS NULL
  1585. #endif /* CONFIG_PM_SLEEP */
  1586. static const struct of_device_id xgmac_of_match[] = {
  1587. { .compatible = "calxeda,hb-xgmac", },
  1588. {},
  1589. };
  1590. MODULE_DEVICE_TABLE(of, xgmac_of_match);
  1591. static struct platform_driver xgmac_driver = {
  1592. .driver = {
  1593. .name = "calxedaxgmac",
  1594. .of_match_table = xgmac_of_match,
  1595. },
  1596. .probe = xgmac_probe,
  1597. .remove = xgmac_remove,
  1598. .driver.pm = XGMAC_PM_OPS,
  1599. };
  1600. module_platform_driver(xgmac_driver);
  1601. MODULE_AUTHOR("Calxeda, Inc.");
  1602. MODULE_DESCRIPTION("Calxeda 10G XGMAC driver");
  1603. MODULE_LICENSE("GPL v2");