bna_tx_rx.c 91 KB

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  1. /*
  2. * Linux network driver for Brocade Converged Network Adapter.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License (GPL) Version 2 as
  6. * published by the Free Software Foundation
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  11. * General Public License for more details.
  12. */
  13. /*
  14. * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15. * All rights reserved
  16. * www.brocade.com
  17. */
  18. #include "bna.h"
  19. #include "bfi.h"
  20. /* IB */
  21. static void
  22. bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
  23. {
  24. ib->coalescing_timeo = coalescing_timeo;
  25. ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
  26. (u32)ib->coalescing_timeo, 0);
  27. }
  28. /* RXF */
  29. #define bna_rxf_vlan_cfg_soft_reset(rxf) \
  30. do { \
  31. (rxf)->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL; \
  32. (rxf)->vlan_strip_pending = true; \
  33. } while (0)
  34. #define bna_rxf_rss_cfg_soft_reset(rxf) \
  35. do { \
  36. if ((rxf)->rss_status == BNA_STATUS_T_ENABLED) \
  37. (rxf)->rss_pending = (BNA_RSS_F_RIT_PENDING | \
  38. BNA_RSS_F_CFG_PENDING | \
  39. BNA_RSS_F_STATUS_PENDING); \
  40. } while (0)
  41. static int bna_rxf_cfg_apply(struct bna_rxf *rxf);
  42. static void bna_rxf_cfg_reset(struct bna_rxf *rxf);
  43. static int bna_rxf_fltr_clear(struct bna_rxf *rxf);
  44. static int bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf);
  45. static int bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf);
  46. static int bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf);
  47. static int bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf);
  48. static int bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf,
  49. enum bna_cleanup_type cleanup);
  50. static int bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf,
  51. enum bna_cleanup_type cleanup);
  52. static int bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf,
  53. enum bna_cleanup_type cleanup);
  54. bfa_fsm_state_decl(bna_rxf, stopped, struct bna_rxf,
  55. enum bna_rxf_event);
  56. bfa_fsm_state_decl(bna_rxf, paused, struct bna_rxf,
  57. enum bna_rxf_event);
  58. bfa_fsm_state_decl(bna_rxf, cfg_wait, struct bna_rxf,
  59. enum bna_rxf_event);
  60. bfa_fsm_state_decl(bna_rxf, started, struct bna_rxf,
  61. enum bna_rxf_event);
  62. bfa_fsm_state_decl(bna_rxf, fltr_clr_wait, struct bna_rxf,
  63. enum bna_rxf_event);
  64. bfa_fsm_state_decl(bna_rxf, last_resp_wait, struct bna_rxf,
  65. enum bna_rxf_event);
  66. static void
  67. bna_rxf_sm_stopped_entry(struct bna_rxf *rxf)
  68. {
  69. call_rxf_stop_cbfn(rxf);
  70. }
  71. static void
  72. bna_rxf_sm_stopped(struct bna_rxf *rxf, enum bna_rxf_event event)
  73. {
  74. switch (event) {
  75. case RXF_E_START:
  76. if (rxf->flags & BNA_RXF_F_PAUSED) {
  77. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  78. call_rxf_start_cbfn(rxf);
  79. } else
  80. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  81. break;
  82. case RXF_E_STOP:
  83. call_rxf_stop_cbfn(rxf);
  84. break;
  85. case RXF_E_FAIL:
  86. /* No-op */
  87. break;
  88. case RXF_E_CONFIG:
  89. call_rxf_cam_fltr_cbfn(rxf);
  90. break;
  91. case RXF_E_PAUSE:
  92. rxf->flags |= BNA_RXF_F_PAUSED;
  93. call_rxf_pause_cbfn(rxf);
  94. break;
  95. case RXF_E_RESUME:
  96. rxf->flags &= ~BNA_RXF_F_PAUSED;
  97. call_rxf_resume_cbfn(rxf);
  98. break;
  99. default:
  100. bfa_sm_fault(event);
  101. }
  102. }
  103. static void
  104. bna_rxf_sm_paused_entry(struct bna_rxf *rxf)
  105. {
  106. call_rxf_pause_cbfn(rxf);
  107. }
  108. static void
  109. bna_rxf_sm_paused(struct bna_rxf *rxf, enum bna_rxf_event event)
  110. {
  111. switch (event) {
  112. case RXF_E_STOP:
  113. case RXF_E_FAIL:
  114. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  115. break;
  116. case RXF_E_CONFIG:
  117. call_rxf_cam_fltr_cbfn(rxf);
  118. break;
  119. case RXF_E_RESUME:
  120. rxf->flags &= ~BNA_RXF_F_PAUSED;
  121. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  122. break;
  123. default:
  124. bfa_sm_fault(event);
  125. }
  126. }
  127. static void
  128. bna_rxf_sm_cfg_wait_entry(struct bna_rxf *rxf)
  129. {
  130. if (!bna_rxf_cfg_apply(rxf)) {
  131. /* No more pending config updates */
  132. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  133. }
  134. }
  135. static void
  136. bna_rxf_sm_cfg_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  137. {
  138. switch (event) {
  139. case RXF_E_STOP:
  140. bfa_fsm_set_state(rxf, bna_rxf_sm_last_resp_wait);
  141. break;
  142. case RXF_E_FAIL:
  143. bna_rxf_cfg_reset(rxf);
  144. call_rxf_start_cbfn(rxf);
  145. call_rxf_cam_fltr_cbfn(rxf);
  146. call_rxf_resume_cbfn(rxf);
  147. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  148. break;
  149. case RXF_E_CONFIG:
  150. /* No-op */
  151. break;
  152. case RXF_E_PAUSE:
  153. rxf->flags |= BNA_RXF_F_PAUSED;
  154. call_rxf_start_cbfn(rxf);
  155. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  156. break;
  157. case RXF_E_FW_RESP:
  158. if (!bna_rxf_cfg_apply(rxf)) {
  159. /* No more pending config updates */
  160. bfa_fsm_set_state(rxf, bna_rxf_sm_started);
  161. }
  162. break;
  163. default:
  164. bfa_sm_fault(event);
  165. }
  166. }
  167. static void
  168. bna_rxf_sm_started_entry(struct bna_rxf *rxf)
  169. {
  170. call_rxf_start_cbfn(rxf);
  171. call_rxf_cam_fltr_cbfn(rxf);
  172. call_rxf_resume_cbfn(rxf);
  173. }
  174. static void
  175. bna_rxf_sm_started(struct bna_rxf *rxf, enum bna_rxf_event event)
  176. {
  177. switch (event) {
  178. case RXF_E_STOP:
  179. case RXF_E_FAIL:
  180. bna_rxf_cfg_reset(rxf);
  181. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  182. break;
  183. case RXF_E_CONFIG:
  184. bfa_fsm_set_state(rxf, bna_rxf_sm_cfg_wait);
  185. break;
  186. case RXF_E_PAUSE:
  187. rxf->flags |= BNA_RXF_F_PAUSED;
  188. if (!bna_rxf_fltr_clear(rxf))
  189. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  190. else
  191. bfa_fsm_set_state(rxf, bna_rxf_sm_fltr_clr_wait);
  192. break;
  193. default:
  194. bfa_sm_fault(event);
  195. }
  196. }
  197. static void
  198. bna_rxf_sm_fltr_clr_wait_entry(struct bna_rxf *rxf)
  199. {
  200. }
  201. static void
  202. bna_rxf_sm_fltr_clr_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  203. {
  204. switch (event) {
  205. case RXF_E_FAIL:
  206. bna_rxf_cfg_reset(rxf);
  207. call_rxf_pause_cbfn(rxf);
  208. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  209. break;
  210. case RXF_E_FW_RESP:
  211. if (!bna_rxf_fltr_clear(rxf)) {
  212. /* No more pending CAM entries to clear */
  213. bfa_fsm_set_state(rxf, bna_rxf_sm_paused);
  214. }
  215. break;
  216. default:
  217. bfa_sm_fault(event);
  218. }
  219. }
  220. static void
  221. bna_rxf_sm_last_resp_wait_entry(struct bna_rxf *rxf)
  222. {
  223. }
  224. static void
  225. bna_rxf_sm_last_resp_wait(struct bna_rxf *rxf, enum bna_rxf_event event)
  226. {
  227. switch (event) {
  228. case RXF_E_FAIL:
  229. case RXF_E_FW_RESP:
  230. bna_rxf_cfg_reset(rxf);
  231. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  232. break;
  233. default:
  234. bfa_sm_fault(event);
  235. }
  236. }
  237. static void
  238. bna_bfi_ucast_req(struct bna_rxf *rxf, struct bna_mac *mac,
  239. enum bfi_enet_h2i_msgs req_type)
  240. {
  241. struct bfi_enet_ucast_req *req = &rxf->bfi_enet_cmd.ucast_req;
  242. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, req_type, 0, rxf->rx->rid);
  243. req->mh.num_entries = htons(
  244. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_ucast_req)));
  245. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  246. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  247. sizeof(struct bfi_enet_ucast_req), &req->mh);
  248. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  249. }
  250. static void
  251. bna_bfi_mcast_add_req(struct bna_rxf *rxf, struct bna_mac *mac)
  252. {
  253. struct bfi_enet_mcast_add_req *req =
  254. &rxf->bfi_enet_cmd.mcast_add_req;
  255. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_ADD_REQ,
  256. 0, rxf->rx->rid);
  257. req->mh.num_entries = htons(
  258. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_add_req)));
  259. memcpy(&req->mac_addr, &mac->addr, sizeof(mac_t));
  260. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  261. sizeof(struct bfi_enet_mcast_add_req), &req->mh);
  262. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  263. }
  264. static void
  265. bna_bfi_mcast_del_req(struct bna_rxf *rxf, u16 handle)
  266. {
  267. struct bfi_enet_mcast_del_req *req =
  268. &rxf->bfi_enet_cmd.mcast_del_req;
  269. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET, BFI_ENET_H2I_MAC_MCAST_DEL_REQ,
  270. 0, rxf->rx->rid);
  271. req->mh.num_entries = htons(
  272. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_mcast_del_req)));
  273. req->handle = htons(handle);
  274. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  275. sizeof(struct bfi_enet_mcast_del_req), &req->mh);
  276. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  277. }
  278. static void
  279. bna_bfi_mcast_filter_req(struct bna_rxf *rxf, enum bna_status status)
  280. {
  281. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  282. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  283. BFI_ENET_H2I_MAC_MCAST_FILTER_REQ, 0, rxf->rx->rid);
  284. req->mh.num_entries = htons(
  285. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  286. req->enable = status;
  287. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  288. sizeof(struct bfi_enet_enable_req), &req->mh);
  289. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  290. }
  291. static void
  292. bna_bfi_rx_promisc_req(struct bna_rxf *rxf, enum bna_status status)
  293. {
  294. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  295. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  296. BFI_ENET_H2I_RX_PROMISCUOUS_REQ, 0, rxf->rx->rid);
  297. req->mh.num_entries = htons(
  298. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  299. req->enable = status;
  300. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  301. sizeof(struct bfi_enet_enable_req), &req->mh);
  302. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  303. }
  304. static void
  305. bna_bfi_rx_vlan_filter_set(struct bna_rxf *rxf, u8 block_idx)
  306. {
  307. struct bfi_enet_rx_vlan_req *req = &rxf->bfi_enet_cmd.vlan_req;
  308. int i;
  309. int j;
  310. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  311. BFI_ENET_H2I_RX_VLAN_SET_REQ, 0, rxf->rx->rid);
  312. req->mh.num_entries = htons(
  313. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_vlan_req)));
  314. req->block_idx = block_idx;
  315. for (i = 0; i < (BFI_ENET_VLAN_BLOCK_SIZE / 32); i++) {
  316. j = (block_idx * (BFI_ENET_VLAN_BLOCK_SIZE / 32)) + i;
  317. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED)
  318. req->bit_mask[i] =
  319. htonl(rxf->vlan_filter_table[j]);
  320. else
  321. req->bit_mask[i] = 0xFFFFFFFF;
  322. }
  323. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  324. sizeof(struct bfi_enet_rx_vlan_req), &req->mh);
  325. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  326. }
  327. static void
  328. bna_bfi_vlan_strip_enable(struct bna_rxf *rxf)
  329. {
  330. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  331. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  332. BFI_ENET_H2I_RX_VLAN_STRIP_ENABLE_REQ, 0, rxf->rx->rid);
  333. req->mh.num_entries = htons(
  334. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  335. req->enable = rxf->vlan_strip_status;
  336. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  337. sizeof(struct bfi_enet_enable_req), &req->mh);
  338. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  339. }
  340. static void
  341. bna_bfi_rit_cfg(struct bna_rxf *rxf)
  342. {
  343. struct bfi_enet_rit_req *req = &rxf->bfi_enet_cmd.rit_req;
  344. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  345. BFI_ENET_H2I_RIT_CFG_REQ, 0, rxf->rx->rid);
  346. req->mh.num_entries = htons(
  347. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rit_req)));
  348. req->size = htons(rxf->rit_size);
  349. memcpy(&req->table[0], rxf->rit, rxf->rit_size);
  350. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  351. sizeof(struct bfi_enet_rit_req), &req->mh);
  352. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  353. }
  354. static void
  355. bna_bfi_rss_cfg(struct bna_rxf *rxf)
  356. {
  357. struct bfi_enet_rss_cfg_req *req = &rxf->bfi_enet_cmd.rss_req;
  358. int i;
  359. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  360. BFI_ENET_H2I_RSS_CFG_REQ, 0, rxf->rx->rid);
  361. req->mh.num_entries = htons(
  362. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rss_cfg_req)));
  363. req->cfg.type = rxf->rss_cfg.hash_type;
  364. req->cfg.mask = rxf->rss_cfg.hash_mask;
  365. for (i = 0; i < BFI_ENET_RSS_KEY_LEN; i++)
  366. req->cfg.key[i] =
  367. htonl(rxf->rss_cfg.toeplitz_hash_key[i]);
  368. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  369. sizeof(struct bfi_enet_rss_cfg_req), &req->mh);
  370. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  371. }
  372. static void
  373. bna_bfi_rss_enable(struct bna_rxf *rxf)
  374. {
  375. struct bfi_enet_enable_req *req = &rxf->bfi_enet_cmd.req;
  376. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  377. BFI_ENET_H2I_RSS_ENABLE_REQ, 0, rxf->rx->rid);
  378. req->mh.num_entries = htons(
  379. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_enable_req)));
  380. req->enable = rxf->rss_status;
  381. bfa_msgq_cmd_set(&rxf->msgq_cmd, NULL, NULL,
  382. sizeof(struct bfi_enet_enable_req), &req->mh);
  383. bfa_msgq_cmd_post(&rxf->rx->bna->msgq, &rxf->msgq_cmd);
  384. }
  385. /* This function gets the multicast MAC that has already been added to CAM */
  386. static struct bna_mac *
  387. bna_rxf_mcmac_get(struct bna_rxf *rxf, u8 *mac_addr)
  388. {
  389. struct bna_mac *mac;
  390. struct list_head *qe;
  391. list_for_each(qe, &rxf->mcast_active_q) {
  392. mac = (struct bna_mac *)qe;
  393. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  394. return mac;
  395. }
  396. list_for_each(qe, &rxf->mcast_pending_del_q) {
  397. mac = (struct bna_mac *)qe;
  398. if (BNA_MAC_IS_EQUAL(&mac->addr, mac_addr))
  399. return mac;
  400. }
  401. return NULL;
  402. }
  403. static struct bna_mcam_handle *
  404. bna_rxf_mchandle_get(struct bna_rxf *rxf, int handle)
  405. {
  406. struct bna_mcam_handle *mchandle;
  407. struct list_head *qe;
  408. list_for_each(qe, &rxf->mcast_handle_q) {
  409. mchandle = (struct bna_mcam_handle *)qe;
  410. if (mchandle->handle == handle)
  411. return mchandle;
  412. }
  413. return NULL;
  414. }
  415. static void
  416. bna_rxf_mchandle_attach(struct bna_rxf *rxf, u8 *mac_addr, int handle)
  417. {
  418. struct bna_mac *mcmac;
  419. struct bna_mcam_handle *mchandle;
  420. mcmac = bna_rxf_mcmac_get(rxf, mac_addr);
  421. mchandle = bna_rxf_mchandle_get(rxf, handle);
  422. if (mchandle == NULL) {
  423. mchandle = bna_mcam_mod_handle_get(&rxf->rx->bna->mcam_mod);
  424. mchandle->handle = handle;
  425. mchandle->refcnt = 0;
  426. list_add_tail(&mchandle->qe, &rxf->mcast_handle_q);
  427. }
  428. mchandle->refcnt++;
  429. mcmac->handle = mchandle;
  430. }
  431. static int
  432. bna_rxf_mcast_del(struct bna_rxf *rxf, struct bna_mac *mac,
  433. enum bna_cleanup_type cleanup)
  434. {
  435. struct bna_mcam_handle *mchandle;
  436. int ret = 0;
  437. mchandle = mac->handle;
  438. if (mchandle == NULL)
  439. return ret;
  440. mchandle->refcnt--;
  441. if (mchandle->refcnt == 0) {
  442. if (cleanup == BNA_HARD_CLEANUP) {
  443. bna_bfi_mcast_del_req(rxf, mchandle->handle);
  444. ret = 1;
  445. }
  446. list_del(&mchandle->qe);
  447. bfa_q_qe_init(&mchandle->qe);
  448. bna_mcam_mod_handle_put(&rxf->rx->bna->mcam_mod, mchandle);
  449. }
  450. mac->handle = NULL;
  451. return ret;
  452. }
  453. static int
  454. bna_rxf_mcast_cfg_apply(struct bna_rxf *rxf)
  455. {
  456. struct bna_mac *mac = NULL;
  457. struct list_head *qe;
  458. int ret;
  459. /* Delete multicast entries previousely added */
  460. while (!list_empty(&rxf->mcast_pending_del_q)) {
  461. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  462. bfa_q_qe_init(qe);
  463. mac = (struct bna_mac *)qe;
  464. ret = bna_rxf_mcast_del(rxf, mac, BNA_HARD_CLEANUP);
  465. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  466. if (ret)
  467. return ret;
  468. }
  469. /* Add multicast entries */
  470. if (!list_empty(&rxf->mcast_pending_add_q)) {
  471. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  472. bfa_q_qe_init(qe);
  473. mac = (struct bna_mac *)qe;
  474. list_add_tail(&mac->qe, &rxf->mcast_active_q);
  475. bna_bfi_mcast_add_req(rxf, mac);
  476. return 1;
  477. }
  478. return 0;
  479. }
  480. static int
  481. bna_rxf_vlan_cfg_apply(struct bna_rxf *rxf)
  482. {
  483. u8 vlan_pending_bitmask;
  484. int block_idx = 0;
  485. if (rxf->vlan_pending_bitmask) {
  486. vlan_pending_bitmask = rxf->vlan_pending_bitmask;
  487. while (!(vlan_pending_bitmask & 0x1)) {
  488. block_idx++;
  489. vlan_pending_bitmask >>= 1;
  490. }
  491. rxf->vlan_pending_bitmask &= ~(1 << block_idx);
  492. bna_bfi_rx_vlan_filter_set(rxf, block_idx);
  493. return 1;
  494. }
  495. return 0;
  496. }
  497. static int
  498. bna_rxf_mcast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  499. {
  500. struct list_head *qe;
  501. struct bna_mac *mac;
  502. int ret;
  503. /* Throw away delete pending mcast entries */
  504. while (!list_empty(&rxf->mcast_pending_del_q)) {
  505. bfa_q_deq(&rxf->mcast_pending_del_q, &qe);
  506. bfa_q_qe_init(qe);
  507. mac = (struct bna_mac *)qe;
  508. ret = bna_rxf_mcast_del(rxf, mac, cleanup);
  509. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  510. if (ret)
  511. return ret;
  512. }
  513. /* Move active mcast entries to pending_add_q */
  514. while (!list_empty(&rxf->mcast_active_q)) {
  515. bfa_q_deq(&rxf->mcast_active_q, &qe);
  516. bfa_q_qe_init(qe);
  517. list_add_tail(qe, &rxf->mcast_pending_add_q);
  518. mac = (struct bna_mac *)qe;
  519. if (bna_rxf_mcast_del(rxf, mac, cleanup))
  520. return 1;
  521. }
  522. return 0;
  523. }
  524. static int
  525. bna_rxf_rss_cfg_apply(struct bna_rxf *rxf)
  526. {
  527. if (rxf->rss_pending) {
  528. if (rxf->rss_pending & BNA_RSS_F_RIT_PENDING) {
  529. rxf->rss_pending &= ~BNA_RSS_F_RIT_PENDING;
  530. bna_bfi_rit_cfg(rxf);
  531. return 1;
  532. }
  533. if (rxf->rss_pending & BNA_RSS_F_CFG_PENDING) {
  534. rxf->rss_pending &= ~BNA_RSS_F_CFG_PENDING;
  535. bna_bfi_rss_cfg(rxf);
  536. return 1;
  537. }
  538. if (rxf->rss_pending & BNA_RSS_F_STATUS_PENDING) {
  539. rxf->rss_pending &= ~BNA_RSS_F_STATUS_PENDING;
  540. bna_bfi_rss_enable(rxf);
  541. return 1;
  542. }
  543. }
  544. return 0;
  545. }
  546. static int
  547. bna_rxf_cfg_apply(struct bna_rxf *rxf)
  548. {
  549. if (bna_rxf_ucast_cfg_apply(rxf))
  550. return 1;
  551. if (bna_rxf_mcast_cfg_apply(rxf))
  552. return 1;
  553. if (bna_rxf_promisc_cfg_apply(rxf))
  554. return 1;
  555. if (bna_rxf_allmulti_cfg_apply(rxf))
  556. return 1;
  557. if (bna_rxf_vlan_cfg_apply(rxf))
  558. return 1;
  559. if (bna_rxf_vlan_strip_cfg_apply(rxf))
  560. return 1;
  561. if (bna_rxf_rss_cfg_apply(rxf))
  562. return 1;
  563. return 0;
  564. }
  565. /* Only software reset */
  566. static int
  567. bna_rxf_fltr_clear(struct bna_rxf *rxf)
  568. {
  569. if (bna_rxf_ucast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  570. return 1;
  571. if (bna_rxf_mcast_cfg_reset(rxf, BNA_HARD_CLEANUP))
  572. return 1;
  573. if (bna_rxf_promisc_cfg_reset(rxf, BNA_HARD_CLEANUP))
  574. return 1;
  575. if (bna_rxf_allmulti_cfg_reset(rxf, BNA_HARD_CLEANUP))
  576. return 1;
  577. return 0;
  578. }
  579. static void
  580. bna_rxf_cfg_reset(struct bna_rxf *rxf)
  581. {
  582. bna_rxf_ucast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  583. bna_rxf_mcast_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  584. bna_rxf_promisc_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  585. bna_rxf_allmulti_cfg_reset(rxf, BNA_SOFT_CLEANUP);
  586. bna_rxf_vlan_cfg_soft_reset(rxf);
  587. bna_rxf_rss_cfg_soft_reset(rxf);
  588. }
  589. static void
  590. bna_rit_init(struct bna_rxf *rxf, int rit_size)
  591. {
  592. struct bna_rx *rx = rxf->rx;
  593. struct bna_rxp *rxp;
  594. struct list_head *qe;
  595. int offset = 0;
  596. rxf->rit_size = rit_size;
  597. list_for_each(qe, &rx->rxp_q) {
  598. rxp = (struct bna_rxp *)qe;
  599. rxf->rit[offset] = rxp->cq.ccb->id;
  600. offset++;
  601. }
  602. }
  603. void
  604. bna_bfi_rxf_cfg_rsp(struct bna_rxf *rxf, struct bfi_msgq_mhdr *msghdr)
  605. {
  606. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  607. }
  608. void
  609. bna_bfi_rxf_mcast_add_rsp(struct bna_rxf *rxf,
  610. struct bfi_msgq_mhdr *msghdr)
  611. {
  612. struct bfi_enet_mcast_add_req *req =
  613. &rxf->bfi_enet_cmd.mcast_add_req;
  614. struct bfi_enet_mcast_add_rsp *rsp =
  615. (struct bfi_enet_mcast_add_rsp *)msghdr;
  616. bna_rxf_mchandle_attach(rxf, (u8 *)&req->mac_addr,
  617. ntohs(rsp->handle));
  618. bfa_fsm_send_event(rxf, RXF_E_FW_RESP);
  619. }
  620. static void
  621. bna_rxf_init(struct bna_rxf *rxf,
  622. struct bna_rx *rx,
  623. struct bna_rx_config *q_config,
  624. struct bna_res_info *res_info)
  625. {
  626. rxf->rx = rx;
  627. INIT_LIST_HEAD(&rxf->ucast_pending_add_q);
  628. INIT_LIST_HEAD(&rxf->ucast_pending_del_q);
  629. rxf->ucast_pending_set = 0;
  630. rxf->ucast_active_set = 0;
  631. INIT_LIST_HEAD(&rxf->ucast_active_q);
  632. rxf->ucast_pending_mac = NULL;
  633. INIT_LIST_HEAD(&rxf->mcast_pending_add_q);
  634. INIT_LIST_HEAD(&rxf->mcast_pending_del_q);
  635. INIT_LIST_HEAD(&rxf->mcast_active_q);
  636. INIT_LIST_HEAD(&rxf->mcast_handle_q);
  637. if (q_config->paused)
  638. rxf->flags |= BNA_RXF_F_PAUSED;
  639. rxf->rit = (u8 *)
  640. res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info.mdl[0].kva;
  641. bna_rit_init(rxf, q_config->num_paths);
  642. rxf->rss_status = q_config->rss_status;
  643. if (rxf->rss_status == BNA_STATUS_T_ENABLED) {
  644. rxf->rss_cfg = q_config->rss_config;
  645. rxf->rss_pending |= BNA_RSS_F_CFG_PENDING;
  646. rxf->rss_pending |= BNA_RSS_F_RIT_PENDING;
  647. rxf->rss_pending |= BNA_RSS_F_STATUS_PENDING;
  648. }
  649. rxf->vlan_filter_status = BNA_STATUS_T_DISABLED;
  650. memset(rxf->vlan_filter_table, 0,
  651. (sizeof(u32) * (BFI_ENET_VLAN_ID_MAX / 32)));
  652. rxf->vlan_filter_table[0] |= 1; /* for pure priority tagged frames */
  653. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  654. rxf->vlan_strip_status = q_config->vlan_strip_status;
  655. bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
  656. }
  657. static void
  658. bna_rxf_uninit(struct bna_rxf *rxf)
  659. {
  660. struct bna_mac *mac;
  661. rxf->ucast_pending_set = 0;
  662. rxf->ucast_active_set = 0;
  663. while (!list_empty(&rxf->ucast_pending_add_q)) {
  664. bfa_q_deq(&rxf->ucast_pending_add_q, &mac);
  665. bfa_q_qe_init(&mac->qe);
  666. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  667. }
  668. if (rxf->ucast_pending_mac) {
  669. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  670. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod,
  671. rxf->ucast_pending_mac);
  672. rxf->ucast_pending_mac = NULL;
  673. }
  674. while (!list_empty(&rxf->mcast_pending_add_q)) {
  675. bfa_q_deq(&rxf->mcast_pending_add_q, &mac);
  676. bfa_q_qe_init(&mac->qe);
  677. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  678. }
  679. rxf->rxmode_pending = 0;
  680. rxf->rxmode_pending_bitmask = 0;
  681. if (rxf->rx->bna->promisc_rid == rxf->rx->rid)
  682. rxf->rx->bna->promisc_rid = BFI_INVALID_RID;
  683. if (rxf->rx->bna->default_mode_rid == rxf->rx->rid)
  684. rxf->rx->bna->default_mode_rid = BFI_INVALID_RID;
  685. rxf->rss_pending = 0;
  686. rxf->vlan_strip_pending = false;
  687. rxf->flags = 0;
  688. rxf->rx = NULL;
  689. }
  690. static void
  691. bna_rx_cb_rxf_started(struct bna_rx *rx)
  692. {
  693. bfa_fsm_send_event(rx, RX_E_RXF_STARTED);
  694. }
  695. static void
  696. bna_rxf_start(struct bna_rxf *rxf)
  697. {
  698. rxf->start_cbfn = bna_rx_cb_rxf_started;
  699. rxf->start_cbarg = rxf->rx;
  700. bfa_fsm_send_event(rxf, RXF_E_START);
  701. }
  702. static void
  703. bna_rx_cb_rxf_stopped(struct bna_rx *rx)
  704. {
  705. bfa_fsm_send_event(rx, RX_E_RXF_STOPPED);
  706. }
  707. static void
  708. bna_rxf_stop(struct bna_rxf *rxf)
  709. {
  710. rxf->stop_cbfn = bna_rx_cb_rxf_stopped;
  711. rxf->stop_cbarg = rxf->rx;
  712. bfa_fsm_send_event(rxf, RXF_E_STOP);
  713. }
  714. static void
  715. bna_rxf_fail(struct bna_rxf *rxf)
  716. {
  717. bfa_fsm_send_event(rxf, RXF_E_FAIL);
  718. }
  719. enum bna_cb_status
  720. bna_rx_ucast_set(struct bna_rx *rx, u8 *ucmac,
  721. void (*cbfn)(struct bnad *, struct bna_rx *))
  722. {
  723. struct bna_rxf *rxf = &rx->rxf;
  724. if (rxf->ucast_pending_mac == NULL) {
  725. rxf->ucast_pending_mac =
  726. bna_ucam_mod_mac_get(&rxf->rx->bna->ucam_mod);
  727. if (rxf->ucast_pending_mac == NULL)
  728. return BNA_CB_UCAST_CAM_FULL;
  729. bfa_q_qe_init(&rxf->ucast_pending_mac->qe);
  730. }
  731. memcpy(rxf->ucast_pending_mac->addr, ucmac, ETH_ALEN);
  732. rxf->ucast_pending_set = 1;
  733. rxf->cam_fltr_cbfn = cbfn;
  734. rxf->cam_fltr_cbarg = rx->bna->bnad;
  735. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  736. return BNA_CB_SUCCESS;
  737. }
  738. enum bna_cb_status
  739. bna_rx_mcast_add(struct bna_rx *rx, u8 *addr,
  740. void (*cbfn)(struct bnad *, struct bna_rx *))
  741. {
  742. struct bna_rxf *rxf = &rx->rxf;
  743. struct bna_mac *mac;
  744. /* Check if already added or pending addition */
  745. if (bna_mac_find(&rxf->mcast_active_q, addr) ||
  746. bna_mac_find(&rxf->mcast_pending_add_q, addr)) {
  747. if (cbfn)
  748. cbfn(rx->bna->bnad, rx);
  749. return BNA_CB_SUCCESS;
  750. }
  751. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  752. if (mac == NULL)
  753. return BNA_CB_MCAST_LIST_FULL;
  754. bfa_q_qe_init(&mac->qe);
  755. memcpy(mac->addr, addr, ETH_ALEN);
  756. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  757. rxf->cam_fltr_cbfn = cbfn;
  758. rxf->cam_fltr_cbarg = rx->bna->bnad;
  759. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  760. return BNA_CB_SUCCESS;
  761. }
  762. enum bna_cb_status
  763. bna_rx_mcast_listset(struct bna_rx *rx, int count, u8 *mclist,
  764. void (*cbfn)(struct bnad *, struct bna_rx *))
  765. {
  766. struct bna_rxf *rxf = &rx->rxf;
  767. struct list_head list_head;
  768. struct list_head *qe;
  769. u8 *mcaddr;
  770. struct bna_mac *mac;
  771. int i;
  772. /* Allocate nodes */
  773. INIT_LIST_HEAD(&list_head);
  774. for (i = 0, mcaddr = mclist; i < count; i++) {
  775. mac = bna_mcam_mod_mac_get(&rxf->rx->bna->mcam_mod);
  776. if (mac == NULL)
  777. goto err_return;
  778. bfa_q_qe_init(&mac->qe);
  779. memcpy(mac->addr, mcaddr, ETH_ALEN);
  780. list_add_tail(&mac->qe, &list_head);
  781. mcaddr += ETH_ALEN;
  782. }
  783. /* Purge the pending_add_q */
  784. while (!list_empty(&rxf->mcast_pending_add_q)) {
  785. bfa_q_deq(&rxf->mcast_pending_add_q, &qe);
  786. bfa_q_qe_init(qe);
  787. mac = (struct bna_mac *)qe;
  788. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  789. }
  790. /* Schedule active_q entries for deletion */
  791. while (!list_empty(&rxf->mcast_active_q)) {
  792. bfa_q_deq(&rxf->mcast_active_q, &qe);
  793. mac = (struct bna_mac *)qe;
  794. bfa_q_qe_init(&mac->qe);
  795. list_add_tail(&mac->qe, &rxf->mcast_pending_del_q);
  796. }
  797. /* Add the new entries */
  798. while (!list_empty(&list_head)) {
  799. bfa_q_deq(&list_head, &qe);
  800. mac = (struct bna_mac *)qe;
  801. bfa_q_qe_init(&mac->qe);
  802. list_add_tail(&mac->qe, &rxf->mcast_pending_add_q);
  803. }
  804. rxf->cam_fltr_cbfn = cbfn;
  805. rxf->cam_fltr_cbarg = rx->bna->bnad;
  806. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  807. return BNA_CB_SUCCESS;
  808. err_return:
  809. while (!list_empty(&list_head)) {
  810. bfa_q_deq(&list_head, &qe);
  811. mac = (struct bna_mac *)qe;
  812. bfa_q_qe_init(&mac->qe);
  813. bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
  814. }
  815. return BNA_CB_MCAST_LIST_FULL;
  816. }
  817. void
  818. bna_rx_vlan_add(struct bna_rx *rx, int vlan_id)
  819. {
  820. struct bna_rxf *rxf = &rx->rxf;
  821. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  822. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  823. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  824. rxf->vlan_filter_table[index] |= bit;
  825. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  826. rxf->vlan_pending_bitmask |= (1 << group_id);
  827. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  828. }
  829. }
  830. void
  831. bna_rx_vlan_del(struct bna_rx *rx, int vlan_id)
  832. {
  833. struct bna_rxf *rxf = &rx->rxf;
  834. int index = (vlan_id >> BFI_VLAN_WORD_SHIFT);
  835. int bit = (1 << (vlan_id & BFI_VLAN_WORD_MASK));
  836. int group_id = (vlan_id >> BFI_VLAN_BLOCK_SHIFT);
  837. rxf->vlan_filter_table[index] &= ~bit;
  838. if (rxf->vlan_filter_status == BNA_STATUS_T_ENABLED) {
  839. rxf->vlan_pending_bitmask |= (1 << group_id);
  840. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  841. }
  842. }
  843. static int
  844. bna_rxf_ucast_cfg_apply(struct bna_rxf *rxf)
  845. {
  846. struct bna_mac *mac = NULL;
  847. struct list_head *qe;
  848. /* Delete MAC addresses previousely added */
  849. if (!list_empty(&rxf->ucast_pending_del_q)) {
  850. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  851. bfa_q_qe_init(qe);
  852. mac = (struct bna_mac *)qe;
  853. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  854. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  855. return 1;
  856. }
  857. /* Set default unicast MAC */
  858. if (rxf->ucast_pending_set) {
  859. rxf->ucast_pending_set = 0;
  860. memcpy(rxf->ucast_active_mac.addr,
  861. rxf->ucast_pending_mac->addr, ETH_ALEN);
  862. rxf->ucast_active_set = 1;
  863. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  864. BFI_ENET_H2I_MAC_UCAST_SET_REQ);
  865. return 1;
  866. }
  867. /* Add additional MAC entries */
  868. if (!list_empty(&rxf->ucast_pending_add_q)) {
  869. bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
  870. bfa_q_qe_init(qe);
  871. mac = (struct bna_mac *)qe;
  872. list_add_tail(&mac->qe, &rxf->ucast_active_q);
  873. bna_bfi_ucast_req(rxf, mac, BFI_ENET_H2I_MAC_UCAST_ADD_REQ);
  874. return 1;
  875. }
  876. return 0;
  877. }
  878. static int
  879. bna_rxf_ucast_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  880. {
  881. struct list_head *qe;
  882. struct bna_mac *mac;
  883. /* Throw away delete pending ucast entries */
  884. while (!list_empty(&rxf->ucast_pending_del_q)) {
  885. bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
  886. bfa_q_qe_init(qe);
  887. mac = (struct bna_mac *)qe;
  888. if (cleanup == BNA_SOFT_CLEANUP)
  889. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  890. else {
  891. bna_bfi_ucast_req(rxf, mac,
  892. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  893. bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
  894. return 1;
  895. }
  896. }
  897. /* Move active ucast entries to pending_add_q */
  898. while (!list_empty(&rxf->ucast_active_q)) {
  899. bfa_q_deq(&rxf->ucast_active_q, &qe);
  900. bfa_q_qe_init(qe);
  901. list_add_tail(qe, &rxf->ucast_pending_add_q);
  902. if (cleanup == BNA_HARD_CLEANUP) {
  903. mac = (struct bna_mac *)qe;
  904. bna_bfi_ucast_req(rxf, mac,
  905. BFI_ENET_H2I_MAC_UCAST_DEL_REQ);
  906. return 1;
  907. }
  908. }
  909. if (rxf->ucast_active_set) {
  910. rxf->ucast_pending_set = 1;
  911. rxf->ucast_active_set = 0;
  912. if (cleanup == BNA_HARD_CLEANUP) {
  913. bna_bfi_ucast_req(rxf, &rxf->ucast_active_mac,
  914. BFI_ENET_H2I_MAC_UCAST_CLR_REQ);
  915. return 1;
  916. }
  917. }
  918. return 0;
  919. }
  920. static int
  921. bna_rxf_promisc_cfg_apply(struct bna_rxf *rxf)
  922. {
  923. struct bna *bna = rxf->rx->bna;
  924. /* Enable/disable promiscuous mode */
  925. if (is_promisc_enable(rxf->rxmode_pending,
  926. rxf->rxmode_pending_bitmask)) {
  927. /* move promisc configuration from pending -> active */
  928. promisc_inactive(rxf->rxmode_pending,
  929. rxf->rxmode_pending_bitmask);
  930. rxf->rxmode_active |= BNA_RXMODE_PROMISC;
  931. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_ENABLED);
  932. return 1;
  933. } else if (is_promisc_disable(rxf->rxmode_pending,
  934. rxf->rxmode_pending_bitmask)) {
  935. /* move promisc configuration from pending -> active */
  936. promisc_inactive(rxf->rxmode_pending,
  937. rxf->rxmode_pending_bitmask);
  938. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  939. bna->promisc_rid = BFI_INVALID_RID;
  940. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  941. return 1;
  942. }
  943. return 0;
  944. }
  945. static int
  946. bna_rxf_promisc_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  947. {
  948. struct bna *bna = rxf->rx->bna;
  949. /* Clear pending promisc mode disable */
  950. if (is_promisc_disable(rxf->rxmode_pending,
  951. rxf->rxmode_pending_bitmask)) {
  952. promisc_inactive(rxf->rxmode_pending,
  953. rxf->rxmode_pending_bitmask);
  954. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  955. bna->promisc_rid = BFI_INVALID_RID;
  956. if (cleanup == BNA_HARD_CLEANUP) {
  957. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  958. return 1;
  959. }
  960. }
  961. /* Move promisc mode config from active -> pending */
  962. if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  963. promisc_enable(rxf->rxmode_pending,
  964. rxf->rxmode_pending_bitmask);
  965. rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
  966. if (cleanup == BNA_HARD_CLEANUP) {
  967. bna_bfi_rx_promisc_req(rxf, BNA_STATUS_T_DISABLED);
  968. return 1;
  969. }
  970. }
  971. return 0;
  972. }
  973. static int
  974. bna_rxf_allmulti_cfg_apply(struct bna_rxf *rxf)
  975. {
  976. /* Enable/disable allmulti mode */
  977. if (is_allmulti_enable(rxf->rxmode_pending,
  978. rxf->rxmode_pending_bitmask)) {
  979. /* move allmulti configuration from pending -> active */
  980. allmulti_inactive(rxf->rxmode_pending,
  981. rxf->rxmode_pending_bitmask);
  982. rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
  983. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_DISABLED);
  984. return 1;
  985. } else if (is_allmulti_disable(rxf->rxmode_pending,
  986. rxf->rxmode_pending_bitmask)) {
  987. /* move allmulti configuration from pending -> active */
  988. allmulti_inactive(rxf->rxmode_pending,
  989. rxf->rxmode_pending_bitmask);
  990. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  991. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  992. return 1;
  993. }
  994. return 0;
  995. }
  996. static int
  997. bna_rxf_allmulti_cfg_reset(struct bna_rxf *rxf, enum bna_cleanup_type cleanup)
  998. {
  999. /* Clear pending allmulti mode disable */
  1000. if (is_allmulti_disable(rxf->rxmode_pending,
  1001. rxf->rxmode_pending_bitmask)) {
  1002. allmulti_inactive(rxf->rxmode_pending,
  1003. rxf->rxmode_pending_bitmask);
  1004. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1005. if (cleanup == BNA_HARD_CLEANUP) {
  1006. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1007. return 1;
  1008. }
  1009. }
  1010. /* Move allmulti mode config from active -> pending */
  1011. if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1012. allmulti_enable(rxf->rxmode_pending,
  1013. rxf->rxmode_pending_bitmask);
  1014. rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
  1015. if (cleanup == BNA_HARD_CLEANUP) {
  1016. bna_bfi_mcast_filter_req(rxf, BNA_STATUS_T_ENABLED);
  1017. return 1;
  1018. }
  1019. }
  1020. return 0;
  1021. }
  1022. static int
  1023. bna_rxf_promisc_enable(struct bna_rxf *rxf)
  1024. {
  1025. struct bna *bna = rxf->rx->bna;
  1026. int ret = 0;
  1027. if (is_promisc_enable(rxf->rxmode_pending,
  1028. rxf->rxmode_pending_bitmask) ||
  1029. (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
  1030. /* Do nothing if pending enable or already enabled */
  1031. } else if (is_promisc_disable(rxf->rxmode_pending,
  1032. rxf->rxmode_pending_bitmask)) {
  1033. /* Turn off pending disable command */
  1034. promisc_inactive(rxf->rxmode_pending,
  1035. rxf->rxmode_pending_bitmask);
  1036. } else {
  1037. /* Schedule enable */
  1038. promisc_enable(rxf->rxmode_pending,
  1039. rxf->rxmode_pending_bitmask);
  1040. bna->promisc_rid = rxf->rx->rid;
  1041. ret = 1;
  1042. }
  1043. return ret;
  1044. }
  1045. static int
  1046. bna_rxf_promisc_disable(struct bna_rxf *rxf)
  1047. {
  1048. struct bna *bna = rxf->rx->bna;
  1049. int ret = 0;
  1050. if (is_promisc_disable(rxf->rxmode_pending,
  1051. rxf->rxmode_pending_bitmask) ||
  1052. (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))) {
  1053. /* Do nothing if pending disable or already disabled */
  1054. } else if (is_promisc_enable(rxf->rxmode_pending,
  1055. rxf->rxmode_pending_bitmask)) {
  1056. /* Turn off pending enable command */
  1057. promisc_inactive(rxf->rxmode_pending,
  1058. rxf->rxmode_pending_bitmask);
  1059. bna->promisc_rid = BFI_INVALID_RID;
  1060. } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
  1061. /* Schedule disable */
  1062. promisc_disable(rxf->rxmode_pending,
  1063. rxf->rxmode_pending_bitmask);
  1064. ret = 1;
  1065. }
  1066. return ret;
  1067. }
  1068. static int
  1069. bna_rxf_allmulti_enable(struct bna_rxf *rxf)
  1070. {
  1071. int ret = 0;
  1072. if (is_allmulti_enable(rxf->rxmode_pending,
  1073. rxf->rxmode_pending_bitmask) ||
  1074. (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
  1075. /* Do nothing if pending enable or already enabled */
  1076. } else if (is_allmulti_disable(rxf->rxmode_pending,
  1077. rxf->rxmode_pending_bitmask)) {
  1078. /* Turn off pending disable command */
  1079. allmulti_inactive(rxf->rxmode_pending,
  1080. rxf->rxmode_pending_bitmask);
  1081. } else {
  1082. /* Schedule enable */
  1083. allmulti_enable(rxf->rxmode_pending,
  1084. rxf->rxmode_pending_bitmask);
  1085. ret = 1;
  1086. }
  1087. return ret;
  1088. }
  1089. static int
  1090. bna_rxf_allmulti_disable(struct bna_rxf *rxf)
  1091. {
  1092. int ret = 0;
  1093. if (is_allmulti_disable(rxf->rxmode_pending,
  1094. rxf->rxmode_pending_bitmask) ||
  1095. (!(rxf->rxmode_active & BNA_RXMODE_ALLMULTI))) {
  1096. /* Do nothing if pending disable or already disabled */
  1097. } else if (is_allmulti_enable(rxf->rxmode_pending,
  1098. rxf->rxmode_pending_bitmask)) {
  1099. /* Turn off pending enable command */
  1100. allmulti_inactive(rxf->rxmode_pending,
  1101. rxf->rxmode_pending_bitmask);
  1102. } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
  1103. /* Schedule disable */
  1104. allmulti_disable(rxf->rxmode_pending,
  1105. rxf->rxmode_pending_bitmask);
  1106. ret = 1;
  1107. }
  1108. return ret;
  1109. }
  1110. static int
  1111. bna_rxf_vlan_strip_cfg_apply(struct bna_rxf *rxf)
  1112. {
  1113. if (rxf->vlan_strip_pending) {
  1114. rxf->vlan_strip_pending = false;
  1115. bna_bfi_vlan_strip_enable(rxf);
  1116. return 1;
  1117. }
  1118. return 0;
  1119. }
  1120. /* RX */
  1121. #define BNA_GET_RXQS(qcfg) (((qcfg)->rxp_type == BNA_RXP_SINGLE) ? \
  1122. (qcfg)->num_paths : ((qcfg)->num_paths * 2))
  1123. #define SIZE_TO_PAGES(size) (((size) >> PAGE_SHIFT) + ((((size) &\
  1124. (PAGE_SIZE - 1)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT))
  1125. #define call_rx_stop_cbfn(rx) \
  1126. do { \
  1127. if ((rx)->stop_cbfn) { \
  1128. void (*cbfn)(void *, struct bna_rx *); \
  1129. void *cbarg; \
  1130. cbfn = (rx)->stop_cbfn; \
  1131. cbarg = (rx)->stop_cbarg; \
  1132. (rx)->stop_cbfn = NULL; \
  1133. (rx)->stop_cbarg = NULL; \
  1134. cbfn(cbarg, rx); \
  1135. } \
  1136. } while (0)
  1137. #define call_rx_stall_cbfn(rx) \
  1138. do { \
  1139. if ((rx)->rx_stall_cbfn) \
  1140. (rx)->rx_stall_cbfn((rx)->bna->bnad, (rx)); \
  1141. } while (0)
  1142. #define bfi_enet_datapath_q_init(bfi_q, bna_qpt) \
  1143. do { \
  1144. struct bna_dma_addr cur_q_addr = \
  1145. *((struct bna_dma_addr *)((bna_qpt)->kv_qpt_ptr)); \
  1146. (bfi_q)->pg_tbl.a32.addr_lo = (bna_qpt)->hw_qpt_ptr.lsb; \
  1147. (bfi_q)->pg_tbl.a32.addr_hi = (bna_qpt)->hw_qpt_ptr.msb; \
  1148. (bfi_q)->first_entry.a32.addr_lo = cur_q_addr.lsb; \
  1149. (bfi_q)->first_entry.a32.addr_hi = cur_q_addr.msb; \
  1150. (bfi_q)->pages = htons((u16)(bna_qpt)->page_count); \
  1151. (bfi_q)->page_sz = htons((u16)(bna_qpt)->page_size);\
  1152. } while (0)
  1153. static void bna_bfi_rx_enet_start(struct bna_rx *rx);
  1154. static void bna_rx_enet_stop(struct bna_rx *rx);
  1155. static void bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx);
  1156. bfa_fsm_state_decl(bna_rx, stopped,
  1157. struct bna_rx, enum bna_rx_event);
  1158. bfa_fsm_state_decl(bna_rx, start_wait,
  1159. struct bna_rx, enum bna_rx_event);
  1160. bfa_fsm_state_decl(bna_rx, start_stop_wait,
  1161. struct bna_rx, enum bna_rx_event);
  1162. bfa_fsm_state_decl(bna_rx, rxf_start_wait,
  1163. struct bna_rx, enum bna_rx_event);
  1164. bfa_fsm_state_decl(bna_rx, started,
  1165. struct bna_rx, enum bna_rx_event);
  1166. bfa_fsm_state_decl(bna_rx, rxf_stop_wait,
  1167. struct bna_rx, enum bna_rx_event);
  1168. bfa_fsm_state_decl(bna_rx, stop_wait,
  1169. struct bna_rx, enum bna_rx_event);
  1170. bfa_fsm_state_decl(bna_rx, cleanup_wait,
  1171. struct bna_rx, enum bna_rx_event);
  1172. bfa_fsm_state_decl(bna_rx, failed,
  1173. struct bna_rx, enum bna_rx_event);
  1174. bfa_fsm_state_decl(bna_rx, quiesce_wait,
  1175. struct bna_rx, enum bna_rx_event);
  1176. static void bna_rx_sm_stopped_entry(struct bna_rx *rx)
  1177. {
  1178. call_rx_stop_cbfn(rx);
  1179. }
  1180. static void bna_rx_sm_stopped(struct bna_rx *rx,
  1181. enum bna_rx_event event)
  1182. {
  1183. switch (event) {
  1184. case RX_E_START:
  1185. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1186. break;
  1187. case RX_E_STOP:
  1188. call_rx_stop_cbfn(rx);
  1189. break;
  1190. case RX_E_FAIL:
  1191. /* no-op */
  1192. break;
  1193. default:
  1194. bfa_sm_fault(event);
  1195. break;
  1196. }
  1197. }
  1198. static void bna_rx_sm_start_wait_entry(struct bna_rx *rx)
  1199. {
  1200. bna_bfi_rx_enet_start(rx);
  1201. }
  1202. void
  1203. bna_rx_sm_stop_wait_entry(struct bna_rx *rx)
  1204. {
  1205. }
  1206. static void
  1207. bna_rx_sm_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1208. {
  1209. switch (event) {
  1210. case RX_E_FAIL:
  1211. case RX_E_STOPPED:
  1212. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1213. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1214. break;
  1215. case RX_E_STARTED:
  1216. bna_rx_enet_stop(rx);
  1217. break;
  1218. default:
  1219. bfa_sm_fault(event);
  1220. break;
  1221. }
  1222. }
  1223. static void bna_rx_sm_start_wait(struct bna_rx *rx,
  1224. enum bna_rx_event event)
  1225. {
  1226. switch (event) {
  1227. case RX_E_STOP:
  1228. bfa_fsm_set_state(rx, bna_rx_sm_start_stop_wait);
  1229. break;
  1230. case RX_E_FAIL:
  1231. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1232. break;
  1233. case RX_E_STARTED:
  1234. bfa_fsm_set_state(rx, bna_rx_sm_rxf_start_wait);
  1235. break;
  1236. default:
  1237. bfa_sm_fault(event);
  1238. break;
  1239. }
  1240. }
  1241. static void bna_rx_sm_rxf_start_wait_entry(struct bna_rx *rx)
  1242. {
  1243. rx->rx_post_cbfn(rx->bna->bnad, rx);
  1244. bna_rxf_start(&rx->rxf);
  1245. }
  1246. void
  1247. bna_rx_sm_rxf_stop_wait_entry(struct bna_rx *rx)
  1248. {
  1249. }
  1250. static void
  1251. bna_rx_sm_rxf_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1252. {
  1253. switch (event) {
  1254. case RX_E_FAIL:
  1255. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1256. bna_rxf_fail(&rx->rxf);
  1257. call_rx_stall_cbfn(rx);
  1258. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1259. break;
  1260. case RX_E_RXF_STARTED:
  1261. bna_rxf_stop(&rx->rxf);
  1262. break;
  1263. case RX_E_RXF_STOPPED:
  1264. bfa_fsm_set_state(rx, bna_rx_sm_stop_wait);
  1265. call_rx_stall_cbfn(rx);
  1266. bna_rx_enet_stop(rx);
  1267. break;
  1268. default:
  1269. bfa_sm_fault(event);
  1270. break;
  1271. }
  1272. }
  1273. static void
  1274. bna_rx_sm_start_stop_wait_entry(struct bna_rx *rx)
  1275. {
  1276. }
  1277. static void
  1278. bna_rx_sm_start_stop_wait(struct bna_rx *rx, enum bna_rx_event event)
  1279. {
  1280. switch (event) {
  1281. case RX_E_FAIL:
  1282. case RX_E_STOPPED:
  1283. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1284. break;
  1285. case RX_E_STARTED:
  1286. bna_rx_enet_stop(rx);
  1287. break;
  1288. default:
  1289. bfa_sm_fault(event);
  1290. }
  1291. }
  1292. void
  1293. bna_rx_sm_started_entry(struct bna_rx *rx)
  1294. {
  1295. struct bna_rxp *rxp;
  1296. struct list_head *qe_rxp;
  1297. int is_regular = (rx->type == BNA_RX_T_REGULAR);
  1298. /* Start IB */
  1299. list_for_each(qe_rxp, &rx->rxp_q) {
  1300. rxp = (struct bna_rxp *)qe_rxp;
  1301. bna_ib_start(rx->bna, &rxp->cq.ib, is_regular);
  1302. }
  1303. bna_ethport_cb_rx_started(&rx->bna->ethport);
  1304. }
  1305. static void
  1306. bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
  1307. {
  1308. switch (event) {
  1309. case RX_E_STOP:
  1310. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1311. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1312. bna_rxf_stop(&rx->rxf);
  1313. break;
  1314. case RX_E_FAIL:
  1315. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1316. bna_ethport_cb_rx_stopped(&rx->bna->ethport);
  1317. bna_rxf_fail(&rx->rxf);
  1318. call_rx_stall_cbfn(rx);
  1319. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1320. break;
  1321. default:
  1322. bfa_sm_fault(event);
  1323. break;
  1324. }
  1325. }
  1326. static void bna_rx_sm_rxf_start_wait(struct bna_rx *rx,
  1327. enum bna_rx_event event)
  1328. {
  1329. switch (event) {
  1330. case RX_E_STOP:
  1331. bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
  1332. break;
  1333. case RX_E_FAIL:
  1334. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1335. bna_rxf_fail(&rx->rxf);
  1336. call_rx_stall_cbfn(rx);
  1337. rx->rx_cleanup_cbfn(rx->bna->bnad, rx);
  1338. break;
  1339. case RX_E_RXF_STARTED:
  1340. bfa_fsm_set_state(rx, bna_rx_sm_started);
  1341. break;
  1342. default:
  1343. bfa_sm_fault(event);
  1344. break;
  1345. }
  1346. }
  1347. void
  1348. bna_rx_sm_cleanup_wait_entry(struct bna_rx *rx)
  1349. {
  1350. }
  1351. void
  1352. bna_rx_sm_cleanup_wait(struct bna_rx *rx, enum bna_rx_event event)
  1353. {
  1354. switch (event) {
  1355. case RX_E_FAIL:
  1356. case RX_E_RXF_STOPPED:
  1357. /* No-op */
  1358. break;
  1359. case RX_E_CLEANUP_DONE:
  1360. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1361. break;
  1362. default:
  1363. bfa_sm_fault(event);
  1364. break;
  1365. }
  1366. }
  1367. static void
  1368. bna_rx_sm_failed_entry(struct bna_rx *rx)
  1369. {
  1370. }
  1371. static void
  1372. bna_rx_sm_failed(struct bna_rx *rx, enum bna_rx_event event)
  1373. {
  1374. switch (event) {
  1375. case RX_E_START:
  1376. bfa_fsm_set_state(rx, bna_rx_sm_quiesce_wait);
  1377. break;
  1378. case RX_E_STOP:
  1379. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1380. break;
  1381. case RX_E_FAIL:
  1382. case RX_E_RXF_STARTED:
  1383. case RX_E_RXF_STOPPED:
  1384. /* No-op */
  1385. break;
  1386. case RX_E_CLEANUP_DONE:
  1387. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  1388. break;
  1389. default:
  1390. bfa_sm_fault(event);
  1391. break;
  1392. } }
  1393. static void
  1394. bna_rx_sm_quiesce_wait_entry(struct bna_rx *rx)
  1395. {
  1396. }
  1397. static void
  1398. bna_rx_sm_quiesce_wait(struct bna_rx *rx, enum bna_rx_event event)
  1399. {
  1400. switch (event) {
  1401. case RX_E_STOP:
  1402. bfa_fsm_set_state(rx, bna_rx_sm_cleanup_wait);
  1403. break;
  1404. case RX_E_FAIL:
  1405. bfa_fsm_set_state(rx, bna_rx_sm_failed);
  1406. break;
  1407. case RX_E_CLEANUP_DONE:
  1408. bfa_fsm_set_state(rx, bna_rx_sm_start_wait);
  1409. break;
  1410. default:
  1411. bfa_sm_fault(event);
  1412. break;
  1413. }
  1414. }
  1415. static void
  1416. bna_bfi_rx_enet_start(struct bna_rx *rx)
  1417. {
  1418. struct bfi_enet_rx_cfg_req *cfg_req = &rx->bfi_enet_cmd.cfg_req;
  1419. struct bna_rxp *rxp = NULL;
  1420. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1421. struct list_head *rxp_qe;
  1422. int i;
  1423. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  1424. BFI_ENET_H2I_RX_CFG_SET_REQ, 0, rx->rid);
  1425. cfg_req->mh.num_entries = htons(
  1426. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_rx_cfg_req)));
  1427. cfg_req->num_queue_sets = rx->num_paths;
  1428. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1429. i < rx->num_paths;
  1430. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1431. rxp = (struct bna_rxp *)rxp_qe;
  1432. GET_RXQS(rxp, q0, q1);
  1433. switch (rxp->type) {
  1434. case BNA_RXP_SLR:
  1435. case BNA_RXP_HDS:
  1436. /* Small RxQ */
  1437. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].qs.q,
  1438. &q1->qpt);
  1439. cfg_req->q_cfg[i].qs.rx_buffer_size =
  1440. htons((u16)q1->buffer_size);
  1441. /* Fall through */
  1442. case BNA_RXP_SINGLE:
  1443. /* Large/Single RxQ */
  1444. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].ql.q,
  1445. &q0->qpt);
  1446. q0->buffer_size =
  1447. bna_enet_mtu_get(&rx->bna->enet);
  1448. cfg_req->q_cfg[i].ql.rx_buffer_size =
  1449. htons((u16)q0->buffer_size);
  1450. break;
  1451. default:
  1452. BUG_ON(1);
  1453. }
  1454. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].cq.q,
  1455. &rxp->cq.qpt);
  1456. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  1457. rxp->cq.ib.ib_seg_host_addr.lsb;
  1458. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  1459. rxp->cq.ib.ib_seg_host_addr.msb;
  1460. cfg_req->q_cfg[i].ib.intr.msix_index =
  1461. htons((u16)rxp->cq.ib.intr_vector);
  1462. }
  1463. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_DISABLED;
  1464. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  1465. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  1466. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_DISABLED;
  1467. cfg_req->ib_cfg.msix = (rxp->cq.ib.intr_type == BNA_INTR_T_MSIX)
  1468. ? BNA_STATUS_T_ENABLED :
  1469. BNA_STATUS_T_DISABLED;
  1470. cfg_req->ib_cfg.coalescing_timeout =
  1471. htonl((u32)rxp->cq.ib.coalescing_timeo);
  1472. cfg_req->ib_cfg.inter_pkt_timeout =
  1473. htonl((u32)rxp->cq.ib.interpkt_timeo);
  1474. cfg_req->ib_cfg.inter_pkt_count = (u8)rxp->cq.ib.interpkt_count;
  1475. switch (rxp->type) {
  1476. case BNA_RXP_SLR:
  1477. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_LARGE_SMALL;
  1478. break;
  1479. case BNA_RXP_HDS:
  1480. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_HDS;
  1481. cfg_req->rx_cfg.hds.type = rx->hds_cfg.hdr_type;
  1482. cfg_req->rx_cfg.hds.force_offset = rx->hds_cfg.forced_offset;
  1483. cfg_req->rx_cfg.hds.max_header_size = rx->hds_cfg.forced_offset;
  1484. break;
  1485. case BNA_RXP_SINGLE:
  1486. cfg_req->rx_cfg.rxq_type = BFI_ENET_RXQ_SINGLE;
  1487. break;
  1488. default:
  1489. BUG_ON(1);
  1490. }
  1491. cfg_req->rx_cfg.strip_vlan = rx->rxf.vlan_strip_status;
  1492. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL,
  1493. sizeof(struct bfi_enet_rx_cfg_req), &cfg_req->mh);
  1494. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1495. }
  1496. static void
  1497. bna_bfi_rx_enet_stop(struct bna_rx *rx)
  1498. {
  1499. struct bfi_enet_req *req = &rx->bfi_enet_cmd.req;
  1500. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  1501. BFI_ENET_H2I_RX_CFG_CLR_REQ, 0, rx->rid);
  1502. req->mh.num_entries = htons(
  1503. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  1504. bfa_msgq_cmd_set(&rx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  1505. &req->mh);
  1506. bfa_msgq_cmd_post(&rx->bna->msgq, &rx->msgq_cmd);
  1507. }
  1508. static void
  1509. bna_rx_enet_stop(struct bna_rx *rx)
  1510. {
  1511. struct bna_rxp *rxp;
  1512. struct list_head *qe_rxp;
  1513. /* Stop IB */
  1514. list_for_each(qe_rxp, &rx->rxp_q) {
  1515. rxp = (struct bna_rxp *)qe_rxp;
  1516. bna_ib_stop(rx->bna, &rxp->cq.ib);
  1517. }
  1518. bna_bfi_rx_enet_stop(rx);
  1519. }
  1520. static int
  1521. bna_rx_res_check(struct bna_rx_mod *rx_mod, struct bna_rx_config *rx_cfg)
  1522. {
  1523. if ((rx_mod->rx_free_count == 0) ||
  1524. (rx_mod->rxp_free_count == 0) ||
  1525. (rx_mod->rxq_free_count == 0))
  1526. return 0;
  1527. if (rx_cfg->rxp_type == BNA_RXP_SINGLE) {
  1528. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1529. (rx_mod->rxq_free_count < rx_cfg->num_paths))
  1530. return 0;
  1531. } else {
  1532. if ((rx_mod->rxp_free_count < rx_cfg->num_paths) ||
  1533. (rx_mod->rxq_free_count < (2 * rx_cfg->num_paths)))
  1534. return 0;
  1535. }
  1536. return 1;
  1537. }
  1538. static struct bna_rxq *
  1539. bna_rxq_get(struct bna_rx_mod *rx_mod)
  1540. {
  1541. struct bna_rxq *rxq = NULL;
  1542. struct list_head *qe = NULL;
  1543. bfa_q_deq(&rx_mod->rxq_free_q, &qe);
  1544. rx_mod->rxq_free_count--;
  1545. rxq = (struct bna_rxq *)qe;
  1546. bfa_q_qe_init(&rxq->qe);
  1547. return rxq;
  1548. }
  1549. static void
  1550. bna_rxq_put(struct bna_rx_mod *rx_mod, struct bna_rxq *rxq)
  1551. {
  1552. bfa_q_qe_init(&rxq->qe);
  1553. list_add_tail(&rxq->qe, &rx_mod->rxq_free_q);
  1554. rx_mod->rxq_free_count++;
  1555. }
  1556. static struct bna_rxp *
  1557. bna_rxp_get(struct bna_rx_mod *rx_mod)
  1558. {
  1559. struct list_head *qe = NULL;
  1560. struct bna_rxp *rxp = NULL;
  1561. bfa_q_deq(&rx_mod->rxp_free_q, &qe);
  1562. rx_mod->rxp_free_count--;
  1563. rxp = (struct bna_rxp *)qe;
  1564. bfa_q_qe_init(&rxp->qe);
  1565. return rxp;
  1566. }
  1567. static void
  1568. bna_rxp_put(struct bna_rx_mod *rx_mod, struct bna_rxp *rxp)
  1569. {
  1570. bfa_q_qe_init(&rxp->qe);
  1571. list_add_tail(&rxp->qe, &rx_mod->rxp_free_q);
  1572. rx_mod->rxp_free_count++;
  1573. }
  1574. static struct bna_rx *
  1575. bna_rx_get(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1576. {
  1577. struct list_head *qe = NULL;
  1578. struct bna_rx *rx = NULL;
  1579. if (type == BNA_RX_T_REGULAR) {
  1580. bfa_q_deq(&rx_mod->rx_free_q, &qe);
  1581. } else
  1582. bfa_q_deq_tail(&rx_mod->rx_free_q, &qe);
  1583. rx_mod->rx_free_count--;
  1584. rx = (struct bna_rx *)qe;
  1585. bfa_q_qe_init(&rx->qe);
  1586. list_add_tail(&rx->qe, &rx_mod->rx_active_q);
  1587. rx->type = type;
  1588. return rx;
  1589. }
  1590. static void
  1591. bna_rx_put(struct bna_rx_mod *rx_mod, struct bna_rx *rx)
  1592. {
  1593. struct list_head *prev_qe = NULL;
  1594. struct list_head *qe;
  1595. bfa_q_qe_init(&rx->qe);
  1596. list_for_each(qe, &rx_mod->rx_free_q) {
  1597. if (((struct bna_rx *)qe)->rid < rx->rid)
  1598. prev_qe = qe;
  1599. else
  1600. break;
  1601. }
  1602. if (prev_qe == NULL) {
  1603. /* This is the first entry */
  1604. bfa_q_enq_head(&rx_mod->rx_free_q, &rx->qe);
  1605. } else if (bfa_q_next(prev_qe) == &rx_mod->rx_free_q) {
  1606. /* This is the last entry */
  1607. list_add_tail(&rx->qe, &rx_mod->rx_free_q);
  1608. } else {
  1609. /* Somewhere in the middle */
  1610. bfa_q_next(&rx->qe) = bfa_q_next(prev_qe);
  1611. bfa_q_prev(&rx->qe) = prev_qe;
  1612. bfa_q_next(prev_qe) = &rx->qe;
  1613. bfa_q_prev(bfa_q_next(&rx->qe)) = &rx->qe;
  1614. }
  1615. rx_mod->rx_free_count++;
  1616. }
  1617. static void
  1618. bna_rxp_add_rxqs(struct bna_rxp *rxp, struct bna_rxq *q0,
  1619. struct bna_rxq *q1)
  1620. {
  1621. switch (rxp->type) {
  1622. case BNA_RXP_SINGLE:
  1623. rxp->rxq.single.only = q0;
  1624. rxp->rxq.single.reserved = NULL;
  1625. break;
  1626. case BNA_RXP_SLR:
  1627. rxp->rxq.slr.large = q0;
  1628. rxp->rxq.slr.small = q1;
  1629. break;
  1630. case BNA_RXP_HDS:
  1631. rxp->rxq.hds.data = q0;
  1632. rxp->rxq.hds.hdr = q1;
  1633. break;
  1634. default:
  1635. break;
  1636. }
  1637. }
  1638. static void
  1639. bna_rxq_qpt_setup(struct bna_rxq *rxq,
  1640. struct bna_rxp *rxp,
  1641. u32 page_count,
  1642. u32 page_size,
  1643. struct bna_mem_descr *qpt_mem,
  1644. struct bna_mem_descr *swqpt_mem,
  1645. struct bna_mem_descr *page_mem)
  1646. {
  1647. u8 *kva;
  1648. u64 dma;
  1649. struct bna_dma_addr bna_dma;
  1650. int i;
  1651. rxq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1652. rxq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1653. rxq->qpt.kv_qpt_ptr = qpt_mem->kva;
  1654. rxq->qpt.page_count = page_count;
  1655. rxq->qpt.page_size = page_size;
  1656. rxq->rcb->sw_qpt = (void **) swqpt_mem->kva;
  1657. rxq->rcb->sw_q = page_mem->kva;
  1658. kva = page_mem->kva;
  1659. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1660. for (i = 0; i < rxq->qpt.page_count; i++) {
  1661. rxq->rcb->sw_qpt[i] = kva;
  1662. kva += PAGE_SIZE;
  1663. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1664. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].lsb =
  1665. bna_dma.lsb;
  1666. ((struct bna_dma_addr *)rxq->qpt.kv_qpt_ptr)[i].msb =
  1667. bna_dma.msb;
  1668. dma += PAGE_SIZE;
  1669. }
  1670. }
  1671. static void
  1672. bna_rxp_cqpt_setup(struct bna_rxp *rxp,
  1673. u32 page_count,
  1674. u32 page_size,
  1675. struct bna_mem_descr *qpt_mem,
  1676. struct bna_mem_descr *swqpt_mem,
  1677. struct bna_mem_descr *page_mem)
  1678. {
  1679. u8 *kva;
  1680. u64 dma;
  1681. struct bna_dma_addr bna_dma;
  1682. int i;
  1683. rxp->cq.qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  1684. rxp->cq.qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  1685. rxp->cq.qpt.kv_qpt_ptr = qpt_mem->kva;
  1686. rxp->cq.qpt.page_count = page_count;
  1687. rxp->cq.qpt.page_size = page_size;
  1688. rxp->cq.ccb->sw_qpt = (void **) swqpt_mem->kva;
  1689. rxp->cq.ccb->sw_q = page_mem->kva;
  1690. kva = page_mem->kva;
  1691. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  1692. for (i = 0; i < rxp->cq.qpt.page_count; i++) {
  1693. rxp->cq.ccb->sw_qpt[i] = kva;
  1694. kva += PAGE_SIZE;
  1695. BNA_SET_DMA_ADDR(dma, &bna_dma);
  1696. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].lsb =
  1697. bna_dma.lsb;
  1698. ((struct bna_dma_addr *)rxp->cq.qpt.kv_qpt_ptr)[i].msb =
  1699. bna_dma.msb;
  1700. dma += PAGE_SIZE;
  1701. }
  1702. }
  1703. static void
  1704. bna_rx_mod_cb_rx_stopped(void *arg, struct bna_rx *rx)
  1705. {
  1706. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1707. bfa_wc_down(&rx_mod->rx_stop_wc);
  1708. }
  1709. static void
  1710. bna_rx_mod_cb_rx_stopped_all(void *arg)
  1711. {
  1712. struct bna_rx_mod *rx_mod = (struct bna_rx_mod *)arg;
  1713. if (rx_mod->stop_cbfn)
  1714. rx_mod->stop_cbfn(&rx_mod->bna->enet);
  1715. rx_mod->stop_cbfn = NULL;
  1716. }
  1717. static void
  1718. bna_rx_start(struct bna_rx *rx)
  1719. {
  1720. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  1721. if (rx->rx_flags & BNA_RX_F_ENABLED)
  1722. bfa_fsm_send_event(rx, RX_E_START);
  1723. }
  1724. static void
  1725. bna_rx_stop(struct bna_rx *rx)
  1726. {
  1727. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1728. if (rx->fsm == (bfa_fsm_t) bna_rx_sm_stopped)
  1729. bna_rx_mod_cb_rx_stopped(&rx->bna->rx_mod, rx);
  1730. else {
  1731. rx->stop_cbfn = bna_rx_mod_cb_rx_stopped;
  1732. rx->stop_cbarg = &rx->bna->rx_mod;
  1733. bfa_fsm_send_event(rx, RX_E_STOP);
  1734. }
  1735. }
  1736. static void
  1737. bna_rx_fail(struct bna_rx *rx)
  1738. {
  1739. /* Indicate Enet is not enabled, and failed */
  1740. rx->rx_flags &= ~BNA_RX_F_ENET_STARTED;
  1741. bfa_fsm_send_event(rx, RX_E_FAIL);
  1742. }
  1743. void
  1744. bna_rx_mod_start(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1745. {
  1746. struct bna_rx *rx;
  1747. struct list_head *qe;
  1748. rx_mod->flags |= BNA_RX_MOD_F_ENET_STARTED;
  1749. if (type == BNA_RX_T_LOOPBACK)
  1750. rx_mod->flags |= BNA_RX_MOD_F_ENET_LOOPBACK;
  1751. list_for_each(qe, &rx_mod->rx_active_q) {
  1752. rx = (struct bna_rx *)qe;
  1753. if (rx->type == type)
  1754. bna_rx_start(rx);
  1755. }
  1756. }
  1757. void
  1758. bna_rx_mod_stop(struct bna_rx_mod *rx_mod, enum bna_rx_type type)
  1759. {
  1760. struct bna_rx *rx;
  1761. struct list_head *qe;
  1762. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1763. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1764. rx_mod->stop_cbfn = bna_enet_cb_rx_stopped;
  1765. bfa_wc_init(&rx_mod->rx_stop_wc, bna_rx_mod_cb_rx_stopped_all, rx_mod);
  1766. list_for_each(qe, &rx_mod->rx_active_q) {
  1767. rx = (struct bna_rx *)qe;
  1768. if (rx->type == type) {
  1769. bfa_wc_up(&rx_mod->rx_stop_wc);
  1770. bna_rx_stop(rx);
  1771. }
  1772. }
  1773. bfa_wc_wait(&rx_mod->rx_stop_wc);
  1774. }
  1775. void
  1776. bna_rx_mod_fail(struct bna_rx_mod *rx_mod)
  1777. {
  1778. struct bna_rx *rx;
  1779. struct list_head *qe;
  1780. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_STARTED;
  1781. rx_mod->flags &= ~BNA_RX_MOD_F_ENET_LOOPBACK;
  1782. list_for_each(qe, &rx_mod->rx_active_q) {
  1783. rx = (struct bna_rx *)qe;
  1784. bna_rx_fail(rx);
  1785. }
  1786. }
  1787. void bna_rx_mod_init(struct bna_rx_mod *rx_mod, struct bna *bna,
  1788. struct bna_res_info *res_info)
  1789. {
  1790. int index;
  1791. struct bna_rx *rx_ptr;
  1792. struct bna_rxp *rxp_ptr;
  1793. struct bna_rxq *rxq_ptr;
  1794. rx_mod->bna = bna;
  1795. rx_mod->flags = 0;
  1796. rx_mod->rx = (struct bna_rx *)
  1797. res_info[BNA_MOD_RES_MEM_T_RX_ARRAY].res_u.mem_info.mdl[0].kva;
  1798. rx_mod->rxp = (struct bna_rxp *)
  1799. res_info[BNA_MOD_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mdl[0].kva;
  1800. rx_mod->rxq = (struct bna_rxq *)
  1801. res_info[BNA_MOD_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  1802. /* Initialize the queues */
  1803. INIT_LIST_HEAD(&rx_mod->rx_free_q);
  1804. rx_mod->rx_free_count = 0;
  1805. INIT_LIST_HEAD(&rx_mod->rxq_free_q);
  1806. rx_mod->rxq_free_count = 0;
  1807. INIT_LIST_HEAD(&rx_mod->rxp_free_q);
  1808. rx_mod->rxp_free_count = 0;
  1809. INIT_LIST_HEAD(&rx_mod->rx_active_q);
  1810. /* Build RX queues */
  1811. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1812. rx_ptr = &rx_mod->rx[index];
  1813. bfa_q_qe_init(&rx_ptr->qe);
  1814. INIT_LIST_HEAD(&rx_ptr->rxp_q);
  1815. rx_ptr->bna = NULL;
  1816. rx_ptr->rid = index;
  1817. rx_ptr->stop_cbfn = NULL;
  1818. rx_ptr->stop_cbarg = NULL;
  1819. list_add_tail(&rx_ptr->qe, &rx_mod->rx_free_q);
  1820. rx_mod->rx_free_count++;
  1821. }
  1822. /* build RX-path queue */
  1823. for (index = 0; index < bna->ioceth.attr.num_rxp; index++) {
  1824. rxp_ptr = &rx_mod->rxp[index];
  1825. bfa_q_qe_init(&rxp_ptr->qe);
  1826. list_add_tail(&rxp_ptr->qe, &rx_mod->rxp_free_q);
  1827. rx_mod->rxp_free_count++;
  1828. }
  1829. /* build RXQ queue */
  1830. for (index = 0; index < (bna->ioceth.attr.num_rxp * 2); index++) {
  1831. rxq_ptr = &rx_mod->rxq[index];
  1832. bfa_q_qe_init(&rxq_ptr->qe);
  1833. list_add_tail(&rxq_ptr->qe, &rx_mod->rxq_free_q);
  1834. rx_mod->rxq_free_count++;
  1835. }
  1836. }
  1837. void
  1838. bna_rx_mod_uninit(struct bna_rx_mod *rx_mod)
  1839. {
  1840. struct list_head *qe;
  1841. int i;
  1842. i = 0;
  1843. list_for_each(qe, &rx_mod->rx_free_q)
  1844. i++;
  1845. i = 0;
  1846. list_for_each(qe, &rx_mod->rxp_free_q)
  1847. i++;
  1848. i = 0;
  1849. list_for_each(qe, &rx_mod->rxq_free_q)
  1850. i++;
  1851. rx_mod->bna = NULL;
  1852. }
  1853. void
  1854. bna_bfi_rx_enet_start_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1855. {
  1856. struct bfi_enet_rx_cfg_rsp *cfg_rsp = &rx->bfi_enet_cmd.cfg_rsp;
  1857. struct bna_rxp *rxp = NULL;
  1858. struct bna_rxq *q0 = NULL, *q1 = NULL;
  1859. struct list_head *rxp_qe;
  1860. int i;
  1861. bfa_msgq_rsp_copy(&rx->bna->msgq, (u8 *)cfg_rsp,
  1862. sizeof(struct bfi_enet_rx_cfg_rsp));
  1863. rx->hw_id = cfg_rsp->hw_id;
  1864. for (i = 0, rxp_qe = bfa_q_first(&rx->rxp_q);
  1865. i < rx->num_paths;
  1866. i++, rxp_qe = bfa_q_next(rxp_qe)) {
  1867. rxp = (struct bna_rxp *)rxp_qe;
  1868. GET_RXQS(rxp, q0, q1);
  1869. /* Setup doorbells */
  1870. rxp->cq.ccb->i_dbell->doorbell_addr =
  1871. rx->bna->pcidev.pci_bar_kva
  1872. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  1873. rxp->hw_id = cfg_rsp->q_handles[i].hw_cqid;
  1874. q0->rcb->q_dbell =
  1875. rx->bna->pcidev.pci_bar_kva
  1876. + ntohl(cfg_rsp->q_handles[i].ql_dbell);
  1877. q0->hw_id = cfg_rsp->q_handles[i].hw_lqid;
  1878. if (q1) {
  1879. q1->rcb->q_dbell =
  1880. rx->bna->pcidev.pci_bar_kva
  1881. + ntohl(cfg_rsp->q_handles[i].qs_dbell);
  1882. q1->hw_id = cfg_rsp->q_handles[i].hw_sqid;
  1883. }
  1884. /* Initialize producer/consumer indexes */
  1885. (*rxp->cq.ccb->hw_producer_index) = 0;
  1886. rxp->cq.ccb->producer_index = 0;
  1887. q0->rcb->producer_index = q0->rcb->consumer_index = 0;
  1888. if (q1)
  1889. q1->rcb->producer_index = q1->rcb->consumer_index = 0;
  1890. }
  1891. bfa_fsm_send_event(rx, RX_E_STARTED);
  1892. }
  1893. void
  1894. bna_bfi_rx_enet_stop_rsp(struct bna_rx *rx, struct bfi_msgq_mhdr *msghdr)
  1895. {
  1896. bfa_fsm_send_event(rx, RX_E_STOPPED);
  1897. }
  1898. void
  1899. bna_rx_res_req(struct bna_rx_config *q_cfg, struct bna_res_info *res_info)
  1900. {
  1901. u32 cq_size, hq_size, dq_size;
  1902. u32 cpage_count, hpage_count, dpage_count;
  1903. struct bna_mem_info *mem_info;
  1904. u32 cq_depth;
  1905. u32 hq_depth;
  1906. u32 dq_depth;
  1907. dq_depth = q_cfg->q_depth;
  1908. hq_depth = ((q_cfg->rxp_type == BNA_RXP_SINGLE) ? 0 : q_cfg->q_depth);
  1909. cq_depth = dq_depth + hq_depth;
  1910. BNA_TO_POWER_OF_2_HIGH(cq_depth);
  1911. cq_size = cq_depth * BFI_CQ_WI_SIZE;
  1912. cq_size = ALIGN(cq_size, PAGE_SIZE);
  1913. cpage_count = SIZE_TO_PAGES(cq_size);
  1914. BNA_TO_POWER_OF_2_HIGH(dq_depth);
  1915. dq_size = dq_depth * BFI_RXQ_WI_SIZE;
  1916. dq_size = ALIGN(dq_size, PAGE_SIZE);
  1917. dpage_count = SIZE_TO_PAGES(dq_size);
  1918. if (BNA_RXP_SINGLE != q_cfg->rxp_type) {
  1919. BNA_TO_POWER_OF_2_HIGH(hq_depth);
  1920. hq_size = hq_depth * BFI_RXQ_WI_SIZE;
  1921. hq_size = ALIGN(hq_size, PAGE_SIZE);
  1922. hpage_count = SIZE_TO_PAGES(hq_size);
  1923. } else
  1924. hpage_count = 0;
  1925. res_info[BNA_RX_RES_MEM_T_CCB].res_type = BNA_RES_T_MEM;
  1926. mem_info = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info;
  1927. mem_info->mem_type = BNA_MEM_T_KVA;
  1928. mem_info->len = sizeof(struct bna_ccb);
  1929. mem_info->num = q_cfg->num_paths;
  1930. res_info[BNA_RX_RES_MEM_T_RCB].res_type = BNA_RES_T_MEM;
  1931. mem_info = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info;
  1932. mem_info->mem_type = BNA_MEM_T_KVA;
  1933. mem_info->len = sizeof(struct bna_rcb);
  1934. mem_info->num = BNA_GET_RXQS(q_cfg);
  1935. res_info[BNA_RX_RES_MEM_T_CQPT].res_type = BNA_RES_T_MEM;
  1936. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info;
  1937. mem_info->mem_type = BNA_MEM_T_DMA;
  1938. mem_info->len = cpage_count * sizeof(struct bna_dma_addr);
  1939. mem_info->num = q_cfg->num_paths;
  1940. res_info[BNA_RX_RES_MEM_T_CSWQPT].res_type = BNA_RES_T_MEM;
  1941. mem_info = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info;
  1942. mem_info->mem_type = BNA_MEM_T_KVA;
  1943. mem_info->len = cpage_count * sizeof(void *);
  1944. mem_info->num = q_cfg->num_paths;
  1945. res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_type = BNA_RES_T_MEM;
  1946. mem_info = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info;
  1947. mem_info->mem_type = BNA_MEM_T_DMA;
  1948. mem_info->len = PAGE_SIZE * cpage_count;
  1949. mem_info->num = q_cfg->num_paths;
  1950. res_info[BNA_RX_RES_MEM_T_DQPT].res_type = BNA_RES_T_MEM;
  1951. mem_info = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info;
  1952. mem_info->mem_type = BNA_MEM_T_DMA;
  1953. mem_info->len = dpage_count * sizeof(struct bna_dma_addr);
  1954. mem_info->num = q_cfg->num_paths;
  1955. res_info[BNA_RX_RES_MEM_T_DSWQPT].res_type = BNA_RES_T_MEM;
  1956. mem_info = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info;
  1957. mem_info->mem_type = BNA_MEM_T_KVA;
  1958. mem_info->len = dpage_count * sizeof(void *);
  1959. mem_info->num = q_cfg->num_paths;
  1960. res_info[BNA_RX_RES_MEM_T_DPAGE].res_type = BNA_RES_T_MEM;
  1961. mem_info = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info;
  1962. mem_info->mem_type = BNA_MEM_T_DMA;
  1963. mem_info->len = PAGE_SIZE * dpage_count;
  1964. mem_info->num = q_cfg->num_paths;
  1965. res_info[BNA_RX_RES_MEM_T_HQPT].res_type = BNA_RES_T_MEM;
  1966. mem_info = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info;
  1967. mem_info->mem_type = BNA_MEM_T_DMA;
  1968. mem_info->len = hpage_count * sizeof(struct bna_dma_addr);
  1969. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1970. res_info[BNA_RX_RES_MEM_T_HSWQPT].res_type = BNA_RES_T_MEM;
  1971. mem_info = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info;
  1972. mem_info->mem_type = BNA_MEM_T_KVA;
  1973. mem_info->len = hpage_count * sizeof(void *);
  1974. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1975. res_info[BNA_RX_RES_MEM_T_HPAGE].res_type = BNA_RES_T_MEM;
  1976. mem_info = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info;
  1977. mem_info->mem_type = BNA_MEM_T_DMA;
  1978. mem_info->len = PAGE_SIZE * hpage_count;
  1979. mem_info->num = (hpage_count ? q_cfg->num_paths : 0);
  1980. res_info[BNA_RX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  1981. mem_info = &res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info;
  1982. mem_info->mem_type = BNA_MEM_T_DMA;
  1983. mem_info->len = BFI_IBIDX_SIZE;
  1984. mem_info->num = q_cfg->num_paths;
  1985. res_info[BNA_RX_RES_MEM_T_RIT].res_type = BNA_RES_T_MEM;
  1986. mem_info = &res_info[BNA_RX_RES_MEM_T_RIT].res_u.mem_info;
  1987. mem_info->mem_type = BNA_MEM_T_KVA;
  1988. mem_info->len = BFI_ENET_RSS_RIT_MAX;
  1989. mem_info->num = 1;
  1990. res_info[BNA_RX_RES_T_INTR].res_type = BNA_RES_T_INTR;
  1991. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.intr_type = BNA_INTR_T_MSIX;
  1992. res_info[BNA_RX_RES_T_INTR].res_u.intr_info.num = q_cfg->num_paths;
  1993. }
  1994. struct bna_rx *
  1995. bna_rx_create(struct bna *bna, struct bnad *bnad,
  1996. struct bna_rx_config *rx_cfg,
  1997. const struct bna_rx_event_cbfn *rx_cbfn,
  1998. struct bna_res_info *res_info,
  1999. void *priv)
  2000. {
  2001. struct bna_rx_mod *rx_mod = &bna->rx_mod;
  2002. struct bna_rx *rx;
  2003. struct bna_rxp *rxp;
  2004. struct bna_rxq *q0;
  2005. struct bna_rxq *q1;
  2006. struct bna_intr_info *intr_info;
  2007. u32 page_count;
  2008. struct bna_mem_descr *ccb_mem;
  2009. struct bna_mem_descr *rcb_mem;
  2010. struct bna_mem_descr *unmapq_mem;
  2011. struct bna_mem_descr *cqpt_mem;
  2012. struct bna_mem_descr *cswqpt_mem;
  2013. struct bna_mem_descr *cpage_mem;
  2014. struct bna_mem_descr *hqpt_mem;
  2015. struct bna_mem_descr *dqpt_mem;
  2016. struct bna_mem_descr *hsqpt_mem;
  2017. struct bna_mem_descr *dsqpt_mem;
  2018. struct bna_mem_descr *hpage_mem;
  2019. struct bna_mem_descr *dpage_mem;
  2020. int i;
  2021. int dpage_count, hpage_count, rcb_idx;
  2022. if (!bna_rx_res_check(rx_mod, rx_cfg))
  2023. return NULL;
  2024. intr_info = &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
  2025. ccb_mem = &res_info[BNA_RX_RES_MEM_T_CCB].res_u.mem_info.mdl[0];
  2026. rcb_mem = &res_info[BNA_RX_RES_MEM_T_RCB].res_u.mem_info.mdl[0];
  2027. unmapq_mem = &res_info[BNA_RX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[0];
  2028. cqpt_mem = &res_info[BNA_RX_RES_MEM_T_CQPT].res_u.mem_info.mdl[0];
  2029. cswqpt_mem = &res_info[BNA_RX_RES_MEM_T_CSWQPT].res_u.mem_info.mdl[0];
  2030. cpage_mem = &res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.mdl[0];
  2031. hqpt_mem = &res_info[BNA_RX_RES_MEM_T_HQPT].res_u.mem_info.mdl[0];
  2032. dqpt_mem = &res_info[BNA_RX_RES_MEM_T_DQPT].res_u.mem_info.mdl[0];
  2033. hsqpt_mem = &res_info[BNA_RX_RES_MEM_T_HSWQPT].res_u.mem_info.mdl[0];
  2034. dsqpt_mem = &res_info[BNA_RX_RES_MEM_T_DSWQPT].res_u.mem_info.mdl[0];
  2035. hpage_mem = &res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.mdl[0];
  2036. dpage_mem = &res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.mdl[0];
  2037. page_count = res_info[BNA_RX_RES_MEM_T_CQPT_PAGE].res_u.mem_info.len /
  2038. PAGE_SIZE;
  2039. dpage_count = res_info[BNA_RX_RES_MEM_T_DPAGE].res_u.mem_info.len /
  2040. PAGE_SIZE;
  2041. hpage_count = res_info[BNA_RX_RES_MEM_T_HPAGE].res_u.mem_info.len /
  2042. PAGE_SIZE;
  2043. rx = bna_rx_get(rx_mod, rx_cfg->rx_type);
  2044. rx->bna = bna;
  2045. rx->rx_flags = 0;
  2046. INIT_LIST_HEAD(&rx->rxp_q);
  2047. rx->stop_cbfn = NULL;
  2048. rx->stop_cbarg = NULL;
  2049. rx->priv = priv;
  2050. rx->rcb_setup_cbfn = rx_cbfn->rcb_setup_cbfn;
  2051. rx->rcb_destroy_cbfn = rx_cbfn->rcb_destroy_cbfn;
  2052. rx->ccb_setup_cbfn = rx_cbfn->ccb_setup_cbfn;
  2053. rx->ccb_destroy_cbfn = rx_cbfn->ccb_destroy_cbfn;
  2054. rx->rx_stall_cbfn = rx_cbfn->rx_stall_cbfn;
  2055. /* Following callbacks are mandatory */
  2056. rx->rx_cleanup_cbfn = rx_cbfn->rx_cleanup_cbfn;
  2057. rx->rx_post_cbfn = rx_cbfn->rx_post_cbfn;
  2058. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_STARTED) {
  2059. switch (rx->type) {
  2060. case BNA_RX_T_REGULAR:
  2061. if (!(rx->bna->rx_mod.flags &
  2062. BNA_RX_MOD_F_ENET_LOOPBACK))
  2063. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2064. break;
  2065. case BNA_RX_T_LOOPBACK:
  2066. if (rx->bna->rx_mod.flags & BNA_RX_MOD_F_ENET_LOOPBACK)
  2067. rx->rx_flags |= BNA_RX_F_ENET_STARTED;
  2068. break;
  2069. }
  2070. }
  2071. rx->num_paths = rx_cfg->num_paths;
  2072. for (i = 0, rcb_idx = 0; i < rx->num_paths; i++) {
  2073. rxp = bna_rxp_get(rx_mod);
  2074. list_add_tail(&rxp->qe, &rx->rxp_q);
  2075. rxp->type = rx_cfg->rxp_type;
  2076. rxp->rx = rx;
  2077. rxp->cq.rx = rx;
  2078. q0 = bna_rxq_get(rx_mod);
  2079. if (BNA_RXP_SINGLE == rx_cfg->rxp_type)
  2080. q1 = NULL;
  2081. else
  2082. q1 = bna_rxq_get(rx_mod);
  2083. if (1 == intr_info->num)
  2084. rxp->vector = intr_info->idl[0].vector;
  2085. else
  2086. rxp->vector = intr_info->idl[i].vector;
  2087. /* Setup IB */
  2088. rxp->cq.ib.ib_seg_host_addr.lsb =
  2089. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  2090. rxp->cq.ib.ib_seg_host_addr.msb =
  2091. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  2092. rxp->cq.ib.ib_seg_host_addr_kva =
  2093. res_info[BNA_RX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  2094. rxp->cq.ib.intr_type = intr_info->intr_type;
  2095. if (intr_info->intr_type == BNA_INTR_T_MSIX)
  2096. rxp->cq.ib.intr_vector = rxp->vector;
  2097. else
  2098. rxp->cq.ib.intr_vector = (1 << rxp->vector);
  2099. rxp->cq.ib.coalescing_timeo = rx_cfg->coalescing_timeo;
  2100. rxp->cq.ib.interpkt_count = BFI_RX_INTERPKT_COUNT;
  2101. rxp->cq.ib.interpkt_timeo = BFI_RX_INTERPKT_TIMEO;
  2102. bna_rxp_add_rxqs(rxp, q0, q1);
  2103. /* Setup large Q */
  2104. q0->rx = rx;
  2105. q0->rxp = rxp;
  2106. q0->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2107. q0->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2108. rcb_idx++;
  2109. q0->rcb->q_depth = rx_cfg->q_depth;
  2110. q0->rcb->rxq = q0;
  2111. q0->rcb->bnad = bna->bnad;
  2112. q0->rcb->id = 0;
  2113. q0->rx_packets = q0->rx_bytes = 0;
  2114. q0->rx_packets_with_error = q0->rxbuf_alloc_failed = 0;
  2115. bna_rxq_qpt_setup(q0, rxp, dpage_count, PAGE_SIZE,
  2116. &dqpt_mem[i], &dsqpt_mem[i], &dpage_mem[i]);
  2117. if (rx->rcb_setup_cbfn)
  2118. rx->rcb_setup_cbfn(bnad, q0->rcb);
  2119. /* Setup small Q */
  2120. if (q1) {
  2121. q1->rx = rx;
  2122. q1->rxp = rxp;
  2123. q1->rcb = (struct bna_rcb *) rcb_mem[rcb_idx].kva;
  2124. q1->rcb->unmap_q = (void *)unmapq_mem[rcb_idx].kva;
  2125. rcb_idx++;
  2126. q1->rcb->q_depth = rx_cfg->q_depth;
  2127. q1->rcb->rxq = q1;
  2128. q1->rcb->bnad = bna->bnad;
  2129. q1->rcb->id = 1;
  2130. q1->buffer_size = (rx_cfg->rxp_type == BNA_RXP_HDS) ?
  2131. rx_cfg->hds_config.forced_offset
  2132. : rx_cfg->small_buff_size;
  2133. q1->rx_packets = q1->rx_bytes = 0;
  2134. q1->rx_packets_with_error = q1->rxbuf_alloc_failed = 0;
  2135. bna_rxq_qpt_setup(q1, rxp, hpage_count, PAGE_SIZE,
  2136. &hqpt_mem[i], &hsqpt_mem[i],
  2137. &hpage_mem[i]);
  2138. if (rx->rcb_setup_cbfn)
  2139. rx->rcb_setup_cbfn(bnad, q1->rcb);
  2140. }
  2141. /* Setup CQ */
  2142. rxp->cq.ccb = (struct bna_ccb *) ccb_mem[i].kva;
  2143. rxp->cq.ccb->q_depth = rx_cfg->q_depth +
  2144. ((rx_cfg->rxp_type == BNA_RXP_SINGLE) ?
  2145. 0 : rx_cfg->q_depth);
  2146. rxp->cq.ccb->cq = &rxp->cq;
  2147. rxp->cq.ccb->rcb[0] = q0->rcb;
  2148. q0->rcb->ccb = rxp->cq.ccb;
  2149. if (q1) {
  2150. rxp->cq.ccb->rcb[1] = q1->rcb;
  2151. q1->rcb->ccb = rxp->cq.ccb;
  2152. }
  2153. rxp->cq.ccb->hw_producer_index =
  2154. (u32 *)rxp->cq.ib.ib_seg_host_addr_kva;
  2155. rxp->cq.ccb->i_dbell = &rxp->cq.ib.door_bell;
  2156. rxp->cq.ccb->intr_type = rxp->cq.ib.intr_type;
  2157. rxp->cq.ccb->intr_vector = rxp->cq.ib.intr_vector;
  2158. rxp->cq.ccb->rx_coalescing_timeo =
  2159. rxp->cq.ib.coalescing_timeo;
  2160. rxp->cq.ccb->pkt_rate.small_pkt_cnt = 0;
  2161. rxp->cq.ccb->pkt_rate.large_pkt_cnt = 0;
  2162. rxp->cq.ccb->bnad = bna->bnad;
  2163. rxp->cq.ccb->id = i;
  2164. bna_rxp_cqpt_setup(rxp, page_count, PAGE_SIZE,
  2165. &cqpt_mem[i], &cswqpt_mem[i], &cpage_mem[i]);
  2166. if (rx->ccb_setup_cbfn)
  2167. rx->ccb_setup_cbfn(bnad, rxp->cq.ccb);
  2168. }
  2169. rx->hds_cfg = rx_cfg->hds_config;
  2170. bna_rxf_init(&rx->rxf, rx, rx_cfg, res_info);
  2171. bfa_fsm_set_state(rx, bna_rx_sm_stopped);
  2172. rx_mod->rid_mask |= (1 << rx->rid);
  2173. return rx;
  2174. }
  2175. void
  2176. bna_rx_destroy(struct bna_rx *rx)
  2177. {
  2178. struct bna_rx_mod *rx_mod = &rx->bna->rx_mod;
  2179. struct bna_rxq *q0 = NULL;
  2180. struct bna_rxq *q1 = NULL;
  2181. struct bna_rxp *rxp;
  2182. struct list_head *qe;
  2183. bna_rxf_uninit(&rx->rxf);
  2184. while (!list_empty(&rx->rxp_q)) {
  2185. bfa_q_deq(&rx->rxp_q, &rxp);
  2186. GET_RXQS(rxp, q0, q1);
  2187. if (rx->rcb_destroy_cbfn)
  2188. rx->rcb_destroy_cbfn(rx->bna->bnad, q0->rcb);
  2189. q0->rcb = NULL;
  2190. q0->rxp = NULL;
  2191. q0->rx = NULL;
  2192. bna_rxq_put(rx_mod, q0);
  2193. if (q1) {
  2194. if (rx->rcb_destroy_cbfn)
  2195. rx->rcb_destroy_cbfn(rx->bna->bnad, q1->rcb);
  2196. q1->rcb = NULL;
  2197. q1->rxp = NULL;
  2198. q1->rx = NULL;
  2199. bna_rxq_put(rx_mod, q1);
  2200. }
  2201. rxp->rxq.slr.large = NULL;
  2202. rxp->rxq.slr.small = NULL;
  2203. if (rx->ccb_destroy_cbfn)
  2204. rx->ccb_destroy_cbfn(rx->bna->bnad, rxp->cq.ccb);
  2205. rxp->cq.ccb = NULL;
  2206. rxp->rx = NULL;
  2207. bna_rxp_put(rx_mod, rxp);
  2208. }
  2209. list_for_each(qe, &rx_mod->rx_active_q) {
  2210. if (qe == &rx->qe) {
  2211. list_del(&rx->qe);
  2212. bfa_q_qe_init(&rx->qe);
  2213. break;
  2214. }
  2215. }
  2216. rx_mod->rid_mask &= ~(1 << rx->rid);
  2217. rx->bna = NULL;
  2218. rx->priv = NULL;
  2219. bna_rx_put(rx_mod, rx);
  2220. }
  2221. void
  2222. bna_rx_enable(struct bna_rx *rx)
  2223. {
  2224. if (rx->fsm != (bfa_sm_t)bna_rx_sm_stopped)
  2225. return;
  2226. rx->rx_flags |= BNA_RX_F_ENABLED;
  2227. if (rx->rx_flags & BNA_RX_F_ENET_STARTED)
  2228. bfa_fsm_send_event(rx, RX_E_START);
  2229. }
  2230. void
  2231. bna_rx_disable(struct bna_rx *rx, enum bna_cleanup_type type,
  2232. void (*cbfn)(void *, struct bna_rx *))
  2233. {
  2234. if (type == BNA_SOFT_CLEANUP) {
  2235. /* h/w should not be accessed. Treat we're stopped */
  2236. (*cbfn)(rx->bna->bnad, rx);
  2237. } else {
  2238. rx->stop_cbfn = cbfn;
  2239. rx->stop_cbarg = rx->bna->bnad;
  2240. rx->rx_flags &= ~BNA_RX_F_ENABLED;
  2241. bfa_fsm_send_event(rx, RX_E_STOP);
  2242. }
  2243. }
  2244. void
  2245. bna_rx_cleanup_complete(struct bna_rx *rx)
  2246. {
  2247. bfa_fsm_send_event(rx, RX_E_CLEANUP_DONE);
  2248. }
  2249. enum bna_cb_status
  2250. bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
  2251. enum bna_rxmode bitmask,
  2252. void (*cbfn)(struct bnad *, struct bna_rx *))
  2253. {
  2254. struct bna_rxf *rxf = &rx->rxf;
  2255. int need_hw_config = 0;
  2256. /* Error checks */
  2257. if (is_promisc_enable(new_mode, bitmask)) {
  2258. /* If promisc mode is already enabled elsewhere in the system */
  2259. if ((rx->bna->promisc_rid != BFI_INVALID_RID) &&
  2260. (rx->bna->promisc_rid != rxf->rx->rid))
  2261. goto err_return;
  2262. /* If default mode is already enabled in the system */
  2263. if (rx->bna->default_mode_rid != BFI_INVALID_RID)
  2264. goto err_return;
  2265. /* Trying to enable promiscuous and default mode together */
  2266. if (is_default_enable(new_mode, bitmask))
  2267. goto err_return;
  2268. }
  2269. if (is_default_enable(new_mode, bitmask)) {
  2270. /* If default mode is already enabled elsewhere in the system */
  2271. if ((rx->bna->default_mode_rid != BFI_INVALID_RID) &&
  2272. (rx->bna->default_mode_rid != rxf->rx->rid)) {
  2273. goto err_return;
  2274. }
  2275. /* If promiscuous mode is already enabled in the system */
  2276. if (rx->bna->promisc_rid != BFI_INVALID_RID)
  2277. goto err_return;
  2278. }
  2279. /* Process the commands */
  2280. if (is_promisc_enable(new_mode, bitmask)) {
  2281. if (bna_rxf_promisc_enable(rxf))
  2282. need_hw_config = 1;
  2283. } else if (is_promisc_disable(new_mode, bitmask)) {
  2284. if (bna_rxf_promisc_disable(rxf))
  2285. need_hw_config = 1;
  2286. }
  2287. if (is_allmulti_enable(new_mode, bitmask)) {
  2288. if (bna_rxf_allmulti_enable(rxf))
  2289. need_hw_config = 1;
  2290. } else if (is_allmulti_disable(new_mode, bitmask)) {
  2291. if (bna_rxf_allmulti_disable(rxf))
  2292. need_hw_config = 1;
  2293. }
  2294. /* Trigger h/w if needed */
  2295. if (need_hw_config) {
  2296. rxf->cam_fltr_cbfn = cbfn;
  2297. rxf->cam_fltr_cbarg = rx->bna->bnad;
  2298. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2299. } else if (cbfn)
  2300. (*cbfn)(rx->bna->bnad, rx);
  2301. return BNA_CB_SUCCESS;
  2302. err_return:
  2303. return BNA_CB_FAIL;
  2304. }
  2305. void
  2306. bna_rx_vlanfilter_enable(struct bna_rx *rx)
  2307. {
  2308. struct bna_rxf *rxf = &rx->rxf;
  2309. if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
  2310. rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
  2311. rxf->vlan_pending_bitmask = (u8)BFI_VLAN_BMASK_ALL;
  2312. bfa_fsm_send_event(rxf, RXF_E_CONFIG);
  2313. }
  2314. }
  2315. void
  2316. bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
  2317. {
  2318. struct bna_rxp *rxp;
  2319. struct list_head *qe;
  2320. list_for_each(qe, &rx->rxp_q) {
  2321. rxp = (struct bna_rxp *)qe;
  2322. rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
  2323. bna_ib_coalescing_timeo_set(&rxp->cq.ib, coalescing_timeo);
  2324. }
  2325. }
  2326. void
  2327. bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
  2328. {
  2329. int i, j;
  2330. for (i = 0; i < BNA_LOAD_T_MAX; i++)
  2331. for (j = 0; j < BNA_BIAS_T_MAX; j++)
  2332. bna->rx_mod.dim_vector[i][j] = vector[i][j];
  2333. }
  2334. void
  2335. bna_rx_dim_update(struct bna_ccb *ccb)
  2336. {
  2337. struct bna *bna = ccb->cq->rx->bna;
  2338. u32 load, bias;
  2339. u32 pkt_rt, small_rt, large_rt;
  2340. u8 coalescing_timeo;
  2341. if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
  2342. (ccb->pkt_rate.large_pkt_cnt == 0))
  2343. return;
  2344. /* Arrive at preconfigured coalescing timeo value based on pkt rate */
  2345. small_rt = ccb->pkt_rate.small_pkt_cnt;
  2346. large_rt = ccb->pkt_rate.large_pkt_cnt;
  2347. pkt_rt = small_rt + large_rt;
  2348. if (pkt_rt < BNA_PKT_RATE_10K)
  2349. load = BNA_LOAD_T_LOW_4;
  2350. else if (pkt_rt < BNA_PKT_RATE_20K)
  2351. load = BNA_LOAD_T_LOW_3;
  2352. else if (pkt_rt < BNA_PKT_RATE_30K)
  2353. load = BNA_LOAD_T_LOW_2;
  2354. else if (pkt_rt < BNA_PKT_RATE_40K)
  2355. load = BNA_LOAD_T_LOW_1;
  2356. else if (pkt_rt < BNA_PKT_RATE_50K)
  2357. load = BNA_LOAD_T_HIGH_1;
  2358. else if (pkt_rt < BNA_PKT_RATE_60K)
  2359. load = BNA_LOAD_T_HIGH_2;
  2360. else if (pkt_rt < BNA_PKT_RATE_80K)
  2361. load = BNA_LOAD_T_HIGH_3;
  2362. else
  2363. load = BNA_LOAD_T_HIGH_4;
  2364. if (small_rt > (large_rt << 1))
  2365. bias = 0;
  2366. else
  2367. bias = 1;
  2368. ccb->pkt_rate.small_pkt_cnt = 0;
  2369. ccb->pkt_rate.large_pkt_cnt = 0;
  2370. coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
  2371. ccb->rx_coalescing_timeo = coalescing_timeo;
  2372. /* Set it to IB */
  2373. bna_ib_coalescing_timeo_set(&ccb->cq->ib, coalescing_timeo);
  2374. }
  2375. const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
  2376. {12, 12},
  2377. {6, 10},
  2378. {5, 10},
  2379. {4, 8},
  2380. {3, 6},
  2381. {3, 6},
  2382. {2, 4},
  2383. {1, 2},
  2384. };
  2385. /* TX */
  2386. #define call_tx_stop_cbfn(tx) \
  2387. do { \
  2388. if ((tx)->stop_cbfn) { \
  2389. void (*cbfn)(void *, struct bna_tx *); \
  2390. void *cbarg; \
  2391. cbfn = (tx)->stop_cbfn; \
  2392. cbarg = (tx)->stop_cbarg; \
  2393. (tx)->stop_cbfn = NULL; \
  2394. (tx)->stop_cbarg = NULL; \
  2395. cbfn(cbarg, (tx)); \
  2396. } \
  2397. } while (0)
  2398. #define call_tx_prio_change_cbfn(tx) \
  2399. do { \
  2400. if ((tx)->prio_change_cbfn) { \
  2401. void (*cbfn)(struct bnad *, struct bna_tx *); \
  2402. cbfn = (tx)->prio_change_cbfn; \
  2403. (tx)->prio_change_cbfn = NULL; \
  2404. cbfn((tx)->bna->bnad, (tx)); \
  2405. } \
  2406. } while (0)
  2407. static void bna_tx_mod_cb_tx_stopped(void *tx_mod, struct bna_tx *tx);
  2408. static void bna_bfi_tx_enet_start(struct bna_tx *tx);
  2409. static void bna_tx_enet_stop(struct bna_tx *tx);
  2410. enum bna_tx_event {
  2411. TX_E_START = 1,
  2412. TX_E_STOP = 2,
  2413. TX_E_FAIL = 3,
  2414. TX_E_STARTED = 4,
  2415. TX_E_STOPPED = 5,
  2416. TX_E_PRIO_CHANGE = 6,
  2417. TX_E_CLEANUP_DONE = 7,
  2418. TX_E_BW_UPDATE = 8,
  2419. };
  2420. bfa_fsm_state_decl(bna_tx, stopped, struct bna_tx, enum bna_tx_event);
  2421. bfa_fsm_state_decl(bna_tx, start_wait, struct bna_tx, enum bna_tx_event);
  2422. bfa_fsm_state_decl(bna_tx, started, struct bna_tx, enum bna_tx_event);
  2423. bfa_fsm_state_decl(bna_tx, stop_wait, struct bna_tx, enum bna_tx_event);
  2424. bfa_fsm_state_decl(bna_tx, cleanup_wait, struct bna_tx,
  2425. enum bna_tx_event);
  2426. bfa_fsm_state_decl(bna_tx, prio_stop_wait, struct bna_tx,
  2427. enum bna_tx_event);
  2428. bfa_fsm_state_decl(bna_tx, prio_cleanup_wait, struct bna_tx,
  2429. enum bna_tx_event);
  2430. bfa_fsm_state_decl(bna_tx, failed, struct bna_tx, enum bna_tx_event);
  2431. bfa_fsm_state_decl(bna_tx, quiesce_wait, struct bna_tx,
  2432. enum bna_tx_event);
  2433. static void
  2434. bna_tx_sm_stopped_entry(struct bna_tx *tx)
  2435. {
  2436. call_tx_stop_cbfn(tx);
  2437. }
  2438. static void
  2439. bna_tx_sm_stopped(struct bna_tx *tx, enum bna_tx_event event)
  2440. {
  2441. switch (event) {
  2442. case TX_E_START:
  2443. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2444. break;
  2445. case TX_E_STOP:
  2446. call_tx_stop_cbfn(tx);
  2447. break;
  2448. case TX_E_FAIL:
  2449. /* No-op */
  2450. break;
  2451. case TX_E_PRIO_CHANGE:
  2452. call_tx_prio_change_cbfn(tx);
  2453. break;
  2454. case TX_E_BW_UPDATE:
  2455. /* No-op */
  2456. break;
  2457. default:
  2458. bfa_sm_fault(event);
  2459. }
  2460. }
  2461. static void
  2462. bna_tx_sm_start_wait_entry(struct bna_tx *tx)
  2463. {
  2464. bna_bfi_tx_enet_start(tx);
  2465. }
  2466. static void
  2467. bna_tx_sm_start_wait(struct bna_tx *tx, enum bna_tx_event event)
  2468. {
  2469. switch (event) {
  2470. case TX_E_STOP:
  2471. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2472. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2473. break;
  2474. case TX_E_FAIL:
  2475. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED);
  2476. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2477. break;
  2478. case TX_E_STARTED:
  2479. if (tx->flags & (BNA_TX_F_PRIO_CHANGED | BNA_TX_F_BW_UPDATED)) {
  2480. tx->flags &= ~(BNA_TX_F_PRIO_CHANGED |
  2481. BNA_TX_F_BW_UPDATED);
  2482. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2483. } else
  2484. bfa_fsm_set_state(tx, bna_tx_sm_started);
  2485. break;
  2486. case TX_E_PRIO_CHANGE:
  2487. tx->flags |= BNA_TX_F_PRIO_CHANGED;
  2488. break;
  2489. case TX_E_BW_UPDATE:
  2490. tx->flags |= BNA_TX_F_BW_UPDATED;
  2491. break;
  2492. default:
  2493. bfa_sm_fault(event);
  2494. }
  2495. }
  2496. static void
  2497. bna_tx_sm_started_entry(struct bna_tx *tx)
  2498. {
  2499. struct bna_txq *txq;
  2500. struct list_head *qe;
  2501. int is_regular = (tx->type == BNA_TX_T_REGULAR);
  2502. list_for_each(qe, &tx->txq_q) {
  2503. txq = (struct bna_txq *)qe;
  2504. txq->tcb->priority = txq->priority;
  2505. /* Start IB */
  2506. bna_ib_start(tx->bna, &txq->ib, is_regular);
  2507. }
  2508. tx->tx_resume_cbfn(tx->bna->bnad, tx);
  2509. }
  2510. static void
  2511. bna_tx_sm_started(struct bna_tx *tx, enum bna_tx_event event)
  2512. {
  2513. switch (event) {
  2514. case TX_E_STOP:
  2515. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2516. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2517. bna_tx_enet_stop(tx);
  2518. break;
  2519. case TX_E_FAIL:
  2520. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2521. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2522. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2523. break;
  2524. case TX_E_PRIO_CHANGE:
  2525. case TX_E_BW_UPDATE:
  2526. bfa_fsm_set_state(tx, bna_tx_sm_prio_stop_wait);
  2527. break;
  2528. default:
  2529. bfa_sm_fault(event);
  2530. }
  2531. }
  2532. static void
  2533. bna_tx_sm_stop_wait_entry(struct bna_tx *tx)
  2534. {
  2535. }
  2536. static void
  2537. bna_tx_sm_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2538. {
  2539. switch (event) {
  2540. case TX_E_FAIL:
  2541. case TX_E_STOPPED:
  2542. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2543. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2544. break;
  2545. case TX_E_STARTED:
  2546. /**
  2547. * We are here due to start_wait -> stop_wait transition on
  2548. * TX_E_STOP event
  2549. */
  2550. bna_tx_enet_stop(tx);
  2551. break;
  2552. case TX_E_PRIO_CHANGE:
  2553. case TX_E_BW_UPDATE:
  2554. /* No-op */
  2555. break;
  2556. default:
  2557. bfa_sm_fault(event);
  2558. }
  2559. }
  2560. static void
  2561. bna_tx_sm_cleanup_wait_entry(struct bna_tx *tx)
  2562. {
  2563. }
  2564. static void
  2565. bna_tx_sm_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2566. {
  2567. switch (event) {
  2568. case TX_E_FAIL:
  2569. case TX_E_PRIO_CHANGE:
  2570. case TX_E_BW_UPDATE:
  2571. /* No-op */
  2572. break;
  2573. case TX_E_CLEANUP_DONE:
  2574. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2575. break;
  2576. default:
  2577. bfa_sm_fault(event);
  2578. }
  2579. }
  2580. static void
  2581. bna_tx_sm_prio_stop_wait_entry(struct bna_tx *tx)
  2582. {
  2583. tx->tx_stall_cbfn(tx->bna->bnad, tx);
  2584. bna_tx_enet_stop(tx);
  2585. }
  2586. static void
  2587. bna_tx_sm_prio_stop_wait(struct bna_tx *tx, enum bna_tx_event event)
  2588. {
  2589. switch (event) {
  2590. case TX_E_STOP:
  2591. bfa_fsm_set_state(tx, bna_tx_sm_stop_wait);
  2592. break;
  2593. case TX_E_FAIL:
  2594. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2595. call_tx_prio_change_cbfn(tx);
  2596. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2597. break;
  2598. case TX_E_STOPPED:
  2599. bfa_fsm_set_state(tx, bna_tx_sm_prio_cleanup_wait);
  2600. break;
  2601. case TX_E_PRIO_CHANGE:
  2602. case TX_E_BW_UPDATE:
  2603. /* No-op */
  2604. break;
  2605. default:
  2606. bfa_sm_fault(event);
  2607. }
  2608. }
  2609. static void
  2610. bna_tx_sm_prio_cleanup_wait_entry(struct bna_tx *tx)
  2611. {
  2612. call_tx_prio_change_cbfn(tx);
  2613. tx->tx_cleanup_cbfn(tx->bna->bnad, tx);
  2614. }
  2615. static void
  2616. bna_tx_sm_prio_cleanup_wait(struct bna_tx *tx, enum bna_tx_event event)
  2617. {
  2618. switch (event) {
  2619. case TX_E_STOP:
  2620. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2621. break;
  2622. case TX_E_FAIL:
  2623. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2624. break;
  2625. case TX_E_PRIO_CHANGE:
  2626. case TX_E_BW_UPDATE:
  2627. /* No-op */
  2628. break;
  2629. case TX_E_CLEANUP_DONE:
  2630. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2631. break;
  2632. default:
  2633. bfa_sm_fault(event);
  2634. }
  2635. }
  2636. static void
  2637. bna_tx_sm_failed_entry(struct bna_tx *tx)
  2638. {
  2639. }
  2640. static void
  2641. bna_tx_sm_failed(struct bna_tx *tx, enum bna_tx_event event)
  2642. {
  2643. switch (event) {
  2644. case TX_E_START:
  2645. bfa_fsm_set_state(tx, bna_tx_sm_quiesce_wait);
  2646. break;
  2647. case TX_E_STOP:
  2648. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2649. break;
  2650. case TX_E_FAIL:
  2651. /* No-op */
  2652. break;
  2653. case TX_E_CLEANUP_DONE:
  2654. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  2655. break;
  2656. default:
  2657. bfa_sm_fault(event);
  2658. }
  2659. }
  2660. static void
  2661. bna_tx_sm_quiesce_wait_entry(struct bna_tx *tx)
  2662. {
  2663. }
  2664. static void
  2665. bna_tx_sm_quiesce_wait(struct bna_tx *tx, enum bna_tx_event event)
  2666. {
  2667. switch (event) {
  2668. case TX_E_STOP:
  2669. bfa_fsm_set_state(tx, bna_tx_sm_cleanup_wait);
  2670. break;
  2671. case TX_E_FAIL:
  2672. bfa_fsm_set_state(tx, bna_tx_sm_failed);
  2673. break;
  2674. case TX_E_CLEANUP_DONE:
  2675. bfa_fsm_set_state(tx, bna_tx_sm_start_wait);
  2676. break;
  2677. case TX_E_BW_UPDATE:
  2678. /* No-op */
  2679. break;
  2680. default:
  2681. bfa_sm_fault(event);
  2682. }
  2683. }
  2684. static void
  2685. bna_bfi_tx_enet_start(struct bna_tx *tx)
  2686. {
  2687. struct bfi_enet_tx_cfg_req *cfg_req = &tx->bfi_enet_cmd.cfg_req;
  2688. struct bna_txq *txq = NULL;
  2689. struct list_head *qe;
  2690. int i;
  2691. bfi_msgq_mhdr_set(cfg_req->mh, BFI_MC_ENET,
  2692. BFI_ENET_H2I_TX_CFG_SET_REQ, 0, tx->rid);
  2693. cfg_req->mh.num_entries = htons(
  2694. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_tx_cfg_req)));
  2695. cfg_req->num_queues = tx->num_txq;
  2696. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2697. i < tx->num_txq;
  2698. i++, qe = bfa_q_next(qe)) {
  2699. txq = (struct bna_txq *)qe;
  2700. bfi_enet_datapath_q_init(&cfg_req->q_cfg[i].q.q, &txq->qpt);
  2701. cfg_req->q_cfg[i].q.priority = txq->priority;
  2702. cfg_req->q_cfg[i].ib.index_addr.a32.addr_lo =
  2703. txq->ib.ib_seg_host_addr.lsb;
  2704. cfg_req->q_cfg[i].ib.index_addr.a32.addr_hi =
  2705. txq->ib.ib_seg_host_addr.msb;
  2706. cfg_req->q_cfg[i].ib.intr.msix_index =
  2707. htons((u16)txq->ib.intr_vector);
  2708. }
  2709. cfg_req->ib_cfg.int_pkt_dma = BNA_STATUS_T_ENABLED;
  2710. cfg_req->ib_cfg.int_enabled = BNA_STATUS_T_ENABLED;
  2711. cfg_req->ib_cfg.int_pkt_enabled = BNA_STATUS_T_DISABLED;
  2712. cfg_req->ib_cfg.continuous_coalescing = BNA_STATUS_T_ENABLED;
  2713. cfg_req->ib_cfg.msix = (txq->ib.intr_type == BNA_INTR_T_MSIX)
  2714. ? BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
  2715. cfg_req->ib_cfg.coalescing_timeout =
  2716. htonl((u32)txq->ib.coalescing_timeo);
  2717. cfg_req->ib_cfg.inter_pkt_timeout =
  2718. htonl((u32)txq->ib.interpkt_timeo);
  2719. cfg_req->ib_cfg.inter_pkt_count = (u8)txq->ib.interpkt_count;
  2720. cfg_req->tx_cfg.vlan_mode = BFI_ENET_TX_VLAN_WI;
  2721. cfg_req->tx_cfg.vlan_id = htons((u16)tx->txf_vlan_id);
  2722. cfg_req->tx_cfg.admit_tagged_frame = BNA_STATUS_T_DISABLED;
  2723. cfg_req->tx_cfg.apply_vlan_filter = BNA_STATUS_T_DISABLED;
  2724. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL,
  2725. sizeof(struct bfi_enet_tx_cfg_req), &cfg_req->mh);
  2726. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2727. }
  2728. static void
  2729. bna_bfi_tx_enet_stop(struct bna_tx *tx)
  2730. {
  2731. struct bfi_enet_req *req = &tx->bfi_enet_cmd.req;
  2732. bfi_msgq_mhdr_set(req->mh, BFI_MC_ENET,
  2733. BFI_ENET_H2I_TX_CFG_CLR_REQ, 0, tx->rid);
  2734. req->mh.num_entries = htons(
  2735. bfi_msgq_num_cmd_entries(sizeof(struct bfi_enet_req)));
  2736. bfa_msgq_cmd_set(&tx->msgq_cmd, NULL, NULL, sizeof(struct bfi_enet_req),
  2737. &req->mh);
  2738. bfa_msgq_cmd_post(&tx->bna->msgq, &tx->msgq_cmd);
  2739. }
  2740. static void
  2741. bna_tx_enet_stop(struct bna_tx *tx)
  2742. {
  2743. struct bna_txq *txq;
  2744. struct list_head *qe;
  2745. /* Stop IB */
  2746. list_for_each(qe, &tx->txq_q) {
  2747. txq = (struct bna_txq *)qe;
  2748. bna_ib_stop(tx->bna, &txq->ib);
  2749. }
  2750. bna_bfi_tx_enet_stop(tx);
  2751. }
  2752. static void
  2753. bna_txq_qpt_setup(struct bna_txq *txq, int page_count, int page_size,
  2754. struct bna_mem_descr *qpt_mem,
  2755. struct bna_mem_descr *swqpt_mem,
  2756. struct bna_mem_descr *page_mem)
  2757. {
  2758. u8 *kva;
  2759. u64 dma;
  2760. struct bna_dma_addr bna_dma;
  2761. int i;
  2762. txq->qpt.hw_qpt_ptr.lsb = qpt_mem->dma.lsb;
  2763. txq->qpt.hw_qpt_ptr.msb = qpt_mem->dma.msb;
  2764. txq->qpt.kv_qpt_ptr = qpt_mem->kva;
  2765. txq->qpt.page_count = page_count;
  2766. txq->qpt.page_size = page_size;
  2767. txq->tcb->sw_qpt = (void **) swqpt_mem->kva;
  2768. txq->tcb->sw_q = page_mem->kva;
  2769. kva = page_mem->kva;
  2770. BNA_GET_DMA_ADDR(&page_mem->dma, dma);
  2771. for (i = 0; i < page_count; i++) {
  2772. txq->tcb->sw_qpt[i] = kva;
  2773. kva += PAGE_SIZE;
  2774. BNA_SET_DMA_ADDR(dma, &bna_dma);
  2775. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].lsb =
  2776. bna_dma.lsb;
  2777. ((struct bna_dma_addr *)txq->qpt.kv_qpt_ptr)[i].msb =
  2778. bna_dma.msb;
  2779. dma += PAGE_SIZE;
  2780. }
  2781. }
  2782. static struct bna_tx *
  2783. bna_tx_get(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  2784. {
  2785. struct list_head *qe = NULL;
  2786. struct bna_tx *tx = NULL;
  2787. if (list_empty(&tx_mod->tx_free_q))
  2788. return NULL;
  2789. if (type == BNA_TX_T_REGULAR) {
  2790. bfa_q_deq(&tx_mod->tx_free_q, &qe);
  2791. } else {
  2792. bfa_q_deq_tail(&tx_mod->tx_free_q, &qe);
  2793. }
  2794. tx = (struct bna_tx *)qe;
  2795. bfa_q_qe_init(&tx->qe);
  2796. tx->type = type;
  2797. return tx;
  2798. }
  2799. static void
  2800. bna_tx_free(struct bna_tx *tx)
  2801. {
  2802. struct bna_tx_mod *tx_mod = &tx->bna->tx_mod;
  2803. struct bna_txq *txq;
  2804. struct list_head *prev_qe;
  2805. struct list_head *qe;
  2806. while (!list_empty(&tx->txq_q)) {
  2807. bfa_q_deq(&tx->txq_q, &txq);
  2808. bfa_q_qe_init(&txq->qe);
  2809. txq->tcb = NULL;
  2810. txq->tx = NULL;
  2811. list_add_tail(&txq->qe, &tx_mod->txq_free_q);
  2812. }
  2813. list_for_each(qe, &tx_mod->tx_active_q) {
  2814. if (qe == &tx->qe) {
  2815. list_del(&tx->qe);
  2816. bfa_q_qe_init(&tx->qe);
  2817. break;
  2818. }
  2819. }
  2820. tx->bna = NULL;
  2821. tx->priv = NULL;
  2822. prev_qe = NULL;
  2823. list_for_each(qe, &tx_mod->tx_free_q) {
  2824. if (((struct bna_tx *)qe)->rid < tx->rid)
  2825. prev_qe = qe;
  2826. else {
  2827. break;
  2828. }
  2829. }
  2830. if (prev_qe == NULL) {
  2831. /* This is the first entry */
  2832. bfa_q_enq_head(&tx_mod->tx_free_q, &tx->qe);
  2833. } else if (bfa_q_next(prev_qe) == &tx_mod->tx_free_q) {
  2834. /* This is the last entry */
  2835. list_add_tail(&tx->qe, &tx_mod->tx_free_q);
  2836. } else {
  2837. /* Somewhere in the middle */
  2838. bfa_q_next(&tx->qe) = bfa_q_next(prev_qe);
  2839. bfa_q_prev(&tx->qe) = prev_qe;
  2840. bfa_q_next(prev_qe) = &tx->qe;
  2841. bfa_q_prev(bfa_q_next(&tx->qe)) = &tx->qe;
  2842. }
  2843. }
  2844. static void
  2845. bna_tx_start(struct bna_tx *tx)
  2846. {
  2847. tx->flags |= BNA_TX_F_ENET_STARTED;
  2848. if (tx->flags & BNA_TX_F_ENABLED)
  2849. bfa_fsm_send_event(tx, TX_E_START);
  2850. }
  2851. static void
  2852. bna_tx_stop(struct bna_tx *tx)
  2853. {
  2854. tx->stop_cbfn = bna_tx_mod_cb_tx_stopped;
  2855. tx->stop_cbarg = &tx->bna->tx_mod;
  2856. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2857. bfa_fsm_send_event(tx, TX_E_STOP);
  2858. }
  2859. static void
  2860. bna_tx_fail(struct bna_tx *tx)
  2861. {
  2862. tx->flags &= ~BNA_TX_F_ENET_STARTED;
  2863. bfa_fsm_send_event(tx, TX_E_FAIL);
  2864. }
  2865. void
  2866. bna_bfi_tx_enet_start_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2867. {
  2868. struct bfi_enet_tx_cfg_rsp *cfg_rsp = &tx->bfi_enet_cmd.cfg_rsp;
  2869. struct bna_txq *txq = NULL;
  2870. struct list_head *qe;
  2871. int i;
  2872. bfa_msgq_rsp_copy(&tx->bna->msgq, (u8 *)cfg_rsp,
  2873. sizeof(struct bfi_enet_tx_cfg_rsp));
  2874. tx->hw_id = cfg_rsp->hw_id;
  2875. for (i = 0, qe = bfa_q_first(&tx->txq_q);
  2876. i < tx->num_txq; i++, qe = bfa_q_next(qe)) {
  2877. txq = (struct bna_txq *)qe;
  2878. /* Setup doorbells */
  2879. txq->tcb->i_dbell->doorbell_addr =
  2880. tx->bna->pcidev.pci_bar_kva
  2881. + ntohl(cfg_rsp->q_handles[i].i_dbell);
  2882. txq->tcb->q_dbell =
  2883. tx->bna->pcidev.pci_bar_kva
  2884. + ntohl(cfg_rsp->q_handles[i].q_dbell);
  2885. txq->hw_id = cfg_rsp->q_handles[i].hw_qid;
  2886. /* Initialize producer/consumer indexes */
  2887. (*txq->tcb->hw_consumer_index) = 0;
  2888. txq->tcb->producer_index = txq->tcb->consumer_index = 0;
  2889. }
  2890. bfa_fsm_send_event(tx, TX_E_STARTED);
  2891. }
  2892. void
  2893. bna_bfi_tx_enet_stop_rsp(struct bna_tx *tx, struct bfi_msgq_mhdr *msghdr)
  2894. {
  2895. bfa_fsm_send_event(tx, TX_E_STOPPED);
  2896. }
  2897. void
  2898. bna_bfi_bw_update_aen(struct bna_tx_mod *tx_mod)
  2899. {
  2900. struct bna_tx *tx;
  2901. struct list_head *qe;
  2902. list_for_each(qe, &tx_mod->tx_active_q) {
  2903. tx = (struct bna_tx *)qe;
  2904. bfa_fsm_send_event(tx, TX_E_BW_UPDATE);
  2905. }
  2906. }
  2907. void
  2908. bna_tx_res_req(int num_txq, int txq_depth, struct bna_res_info *res_info)
  2909. {
  2910. u32 q_size;
  2911. u32 page_count;
  2912. struct bna_mem_info *mem_info;
  2913. res_info[BNA_TX_RES_MEM_T_TCB].res_type = BNA_RES_T_MEM;
  2914. mem_info = &res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info;
  2915. mem_info->mem_type = BNA_MEM_T_KVA;
  2916. mem_info->len = sizeof(struct bna_tcb);
  2917. mem_info->num = num_txq;
  2918. q_size = txq_depth * BFI_TXQ_WI_SIZE;
  2919. q_size = ALIGN(q_size, PAGE_SIZE);
  2920. page_count = q_size >> PAGE_SHIFT;
  2921. res_info[BNA_TX_RES_MEM_T_QPT].res_type = BNA_RES_T_MEM;
  2922. mem_info = &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info;
  2923. mem_info->mem_type = BNA_MEM_T_DMA;
  2924. mem_info->len = page_count * sizeof(struct bna_dma_addr);
  2925. mem_info->num = num_txq;
  2926. res_info[BNA_TX_RES_MEM_T_SWQPT].res_type = BNA_RES_T_MEM;
  2927. mem_info = &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info;
  2928. mem_info->mem_type = BNA_MEM_T_KVA;
  2929. mem_info->len = page_count * sizeof(void *);
  2930. mem_info->num = num_txq;
  2931. res_info[BNA_TX_RES_MEM_T_PAGE].res_type = BNA_RES_T_MEM;
  2932. mem_info = &res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info;
  2933. mem_info->mem_type = BNA_MEM_T_DMA;
  2934. mem_info->len = PAGE_SIZE * page_count;
  2935. mem_info->num = num_txq;
  2936. res_info[BNA_TX_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
  2937. mem_info = &res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info;
  2938. mem_info->mem_type = BNA_MEM_T_DMA;
  2939. mem_info->len = BFI_IBIDX_SIZE;
  2940. mem_info->num = num_txq;
  2941. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_type = BNA_RES_T_INTR;
  2942. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.intr_type =
  2943. BNA_INTR_T_MSIX;
  2944. res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info.num = num_txq;
  2945. }
  2946. struct bna_tx *
  2947. bna_tx_create(struct bna *bna, struct bnad *bnad,
  2948. struct bna_tx_config *tx_cfg,
  2949. const struct bna_tx_event_cbfn *tx_cbfn,
  2950. struct bna_res_info *res_info, void *priv)
  2951. {
  2952. struct bna_intr_info *intr_info;
  2953. struct bna_tx_mod *tx_mod = &bna->tx_mod;
  2954. struct bna_tx *tx;
  2955. struct bna_txq *txq;
  2956. struct list_head *qe;
  2957. int page_count;
  2958. int i;
  2959. intr_info = &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
  2960. page_count = (res_info[BNA_TX_RES_MEM_T_PAGE].res_u.mem_info.len) /
  2961. PAGE_SIZE;
  2962. /**
  2963. * Get resources
  2964. */
  2965. if ((intr_info->num != 1) && (intr_info->num != tx_cfg->num_txq))
  2966. return NULL;
  2967. /* Tx */
  2968. tx = bna_tx_get(tx_mod, tx_cfg->tx_type);
  2969. if (!tx)
  2970. return NULL;
  2971. tx->bna = bna;
  2972. tx->priv = priv;
  2973. /* TxQs */
  2974. INIT_LIST_HEAD(&tx->txq_q);
  2975. for (i = 0; i < tx_cfg->num_txq; i++) {
  2976. if (list_empty(&tx_mod->txq_free_q))
  2977. goto err_return;
  2978. bfa_q_deq(&tx_mod->txq_free_q, &txq);
  2979. bfa_q_qe_init(&txq->qe);
  2980. list_add_tail(&txq->qe, &tx->txq_q);
  2981. txq->tx = tx;
  2982. }
  2983. /*
  2984. * Initialize
  2985. */
  2986. /* Tx */
  2987. tx->tcb_setup_cbfn = tx_cbfn->tcb_setup_cbfn;
  2988. tx->tcb_destroy_cbfn = tx_cbfn->tcb_destroy_cbfn;
  2989. /* Following callbacks are mandatory */
  2990. tx->tx_stall_cbfn = tx_cbfn->tx_stall_cbfn;
  2991. tx->tx_resume_cbfn = tx_cbfn->tx_resume_cbfn;
  2992. tx->tx_cleanup_cbfn = tx_cbfn->tx_cleanup_cbfn;
  2993. list_add_tail(&tx->qe, &tx_mod->tx_active_q);
  2994. tx->num_txq = tx_cfg->num_txq;
  2995. tx->flags = 0;
  2996. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_STARTED) {
  2997. switch (tx->type) {
  2998. case BNA_TX_T_REGULAR:
  2999. if (!(tx->bna->tx_mod.flags &
  3000. BNA_TX_MOD_F_ENET_LOOPBACK))
  3001. tx->flags |= BNA_TX_F_ENET_STARTED;
  3002. break;
  3003. case BNA_TX_T_LOOPBACK:
  3004. if (tx->bna->tx_mod.flags & BNA_TX_MOD_F_ENET_LOOPBACK)
  3005. tx->flags |= BNA_TX_F_ENET_STARTED;
  3006. break;
  3007. }
  3008. }
  3009. /* TxQ */
  3010. i = 0;
  3011. list_for_each(qe, &tx->txq_q) {
  3012. txq = (struct bna_txq *)qe;
  3013. txq->tcb = (struct bna_tcb *)
  3014. res_info[BNA_TX_RES_MEM_T_TCB].res_u.mem_info.mdl[i].kva;
  3015. txq->tx_packets = 0;
  3016. txq->tx_bytes = 0;
  3017. /* IB */
  3018. txq->ib.ib_seg_host_addr.lsb =
  3019. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.lsb;
  3020. txq->ib.ib_seg_host_addr.msb =
  3021. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].dma.msb;
  3022. txq->ib.ib_seg_host_addr_kva =
  3023. res_info[BNA_TX_RES_MEM_T_IBIDX].res_u.mem_info.mdl[i].kva;
  3024. txq->ib.intr_type = intr_info->intr_type;
  3025. txq->ib.intr_vector = (intr_info->num == 1) ?
  3026. intr_info->idl[0].vector :
  3027. intr_info->idl[i].vector;
  3028. if (intr_info->intr_type == BNA_INTR_T_INTX)
  3029. txq->ib.intr_vector = (1 << txq->ib.intr_vector);
  3030. txq->ib.coalescing_timeo = tx_cfg->coalescing_timeo;
  3031. txq->ib.interpkt_timeo = BFI_TX_INTERPKT_TIMEO;
  3032. txq->ib.interpkt_count = BFI_TX_INTERPKT_COUNT;
  3033. /* TCB */
  3034. txq->tcb->q_depth = tx_cfg->txq_depth;
  3035. txq->tcb->unmap_q = (void *)
  3036. res_info[BNA_TX_RES_MEM_T_UNMAPQ].res_u.mem_info.mdl[i].kva;
  3037. txq->tcb->hw_consumer_index =
  3038. (u32 *)txq->ib.ib_seg_host_addr_kva;
  3039. txq->tcb->i_dbell = &txq->ib.door_bell;
  3040. txq->tcb->intr_type = txq->ib.intr_type;
  3041. txq->tcb->intr_vector = txq->ib.intr_vector;
  3042. txq->tcb->txq = txq;
  3043. txq->tcb->bnad = bnad;
  3044. txq->tcb->id = i;
  3045. /* QPT, SWQPT, Pages */
  3046. bna_txq_qpt_setup(txq, page_count, PAGE_SIZE,
  3047. &res_info[BNA_TX_RES_MEM_T_QPT].res_u.mem_info.mdl[i],
  3048. &res_info[BNA_TX_RES_MEM_T_SWQPT].res_u.mem_info.mdl[i],
  3049. &res_info[BNA_TX_RES_MEM_T_PAGE].
  3050. res_u.mem_info.mdl[i]);
  3051. /* Callback to bnad for setting up TCB */
  3052. if (tx->tcb_setup_cbfn)
  3053. (tx->tcb_setup_cbfn)(bna->bnad, txq->tcb);
  3054. if (tx_cfg->num_txq == BFI_TX_MAX_PRIO)
  3055. txq->priority = txq->tcb->id;
  3056. else
  3057. txq->priority = tx_mod->default_prio;
  3058. i++;
  3059. }
  3060. tx->txf_vlan_id = 0;
  3061. bfa_fsm_set_state(tx, bna_tx_sm_stopped);
  3062. tx_mod->rid_mask |= (1 << tx->rid);
  3063. return tx;
  3064. err_return:
  3065. bna_tx_free(tx);
  3066. return NULL;
  3067. }
  3068. void
  3069. bna_tx_destroy(struct bna_tx *tx)
  3070. {
  3071. struct bna_txq *txq;
  3072. struct list_head *qe;
  3073. list_for_each(qe, &tx->txq_q) {
  3074. txq = (struct bna_txq *)qe;
  3075. if (tx->tcb_destroy_cbfn)
  3076. (tx->tcb_destroy_cbfn)(tx->bna->bnad, txq->tcb);
  3077. }
  3078. tx->bna->tx_mod.rid_mask &= ~(1 << tx->rid);
  3079. bna_tx_free(tx);
  3080. }
  3081. void
  3082. bna_tx_enable(struct bna_tx *tx)
  3083. {
  3084. if (tx->fsm != (bfa_sm_t)bna_tx_sm_stopped)
  3085. return;
  3086. tx->flags |= BNA_TX_F_ENABLED;
  3087. if (tx->flags & BNA_TX_F_ENET_STARTED)
  3088. bfa_fsm_send_event(tx, TX_E_START);
  3089. }
  3090. void
  3091. bna_tx_disable(struct bna_tx *tx, enum bna_cleanup_type type,
  3092. void (*cbfn)(void *, struct bna_tx *))
  3093. {
  3094. if (type == BNA_SOFT_CLEANUP) {
  3095. (*cbfn)(tx->bna->bnad, tx);
  3096. return;
  3097. }
  3098. tx->stop_cbfn = cbfn;
  3099. tx->stop_cbarg = tx->bna->bnad;
  3100. tx->flags &= ~BNA_TX_F_ENABLED;
  3101. bfa_fsm_send_event(tx, TX_E_STOP);
  3102. }
  3103. void
  3104. bna_tx_cleanup_complete(struct bna_tx *tx)
  3105. {
  3106. bfa_fsm_send_event(tx, TX_E_CLEANUP_DONE);
  3107. }
  3108. static void
  3109. bna_tx_mod_cb_tx_stopped(void *arg, struct bna_tx *tx)
  3110. {
  3111. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3112. bfa_wc_down(&tx_mod->tx_stop_wc);
  3113. }
  3114. static void
  3115. bna_tx_mod_cb_tx_stopped_all(void *arg)
  3116. {
  3117. struct bna_tx_mod *tx_mod = (struct bna_tx_mod *)arg;
  3118. if (tx_mod->stop_cbfn)
  3119. tx_mod->stop_cbfn(&tx_mod->bna->enet);
  3120. tx_mod->stop_cbfn = NULL;
  3121. }
  3122. void
  3123. bna_tx_mod_init(struct bna_tx_mod *tx_mod, struct bna *bna,
  3124. struct bna_res_info *res_info)
  3125. {
  3126. int i;
  3127. tx_mod->bna = bna;
  3128. tx_mod->flags = 0;
  3129. tx_mod->tx = (struct bna_tx *)
  3130. res_info[BNA_MOD_RES_MEM_T_TX_ARRAY].res_u.mem_info.mdl[0].kva;
  3131. tx_mod->txq = (struct bna_txq *)
  3132. res_info[BNA_MOD_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mdl[0].kva;
  3133. INIT_LIST_HEAD(&tx_mod->tx_free_q);
  3134. INIT_LIST_HEAD(&tx_mod->tx_active_q);
  3135. INIT_LIST_HEAD(&tx_mod->txq_free_q);
  3136. for (i = 0; i < bna->ioceth.attr.num_txq; i++) {
  3137. tx_mod->tx[i].rid = i;
  3138. bfa_q_qe_init(&tx_mod->tx[i].qe);
  3139. list_add_tail(&tx_mod->tx[i].qe, &tx_mod->tx_free_q);
  3140. bfa_q_qe_init(&tx_mod->txq[i].qe);
  3141. list_add_tail(&tx_mod->txq[i].qe, &tx_mod->txq_free_q);
  3142. }
  3143. tx_mod->prio_map = BFI_TX_PRIO_MAP_ALL;
  3144. tx_mod->default_prio = 0;
  3145. tx_mod->iscsi_over_cee = BNA_STATUS_T_DISABLED;
  3146. tx_mod->iscsi_prio = -1;
  3147. }
  3148. void
  3149. bna_tx_mod_uninit(struct bna_tx_mod *tx_mod)
  3150. {
  3151. struct list_head *qe;
  3152. int i;
  3153. i = 0;
  3154. list_for_each(qe, &tx_mod->tx_free_q)
  3155. i++;
  3156. i = 0;
  3157. list_for_each(qe, &tx_mod->txq_free_q)
  3158. i++;
  3159. tx_mod->bna = NULL;
  3160. }
  3161. void
  3162. bna_tx_mod_start(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3163. {
  3164. struct bna_tx *tx;
  3165. struct list_head *qe;
  3166. tx_mod->flags |= BNA_TX_MOD_F_ENET_STARTED;
  3167. if (type == BNA_TX_T_LOOPBACK)
  3168. tx_mod->flags |= BNA_TX_MOD_F_ENET_LOOPBACK;
  3169. list_for_each(qe, &tx_mod->tx_active_q) {
  3170. tx = (struct bna_tx *)qe;
  3171. if (tx->type == type)
  3172. bna_tx_start(tx);
  3173. }
  3174. }
  3175. void
  3176. bna_tx_mod_stop(struct bna_tx_mod *tx_mod, enum bna_tx_type type)
  3177. {
  3178. struct bna_tx *tx;
  3179. struct list_head *qe;
  3180. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3181. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3182. tx_mod->stop_cbfn = bna_enet_cb_tx_stopped;
  3183. bfa_wc_init(&tx_mod->tx_stop_wc, bna_tx_mod_cb_tx_stopped_all, tx_mod);
  3184. list_for_each(qe, &tx_mod->tx_active_q) {
  3185. tx = (struct bna_tx *)qe;
  3186. if (tx->type == type) {
  3187. bfa_wc_up(&tx_mod->tx_stop_wc);
  3188. bna_tx_stop(tx);
  3189. }
  3190. }
  3191. bfa_wc_wait(&tx_mod->tx_stop_wc);
  3192. }
  3193. void
  3194. bna_tx_mod_fail(struct bna_tx_mod *tx_mod)
  3195. {
  3196. struct bna_tx *tx;
  3197. struct list_head *qe;
  3198. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_STARTED;
  3199. tx_mod->flags &= ~BNA_TX_MOD_F_ENET_LOOPBACK;
  3200. list_for_each(qe, &tx_mod->tx_active_q) {
  3201. tx = (struct bna_tx *)qe;
  3202. bna_tx_fail(tx);
  3203. }
  3204. }
  3205. void
  3206. bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
  3207. {
  3208. struct bna_txq *txq;
  3209. struct list_head *qe;
  3210. list_for_each(qe, &tx->txq_q) {
  3211. txq = (struct bna_txq *)qe;
  3212. bna_ib_coalescing_timeo_set(&txq->ib, coalescing_timeo);
  3213. }
  3214. }