atl1c_main.c 76 KB

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  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. /*
  26. * atl1c_pci_tbl - PCI Device ID Table
  27. *
  28. * Wildcard entries (PCI_ANY_ID) should come last
  29. * Last entry must be all 0s
  30. *
  31. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  32. * Class, Class Mask, private data (not used) }
  33. */
  34. static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
  35. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  36. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  37. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  38. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  39. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  40. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  41. /* required last entry */
  42. { 0 }
  43. };
  44. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  45. MODULE_AUTHOR("Jie Yang");
  46. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  47. MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
  48. MODULE_LICENSE("GPL");
  49. MODULE_VERSION(ATL1C_DRV_VERSION);
  50. static int atl1c_stop_mac(struct atl1c_hw *hw);
  51. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  52. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  53. static void atl1c_start_mac(struct atl1c_adapter *adapter);
  54. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  55. int *work_done, int work_to_do);
  56. static int atl1c_up(struct atl1c_adapter *adapter);
  57. static void atl1c_down(struct atl1c_adapter *adapter);
  58. static int atl1c_reset_mac(struct atl1c_hw *hw);
  59. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter);
  60. static int atl1c_configure(struct atl1c_adapter *adapter);
  61. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter);
  62. static const u16 atl1c_pay_load_size[] = {
  63. 128, 256, 512, 1024, 2048, 4096,
  64. };
  65. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  66. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  67. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  68. {
  69. u32 mst_data, data;
  70. /* pclk sel could switch to 25M */
  71. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  72. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  73. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  74. /* WoL/PCIE related settings */
  75. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  76. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  77. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  78. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  79. } else { /* new dev set bit5 of MASTER */
  80. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  81. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  82. mst_data | MASTER_CTRL_WAKEN_25M);
  83. }
  84. /* aspm/PCIE setting only for l2cb 1.0 */
  85. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  86. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  87. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  88. L2CB1_PCIE_PHYMISC2_CDR_BW);
  89. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  90. L2CB1_PCIE_PHYMISC2_L0S_TH);
  91. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  92. /* extend L1 sync timer */
  93. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  94. data |= LINK_CTRL_EXT_SYNC;
  95. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  96. }
  97. /* l2cb 1.x & l1d 1.x */
  98. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  99. AT_READ_REG(hw, REG_PM_CTRL, &data);
  100. data |= PM_CTRL_L0S_BUFSRX_EN;
  101. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  102. /* clear vendor msg */
  103. AT_READ_REG(hw, REG_DMA_DBG, &data);
  104. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  105. }
  106. }
  107. /* FIXME: no need any more ? */
  108. /*
  109. * atl1c_init_pcie - init PCIE module
  110. */
  111. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  112. {
  113. u32 data;
  114. u32 pci_cmd;
  115. struct pci_dev *pdev = hw->adapter->pdev;
  116. int pos;
  117. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  118. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  119. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  120. PCI_COMMAND_IO);
  121. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  122. /*
  123. * Clear any PowerSaveing Settings
  124. */
  125. pci_enable_wake(pdev, PCI_D3hot, 0);
  126. pci_enable_wake(pdev, PCI_D3cold, 0);
  127. /* wol sts read-clear */
  128. AT_READ_REG(hw, REG_WOL_CTRL, &data);
  129. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  130. /*
  131. * Mask some pcie error bits
  132. */
  133. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  134. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  135. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  136. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  137. /* clear error status */
  138. pcie_capability_write_word(pdev, PCI_EXP_DEVSTA,
  139. PCI_EXP_DEVSTA_NFED |
  140. PCI_EXP_DEVSTA_FED |
  141. PCI_EXP_DEVSTA_CED |
  142. PCI_EXP_DEVSTA_URD);
  143. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  144. data &= ~LTSSM_ID_EN_WRO;
  145. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  146. atl1c_pcie_patch(hw);
  147. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  148. atl1c_disable_l0s_l1(hw);
  149. msleep(5);
  150. }
  151. /**
  152. * atl1c_irq_enable - Enable default interrupt generation settings
  153. * @adapter: board private structure
  154. */
  155. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  156. {
  157. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  158. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  159. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  160. AT_WRITE_FLUSH(&adapter->hw);
  161. }
  162. }
  163. /**
  164. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  165. * @adapter: board private structure
  166. */
  167. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  168. {
  169. atomic_inc(&adapter->irq_sem);
  170. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  171. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  172. AT_WRITE_FLUSH(&adapter->hw);
  173. synchronize_irq(adapter->pdev->irq);
  174. }
  175. /**
  176. * atl1c_irq_reset - reset interrupt confiure on the NIC
  177. * @adapter: board private structure
  178. */
  179. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  180. {
  181. atomic_set(&adapter->irq_sem, 1);
  182. atl1c_irq_enable(adapter);
  183. }
  184. /*
  185. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  186. * of the idle status register until the device is actually idle
  187. */
  188. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  189. {
  190. int timeout;
  191. u32 data;
  192. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  193. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  194. if ((data & modu_ctrl) == 0)
  195. return 0;
  196. msleep(1);
  197. }
  198. return data;
  199. }
  200. /**
  201. * atl1c_phy_config - Timer Call-back
  202. * @data: pointer to netdev cast into an unsigned long
  203. */
  204. static void atl1c_phy_config(unsigned long data)
  205. {
  206. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  207. struct atl1c_hw *hw = &adapter->hw;
  208. unsigned long flags;
  209. spin_lock_irqsave(&adapter->mdio_lock, flags);
  210. atl1c_restart_autoneg(hw);
  211. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  212. }
  213. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  214. {
  215. WARN_ON(in_interrupt());
  216. atl1c_down(adapter);
  217. atl1c_up(adapter);
  218. clear_bit(__AT_RESETTING, &adapter->flags);
  219. }
  220. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  221. {
  222. struct atl1c_hw *hw = &adapter->hw;
  223. struct net_device *netdev = adapter->netdev;
  224. struct pci_dev *pdev = adapter->pdev;
  225. int err;
  226. unsigned long flags;
  227. u16 speed, duplex, phy_data;
  228. spin_lock_irqsave(&adapter->mdio_lock, flags);
  229. /* MII_BMSR must read twise */
  230. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  231. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  232. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  233. if ((phy_data & BMSR_LSTATUS) == 0) {
  234. /* link down */
  235. netif_carrier_off(netdev);
  236. hw->hibernate = true;
  237. if (atl1c_reset_mac(hw) != 0)
  238. if (netif_msg_hw(adapter))
  239. dev_warn(&pdev->dev, "reset mac failed\n");
  240. atl1c_set_aspm(hw, SPEED_0);
  241. atl1c_post_phy_linkchg(hw, SPEED_0);
  242. atl1c_reset_dma_ring(adapter);
  243. atl1c_configure(adapter);
  244. } else {
  245. /* Link Up */
  246. hw->hibernate = false;
  247. spin_lock_irqsave(&adapter->mdio_lock, flags);
  248. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  249. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  250. if (unlikely(err))
  251. return;
  252. /* link result is our setting */
  253. if (adapter->link_speed != speed ||
  254. adapter->link_duplex != duplex) {
  255. adapter->link_speed = speed;
  256. adapter->link_duplex = duplex;
  257. atl1c_set_aspm(hw, speed);
  258. atl1c_post_phy_linkchg(hw, speed);
  259. atl1c_start_mac(adapter);
  260. if (netif_msg_link(adapter))
  261. dev_info(&pdev->dev,
  262. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  263. atl1c_driver_name, netdev->name,
  264. adapter->link_speed,
  265. adapter->link_duplex == FULL_DUPLEX ?
  266. "Full Duplex" : "Half Duplex");
  267. }
  268. if (!netif_carrier_ok(netdev))
  269. netif_carrier_on(netdev);
  270. }
  271. }
  272. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  273. {
  274. struct net_device *netdev = adapter->netdev;
  275. struct pci_dev *pdev = adapter->pdev;
  276. u16 phy_data;
  277. u16 link_up;
  278. spin_lock(&adapter->mdio_lock);
  279. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  280. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  281. spin_unlock(&adapter->mdio_lock);
  282. link_up = phy_data & BMSR_LSTATUS;
  283. /* notify upper layer link down ASAP */
  284. if (!link_up) {
  285. if (netif_carrier_ok(netdev)) {
  286. /* old link state: Up */
  287. netif_carrier_off(netdev);
  288. if (netif_msg_link(adapter))
  289. dev_info(&pdev->dev,
  290. "%s: %s NIC Link is Down\n",
  291. atl1c_driver_name, netdev->name);
  292. adapter->link_speed = SPEED_0;
  293. }
  294. }
  295. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  296. schedule_work(&adapter->common_task);
  297. }
  298. static void atl1c_common_task(struct work_struct *work)
  299. {
  300. struct atl1c_adapter *adapter;
  301. struct net_device *netdev;
  302. adapter = container_of(work, struct atl1c_adapter, common_task);
  303. netdev = adapter->netdev;
  304. if (test_bit(__AT_DOWN, &adapter->flags))
  305. return;
  306. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  307. netif_device_detach(netdev);
  308. atl1c_down(adapter);
  309. atl1c_up(adapter);
  310. netif_device_attach(netdev);
  311. }
  312. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  313. &adapter->work_event)) {
  314. atl1c_irq_disable(adapter);
  315. atl1c_check_link_status(adapter);
  316. atl1c_irq_enable(adapter);
  317. }
  318. }
  319. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  320. {
  321. del_timer_sync(&adapter->phy_config_timer);
  322. }
  323. /**
  324. * atl1c_tx_timeout - Respond to a Tx Hang
  325. * @netdev: network interface device structure
  326. */
  327. static void atl1c_tx_timeout(struct net_device *netdev)
  328. {
  329. struct atl1c_adapter *adapter = netdev_priv(netdev);
  330. /* Do the reset outside of interrupt context */
  331. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  332. schedule_work(&adapter->common_task);
  333. }
  334. /**
  335. * atl1c_set_multi - Multicast and Promiscuous mode set
  336. * @netdev: network interface device structure
  337. *
  338. * The set_multi entry point is called whenever the multicast address
  339. * list or the network interface flags are updated. This routine is
  340. * responsible for configuring the hardware for proper multicast,
  341. * promiscuous mode, and all-multi behavior.
  342. */
  343. static void atl1c_set_multi(struct net_device *netdev)
  344. {
  345. struct atl1c_adapter *adapter = netdev_priv(netdev);
  346. struct atl1c_hw *hw = &adapter->hw;
  347. struct netdev_hw_addr *ha;
  348. u32 mac_ctrl_data;
  349. u32 hash_value;
  350. /* Check for Promiscuous and All Multicast modes */
  351. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  352. if (netdev->flags & IFF_PROMISC) {
  353. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  354. } else if (netdev->flags & IFF_ALLMULTI) {
  355. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  356. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  357. } else {
  358. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  359. }
  360. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  361. /* clear the old settings from the multicast hash table */
  362. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  363. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  364. /* comoute mc addresses' hash value ,and put it into hash table */
  365. netdev_for_each_mc_addr(ha, netdev) {
  366. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  367. atl1c_hash_set(hw, hash_value);
  368. }
  369. }
  370. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  371. {
  372. if (features & NETIF_F_HW_VLAN_RX) {
  373. /* enable VLAN tag insert/strip */
  374. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  375. } else {
  376. /* disable VLAN tag insert/strip */
  377. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  378. }
  379. }
  380. static void atl1c_vlan_mode(struct net_device *netdev,
  381. netdev_features_t features)
  382. {
  383. struct atl1c_adapter *adapter = netdev_priv(netdev);
  384. struct pci_dev *pdev = adapter->pdev;
  385. u32 mac_ctrl_data = 0;
  386. if (netif_msg_pktdata(adapter))
  387. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  388. atl1c_irq_disable(adapter);
  389. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  390. __atl1c_vlan_mode(features, &mac_ctrl_data);
  391. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  392. atl1c_irq_enable(adapter);
  393. }
  394. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  395. {
  396. struct pci_dev *pdev = adapter->pdev;
  397. if (netif_msg_pktdata(adapter))
  398. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  399. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  400. }
  401. /**
  402. * atl1c_set_mac - Change the Ethernet Address of the NIC
  403. * @netdev: network interface device structure
  404. * @p: pointer to an address structure
  405. *
  406. * Returns 0 on success, negative on failure
  407. */
  408. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  409. {
  410. struct atl1c_adapter *adapter = netdev_priv(netdev);
  411. struct sockaddr *addr = p;
  412. if (!is_valid_ether_addr(addr->sa_data))
  413. return -EADDRNOTAVAIL;
  414. if (netif_running(netdev))
  415. return -EBUSY;
  416. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  417. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  418. netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
  419. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  420. return 0;
  421. }
  422. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  423. struct net_device *dev)
  424. {
  425. int mtu = dev->mtu;
  426. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  427. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  428. }
  429. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  430. netdev_features_t features)
  431. {
  432. /*
  433. * Since there is no support for separate rx/tx vlan accel
  434. * enable/disable make sure tx flag is always in same state as rx.
  435. */
  436. if (features & NETIF_F_HW_VLAN_RX)
  437. features |= NETIF_F_HW_VLAN_TX;
  438. else
  439. features &= ~NETIF_F_HW_VLAN_TX;
  440. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  441. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  442. return features;
  443. }
  444. static int atl1c_set_features(struct net_device *netdev,
  445. netdev_features_t features)
  446. {
  447. netdev_features_t changed = netdev->features ^ features;
  448. if (changed & NETIF_F_HW_VLAN_RX)
  449. atl1c_vlan_mode(netdev, features);
  450. return 0;
  451. }
  452. /**
  453. * atl1c_change_mtu - Change the Maximum Transfer Unit
  454. * @netdev: network interface device structure
  455. * @new_mtu: new value for maximum frame size
  456. *
  457. * Returns 0 on success, negative on failure
  458. */
  459. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  460. {
  461. struct atl1c_adapter *adapter = netdev_priv(netdev);
  462. struct atl1c_hw *hw = &adapter->hw;
  463. int old_mtu = netdev->mtu;
  464. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  465. /* Fast Ethernet controller doesn't support jumbo packet */
  466. if (((hw->nic_type == athr_l2c ||
  467. hw->nic_type == athr_l2c_b ||
  468. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  469. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  470. max_frame > MAX_JUMBO_FRAME_SIZE) {
  471. if (netif_msg_link(adapter))
  472. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  473. return -EINVAL;
  474. }
  475. /* set MTU */
  476. if (old_mtu != new_mtu && netif_running(netdev)) {
  477. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  478. msleep(1);
  479. netdev->mtu = new_mtu;
  480. adapter->hw.max_frame_size = new_mtu;
  481. atl1c_set_rxbufsize(adapter, netdev);
  482. atl1c_down(adapter);
  483. netdev_update_features(netdev);
  484. atl1c_up(adapter);
  485. clear_bit(__AT_RESETTING, &adapter->flags);
  486. }
  487. return 0;
  488. }
  489. /*
  490. * caller should hold mdio_lock
  491. */
  492. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  493. {
  494. struct atl1c_adapter *adapter = netdev_priv(netdev);
  495. u16 result;
  496. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  497. return result;
  498. }
  499. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  500. int reg_num, int val)
  501. {
  502. struct atl1c_adapter *adapter = netdev_priv(netdev);
  503. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  504. }
  505. static int atl1c_mii_ioctl(struct net_device *netdev,
  506. struct ifreq *ifr, int cmd)
  507. {
  508. struct atl1c_adapter *adapter = netdev_priv(netdev);
  509. struct pci_dev *pdev = adapter->pdev;
  510. struct mii_ioctl_data *data = if_mii(ifr);
  511. unsigned long flags;
  512. int retval = 0;
  513. if (!netif_running(netdev))
  514. return -EINVAL;
  515. spin_lock_irqsave(&adapter->mdio_lock, flags);
  516. switch (cmd) {
  517. case SIOCGMIIPHY:
  518. data->phy_id = 0;
  519. break;
  520. case SIOCGMIIREG:
  521. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  522. &data->val_out)) {
  523. retval = -EIO;
  524. goto out;
  525. }
  526. break;
  527. case SIOCSMIIREG:
  528. if (data->reg_num & ~(0x1F)) {
  529. retval = -EFAULT;
  530. goto out;
  531. }
  532. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  533. data->reg_num, data->val_in);
  534. if (atl1c_write_phy_reg(&adapter->hw,
  535. data->reg_num, data->val_in)) {
  536. retval = -EIO;
  537. goto out;
  538. }
  539. break;
  540. default:
  541. retval = -EOPNOTSUPP;
  542. break;
  543. }
  544. out:
  545. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  546. return retval;
  547. }
  548. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  549. {
  550. switch (cmd) {
  551. case SIOCGMIIPHY:
  552. case SIOCGMIIREG:
  553. case SIOCSMIIREG:
  554. return atl1c_mii_ioctl(netdev, ifr, cmd);
  555. default:
  556. return -EOPNOTSUPP;
  557. }
  558. }
  559. /**
  560. * atl1c_alloc_queues - Allocate memory for all rings
  561. * @adapter: board private structure to initialize
  562. *
  563. */
  564. static int atl1c_alloc_queues(struct atl1c_adapter *adapter)
  565. {
  566. return 0;
  567. }
  568. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  569. {
  570. switch (hw->device_id) {
  571. case PCI_DEVICE_ID_ATTANSIC_L2C:
  572. hw->nic_type = athr_l2c;
  573. break;
  574. case PCI_DEVICE_ID_ATTANSIC_L1C:
  575. hw->nic_type = athr_l1c;
  576. break;
  577. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  578. hw->nic_type = athr_l2c_b;
  579. break;
  580. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  581. hw->nic_type = athr_l2c_b2;
  582. break;
  583. case PCI_DEVICE_ID_ATHEROS_L1D:
  584. hw->nic_type = athr_l1d;
  585. break;
  586. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  587. hw->nic_type = athr_l1d_2;
  588. break;
  589. default:
  590. break;
  591. }
  592. }
  593. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  594. {
  595. u32 link_ctrl_data;
  596. atl1c_set_mac_type(hw);
  597. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  598. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  599. ATL1C_TXQ_MODE_ENHANCE;
  600. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  601. ATL1C_ASPM_L1_SUPPORT;
  602. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  603. if (hw->nic_type == athr_l1c ||
  604. hw->nic_type == athr_l1d ||
  605. hw->nic_type == athr_l1d_2)
  606. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  607. return 0;
  608. }
  609. struct atl1c_platform_patch {
  610. u16 pci_did;
  611. u8 pci_revid;
  612. u16 subsystem_vid;
  613. u16 subsystem_did;
  614. u32 patch_flag;
  615. #define ATL1C_LINK_PATCH 0x1
  616. };
  617. static const struct atl1c_platform_patch plats[] = {
  618. {0x2060, 0xC1, 0x1019, 0x8152, 0x1},
  619. {0x2060, 0xC1, 0x1019, 0x2060, 0x1},
  620. {0x2060, 0xC1, 0x1019, 0xE000, 0x1},
  621. {0x2062, 0xC0, 0x1019, 0x8152, 0x1},
  622. {0x2062, 0xC0, 0x1019, 0x2062, 0x1},
  623. {0x2062, 0xC0, 0x1458, 0xE000, 0x1},
  624. {0x2062, 0xC1, 0x1019, 0x8152, 0x1},
  625. {0x2062, 0xC1, 0x1019, 0x2062, 0x1},
  626. {0x2062, 0xC1, 0x1458, 0xE000, 0x1},
  627. {0x2062, 0xC1, 0x1565, 0x2802, 0x1},
  628. {0x2062, 0xC1, 0x1565, 0x2801, 0x1},
  629. {0x1073, 0xC0, 0x1019, 0x8151, 0x1},
  630. {0x1073, 0xC0, 0x1019, 0x1073, 0x1},
  631. {0x1073, 0xC0, 0x1458, 0xE000, 0x1},
  632. {0x1083, 0xC0, 0x1458, 0xE000, 0x1},
  633. {0x1083, 0xC0, 0x1019, 0x8151, 0x1},
  634. {0x1083, 0xC0, 0x1019, 0x1083, 0x1},
  635. {0x1083, 0xC0, 0x1462, 0x7680, 0x1},
  636. {0x1083, 0xC0, 0x1565, 0x2803, 0x1},
  637. {0},
  638. };
  639. static void atl1c_patch_assign(struct atl1c_hw *hw)
  640. {
  641. struct pci_dev *pdev = hw->adapter->pdev;
  642. u32 misc_ctrl;
  643. int i = 0;
  644. hw->msi_lnkpatch = false;
  645. while (plats[i].pci_did != 0) {
  646. if (plats[i].pci_did == hw->device_id &&
  647. plats[i].pci_revid == hw->revision_id &&
  648. plats[i].subsystem_vid == hw->subsystem_vendor_id &&
  649. plats[i].subsystem_did == hw->subsystem_id) {
  650. if (plats[i].patch_flag & ATL1C_LINK_PATCH)
  651. hw->msi_lnkpatch = true;
  652. }
  653. i++;
  654. }
  655. if (hw->device_id == PCI_DEVICE_ID_ATHEROS_L2C_B2 &&
  656. hw->revision_id == L2CB_V21) {
  657. /* config acess mode */
  658. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  659. REG_PCIE_DEV_MISC_CTRL);
  660. pci_read_config_dword(pdev, REG_PCIE_IND_ACC_DATA, &misc_ctrl);
  661. misc_ctrl &= ~0x100;
  662. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_ADDR,
  663. REG_PCIE_DEV_MISC_CTRL);
  664. pci_write_config_dword(pdev, REG_PCIE_IND_ACC_DATA, misc_ctrl);
  665. }
  666. }
  667. /**
  668. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  669. * @adapter: board private structure to initialize
  670. *
  671. * atl1c_sw_init initializes the Adapter private data structure.
  672. * Fields are initialized based on PCI device information and
  673. * OS network device settings (MTU size).
  674. */
  675. static int atl1c_sw_init(struct atl1c_adapter *adapter)
  676. {
  677. struct atl1c_hw *hw = &adapter->hw;
  678. struct pci_dev *pdev = adapter->pdev;
  679. u32 revision;
  680. adapter->wol = 0;
  681. device_set_wakeup_enable(&pdev->dev, false);
  682. adapter->link_speed = SPEED_0;
  683. adapter->link_duplex = FULL_DUPLEX;
  684. adapter->tpd_ring[0].count = 1024;
  685. adapter->rfd_ring.count = 512;
  686. hw->vendor_id = pdev->vendor;
  687. hw->device_id = pdev->device;
  688. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  689. hw->subsystem_id = pdev->subsystem_device;
  690. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &revision);
  691. hw->revision_id = revision & 0xFF;
  692. /* before link up, we assume hibernate is true */
  693. hw->hibernate = true;
  694. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  695. if (atl1c_setup_mac_funcs(hw) != 0) {
  696. dev_err(&pdev->dev, "set mac function pointers failed\n");
  697. return -1;
  698. }
  699. atl1c_patch_assign(hw);
  700. hw->intr_mask = IMR_NORMAL_MASK;
  701. hw->phy_configured = false;
  702. hw->preamble_len = 7;
  703. hw->max_frame_size = adapter->netdev->mtu;
  704. hw->autoneg_advertised = ADVERTISED_Autoneg;
  705. hw->indirect_tab = 0xE4E4E4E4;
  706. hw->base_cpu = 0;
  707. hw->ict = 50000; /* 100ms */
  708. hw->smb_timer = 200000; /* 400ms */
  709. hw->rx_imt = 200;
  710. hw->tx_imt = 1000;
  711. hw->tpd_burst = 5;
  712. hw->rfd_burst = 8;
  713. hw->dma_order = atl1c_dma_ord_out;
  714. hw->dmar_block = atl1c_dma_req_1024;
  715. if (atl1c_alloc_queues(adapter)) {
  716. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  717. return -ENOMEM;
  718. }
  719. /* TODO */
  720. atl1c_set_rxbufsize(adapter, adapter->netdev);
  721. atomic_set(&adapter->irq_sem, 1);
  722. spin_lock_init(&adapter->mdio_lock);
  723. spin_lock_init(&adapter->tx_lock);
  724. set_bit(__AT_DOWN, &adapter->flags);
  725. return 0;
  726. }
  727. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  728. struct atl1c_buffer *buffer_info, int in_irq)
  729. {
  730. u16 pci_driection;
  731. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  732. return;
  733. if (buffer_info->dma) {
  734. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  735. pci_driection = PCI_DMA_FROMDEVICE;
  736. else
  737. pci_driection = PCI_DMA_TODEVICE;
  738. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  739. pci_unmap_single(pdev, buffer_info->dma,
  740. buffer_info->length, pci_driection);
  741. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  742. pci_unmap_page(pdev, buffer_info->dma,
  743. buffer_info->length, pci_driection);
  744. }
  745. if (buffer_info->skb) {
  746. if (in_irq)
  747. dev_kfree_skb_irq(buffer_info->skb);
  748. else
  749. dev_kfree_skb(buffer_info->skb);
  750. }
  751. buffer_info->dma = 0;
  752. buffer_info->skb = NULL;
  753. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  754. }
  755. /**
  756. * atl1c_clean_tx_ring - Free Tx-skb
  757. * @adapter: board private structure
  758. */
  759. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  760. enum atl1c_trans_queue type)
  761. {
  762. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  763. struct atl1c_buffer *buffer_info;
  764. struct pci_dev *pdev = adapter->pdev;
  765. u16 index, ring_count;
  766. ring_count = tpd_ring->count;
  767. for (index = 0; index < ring_count; index++) {
  768. buffer_info = &tpd_ring->buffer_info[index];
  769. atl1c_clean_buffer(pdev, buffer_info, 0);
  770. }
  771. /* Zero out Tx-buffers */
  772. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  773. ring_count);
  774. atomic_set(&tpd_ring->next_to_clean, 0);
  775. tpd_ring->next_to_use = 0;
  776. }
  777. /**
  778. * atl1c_clean_rx_ring - Free rx-reservation skbs
  779. * @adapter: board private structure
  780. */
  781. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  782. {
  783. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  784. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  785. struct atl1c_buffer *buffer_info;
  786. struct pci_dev *pdev = adapter->pdev;
  787. int j;
  788. for (j = 0; j < rfd_ring->count; j++) {
  789. buffer_info = &rfd_ring->buffer_info[j];
  790. atl1c_clean_buffer(pdev, buffer_info, 0);
  791. }
  792. /* zero out the descriptor ring */
  793. memset(rfd_ring->desc, 0, rfd_ring->size);
  794. rfd_ring->next_to_clean = 0;
  795. rfd_ring->next_to_use = 0;
  796. rrd_ring->next_to_use = 0;
  797. rrd_ring->next_to_clean = 0;
  798. }
  799. /*
  800. * Read / Write Ptr Initialize:
  801. */
  802. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  803. {
  804. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  805. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  806. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  807. struct atl1c_buffer *buffer_info;
  808. int i, j;
  809. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  810. tpd_ring[i].next_to_use = 0;
  811. atomic_set(&tpd_ring[i].next_to_clean, 0);
  812. buffer_info = tpd_ring[i].buffer_info;
  813. for (j = 0; j < tpd_ring->count; j++)
  814. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  815. ATL1C_BUFFER_FREE);
  816. }
  817. rfd_ring->next_to_use = 0;
  818. rfd_ring->next_to_clean = 0;
  819. rrd_ring->next_to_use = 0;
  820. rrd_ring->next_to_clean = 0;
  821. for (j = 0; j < rfd_ring->count; j++) {
  822. buffer_info = &rfd_ring->buffer_info[j];
  823. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  824. }
  825. }
  826. /**
  827. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  828. * @adapter: board private structure
  829. *
  830. * Free all transmit software resources
  831. */
  832. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  833. {
  834. struct pci_dev *pdev = adapter->pdev;
  835. pci_free_consistent(pdev, adapter->ring_header.size,
  836. adapter->ring_header.desc,
  837. adapter->ring_header.dma);
  838. adapter->ring_header.desc = NULL;
  839. /* Note: just free tdp_ring.buffer_info,
  840. * it contain rfd_ring.buffer_info, do not double free */
  841. if (adapter->tpd_ring[0].buffer_info) {
  842. kfree(adapter->tpd_ring[0].buffer_info);
  843. adapter->tpd_ring[0].buffer_info = NULL;
  844. }
  845. }
  846. /**
  847. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  848. * @adapter: board private structure
  849. *
  850. * Return 0 on success, negative on failure
  851. */
  852. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  853. {
  854. struct pci_dev *pdev = adapter->pdev;
  855. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  856. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  857. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  858. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  859. int size;
  860. int i;
  861. int count = 0;
  862. int rx_desc_count = 0;
  863. u32 offset = 0;
  864. rrd_ring->count = rfd_ring->count;
  865. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  866. tpd_ring[i].count = tpd_ring[0].count;
  867. /* 2 tpd queue, one high priority queue,
  868. * another normal priority queue */
  869. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  870. rfd_ring->count);
  871. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  872. if (unlikely(!tpd_ring->buffer_info)) {
  873. dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
  874. size);
  875. goto err_nomem;
  876. }
  877. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  878. tpd_ring[i].buffer_info =
  879. (tpd_ring->buffer_info + count);
  880. count += tpd_ring[i].count;
  881. }
  882. rfd_ring->buffer_info =
  883. (tpd_ring->buffer_info + count);
  884. count += rfd_ring->count;
  885. rx_desc_count += rfd_ring->count;
  886. /*
  887. * real ring DMA buffer
  888. * each ring/block may need up to 8 bytes for alignment, hence the
  889. * additional bytes tacked onto the end.
  890. */
  891. ring_header->size = size =
  892. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  893. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  894. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  895. 8 * 4;
  896. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  897. &ring_header->dma);
  898. if (unlikely(!ring_header->desc)) {
  899. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  900. goto err_nomem;
  901. }
  902. memset(ring_header->desc, 0, ring_header->size);
  903. /* init TPD ring */
  904. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  905. offset = tpd_ring[0].dma - ring_header->dma;
  906. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  907. tpd_ring[i].dma = ring_header->dma + offset;
  908. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  909. tpd_ring[i].size =
  910. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  911. offset += roundup(tpd_ring[i].size, 8);
  912. }
  913. /* init RFD ring */
  914. rfd_ring->dma = ring_header->dma + offset;
  915. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  916. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  917. offset += roundup(rfd_ring->size, 8);
  918. /* init RRD ring */
  919. rrd_ring->dma = ring_header->dma + offset;
  920. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  921. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  922. rrd_ring->count;
  923. offset += roundup(rrd_ring->size, 8);
  924. return 0;
  925. err_nomem:
  926. kfree(tpd_ring->buffer_info);
  927. return -ENOMEM;
  928. }
  929. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  930. {
  931. struct atl1c_hw *hw = &adapter->hw;
  932. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  933. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  934. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  935. adapter->tpd_ring;
  936. /* TPD */
  937. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  938. (u32)((tpd_ring[atl1c_trans_normal].dma &
  939. AT_DMA_HI_ADDR_MASK) >> 32));
  940. /* just enable normal priority TX queue */
  941. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  942. (u32)(tpd_ring[atl1c_trans_normal].dma &
  943. AT_DMA_LO_ADDR_MASK));
  944. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  945. (u32)(tpd_ring[atl1c_trans_high].dma &
  946. AT_DMA_LO_ADDR_MASK));
  947. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  948. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  949. /* RFD */
  950. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  951. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  952. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  953. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  954. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  955. rfd_ring->count & RFD_RING_SIZE_MASK);
  956. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  957. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  958. /* RRD */
  959. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  960. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  961. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  962. (rrd_ring->count & RRD_RING_SIZE_MASK));
  963. if (hw->nic_type == athr_l2c_b) {
  964. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  965. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  966. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  967. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  968. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  969. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  970. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  971. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  972. }
  973. /* Load all of base address above */
  974. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  975. }
  976. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  977. {
  978. struct atl1c_hw *hw = &adapter->hw;
  979. int max_pay_load;
  980. u16 tx_offload_thresh;
  981. u32 txq_ctrl_data;
  982. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  983. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  984. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  985. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  986. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  987. /*
  988. * if BIOS had changed the dam-read-max-length to an invalid value,
  989. * restore it to default value
  990. */
  991. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  992. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  993. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  994. }
  995. txq_ctrl_data =
  996. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  997. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  998. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  999. }
  1000. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  1001. {
  1002. struct atl1c_hw *hw = &adapter->hw;
  1003. u32 rxq_ctrl_data;
  1004. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  1005. RXQ_RFD_BURST_NUM_SHIFT;
  1006. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  1007. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  1008. /* aspm for gigabit */
  1009. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  1010. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  1011. ASPM_THRUPUT_LIMIT_100M);
  1012. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  1013. }
  1014. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  1015. {
  1016. struct atl1c_hw *hw = &adapter->hw;
  1017. u32 dma_ctrl_data;
  1018. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  1019. DMA_CTRL_RREQ_PRI_DATA |
  1020. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  1021. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  1022. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  1023. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  1024. }
  1025. /*
  1026. * Stop the mac, transmit and receive units
  1027. * hw - Struct containing variables accessed by shared code
  1028. * return : 0 or idle status (if error)
  1029. */
  1030. static int atl1c_stop_mac(struct atl1c_hw *hw)
  1031. {
  1032. u32 data;
  1033. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1034. data &= ~RXQ_CTRL_EN;
  1035. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1036. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1037. data &= ~TXQ_CTRL_EN;
  1038. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1039. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  1040. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  1041. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  1042. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  1043. return (int)atl1c_wait_until_idle(hw,
  1044. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1045. }
  1046. static void atl1c_start_mac(struct atl1c_adapter *adapter)
  1047. {
  1048. struct atl1c_hw *hw = &adapter->hw;
  1049. u32 mac, txq, rxq;
  1050. hw->mac_duplex = adapter->link_duplex == FULL_DUPLEX ? true : false;
  1051. hw->mac_speed = adapter->link_speed == SPEED_1000 ?
  1052. atl1c_mac_speed_1000 : atl1c_mac_speed_10_100;
  1053. AT_READ_REG(hw, REG_TXQ_CTRL, &txq);
  1054. AT_READ_REG(hw, REG_RXQ_CTRL, &rxq);
  1055. AT_READ_REG(hw, REG_MAC_CTRL, &mac);
  1056. txq |= TXQ_CTRL_EN;
  1057. rxq |= RXQ_CTRL_EN;
  1058. mac |= MAC_CTRL_TX_EN | MAC_CTRL_TX_FLOW |
  1059. MAC_CTRL_RX_EN | MAC_CTRL_RX_FLOW |
  1060. MAC_CTRL_ADD_CRC | MAC_CTRL_PAD |
  1061. MAC_CTRL_BC_EN | MAC_CTRL_SINGLE_PAUSE_EN |
  1062. MAC_CTRL_HASH_ALG_CRC32;
  1063. if (hw->mac_duplex)
  1064. mac |= MAC_CTRL_DUPLX;
  1065. else
  1066. mac &= ~MAC_CTRL_DUPLX;
  1067. mac = FIELD_SETX(mac, MAC_CTRL_SPEED, hw->mac_speed);
  1068. mac = FIELD_SETX(mac, MAC_CTRL_PRMLEN, hw->preamble_len);
  1069. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq);
  1070. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq);
  1071. AT_WRITE_REG(hw, REG_MAC_CTRL, mac);
  1072. }
  1073. /*
  1074. * Reset the transmit and receive units; mask and clear all interrupts.
  1075. * hw - Struct containing variables accessed by shared code
  1076. * return : 0 or idle status (if error)
  1077. */
  1078. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1079. {
  1080. struct atl1c_adapter *adapter = hw->adapter;
  1081. struct pci_dev *pdev = adapter->pdev;
  1082. u32 ctrl_data = 0;
  1083. atl1c_stop_mac(hw);
  1084. /*
  1085. * Issue Soft Reset to the MAC. This will reset the chip's
  1086. * transmit, receive, DMA. It will not effect
  1087. * the current PCI configuration. The global reset bit is self-
  1088. * clearing, and should clear within a microsecond.
  1089. */
  1090. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1091. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1092. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1093. AT_WRITE_FLUSH(hw);
  1094. msleep(10);
  1095. /* Wait at least 10ms for All module to be Idle */
  1096. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1097. dev_err(&pdev->dev,
  1098. "MAC state machine can't be idle since"
  1099. " disabled for 10ms second\n");
  1100. return -1;
  1101. }
  1102. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1103. /* driver control speed/duplex */
  1104. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1105. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1106. /* clk switch setting */
  1107. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1108. switch (hw->nic_type) {
  1109. case athr_l2c_b:
  1110. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1111. SERDES_MAC_CLK_SLOWDOWN);
  1112. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1113. break;
  1114. case athr_l2c_b2:
  1115. case athr_l1d_2:
  1116. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1117. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1118. break;
  1119. default:
  1120. break;
  1121. }
  1122. return 0;
  1123. }
  1124. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1125. {
  1126. u16 ctrl_flags = hw->ctrl_flags;
  1127. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1128. atl1c_set_aspm(hw, SPEED_0);
  1129. hw->ctrl_flags = ctrl_flags;
  1130. }
  1131. /*
  1132. * Set ASPM state.
  1133. * Enable/disable L0s/L1 depend on link state.
  1134. */
  1135. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1136. {
  1137. u32 pm_ctrl_data;
  1138. u32 link_l1_timer;
  1139. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1140. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1141. PM_CTRL_ASPM_L0S_EN |
  1142. PM_CTRL_MAC_ASPM_CHK);
  1143. /* L1 timer */
  1144. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1145. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1146. link_l1_timer =
  1147. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1148. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1149. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1150. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1151. } else {
  1152. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1153. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1154. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1155. link_l1_timer = 1;
  1156. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1157. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1158. }
  1159. /* L0S/L1 enable */
  1160. if ((hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT) && link_speed != SPEED_0)
  1161. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1162. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1163. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1164. /* l2cb & l1d & l2cb2 & l1d2 */
  1165. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1166. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1167. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1168. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1169. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1170. PM_CTRL_SERDES_PD_EX_L1 |
  1171. PM_CTRL_CLK_SWH_L1;
  1172. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1173. PM_CTRL_SERDES_PLL_L1_EN |
  1174. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1175. PM_CTRL_SA_DLY_EN |
  1176. PM_CTRL_HOTRST);
  1177. /* disable l0s if link down or l2cb */
  1178. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1179. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1180. } else { /* l1c */
  1181. pm_ctrl_data =
  1182. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1183. if (link_speed != SPEED_0) {
  1184. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1185. PM_CTRL_SERDES_PLL_L1_EN |
  1186. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1187. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1188. PM_CTRL_CLK_SWH_L1 |
  1189. PM_CTRL_ASPM_L0S_EN |
  1190. PM_CTRL_ASPM_L1_EN);
  1191. } else { /* link down */
  1192. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1193. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1194. PM_CTRL_SERDES_PLL_L1_EN |
  1195. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1196. PM_CTRL_ASPM_L0S_EN);
  1197. }
  1198. }
  1199. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1200. return;
  1201. }
  1202. /**
  1203. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1204. * @adapter: board private structure
  1205. *
  1206. * Configure the Tx /Rx unit of the MAC after a reset.
  1207. */
  1208. static int atl1c_configure_mac(struct atl1c_adapter *adapter)
  1209. {
  1210. struct atl1c_hw *hw = &adapter->hw;
  1211. u32 master_ctrl_data = 0;
  1212. u32 intr_modrt_data;
  1213. u32 data;
  1214. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1215. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1216. MASTER_CTRL_RX_ITIMER_EN |
  1217. MASTER_CTRL_INT_RDCLR);
  1218. /* clear interrupt status */
  1219. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1220. /* Clear any WOL status */
  1221. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1222. /* set Interrupt Clear Timer
  1223. * HW will enable self to assert interrupt event to system after
  1224. * waiting x-time for software to notify it accept interrupt.
  1225. */
  1226. data = CLK_GATING_EN_ALL;
  1227. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1228. if (hw->nic_type == athr_l2c_b)
  1229. data &= ~CLK_GATING_RXMAC_EN;
  1230. } else
  1231. data = 0;
  1232. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1233. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1234. hw->ict & INT_RETRIG_TIMER_MASK);
  1235. atl1c_configure_des_ring(adapter);
  1236. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1237. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1238. IRQ_MODRT_TX_TIMER_SHIFT;
  1239. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1240. IRQ_MODRT_RX_TIMER_SHIFT;
  1241. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1242. master_ctrl_data |=
  1243. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1244. }
  1245. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1246. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1247. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1248. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1249. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1250. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1251. /* set MTU */
  1252. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1253. VLAN_HLEN + ETH_FCS_LEN);
  1254. atl1c_configure_tx(adapter);
  1255. atl1c_configure_rx(adapter);
  1256. atl1c_configure_dma(adapter);
  1257. return 0;
  1258. }
  1259. static int atl1c_configure(struct atl1c_adapter *adapter)
  1260. {
  1261. struct net_device *netdev = adapter->netdev;
  1262. int num;
  1263. atl1c_init_ring_ptrs(adapter);
  1264. atl1c_set_multi(netdev);
  1265. atl1c_restore_vlan(adapter);
  1266. num = atl1c_alloc_rx_buffer(adapter);
  1267. if (unlikely(num == 0))
  1268. return -ENOMEM;
  1269. if (atl1c_configure_mac(adapter))
  1270. return -EIO;
  1271. return 0;
  1272. }
  1273. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1274. {
  1275. u16 hw_reg_addr = 0;
  1276. unsigned long *stats_item = NULL;
  1277. u32 data;
  1278. /* update rx status */
  1279. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1280. stats_item = &adapter->hw_stats.rx_ok;
  1281. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1282. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1283. *stats_item += data;
  1284. stats_item++;
  1285. hw_reg_addr += 4;
  1286. }
  1287. /* update tx status */
  1288. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1289. stats_item = &adapter->hw_stats.tx_ok;
  1290. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1291. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1292. *stats_item += data;
  1293. stats_item++;
  1294. hw_reg_addr += 4;
  1295. }
  1296. }
  1297. /**
  1298. * atl1c_get_stats - Get System Network Statistics
  1299. * @netdev: network interface device structure
  1300. *
  1301. * Returns the address of the device statistics structure.
  1302. * The statistics are actually updated from the timer callback.
  1303. */
  1304. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1305. {
  1306. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1307. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1308. struct net_device_stats *net_stats = &netdev->stats;
  1309. atl1c_update_hw_stats(adapter);
  1310. net_stats->rx_packets = hw_stats->rx_ok;
  1311. net_stats->tx_packets = hw_stats->tx_ok;
  1312. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1313. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1314. net_stats->multicast = hw_stats->rx_mcast;
  1315. net_stats->collisions = hw_stats->tx_1_col +
  1316. hw_stats->tx_2_col * 2 +
  1317. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1318. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1319. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1320. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1321. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1322. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1323. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1324. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1325. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1326. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1327. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1328. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1329. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1330. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1331. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1332. return net_stats;
  1333. }
  1334. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1335. {
  1336. u16 phy_data;
  1337. spin_lock(&adapter->mdio_lock);
  1338. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1339. spin_unlock(&adapter->mdio_lock);
  1340. }
  1341. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1342. enum atl1c_trans_queue type)
  1343. {
  1344. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1345. struct atl1c_buffer *buffer_info;
  1346. struct pci_dev *pdev = adapter->pdev;
  1347. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1348. u16 hw_next_to_clean;
  1349. u16 reg;
  1350. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1351. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1352. while (next_to_clean != hw_next_to_clean) {
  1353. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1354. atl1c_clean_buffer(pdev, buffer_info, 1);
  1355. if (++next_to_clean == tpd_ring->count)
  1356. next_to_clean = 0;
  1357. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1358. }
  1359. if (netif_queue_stopped(adapter->netdev) &&
  1360. netif_carrier_ok(adapter->netdev)) {
  1361. netif_wake_queue(adapter->netdev);
  1362. }
  1363. return true;
  1364. }
  1365. /**
  1366. * atl1c_intr - Interrupt Handler
  1367. * @irq: interrupt number
  1368. * @data: pointer to a network interface device structure
  1369. */
  1370. static irqreturn_t atl1c_intr(int irq, void *data)
  1371. {
  1372. struct net_device *netdev = data;
  1373. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1374. struct pci_dev *pdev = adapter->pdev;
  1375. struct atl1c_hw *hw = &adapter->hw;
  1376. int max_ints = AT_MAX_INT_WORK;
  1377. int handled = IRQ_NONE;
  1378. u32 status;
  1379. u32 reg_data;
  1380. do {
  1381. AT_READ_REG(hw, REG_ISR, &reg_data);
  1382. status = reg_data & hw->intr_mask;
  1383. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1384. if (max_ints != AT_MAX_INT_WORK)
  1385. handled = IRQ_HANDLED;
  1386. break;
  1387. }
  1388. /* link event */
  1389. if (status & ISR_GPHY)
  1390. atl1c_clear_phy_int(adapter);
  1391. /* Ack ISR */
  1392. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1393. if (status & ISR_RX_PKT) {
  1394. if (likely(napi_schedule_prep(&adapter->napi))) {
  1395. hw->intr_mask &= ~ISR_RX_PKT;
  1396. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1397. __napi_schedule(&adapter->napi);
  1398. }
  1399. }
  1400. if (status & ISR_TX_PKT)
  1401. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1402. handled = IRQ_HANDLED;
  1403. /* check if PCIE PHY Link down */
  1404. if (status & ISR_ERROR) {
  1405. if (netif_msg_hw(adapter))
  1406. dev_err(&pdev->dev,
  1407. "atl1c hardware error (status = 0x%x)\n",
  1408. status & ISR_ERROR);
  1409. /* reset MAC */
  1410. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1411. schedule_work(&adapter->common_task);
  1412. return IRQ_HANDLED;
  1413. }
  1414. if (status & ISR_OVER)
  1415. if (netif_msg_intr(adapter))
  1416. dev_warn(&pdev->dev,
  1417. "TX/RX overflow (status = 0x%x)\n",
  1418. status & ISR_OVER);
  1419. /* link event */
  1420. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1421. netdev->stats.tx_carrier_errors++;
  1422. atl1c_link_chg_event(adapter);
  1423. break;
  1424. }
  1425. } while (--max_ints > 0);
  1426. /* re-enable Interrupt*/
  1427. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1428. return handled;
  1429. }
  1430. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1431. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1432. {
  1433. /*
  1434. * The pid field in RRS in not correct sometimes, so we
  1435. * cannot figure out if the packet is fragmented or not,
  1436. * so we tell the KERNEL CHECKSUM_NONE
  1437. */
  1438. skb_checksum_none_assert(skb);
  1439. }
  1440. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1441. {
  1442. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1443. struct pci_dev *pdev = adapter->pdev;
  1444. struct atl1c_buffer *buffer_info, *next_info;
  1445. struct sk_buff *skb;
  1446. void *vir_addr = NULL;
  1447. u16 num_alloc = 0;
  1448. u16 rfd_next_to_use, next_next;
  1449. struct atl1c_rx_free_desc *rfd_desc;
  1450. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1451. if (++next_next == rfd_ring->count)
  1452. next_next = 0;
  1453. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1454. next_info = &rfd_ring->buffer_info[next_next];
  1455. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1456. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1457. skb = netdev_alloc_skb(adapter->netdev, adapter->rx_buffer_len);
  1458. if (unlikely(!skb)) {
  1459. if (netif_msg_rx_err(adapter))
  1460. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1461. break;
  1462. }
  1463. /*
  1464. * Make buffer alignment 2 beyond a 16 byte boundary
  1465. * this will result in a 16 byte aligned IP header after
  1466. * the 14 byte MAC header is removed
  1467. */
  1468. vir_addr = skb->data;
  1469. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1470. buffer_info->skb = skb;
  1471. buffer_info->length = adapter->rx_buffer_len;
  1472. buffer_info->dma = pci_map_single(pdev, vir_addr,
  1473. buffer_info->length,
  1474. PCI_DMA_FROMDEVICE);
  1475. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1476. ATL1C_PCIMAP_FROMDEVICE);
  1477. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1478. rfd_next_to_use = next_next;
  1479. if (++next_next == rfd_ring->count)
  1480. next_next = 0;
  1481. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1482. next_info = &rfd_ring->buffer_info[next_next];
  1483. num_alloc++;
  1484. }
  1485. if (num_alloc) {
  1486. /* TODO: update mailbox here */
  1487. wmb();
  1488. rfd_ring->next_to_use = rfd_next_to_use;
  1489. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1490. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1491. }
  1492. return num_alloc;
  1493. }
  1494. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1495. struct atl1c_recv_ret_status *rrs, u16 num)
  1496. {
  1497. u16 i;
  1498. /* the relationship between rrd and rfd is one map one */
  1499. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1500. rrd_ring->next_to_clean)) {
  1501. rrs->word3 &= ~RRS_RXD_UPDATED;
  1502. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1503. rrd_ring->next_to_clean = 0;
  1504. }
  1505. }
  1506. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1507. struct atl1c_recv_ret_status *rrs, u16 num)
  1508. {
  1509. u16 i;
  1510. u16 rfd_index;
  1511. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1512. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1513. RRS_RX_RFD_INDEX_MASK;
  1514. for (i = 0; i < num; i++) {
  1515. buffer_info[rfd_index].skb = NULL;
  1516. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1517. ATL1C_BUFFER_FREE);
  1518. if (++rfd_index == rfd_ring->count)
  1519. rfd_index = 0;
  1520. }
  1521. rfd_ring->next_to_clean = rfd_index;
  1522. }
  1523. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1524. int *work_done, int work_to_do)
  1525. {
  1526. u16 rfd_num, rfd_index;
  1527. u16 count = 0;
  1528. u16 length;
  1529. struct pci_dev *pdev = adapter->pdev;
  1530. struct net_device *netdev = adapter->netdev;
  1531. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1532. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1533. struct sk_buff *skb;
  1534. struct atl1c_recv_ret_status *rrs;
  1535. struct atl1c_buffer *buffer_info;
  1536. while (1) {
  1537. if (*work_done >= work_to_do)
  1538. break;
  1539. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1540. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1541. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1542. RRS_RX_RFD_CNT_MASK;
  1543. if (unlikely(rfd_num != 1))
  1544. /* TODO support mul rfd*/
  1545. if (netif_msg_rx_err(adapter))
  1546. dev_warn(&pdev->dev,
  1547. "Multi rfd not support yet!\n");
  1548. goto rrs_checked;
  1549. } else {
  1550. break;
  1551. }
  1552. rrs_checked:
  1553. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1554. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1555. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1556. if (netif_msg_rx_err(adapter))
  1557. dev_warn(&pdev->dev,
  1558. "wrong packet! rrs word3 is %x\n",
  1559. rrs->word3);
  1560. continue;
  1561. }
  1562. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1563. RRS_PKT_SIZE_MASK);
  1564. /* Good Receive */
  1565. if (likely(rfd_num == 1)) {
  1566. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1567. RRS_RX_RFD_INDEX_MASK;
  1568. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1569. pci_unmap_single(pdev, buffer_info->dma,
  1570. buffer_info->length, PCI_DMA_FROMDEVICE);
  1571. skb = buffer_info->skb;
  1572. } else {
  1573. /* TODO */
  1574. if (netif_msg_rx_err(adapter))
  1575. dev_warn(&pdev->dev,
  1576. "Multi rfd not support yet!\n");
  1577. break;
  1578. }
  1579. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1580. skb_put(skb, length - ETH_FCS_LEN);
  1581. skb->protocol = eth_type_trans(skb, netdev);
  1582. atl1c_rx_checksum(adapter, skb, rrs);
  1583. if (rrs->word3 & RRS_VLAN_INS) {
  1584. u16 vlan;
  1585. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1586. vlan = le16_to_cpu(vlan);
  1587. __vlan_hwaccel_put_tag(skb, vlan);
  1588. }
  1589. netif_receive_skb(skb);
  1590. (*work_done)++;
  1591. count++;
  1592. }
  1593. if (count)
  1594. atl1c_alloc_rx_buffer(adapter);
  1595. }
  1596. /**
  1597. * atl1c_clean - NAPI Rx polling callback
  1598. */
  1599. static int atl1c_clean(struct napi_struct *napi, int budget)
  1600. {
  1601. struct atl1c_adapter *adapter =
  1602. container_of(napi, struct atl1c_adapter, napi);
  1603. int work_done = 0;
  1604. /* Keep link state information with original netdev */
  1605. if (!netif_carrier_ok(adapter->netdev))
  1606. goto quit_polling;
  1607. /* just enable one RXQ */
  1608. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1609. if (work_done < budget) {
  1610. quit_polling:
  1611. napi_complete(napi);
  1612. adapter->hw.intr_mask |= ISR_RX_PKT;
  1613. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1614. }
  1615. return work_done;
  1616. }
  1617. #ifdef CONFIG_NET_POLL_CONTROLLER
  1618. /*
  1619. * Polling 'interrupt' - used by things like netconsole to send skbs
  1620. * without having to re-enable interrupts. It's not called while
  1621. * the interrupt routine is executing.
  1622. */
  1623. static void atl1c_netpoll(struct net_device *netdev)
  1624. {
  1625. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1626. disable_irq(adapter->pdev->irq);
  1627. atl1c_intr(adapter->pdev->irq, netdev);
  1628. enable_irq(adapter->pdev->irq);
  1629. }
  1630. #endif
  1631. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1632. {
  1633. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1634. u16 next_to_use = 0;
  1635. u16 next_to_clean = 0;
  1636. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1637. next_to_use = tpd_ring->next_to_use;
  1638. return (u16)(next_to_clean > next_to_use) ?
  1639. (next_to_clean - next_to_use - 1) :
  1640. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1641. }
  1642. /*
  1643. * get next usable tpd
  1644. * Note: should call atl1c_tdp_avail to make sure
  1645. * there is enough tpd to use
  1646. */
  1647. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1648. enum atl1c_trans_queue type)
  1649. {
  1650. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1651. struct atl1c_tpd_desc *tpd_desc;
  1652. u16 next_to_use = 0;
  1653. next_to_use = tpd_ring->next_to_use;
  1654. if (++tpd_ring->next_to_use == tpd_ring->count)
  1655. tpd_ring->next_to_use = 0;
  1656. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1657. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1658. return tpd_desc;
  1659. }
  1660. static struct atl1c_buffer *
  1661. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1662. {
  1663. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1664. return &tpd_ring->buffer_info[tpd -
  1665. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1666. }
  1667. /* Calculate the transmit packet descript needed*/
  1668. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1669. {
  1670. u16 tpd_req;
  1671. u16 proto_hdr_len = 0;
  1672. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1673. if (skb_is_gso(skb)) {
  1674. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1675. if (proto_hdr_len < skb_headlen(skb))
  1676. tpd_req++;
  1677. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1678. tpd_req++;
  1679. }
  1680. return tpd_req;
  1681. }
  1682. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1683. struct sk_buff *skb,
  1684. struct atl1c_tpd_desc **tpd,
  1685. enum atl1c_trans_queue type)
  1686. {
  1687. struct pci_dev *pdev = adapter->pdev;
  1688. u8 hdr_len;
  1689. u32 real_len;
  1690. unsigned short offload_type;
  1691. int err;
  1692. if (skb_is_gso(skb)) {
  1693. if (skb_header_cloned(skb)) {
  1694. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1695. if (unlikely(err))
  1696. return -1;
  1697. }
  1698. offload_type = skb_shinfo(skb)->gso_type;
  1699. if (offload_type & SKB_GSO_TCPV4) {
  1700. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1701. + ntohs(ip_hdr(skb)->tot_len));
  1702. if (real_len < skb->len)
  1703. pskb_trim(skb, real_len);
  1704. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1705. if (unlikely(skb->len == hdr_len)) {
  1706. /* only xsum need */
  1707. if (netif_msg_tx_queued(adapter))
  1708. dev_warn(&pdev->dev,
  1709. "IPV4 tso with zero data??\n");
  1710. goto check_sum;
  1711. } else {
  1712. ip_hdr(skb)->check = 0;
  1713. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1714. ip_hdr(skb)->saddr,
  1715. ip_hdr(skb)->daddr,
  1716. 0, IPPROTO_TCP, 0);
  1717. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1718. }
  1719. }
  1720. if (offload_type & SKB_GSO_TCPV6) {
  1721. struct atl1c_tpd_ext_desc *etpd =
  1722. *(struct atl1c_tpd_ext_desc **)(tpd);
  1723. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1724. *tpd = atl1c_get_tpd(adapter, type);
  1725. ipv6_hdr(skb)->payload_len = 0;
  1726. /* check payload == 0 byte ? */
  1727. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1728. if (unlikely(skb->len == hdr_len)) {
  1729. /* only xsum need */
  1730. if (netif_msg_tx_queued(adapter))
  1731. dev_warn(&pdev->dev,
  1732. "IPV6 tso with zero data??\n");
  1733. goto check_sum;
  1734. } else
  1735. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1736. &ipv6_hdr(skb)->saddr,
  1737. &ipv6_hdr(skb)->daddr,
  1738. 0, IPPROTO_TCP, 0);
  1739. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1740. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1741. etpd->pkt_len = cpu_to_le32(skb->len);
  1742. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1743. }
  1744. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1745. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1746. TPD_TCPHDR_OFFSET_SHIFT;
  1747. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1748. TPD_MSS_SHIFT;
  1749. return 0;
  1750. }
  1751. check_sum:
  1752. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1753. u8 css, cso;
  1754. cso = skb_checksum_start_offset(skb);
  1755. if (unlikely(cso & 0x1)) {
  1756. if (netif_msg_tx_err(adapter))
  1757. dev_err(&adapter->pdev->dev,
  1758. "payload offset should not an event number\n");
  1759. return -1;
  1760. } else {
  1761. css = cso + skb->csum_offset;
  1762. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1763. TPD_PLOADOFFSET_SHIFT;
  1764. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1765. TPD_CCSUM_OFFSET_SHIFT;
  1766. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1767. }
  1768. }
  1769. return 0;
  1770. }
  1771. static void atl1c_tx_map(struct atl1c_adapter *adapter,
  1772. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1773. enum atl1c_trans_queue type)
  1774. {
  1775. struct atl1c_tpd_desc *use_tpd = NULL;
  1776. struct atl1c_buffer *buffer_info = NULL;
  1777. u16 buf_len = skb_headlen(skb);
  1778. u16 map_len = 0;
  1779. u16 mapped_len = 0;
  1780. u16 hdr_len = 0;
  1781. u16 nr_frags;
  1782. u16 f;
  1783. int tso;
  1784. nr_frags = skb_shinfo(skb)->nr_frags;
  1785. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1786. if (tso) {
  1787. /* TSO */
  1788. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1789. use_tpd = tpd;
  1790. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1791. buffer_info->length = map_len;
  1792. buffer_info->dma = pci_map_single(adapter->pdev,
  1793. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1794. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1795. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1796. ATL1C_PCIMAP_TODEVICE);
  1797. mapped_len += map_len;
  1798. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1799. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1800. }
  1801. if (mapped_len < buf_len) {
  1802. /* mapped_len == 0, means we should use the first tpd,
  1803. which is given by caller */
  1804. if (mapped_len == 0)
  1805. use_tpd = tpd;
  1806. else {
  1807. use_tpd = atl1c_get_tpd(adapter, type);
  1808. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1809. }
  1810. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1811. buffer_info->length = buf_len - mapped_len;
  1812. buffer_info->dma =
  1813. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1814. buffer_info->length, PCI_DMA_TODEVICE);
  1815. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1816. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1817. ATL1C_PCIMAP_TODEVICE);
  1818. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1819. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1820. }
  1821. for (f = 0; f < nr_frags; f++) {
  1822. struct skb_frag_struct *frag;
  1823. frag = &skb_shinfo(skb)->frags[f];
  1824. use_tpd = atl1c_get_tpd(adapter, type);
  1825. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1826. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1827. buffer_info->length = skb_frag_size(frag);
  1828. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1829. frag, 0,
  1830. buffer_info->length,
  1831. DMA_TO_DEVICE);
  1832. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1833. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1834. ATL1C_PCIMAP_TODEVICE);
  1835. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1836. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1837. }
  1838. /* The last tpd */
  1839. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1840. /* The last buffer info contain the skb address,
  1841. so it will be free after unmap */
  1842. buffer_info->skb = skb;
  1843. }
  1844. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1845. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1846. {
  1847. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1848. u16 reg;
  1849. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1850. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1851. }
  1852. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1853. struct net_device *netdev)
  1854. {
  1855. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1856. unsigned long flags;
  1857. u16 tpd_req = 1;
  1858. struct atl1c_tpd_desc *tpd;
  1859. enum atl1c_trans_queue type = atl1c_trans_normal;
  1860. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1861. dev_kfree_skb_any(skb);
  1862. return NETDEV_TX_OK;
  1863. }
  1864. tpd_req = atl1c_cal_tpd_req(skb);
  1865. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1866. if (netif_msg_pktdata(adapter))
  1867. dev_info(&adapter->pdev->dev, "tx locked\n");
  1868. return NETDEV_TX_LOCKED;
  1869. }
  1870. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1871. /* no enough descriptor, just stop queue */
  1872. netif_stop_queue(netdev);
  1873. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1874. return NETDEV_TX_BUSY;
  1875. }
  1876. tpd = atl1c_get_tpd(adapter, type);
  1877. /* do TSO and check sum */
  1878. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1879. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1880. dev_kfree_skb_any(skb);
  1881. return NETDEV_TX_OK;
  1882. }
  1883. if (unlikely(vlan_tx_tag_present(skb))) {
  1884. u16 vlan = vlan_tx_tag_get(skb);
  1885. __le16 tag;
  1886. vlan = cpu_to_le16(vlan);
  1887. AT_VLAN_TO_TAG(vlan, tag);
  1888. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1889. tpd->vlan_tag = tag;
  1890. }
  1891. if (skb_network_offset(skb) != ETH_HLEN)
  1892. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1893. atl1c_tx_map(adapter, skb, tpd, type);
  1894. atl1c_tx_queue(adapter, skb, tpd, type);
  1895. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1896. return NETDEV_TX_OK;
  1897. }
  1898. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1899. {
  1900. struct net_device *netdev = adapter->netdev;
  1901. free_irq(adapter->pdev->irq, netdev);
  1902. if (adapter->have_msi)
  1903. pci_disable_msi(adapter->pdev);
  1904. }
  1905. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1906. {
  1907. struct pci_dev *pdev = adapter->pdev;
  1908. struct net_device *netdev = adapter->netdev;
  1909. int flags = 0;
  1910. int err = 0;
  1911. adapter->have_msi = true;
  1912. err = pci_enable_msi(adapter->pdev);
  1913. if (err) {
  1914. if (netif_msg_ifup(adapter))
  1915. dev_err(&pdev->dev,
  1916. "Unable to allocate MSI interrupt Error: %d\n",
  1917. err);
  1918. adapter->have_msi = false;
  1919. }
  1920. if (!adapter->have_msi)
  1921. flags |= IRQF_SHARED;
  1922. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  1923. netdev->name, netdev);
  1924. if (err) {
  1925. if (netif_msg_ifup(adapter))
  1926. dev_err(&pdev->dev,
  1927. "Unable to allocate interrupt Error: %d\n",
  1928. err);
  1929. if (adapter->have_msi)
  1930. pci_disable_msi(adapter->pdev);
  1931. return err;
  1932. }
  1933. if (netif_msg_ifup(adapter))
  1934. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1935. return err;
  1936. }
  1937. static void atl1c_reset_dma_ring(struct atl1c_adapter *adapter)
  1938. {
  1939. /* release tx-pending skbs and reset tx/rx ring index */
  1940. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1941. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1942. atl1c_clean_rx_ring(adapter);
  1943. }
  1944. static int atl1c_up(struct atl1c_adapter *adapter)
  1945. {
  1946. struct net_device *netdev = adapter->netdev;
  1947. int err;
  1948. netif_carrier_off(netdev);
  1949. err = atl1c_configure(adapter);
  1950. if (unlikely(err))
  1951. goto err_up;
  1952. err = atl1c_request_irq(adapter);
  1953. if (unlikely(err))
  1954. goto err_up;
  1955. atl1c_check_link_status(adapter);
  1956. clear_bit(__AT_DOWN, &adapter->flags);
  1957. napi_enable(&adapter->napi);
  1958. atl1c_irq_enable(adapter);
  1959. netif_start_queue(netdev);
  1960. return err;
  1961. err_up:
  1962. atl1c_clean_rx_ring(adapter);
  1963. return err;
  1964. }
  1965. static void atl1c_down(struct atl1c_adapter *adapter)
  1966. {
  1967. struct net_device *netdev = adapter->netdev;
  1968. atl1c_del_timer(adapter);
  1969. adapter->work_event = 0; /* clear all event */
  1970. /* signal that we're down so the interrupt handler does not
  1971. * reschedule our watchdog timer */
  1972. set_bit(__AT_DOWN, &adapter->flags);
  1973. netif_carrier_off(netdev);
  1974. napi_disable(&adapter->napi);
  1975. atl1c_irq_disable(adapter);
  1976. atl1c_free_irq(adapter);
  1977. /* disable ASPM if device inactive */
  1978. atl1c_disable_l0s_l1(&adapter->hw);
  1979. /* reset MAC to disable all RX/TX */
  1980. atl1c_reset_mac(&adapter->hw);
  1981. msleep(1);
  1982. adapter->link_speed = SPEED_0;
  1983. adapter->link_duplex = -1;
  1984. atl1c_reset_dma_ring(adapter);
  1985. }
  1986. /**
  1987. * atl1c_open - Called when a network interface is made active
  1988. * @netdev: network interface device structure
  1989. *
  1990. * Returns 0 on success, negative value on failure
  1991. *
  1992. * The open entry point is called when a network interface is made
  1993. * active by the system (IFF_UP). At this point all resources needed
  1994. * for transmit and receive operations are allocated, the interrupt
  1995. * handler is registered with the OS, the watchdog timer is started,
  1996. * and the stack is notified that the interface is ready.
  1997. */
  1998. static int atl1c_open(struct net_device *netdev)
  1999. {
  2000. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2001. int err;
  2002. /* disallow open during test */
  2003. if (test_bit(__AT_TESTING, &adapter->flags))
  2004. return -EBUSY;
  2005. /* allocate rx/tx dma buffer & descriptors */
  2006. err = atl1c_setup_ring_resources(adapter);
  2007. if (unlikely(err))
  2008. return err;
  2009. err = atl1c_up(adapter);
  2010. if (unlikely(err))
  2011. goto err_up;
  2012. return 0;
  2013. err_up:
  2014. atl1c_free_irq(adapter);
  2015. atl1c_free_ring_resources(adapter);
  2016. atl1c_reset_mac(&adapter->hw);
  2017. return err;
  2018. }
  2019. /**
  2020. * atl1c_close - Disables a network interface
  2021. * @netdev: network interface device structure
  2022. *
  2023. * Returns 0, this is not allowed to fail
  2024. *
  2025. * The close entry point is called when an interface is de-activated
  2026. * by the OS. The hardware is still under the drivers control, but
  2027. * needs to be disabled. A global MAC reset is issued to stop the
  2028. * hardware, and all transmit and receive resources are freed.
  2029. */
  2030. static int atl1c_close(struct net_device *netdev)
  2031. {
  2032. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2033. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2034. set_bit(__AT_DOWN, &adapter->flags);
  2035. cancel_work_sync(&adapter->common_task);
  2036. atl1c_down(adapter);
  2037. atl1c_free_ring_resources(adapter);
  2038. return 0;
  2039. }
  2040. static int atl1c_suspend(struct device *dev)
  2041. {
  2042. struct pci_dev *pdev = to_pci_dev(dev);
  2043. struct net_device *netdev = pci_get_drvdata(pdev);
  2044. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2045. struct atl1c_hw *hw = &adapter->hw;
  2046. u32 wufc = adapter->wol;
  2047. atl1c_disable_l0s_l1(hw);
  2048. if (netif_running(netdev)) {
  2049. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2050. atl1c_down(adapter);
  2051. }
  2052. netif_device_detach(netdev);
  2053. if (wufc)
  2054. if (atl1c_phy_to_ps_link(hw) != 0)
  2055. dev_dbg(&pdev->dev, "phy power saving failed");
  2056. atl1c_power_saving(hw, wufc);
  2057. return 0;
  2058. }
  2059. #ifdef CONFIG_PM_SLEEP
  2060. static int atl1c_resume(struct device *dev)
  2061. {
  2062. struct pci_dev *pdev = to_pci_dev(dev);
  2063. struct net_device *netdev = pci_get_drvdata(pdev);
  2064. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2065. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2066. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2067. atl1c_phy_reset(&adapter->hw);
  2068. atl1c_reset_mac(&adapter->hw);
  2069. atl1c_phy_init(&adapter->hw);
  2070. #if 0
  2071. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2072. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2073. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2074. #endif
  2075. netif_device_attach(netdev);
  2076. if (netif_running(netdev))
  2077. atl1c_up(adapter);
  2078. return 0;
  2079. }
  2080. #endif
  2081. static void atl1c_shutdown(struct pci_dev *pdev)
  2082. {
  2083. struct net_device *netdev = pci_get_drvdata(pdev);
  2084. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2085. atl1c_suspend(&pdev->dev);
  2086. pci_wake_from_d3(pdev, adapter->wol);
  2087. pci_set_power_state(pdev, PCI_D3hot);
  2088. }
  2089. static const struct net_device_ops atl1c_netdev_ops = {
  2090. .ndo_open = atl1c_open,
  2091. .ndo_stop = atl1c_close,
  2092. .ndo_validate_addr = eth_validate_addr,
  2093. .ndo_start_xmit = atl1c_xmit_frame,
  2094. .ndo_set_mac_address = atl1c_set_mac_addr,
  2095. .ndo_set_rx_mode = atl1c_set_multi,
  2096. .ndo_change_mtu = atl1c_change_mtu,
  2097. .ndo_fix_features = atl1c_fix_features,
  2098. .ndo_set_features = atl1c_set_features,
  2099. .ndo_do_ioctl = atl1c_ioctl,
  2100. .ndo_tx_timeout = atl1c_tx_timeout,
  2101. .ndo_get_stats = atl1c_get_stats,
  2102. #ifdef CONFIG_NET_POLL_CONTROLLER
  2103. .ndo_poll_controller = atl1c_netpoll,
  2104. #endif
  2105. };
  2106. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2107. {
  2108. SET_NETDEV_DEV(netdev, &pdev->dev);
  2109. pci_set_drvdata(pdev, netdev);
  2110. netdev->netdev_ops = &atl1c_netdev_ops;
  2111. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2112. atl1c_set_ethtool_ops(netdev);
  2113. /* TODO: add when ready */
  2114. netdev->hw_features = NETIF_F_SG |
  2115. NETIF_F_HW_CSUM |
  2116. NETIF_F_HW_VLAN_RX |
  2117. NETIF_F_TSO |
  2118. NETIF_F_TSO6;
  2119. netdev->features = netdev->hw_features |
  2120. NETIF_F_HW_VLAN_TX;
  2121. return 0;
  2122. }
  2123. /**
  2124. * atl1c_probe - Device Initialization Routine
  2125. * @pdev: PCI device information struct
  2126. * @ent: entry in atl1c_pci_tbl
  2127. *
  2128. * Returns 0 on success, negative on failure
  2129. *
  2130. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2131. * The OS initialization, configuring of the adapter private structure,
  2132. * and a hardware reset occur.
  2133. */
  2134. static int atl1c_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2135. {
  2136. struct net_device *netdev;
  2137. struct atl1c_adapter *adapter;
  2138. static int cards_found;
  2139. int err = 0;
  2140. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2141. err = pci_enable_device_mem(pdev);
  2142. if (err) {
  2143. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2144. return err;
  2145. }
  2146. /*
  2147. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2148. * shared register for the high 32 bits, so only a single, aligned,
  2149. * 4 GB physical address range can be used at a time.
  2150. *
  2151. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2152. * worth. It is far easier to limit to 32-bit DMA than update
  2153. * various kernel subsystems to support the mechanics required by a
  2154. * fixed-high-32-bit system.
  2155. */
  2156. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2157. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2158. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2159. goto err_dma;
  2160. }
  2161. err = pci_request_regions(pdev, atl1c_driver_name);
  2162. if (err) {
  2163. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2164. goto err_pci_reg;
  2165. }
  2166. pci_set_master(pdev);
  2167. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2168. if (netdev == NULL) {
  2169. err = -ENOMEM;
  2170. goto err_alloc_etherdev;
  2171. }
  2172. err = atl1c_init_netdev(netdev, pdev);
  2173. if (err) {
  2174. dev_err(&pdev->dev, "init netdevice failed\n");
  2175. goto err_init_netdev;
  2176. }
  2177. adapter = netdev_priv(netdev);
  2178. adapter->bd_number = cards_found;
  2179. adapter->netdev = netdev;
  2180. adapter->pdev = pdev;
  2181. adapter->hw.adapter = adapter;
  2182. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2183. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2184. if (!adapter->hw.hw_addr) {
  2185. err = -EIO;
  2186. dev_err(&pdev->dev, "cannot map device registers\n");
  2187. goto err_ioremap;
  2188. }
  2189. /* init mii data */
  2190. adapter->mii.dev = netdev;
  2191. adapter->mii.mdio_read = atl1c_mdio_read;
  2192. adapter->mii.mdio_write = atl1c_mdio_write;
  2193. adapter->mii.phy_id_mask = 0x1f;
  2194. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2195. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2196. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2197. (unsigned long)adapter);
  2198. /* setup the private structure */
  2199. err = atl1c_sw_init(adapter);
  2200. if (err) {
  2201. dev_err(&pdev->dev, "net device private data init failed\n");
  2202. goto err_sw_init;
  2203. }
  2204. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2205. /* Init GPHY as early as possible due to power saving issue */
  2206. atl1c_phy_reset(&adapter->hw);
  2207. err = atl1c_reset_mac(&adapter->hw);
  2208. if (err) {
  2209. err = -EIO;
  2210. goto err_reset;
  2211. }
  2212. /* reset the controller to
  2213. * put the device in a known good starting state */
  2214. err = atl1c_phy_init(&adapter->hw);
  2215. if (err) {
  2216. err = -EIO;
  2217. goto err_reset;
  2218. }
  2219. if (atl1c_read_mac_addr(&adapter->hw)) {
  2220. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2221. netdev->addr_assign_type |= NET_ADDR_RANDOM;
  2222. }
  2223. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2224. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  2225. if (netif_msg_probe(adapter))
  2226. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2227. adapter->hw.mac_addr);
  2228. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.mac_addr);
  2229. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2230. adapter->work_event = 0;
  2231. err = register_netdev(netdev);
  2232. if (err) {
  2233. dev_err(&pdev->dev, "register netdevice failed\n");
  2234. goto err_register;
  2235. }
  2236. if (netif_msg_probe(adapter))
  2237. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2238. cards_found++;
  2239. return 0;
  2240. err_reset:
  2241. err_register:
  2242. err_sw_init:
  2243. iounmap(adapter->hw.hw_addr);
  2244. err_init_netdev:
  2245. err_ioremap:
  2246. free_netdev(netdev);
  2247. err_alloc_etherdev:
  2248. pci_release_regions(pdev);
  2249. err_pci_reg:
  2250. err_dma:
  2251. pci_disable_device(pdev);
  2252. return err;
  2253. }
  2254. /**
  2255. * atl1c_remove - Device Removal Routine
  2256. * @pdev: PCI device information struct
  2257. *
  2258. * atl1c_remove is called by the PCI subsystem to alert the driver
  2259. * that it should release a PCI device. The could be caused by a
  2260. * Hot-Plug event, or because the driver is going to be removed from
  2261. * memory.
  2262. */
  2263. static void atl1c_remove(struct pci_dev *pdev)
  2264. {
  2265. struct net_device *netdev = pci_get_drvdata(pdev);
  2266. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2267. unregister_netdev(netdev);
  2268. /* restore permanent address */
  2269. atl1c_hw_set_mac_addr(&adapter->hw, adapter->hw.perm_mac_addr);
  2270. atl1c_phy_disable(&adapter->hw);
  2271. iounmap(adapter->hw.hw_addr);
  2272. pci_release_regions(pdev);
  2273. pci_disable_device(pdev);
  2274. free_netdev(netdev);
  2275. }
  2276. /**
  2277. * atl1c_io_error_detected - called when PCI error is detected
  2278. * @pdev: Pointer to PCI device
  2279. * @state: The current pci connection state
  2280. *
  2281. * This function is called after a PCI bus error affecting
  2282. * this device has been detected.
  2283. */
  2284. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2285. pci_channel_state_t state)
  2286. {
  2287. struct net_device *netdev = pci_get_drvdata(pdev);
  2288. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2289. netif_device_detach(netdev);
  2290. if (state == pci_channel_io_perm_failure)
  2291. return PCI_ERS_RESULT_DISCONNECT;
  2292. if (netif_running(netdev))
  2293. atl1c_down(adapter);
  2294. pci_disable_device(pdev);
  2295. /* Request a slot slot reset. */
  2296. return PCI_ERS_RESULT_NEED_RESET;
  2297. }
  2298. /**
  2299. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2300. * @pdev: Pointer to PCI device
  2301. *
  2302. * Restart the card from scratch, as if from a cold-boot. Implementation
  2303. * resembles the first-half of the e1000_resume routine.
  2304. */
  2305. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2306. {
  2307. struct net_device *netdev = pci_get_drvdata(pdev);
  2308. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2309. if (pci_enable_device(pdev)) {
  2310. if (netif_msg_hw(adapter))
  2311. dev_err(&pdev->dev,
  2312. "Cannot re-enable PCI device after reset\n");
  2313. return PCI_ERS_RESULT_DISCONNECT;
  2314. }
  2315. pci_set_master(pdev);
  2316. pci_enable_wake(pdev, PCI_D3hot, 0);
  2317. pci_enable_wake(pdev, PCI_D3cold, 0);
  2318. atl1c_reset_mac(&adapter->hw);
  2319. return PCI_ERS_RESULT_RECOVERED;
  2320. }
  2321. /**
  2322. * atl1c_io_resume - called when traffic can start flowing again.
  2323. * @pdev: Pointer to PCI device
  2324. *
  2325. * This callback is called when the error recovery driver tells us that
  2326. * its OK to resume normal operation. Implementation resembles the
  2327. * second-half of the atl1c_resume routine.
  2328. */
  2329. static void atl1c_io_resume(struct pci_dev *pdev)
  2330. {
  2331. struct net_device *netdev = pci_get_drvdata(pdev);
  2332. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2333. if (netif_running(netdev)) {
  2334. if (atl1c_up(adapter)) {
  2335. if (netif_msg_hw(adapter))
  2336. dev_err(&pdev->dev,
  2337. "Cannot bring device back up after reset\n");
  2338. return;
  2339. }
  2340. }
  2341. netif_device_attach(netdev);
  2342. }
  2343. static const struct pci_error_handlers atl1c_err_handler = {
  2344. .error_detected = atl1c_io_error_detected,
  2345. .slot_reset = atl1c_io_slot_reset,
  2346. .resume = atl1c_io_resume,
  2347. };
  2348. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2349. static struct pci_driver atl1c_driver = {
  2350. .name = atl1c_driver_name,
  2351. .id_table = atl1c_pci_tbl,
  2352. .probe = atl1c_probe,
  2353. .remove = atl1c_remove,
  2354. .shutdown = atl1c_shutdown,
  2355. .err_handler = &atl1c_err_handler,
  2356. .driver.pm = &atl1c_pm_ops,
  2357. };
  2358. /**
  2359. * atl1c_init_module - Driver Registration Routine
  2360. *
  2361. * atl1c_init_module is the first routine called when the driver is
  2362. * loaded. All it does is register with the PCI subsystem.
  2363. */
  2364. static int __init atl1c_init_module(void)
  2365. {
  2366. return pci_register_driver(&atl1c_driver);
  2367. }
  2368. /**
  2369. * atl1c_exit_module - Driver Exit Cleanup Routine
  2370. *
  2371. * atl1c_exit_module is called just before the driver is removed
  2372. * from memory.
  2373. */
  2374. static void __exit atl1c_exit_module(void)
  2375. {
  2376. pci_unregister_driver(&atl1c_driver);
  2377. }
  2378. module_init(atl1c_init_module);
  2379. module_exit(atl1c_exit_module);