mxc_nand.c 41 KB

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  1. /*
  2. * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  3. * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17. * MA 02110-1301, USA.
  18. */
  19. #include <linux/delay.h>
  20. #include <linux/slab.h>
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/nand.h>
  25. #include <linux/mtd/partitions.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/device.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/clk.h>
  30. #include <linux/err.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include <linux/completion.h>
  34. #include <linux/of_device.h>
  35. #include <linux/of_mtd.h>
  36. #include <asm/mach/flash.h>
  37. #include <linux/platform_data/mtd-mxc_nand.h>
  38. #define DRIVER_NAME "mxc_nand"
  39. /* Addresses for NFC registers */
  40. #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
  41. #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
  42. #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
  43. #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
  44. #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
  45. #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
  46. #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
  47. #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
  48. #define NFC_V1_V2_WRPROT (host->regs + 0x12)
  49. #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
  50. #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
  51. #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
  52. #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
  53. #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
  54. #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
  55. #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
  56. #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
  57. #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
  58. #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
  59. #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
  60. #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
  61. #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
  62. #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
  63. #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
  64. #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
  65. #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
  66. #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
  67. #define NFC_V1_V2_CONFIG1_RST (1 << 6)
  68. #define NFC_V1_V2_CONFIG1_CE (1 << 7)
  69. #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
  70. #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
  71. #define NFC_V2_CONFIG1_FP_INT (1 << 11)
  72. #define NFC_V1_V2_CONFIG2_INT (1 << 15)
  73. /*
  74. * Operation modes for the NFC. Valid for v1, v2 and v3
  75. * type controllers.
  76. */
  77. #define NFC_CMD (1 << 0)
  78. #define NFC_ADDR (1 << 1)
  79. #define NFC_INPUT (1 << 2)
  80. #define NFC_OUTPUT (1 << 3)
  81. #define NFC_ID (1 << 4)
  82. #define NFC_STATUS (1 << 5)
  83. #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
  84. #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
  85. #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
  86. #define NFC_V3_CONFIG1_SP_EN (1 << 0)
  87. #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
  88. #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
  89. #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
  90. #define NFC_V3_WRPROT (host->regs_ip + 0x0)
  91. #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
  92. #define NFC_V3_WRPROT_LOCK (1 << 1)
  93. #define NFC_V3_WRPROT_UNLOCK (1 << 2)
  94. #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
  95. #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
  96. #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
  97. #define NFC_V3_CONFIG2_PS_512 (0 << 0)
  98. #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
  99. #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
  100. #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
  101. #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
  102. #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
  103. #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
  104. #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
  105. #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
  106. #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
  107. #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
  108. #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
  109. #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
  110. #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
  111. #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
  112. #define NFC_V3_CONFIG3_FW8 (1 << 3)
  113. #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
  114. #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
  115. #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
  116. #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
  117. #define NFC_V3_IPC (host->regs_ip + 0x2C)
  118. #define NFC_V3_IPC_CREQ (1 << 0)
  119. #define NFC_V3_IPC_INT (1 << 31)
  120. #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
  121. struct mxc_nand_host;
  122. struct mxc_nand_devtype_data {
  123. void (*preset)(struct mtd_info *);
  124. void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
  125. void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
  126. void (*send_page)(struct mtd_info *, unsigned int);
  127. void (*send_read_id)(struct mxc_nand_host *);
  128. uint16_t (*get_dev_status)(struct mxc_nand_host *);
  129. int (*check_int)(struct mxc_nand_host *);
  130. void (*irq_control)(struct mxc_nand_host *, int);
  131. u32 (*get_ecc_status)(struct mxc_nand_host *);
  132. struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
  133. void (*select_chip)(struct mtd_info *mtd, int chip);
  134. int (*correct_data)(struct mtd_info *mtd, u_char *dat,
  135. u_char *read_ecc, u_char *calc_ecc);
  136. /*
  137. * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
  138. * (CONFIG1:INT_MSK is set). To handle this the driver uses
  139. * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
  140. */
  141. int irqpending_quirk;
  142. int needs_ip;
  143. size_t regs_offset;
  144. size_t spare0_offset;
  145. size_t axi_offset;
  146. int spare_len;
  147. int eccbytes;
  148. int eccsize;
  149. int ppb_shift;
  150. };
  151. struct mxc_nand_host {
  152. struct mtd_info mtd;
  153. struct nand_chip nand;
  154. struct device *dev;
  155. void __iomem *spare0;
  156. void __iomem *main_area0;
  157. void __iomem *base;
  158. void __iomem *regs;
  159. void __iomem *regs_axi;
  160. void __iomem *regs_ip;
  161. int status_request;
  162. struct clk *clk;
  163. int clk_act;
  164. int irq;
  165. int eccsize;
  166. int active_cs;
  167. struct completion op_completion;
  168. uint8_t *data_buf;
  169. unsigned int buf_start;
  170. const struct mxc_nand_devtype_data *devtype_data;
  171. struct mxc_nand_platform_data pdata;
  172. };
  173. /* OOB placement block for use with hardware ecc generation */
  174. static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
  175. .eccbytes = 5,
  176. .eccpos = {6, 7, 8, 9, 10},
  177. .oobfree = {{0, 5}, {12, 4}, }
  178. };
  179. static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
  180. .eccbytes = 20,
  181. .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
  182. 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
  183. .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
  184. };
  185. /* OOB description for 512 byte pages with 16 byte OOB */
  186. static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
  187. .eccbytes = 1 * 9,
  188. .eccpos = {
  189. 7, 8, 9, 10, 11, 12, 13, 14, 15
  190. },
  191. .oobfree = {
  192. {.offset = 0, .length = 5}
  193. }
  194. };
  195. /* OOB description for 2048 byte pages with 64 byte OOB */
  196. static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
  197. .eccbytes = 4 * 9,
  198. .eccpos = {
  199. 7, 8, 9, 10, 11, 12, 13, 14, 15,
  200. 23, 24, 25, 26, 27, 28, 29, 30, 31,
  201. 39, 40, 41, 42, 43, 44, 45, 46, 47,
  202. 55, 56, 57, 58, 59, 60, 61, 62, 63
  203. },
  204. .oobfree = {
  205. {.offset = 2, .length = 4},
  206. {.offset = 16, .length = 7},
  207. {.offset = 32, .length = 7},
  208. {.offset = 48, .length = 7}
  209. }
  210. };
  211. /* OOB description for 4096 byte pages with 128 byte OOB */
  212. static struct nand_ecclayout nandv2_hw_eccoob_4k = {
  213. .eccbytes = 8 * 9,
  214. .eccpos = {
  215. 7, 8, 9, 10, 11, 12, 13, 14, 15,
  216. 23, 24, 25, 26, 27, 28, 29, 30, 31,
  217. 39, 40, 41, 42, 43, 44, 45, 46, 47,
  218. 55, 56, 57, 58, 59, 60, 61, 62, 63,
  219. 71, 72, 73, 74, 75, 76, 77, 78, 79,
  220. 87, 88, 89, 90, 91, 92, 93, 94, 95,
  221. 103, 104, 105, 106, 107, 108, 109, 110, 111,
  222. 119, 120, 121, 122, 123, 124, 125, 126, 127,
  223. },
  224. .oobfree = {
  225. {.offset = 2, .length = 4},
  226. {.offset = 16, .length = 7},
  227. {.offset = 32, .length = 7},
  228. {.offset = 48, .length = 7},
  229. {.offset = 64, .length = 7},
  230. {.offset = 80, .length = 7},
  231. {.offset = 96, .length = 7},
  232. {.offset = 112, .length = 7},
  233. }
  234. };
  235. static const char const *part_probes[] = {
  236. "cmdlinepart", "RedBoot", "ofpart", NULL };
  237. static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
  238. {
  239. int i;
  240. u32 *t = trg;
  241. const __iomem u32 *s = src;
  242. for (i = 0; i < (size >> 2); i++)
  243. *t++ = __raw_readl(s++);
  244. }
  245. static void memcpy32_toio(void __iomem *trg, const void *src, int size)
  246. {
  247. int i;
  248. u32 __iomem *t = trg;
  249. const u32 *s = src;
  250. for (i = 0; i < (size >> 2); i++)
  251. __raw_writel(*s++, t++);
  252. }
  253. static int check_int_v3(struct mxc_nand_host *host)
  254. {
  255. uint32_t tmp;
  256. tmp = readl(NFC_V3_IPC);
  257. if (!(tmp & NFC_V3_IPC_INT))
  258. return 0;
  259. tmp &= ~NFC_V3_IPC_INT;
  260. writel(tmp, NFC_V3_IPC);
  261. return 1;
  262. }
  263. static int check_int_v1_v2(struct mxc_nand_host *host)
  264. {
  265. uint32_t tmp;
  266. tmp = readw(NFC_V1_V2_CONFIG2);
  267. if (!(tmp & NFC_V1_V2_CONFIG2_INT))
  268. return 0;
  269. if (!host->devtype_data->irqpending_quirk)
  270. writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
  271. return 1;
  272. }
  273. static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
  274. {
  275. uint16_t tmp;
  276. tmp = readw(NFC_V1_V2_CONFIG1);
  277. if (activate)
  278. tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
  279. else
  280. tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
  281. writew(tmp, NFC_V1_V2_CONFIG1);
  282. }
  283. static void irq_control_v3(struct mxc_nand_host *host, int activate)
  284. {
  285. uint32_t tmp;
  286. tmp = readl(NFC_V3_CONFIG2);
  287. if (activate)
  288. tmp &= ~NFC_V3_CONFIG2_INT_MSK;
  289. else
  290. tmp |= NFC_V3_CONFIG2_INT_MSK;
  291. writel(tmp, NFC_V3_CONFIG2);
  292. }
  293. static void irq_control(struct mxc_nand_host *host, int activate)
  294. {
  295. if (host->devtype_data->irqpending_quirk) {
  296. if (activate)
  297. enable_irq(host->irq);
  298. else
  299. disable_irq_nosync(host->irq);
  300. } else {
  301. host->devtype_data->irq_control(host, activate);
  302. }
  303. }
  304. static u32 get_ecc_status_v1(struct mxc_nand_host *host)
  305. {
  306. return readw(NFC_V1_V2_ECC_STATUS_RESULT);
  307. }
  308. static u32 get_ecc_status_v2(struct mxc_nand_host *host)
  309. {
  310. return readl(NFC_V1_V2_ECC_STATUS_RESULT);
  311. }
  312. static u32 get_ecc_status_v3(struct mxc_nand_host *host)
  313. {
  314. return readl(NFC_V3_ECC_STATUS_RESULT);
  315. }
  316. static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
  317. {
  318. struct mxc_nand_host *host = dev_id;
  319. if (!host->devtype_data->check_int(host))
  320. return IRQ_NONE;
  321. irq_control(host, 0);
  322. complete(&host->op_completion);
  323. return IRQ_HANDLED;
  324. }
  325. /* This function polls the NANDFC to wait for the basic operation to
  326. * complete by checking the INT bit of config2 register.
  327. */
  328. static void wait_op_done(struct mxc_nand_host *host, int useirq)
  329. {
  330. int max_retries = 8000;
  331. if (useirq) {
  332. if (!host->devtype_data->check_int(host)) {
  333. INIT_COMPLETION(host->op_completion);
  334. irq_control(host, 1);
  335. wait_for_completion(&host->op_completion);
  336. }
  337. } else {
  338. while (max_retries-- > 0) {
  339. if (host->devtype_data->check_int(host))
  340. break;
  341. udelay(1);
  342. }
  343. if (max_retries < 0)
  344. pr_debug("%s: INT not set\n", __func__);
  345. }
  346. }
  347. static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
  348. {
  349. /* fill command */
  350. writel(cmd, NFC_V3_FLASH_CMD);
  351. /* send out command */
  352. writel(NFC_CMD, NFC_V3_LAUNCH);
  353. /* Wait for operation to complete */
  354. wait_op_done(host, useirq);
  355. }
  356. /* This function issues the specified command to the NAND device and
  357. * waits for completion. */
  358. static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
  359. {
  360. pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
  361. writew(cmd, NFC_V1_V2_FLASH_CMD);
  362. writew(NFC_CMD, NFC_V1_V2_CONFIG2);
  363. if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
  364. int max_retries = 100;
  365. /* Reset completion is indicated by NFC_CONFIG2 */
  366. /* being set to 0 */
  367. while (max_retries-- > 0) {
  368. if (readw(NFC_V1_V2_CONFIG2) == 0) {
  369. break;
  370. }
  371. udelay(1);
  372. }
  373. if (max_retries < 0)
  374. pr_debug("%s: RESET failed\n", __func__);
  375. } else {
  376. /* Wait for operation to complete */
  377. wait_op_done(host, useirq);
  378. }
  379. }
  380. static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
  381. {
  382. /* fill address */
  383. writel(addr, NFC_V3_FLASH_ADDR0);
  384. /* send out address */
  385. writel(NFC_ADDR, NFC_V3_LAUNCH);
  386. wait_op_done(host, 0);
  387. }
  388. /* This function sends an address (or partial address) to the
  389. * NAND device. The address is used to select the source/destination for
  390. * a NAND command. */
  391. static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
  392. {
  393. pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
  394. writew(addr, NFC_V1_V2_FLASH_ADDR);
  395. writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
  396. /* Wait for operation to complete */
  397. wait_op_done(host, islast);
  398. }
  399. static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
  400. {
  401. struct nand_chip *nand_chip = mtd->priv;
  402. struct mxc_nand_host *host = nand_chip->priv;
  403. uint32_t tmp;
  404. tmp = readl(NFC_V3_CONFIG1);
  405. tmp &= ~(7 << 4);
  406. writel(tmp, NFC_V3_CONFIG1);
  407. /* transfer data from NFC ram to nand */
  408. writel(ops, NFC_V3_LAUNCH);
  409. wait_op_done(host, false);
  410. }
  411. static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
  412. {
  413. struct nand_chip *nand_chip = mtd->priv;
  414. struct mxc_nand_host *host = nand_chip->priv;
  415. /* NANDFC buffer 0 is used for page read/write */
  416. writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
  417. writew(ops, NFC_V1_V2_CONFIG2);
  418. /* Wait for operation to complete */
  419. wait_op_done(host, true);
  420. }
  421. static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
  422. {
  423. struct nand_chip *nand_chip = mtd->priv;
  424. struct mxc_nand_host *host = nand_chip->priv;
  425. int bufs, i;
  426. if (mtd->writesize > 512)
  427. bufs = 4;
  428. else
  429. bufs = 1;
  430. for (i = 0; i < bufs; i++) {
  431. /* NANDFC buffer 0 is used for page read/write */
  432. writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
  433. writew(ops, NFC_V1_V2_CONFIG2);
  434. /* Wait for operation to complete */
  435. wait_op_done(host, true);
  436. }
  437. }
  438. static void send_read_id_v3(struct mxc_nand_host *host)
  439. {
  440. /* Read ID into main buffer */
  441. writel(NFC_ID, NFC_V3_LAUNCH);
  442. wait_op_done(host, true);
  443. memcpy32_fromio(host->data_buf, host->main_area0, 16);
  444. }
  445. /* Request the NANDFC to perform a read of the NAND device ID. */
  446. static void send_read_id_v1_v2(struct mxc_nand_host *host)
  447. {
  448. struct nand_chip *this = &host->nand;
  449. /* NANDFC buffer 0 is used for device ID output */
  450. writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
  451. writew(NFC_ID, NFC_V1_V2_CONFIG2);
  452. /* Wait for operation to complete */
  453. wait_op_done(host, true);
  454. memcpy32_fromio(host->data_buf, host->main_area0, 16);
  455. if (this->options & NAND_BUSWIDTH_16) {
  456. /* compress the ID info */
  457. host->data_buf[1] = host->data_buf[2];
  458. host->data_buf[2] = host->data_buf[4];
  459. host->data_buf[3] = host->data_buf[6];
  460. host->data_buf[4] = host->data_buf[8];
  461. host->data_buf[5] = host->data_buf[10];
  462. }
  463. }
  464. static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
  465. {
  466. writew(NFC_STATUS, NFC_V3_LAUNCH);
  467. wait_op_done(host, true);
  468. return readl(NFC_V3_CONFIG1) >> 16;
  469. }
  470. /* This function requests the NANDFC to perform a read of the
  471. * NAND device status and returns the current status. */
  472. static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
  473. {
  474. void __iomem *main_buf = host->main_area0;
  475. uint32_t store;
  476. uint16_t ret;
  477. writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
  478. /*
  479. * The device status is stored in main_area0. To
  480. * prevent corruption of the buffer save the value
  481. * and restore it afterwards.
  482. */
  483. store = readl(main_buf);
  484. writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
  485. wait_op_done(host, true);
  486. ret = readw(main_buf);
  487. writel(store, main_buf);
  488. return ret;
  489. }
  490. /* This functions is used by upper layer to checks if device is ready */
  491. static int mxc_nand_dev_ready(struct mtd_info *mtd)
  492. {
  493. /*
  494. * NFC handles R/B internally. Therefore, this function
  495. * always returns status as ready.
  496. */
  497. return 1;
  498. }
  499. static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
  500. {
  501. /*
  502. * If HW ECC is enabled, we turn it on during init. There is
  503. * no need to enable again here.
  504. */
  505. }
  506. static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
  507. u_char *read_ecc, u_char *calc_ecc)
  508. {
  509. struct nand_chip *nand_chip = mtd->priv;
  510. struct mxc_nand_host *host = nand_chip->priv;
  511. /*
  512. * 1-Bit errors are automatically corrected in HW. No need for
  513. * additional correction. 2-Bit errors cannot be corrected by
  514. * HW ECC, so we need to return failure
  515. */
  516. uint16_t ecc_status = get_ecc_status_v1(host);
  517. if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
  518. pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
  519. return -1;
  520. }
  521. return 0;
  522. }
  523. static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
  524. u_char *read_ecc, u_char *calc_ecc)
  525. {
  526. struct nand_chip *nand_chip = mtd->priv;
  527. struct mxc_nand_host *host = nand_chip->priv;
  528. u32 ecc_stat, err;
  529. int no_subpages = 1;
  530. int ret = 0;
  531. u8 ecc_bit_mask, err_limit;
  532. ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
  533. err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
  534. no_subpages = mtd->writesize >> 9;
  535. ecc_stat = host->devtype_data->get_ecc_status(host);
  536. do {
  537. err = ecc_stat & ecc_bit_mask;
  538. if (err > err_limit) {
  539. printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
  540. return -1;
  541. } else {
  542. ret += err;
  543. }
  544. ecc_stat >>= 4;
  545. } while (--no_subpages);
  546. mtd->ecc_stats.corrected += ret;
  547. pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
  548. return ret;
  549. }
  550. static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
  551. u_char *ecc_code)
  552. {
  553. return 0;
  554. }
  555. static u_char mxc_nand_read_byte(struct mtd_info *mtd)
  556. {
  557. struct nand_chip *nand_chip = mtd->priv;
  558. struct mxc_nand_host *host = nand_chip->priv;
  559. uint8_t ret;
  560. /* Check for status request */
  561. if (host->status_request)
  562. return host->devtype_data->get_dev_status(host) & 0xFF;
  563. ret = *(uint8_t *)(host->data_buf + host->buf_start);
  564. host->buf_start++;
  565. return ret;
  566. }
  567. static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
  568. {
  569. struct nand_chip *nand_chip = mtd->priv;
  570. struct mxc_nand_host *host = nand_chip->priv;
  571. uint16_t ret;
  572. ret = *(uint16_t *)(host->data_buf + host->buf_start);
  573. host->buf_start += 2;
  574. return ret;
  575. }
  576. /* Write data of length len to buffer buf. The data to be
  577. * written on NAND Flash is first copied to RAMbuffer. After the Data Input
  578. * Operation by the NFC, the data is written to NAND Flash */
  579. static void mxc_nand_write_buf(struct mtd_info *mtd,
  580. const u_char *buf, int len)
  581. {
  582. struct nand_chip *nand_chip = mtd->priv;
  583. struct mxc_nand_host *host = nand_chip->priv;
  584. u16 col = host->buf_start;
  585. int n = mtd->oobsize + mtd->writesize - col;
  586. n = min(n, len);
  587. memcpy(host->data_buf + col, buf, n);
  588. host->buf_start += n;
  589. }
  590. /* Read the data buffer from the NAND Flash. To read the data from NAND
  591. * Flash first the data output cycle is initiated by the NFC, which copies
  592. * the data to RAMbuffer. This data of length len is then copied to buffer buf.
  593. */
  594. static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  595. {
  596. struct nand_chip *nand_chip = mtd->priv;
  597. struct mxc_nand_host *host = nand_chip->priv;
  598. u16 col = host->buf_start;
  599. int n = mtd->oobsize + mtd->writesize - col;
  600. n = min(n, len);
  601. memcpy(buf, host->data_buf + col, n);
  602. host->buf_start += n;
  603. }
  604. /* This function is used by upper layer for select and
  605. * deselect of the NAND chip */
  606. static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
  607. {
  608. struct nand_chip *nand_chip = mtd->priv;
  609. struct mxc_nand_host *host = nand_chip->priv;
  610. if (chip == -1) {
  611. /* Disable the NFC clock */
  612. if (host->clk_act) {
  613. clk_disable_unprepare(host->clk);
  614. host->clk_act = 0;
  615. }
  616. return;
  617. }
  618. if (!host->clk_act) {
  619. /* Enable the NFC clock */
  620. clk_prepare_enable(host->clk);
  621. host->clk_act = 1;
  622. }
  623. }
  624. static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
  625. {
  626. struct nand_chip *nand_chip = mtd->priv;
  627. struct mxc_nand_host *host = nand_chip->priv;
  628. if (chip == -1) {
  629. /* Disable the NFC clock */
  630. if (host->clk_act) {
  631. clk_disable_unprepare(host->clk);
  632. host->clk_act = 0;
  633. }
  634. return;
  635. }
  636. if (!host->clk_act) {
  637. /* Enable the NFC clock */
  638. clk_prepare_enable(host->clk);
  639. host->clk_act = 1;
  640. }
  641. host->active_cs = chip;
  642. writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
  643. }
  644. /*
  645. * Function to transfer data to/from spare area.
  646. */
  647. static void copy_spare(struct mtd_info *mtd, bool bfrom)
  648. {
  649. struct nand_chip *this = mtd->priv;
  650. struct mxc_nand_host *host = this->priv;
  651. u16 i, j;
  652. u16 n = mtd->writesize >> 9;
  653. u8 *d = host->data_buf + mtd->writesize;
  654. u8 __iomem *s = host->spare0;
  655. u16 t = host->devtype_data->spare_len;
  656. j = (mtd->oobsize / n >> 1) << 1;
  657. if (bfrom) {
  658. for (i = 0; i < n - 1; i++)
  659. memcpy32_fromio(d + i * j, s + i * t, j);
  660. /* the last section */
  661. memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
  662. } else {
  663. for (i = 0; i < n - 1; i++)
  664. memcpy32_toio(&s[i * t], &d[i * j], j);
  665. /* the last section */
  666. memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
  667. }
  668. }
  669. static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
  670. {
  671. struct nand_chip *nand_chip = mtd->priv;
  672. struct mxc_nand_host *host = nand_chip->priv;
  673. /* Write out column address, if necessary */
  674. if (column != -1) {
  675. /*
  676. * MXC NANDFC can only perform full page+spare or
  677. * spare-only read/write. When the upper layers
  678. * perform a read/write buf operation, the saved column
  679. * address is used to index into the full page.
  680. */
  681. host->devtype_data->send_addr(host, 0, page_addr == -1);
  682. if (mtd->writesize > 512)
  683. /* another col addr cycle for 2k page */
  684. host->devtype_data->send_addr(host, 0, false);
  685. }
  686. /* Write out page address, if necessary */
  687. if (page_addr != -1) {
  688. /* paddr_0 - p_addr_7 */
  689. host->devtype_data->send_addr(host, (page_addr & 0xff), false);
  690. if (mtd->writesize > 512) {
  691. if (mtd->size >= 0x10000000) {
  692. /* paddr_8 - paddr_15 */
  693. host->devtype_data->send_addr(host,
  694. (page_addr >> 8) & 0xff,
  695. false);
  696. host->devtype_data->send_addr(host,
  697. (page_addr >> 16) & 0xff,
  698. true);
  699. } else
  700. /* paddr_8 - paddr_15 */
  701. host->devtype_data->send_addr(host,
  702. (page_addr >> 8) & 0xff, true);
  703. } else {
  704. /* One more address cycle for higher density devices */
  705. if (mtd->size >= 0x4000000) {
  706. /* paddr_8 - paddr_15 */
  707. host->devtype_data->send_addr(host,
  708. (page_addr >> 8) & 0xff,
  709. false);
  710. host->devtype_data->send_addr(host,
  711. (page_addr >> 16) & 0xff,
  712. true);
  713. } else
  714. /* paddr_8 - paddr_15 */
  715. host->devtype_data->send_addr(host,
  716. (page_addr >> 8) & 0xff, true);
  717. }
  718. }
  719. }
  720. /*
  721. * v2 and v3 type controllers can do 4bit or 8bit ecc depending
  722. * on how much oob the nand chip has. For 8bit ecc we need at least
  723. * 26 bytes of oob data per 512 byte block.
  724. */
  725. static int get_eccsize(struct mtd_info *mtd)
  726. {
  727. int oobbytes_per_512 = 0;
  728. oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
  729. if (oobbytes_per_512 < 26)
  730. return 4;
  731. else
  732. return 8;
  733. }
  734. static void preset_v1(struct mtd_info *mtd)
  735. {
  736. struct nand_chip *nand_chip = mtd->priv;
  737. struct mxc_nand_host *host = nand_chip->priv;
  738. uint16_t config1 = 0;
  739. if (nand_chip->ecc.mode == NAND_ECC_HW)
  740. config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
  741. if (!host->devtype_data->irqpending_quirk)
  742. config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
  743. host->eccsize = 1;
  744. writew(config1, NFC_V1_V2_CONFIG1);
  745. /* preset operation */
  746. /* Unlock the internal RAM Buffer */
  747. writew(0x2, NFC_V1_V2_CONFIG);
  748. /* Blocks to be unlocked */
  749. writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
  750. writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
  751. /* Unlock Block Command for given address range */
  752. writew(0x4, NFC_V1_V2_WRPROT);
  753. }
  754. static void preset_v2(struct mtd_info *mtd)
  755. {
  756. struct nand_chip *nand_chip = mtd->priv;
  757. struct mxc_nand_host *host = nand_chip->priv;
  758. uint16_t config1 = 0;
  759. if (nand_chip->ecc.mode == NAND_ECC_HW)
  760. config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
  761. config1 |= NFC_V2_CONFIG1_FP_INT;
  762. if (!host->devtype_data->irqpending_quirk)
  763. config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
  764. if (mtd->writesize) {
  765. uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
  766. host->eccsize = get_eccsize(mtd);
  767. if (host->eccsize == 4)
  768. config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
  769. config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
  770. } else {
  771. host->eccsize = 1;
  772. }
  773. writew(config1, NFC_V1_V2_CONFIG1);
  774. /* preset operation */
  775. /* Unlock the internal RAM Buffer */
  776. writew(0x2, NFC_V1_V2_CONFIG);
  777. /* Blocks to be unlocked */
  778. writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
  779. writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
  780. writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
  781. writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
  782. writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
  783. writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
  784. writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
  785. writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
  786. /* Unlock Block Command for given address range */
  787. writew(0x4, NFC_V1_V2_WRPROT);
  788. }
  789. static void preset_v3(struct mtd_info *mtd)
  790. {
  791. struct nand_chip *chip = mtd->priv;
  792. struct mxc_nand_host *host = chip->priv;
  793. uint32_t config2, config3;
  794. int i, addr_phases;
  795. writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
  796. writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
  797. /* Unlock the internal RAM Buffer */
  798. writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
  799. NFC_V3_WRPROT);
  800. /* Blocks to be unlocked */
  801. for (i = 0; i < NAND_MAX_CHIPS; i++)
  802. writel(0x0 | (0xffff << 16),
  803. NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
  804. writel(0, NFC_V3_IPC);
  805. config2 = NFC_V3_CONFIG2_ONE_CYCLE |
  806. NFC_V3_CONFIG2_2CMD_PHASES |
  807. NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
  808. NFC_V3_CONFIG2_ST_CMD(0x70) |
  809. NFC_V3_CONFIG2_INT_MSK |
  810. NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
  811. if (chip->ecc.mode == NAND_ECC_HW)
  812. config2 |= NFC_V3_CONFIG2_ECC_EN;
  813. addr_phases = fls(chip->pagemask) >> 3;
  814. if (mtd->writesize == 2048) {
  815. config2 |= NFC_V3_CONFIG2_PS_2048;
  816. config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
  817. } else if (mtd->writesize == 4096) {
  818. config2 |= NFC_V3_CONFIG2_PS_4096;
  819. config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
  820. } else {
  821. config2 |= NFC_V3_CONFIG2_PS_512;
  822. config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
  823. }
  824. if (mtd->writesize) {
  825. config2 |= NFC_V3_CONFIG2_PPB(
  826. ffs(mtd->erasesize / mtd->writesize) - 6,
  827. host->devtype_data->ppb_shift);
  828. host->eccsize = get_eccsize(mtd);
  829. if (host->eccsize == 8)
  830. config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
  831. }
  832. writel(config2, NFC_V3_CONFIG2);
  833. config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
  834. NFC_V3_CONFIG3_NO_SDMA |
  835. NFC_V3_CONFIG3_RBB_MODE |
  836. NFC_V3_CONFIG3_SBB(6) | /* Reset default */
  837. NFC_V3_CONFIG3_ADD_OP(0);
  838. if (!(chip->options & NAND_BUSWIDTH_16))
  839. config3 |= NFC_V3_CONFIG3_FW8;
  840. writel(config3, NFC_V3_CONFIG3);
  841. writel(0, NFC_V3_DELAY_LINE);
  842. }
  843. /* Used by the upper layer to write command to NAND Flash for
  844. * different operations to be carried out on NAND Flash */
  845. static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
  846. int column, int page_addr)
  847. {
  848. struct nand_chip *nand_chip = mtd->priv;
  849. struct mxc_nand_host *host = nand_chip->priv;
  850. pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
  851. command, column, page_addr);
  852. /* Reset command state information */
  853. host->status_request = false;
  854. /* Command pre-processing step */
  855. switch (command) {
  856. case NAND_CMD_RESET:
  857. host->devtype_data->preset(mtd);
  858. host->devtype_data->send_cmd(host, command, false);
  859. break;
  860. case NAND_CMD_STATUS:
  861. host->buf_start = 0;
  862. host->status_request = true;
  863. host->devtype_data->send_cmd(host, command, true);
  864. mxc_do_addr_cycle(mtd, column, page_addr);
  865. break;
  866. case NAND_CMD_READ0:
  867. case NAND_CMD_READOOB:
  868. if (command == NAND_CMD_READ0)
  869. host->buf_start = column;
  870. else
  871. host->buf_start = column + mtd->writesize;
  872. command = NAND_CMD_READ0; /* only READ0 is valid */
  873. host->devtype_data->send_cmd(host, command, false);
  874. mxc_do_addr_cycle(mtd, column, page_addr);
  875. if (mtd->writesize > 512)
  876. host->devtype_data->send_cmd(host,
  877. NAND_CMD_READSTART, true);
  878. host->devtype_data->send_page(mtd, NFC_OUTPUT);
  879. memcpy32_fromio(host->data_buf, host->main_area0,
  880. mtd->writesize);
  881. copy_spare(mtd, true);
  882. break;
  883. case NAND_CMD_SEQIN:
  884. if (column >= mtd->writesize)
  885. /* call ourself to read a page */
  886. mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
  887. host->buf_start = column;
  888. host->devtype_data->send_cmd(host, command, false);
  889. mxc_do_addr_cycle(mtd, column, page_addr);
  890. break;
  891. case NAND_CMD_PAGEPROG:
  892. memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
  893. copy_spare(mtd, false);
  894. host->devtype_data->send_page(mtd, NFC_INPUT);
  895. host->devtype_data->send_cmd(host, command, true);
  896. mxc_do_addr_cycle(mtd, column, page_addr);
  897. break;
  898. case NAND_CMD_READID:
  899. host->devtype_data->send_cmd(host, command, true);
  900. mxc_do_addr_cycle(mtd, column, page_addr);
  901. host->devtype_data->send_read_id(host);
  902. host->buf_start = column;
  903. break;
  904. case NAND_CMD_ERASE1:
  905. case NAND_CMD_ERASE2:
  906. host->devtype_data->send_cmd(host, command, false);
  907. mxc_do_addr_cycle(mtd, column, page_addr);
  908. break;
  909. }
  910. }
  911. /*
  912. * The generic flash bbt decriptors overlap with our ecc
  913. * hardware, so define some i.MX specific ones.
  914. */
  915. static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
  916. static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
  917. static struct nand_bbt_descr bbt_main_descr = {
  918. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  919. | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  920. .offs = 0,
  921. .len = 4,
  922. .veroffs = 4,
  923. .maxblocks = 4,
  924. .pattern = bbt_pattern,
  925. };
  926. static struct nand_bbt_descr bbt_mirror_descr = {
  927. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  928. | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  929. .offs = 0,
  930. .len = 4,
  931. .veroffs = 4,
  932. .maxblocks = 4,
  933. .pattern = mirror_pattern,
  934. };
  935. /* v1 + irqpending_quirk: i.MX21 */
  936. static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
  937. .preset = preset_v1,
  938. .send_cmd = send_cmd_v1_v2,
  939. .send_addr = send_addr_v1_v2,
  940. .send_page = send_page_v1,
  941. .send_read_id = send_read_id_v1_v2,
  942. .get_dev_status = get_dev_status_v1_v2,
  943. .check_int = check_int_v1_v2,
  944. .irq_control = irq_control_v1_v2,
  945. .get_ecc_status = get_ecc_status_v1,
  946. .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
  947. .ecclayout_2k = &nandv1_hw_eccoob_largepage,
  948. .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
  949. .select_chip = mxc_nand_select_chip_v1_v3,
  950. .correct_data = mxc_nand_correct_data_v1,
  951. .irqpending_quirk = 1,
  952. .needs_ip = 0,
  953. .regs_offset = 0xe00,
  954. .spare0_offset = 0x800,
  955. .spare_len = 16,
  956. .eccbytes = 3,
  957. .eccsize = 1,
  958. };
  959. /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
  960. static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
  961. .preset = preset_v1,
  962. .send_cmd = send_cmd_v1_v2,
  963. .send_addr = send_addr_v1_v2,
  964. .send_page = send_page_v1,
  965. .send_read_id = send_read_id_v1_v2,
  966. .get_dev_status = get_dev_status_v1_v2,
  967. .check_int = check_int_v1_v2,
  968. .irq_control = irq_control_v1_v2,
  969. .get_ecc_status = get_ecc_status_v1,
  970. .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
  971. .ecclayout_2k = &nandv1_hw_eccoob_largepage,
  972. .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
  973. .select_chip = mxc_nand_select_chip_v1_v3,
  974. .correct_data = mxc_nand_correct_data_v1,
  975. .irqpending_quirk = 0,
  976. .needs_ip = 0,
  977. .regs_offset = 0xe00,
  978. .spare0_offset = 0x800,
  979. .axi_offset = 0,
  980. .spare_len = 16,
  981. .eccbytes = 3,
  982. .eccsize = 1,
  983. };
  984. /* v21: i.MX25, i.MX35 */
  985. static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
  986. .preset = preset_v2,
  987. .send_cmd = send_cmd_v1_v2,
  988. .send_addr = send_addr_v1_v2,
  989. .send_page = send_page_v2,
  990. .send_read_id = send_read_id_v1_v2,
  991. .get_dev_status = get_dev_status_v1_v2,
  992. .check_int = check_int_v1_v2,
  993. .irq_control = irq_control_v1_v2,
  994. .get_ecc_status = get_ecc_status_v2,
  995. .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
  996. .ecclayout_2k = &nandv2_hw_eccoob_largepage,
  997. .ecclayout_4k = &nandv2_hw_eccoob_4k,
  998. .select_chip = mxc_nand_select_chip_v2,
  999. .correct_data = mxc_nand_correct_data_v2_v3,
  1000. .irqpending_quirk = 0,
  1001. .needs_ip = 0,
  1002. .regs_offset = 0x1e00,
  1003. .spare0_offset = 0x1000,
  1004. .axi_offset = 0,
  1005. .spare_len = 64,
  1006. .eccbytes = 9,
  1007. .eccsize = 0,
  1008. };
  1009. /* v3.2a: i.MX51 */
  1010. static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
  1011. .preset = preset_v3,
  1012. .send_cmd = send_cmd_v3,
  1013. .send_addr = send_addr_v3,
  1014. .send_page = send_page_v3,
  1015. .send_read_id = send_read_id_v3,
  1016. .get_dev_status = get_dev_status_v3,
  1017. .check_int = check_int_v3,
  1018. .irq_control = irq_control_v3,
  1019. .get_ecc_status = get_ecc_status_v3,
  1020. .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
  1021. .ecclayout_2k = &nandv2_hw_eccoob_largepage,
  1022. .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
  1023. .select_chip = mxc_nand_select_chip_v1_v3,
  1024. .correct_data = mxc_nand_correct_data_v2_v3,
  1025. .irqpending_quirk = 0,
  1026. .needs_ip = 1,
  1027. .regs_offset = 0,
  1028. .spare0_offset = 0x1000,
  1029. .axi_offset = 0x1e00,
  1030. .spare_len = 64,
  1031. .eccbytes = 0,
  1032. .eccsize = 0,
  1033. .ppb_shift = 7,
  1034. };
  1035. /* v3.2b: i.MX53 */
  1036. static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
  1037. .preset = preset_v3,
  1038. .send_cmd = send_cmd_v3,
  1039. .send_addr = send_addr_v3,
  1040. .send_page = send_page_v3,
  1041. .send_read_id = send_read_id_v3,
  1042. .get_dev_status = get_dev_status_v3,
  1043. .check_int = check_int_v3,
  1044. .irq_control = irq_control_v3,
  1045. .get_ecc_status = get_ecc_status_v3,
  1046. .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
  1047. .ecclayout_2k = &nandv2_hw_eccoob_largepage,
  1048. .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
  1049. .select_chip = mxc_nand_select_chip_v1_v3,
  1050. .correct_data = mxc_nand_correct_data_v2_v3,
  1051. .irqpending_quirk = 0,
  1052. .needs_ip = 1,
  1053. .regs_offset = 0,
  1054. .spare0_offset = 0x1000,
  1055. .axi_offset = 0x1e00,
  1056. .spare_len = 64,
  1057. .eccbytes = 0,
  1058. .eccsize = 0,
  1059. .ppb_shift = 8,
  1060. };
  1061. static inline int is_imx21_nfc(struct mxc_nand_host *host)
  1062. {
  1063. return host->devtype_data == &imx21_nand_devtype_data;
  1064. }
  1065. static inline int is_imx27_nfc(struct mxc_nand_host *host)
  1066. {
  1067. return host->devtype_data == &imx27_nand_devtype_data;
  1068. }
  1069. static inline int is_imx25_nfc(struct mxc_nand_host *host)
  1070. {
  1071. return host->devtype_data == &imx25_nand_devtype_data;
  1072. }
  1073. static inline int is_imx51_nfc(struct mxc_nand_host *host)
  1074. {
  1075. return host->devtype_data == &imx51_nand_devtype_data;
  1076. }
  1077. static inline int is_imx53_nfc(struct mxc_nand_host *host)
  1078. {
  1079. return host->devtype_data == &imx53_nand_devtype_data;
  1080. }
  1081. static struct platform_device_id mxcnd_devtype[] = {
  1082. {
  1083. .name = "imx21-nand",
  1084. .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
  1085. }, {
  1086. .name = "imx27-nand",
  1087. .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
  1088. }, {
  1089. .name = "imx25-nand",
  1090. .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
  1091. }, {
  1092. .name = "imx51-nand",
  1093. .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
  1094. }, {
  1095. .name = "imx53-nand",
  1096. .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
  1097. }, {
  1098. /* sentinel */
  1099. }
  1100. };
  1101. MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
  1102. #ifdef CONFIG_OF_MTD
  1103. static const struct of_device_id mxcnd_dt_ids[] = {
  1104. {
  1105. .compatible = "fsl,imx21-nand",
  1106. .data = &imx21_nand_devtype_data,
  1107. }, {
  1108. .compatible = "fsl,imx27-nand",
  1109. .data = &imx27_nand_devtype_data,
  1110. }, {
  1111. .compatible = "fsl,imx25-nand",
  1112. .data = &imx25_nand_devtype_data,
  1113. }, {
  1114. .compatible = "fsl,imx51-nand",
  1115. .data = &imx51_nand_devtype_data,
  1116. }, {
  1117. .compatible = "fsl,imx53-nand",
  1118. .data = &imx53_nand_devtype_data,
  1119. },
  1120. { /* sentinel */ }
  1121. };
  1122. static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
  1123. {
  1124. struct device_node *np = host->dev->of_node;
  1125. struct mxc_nand_platform_data *pdata = &host->pdata;
  1126. const struct of_device_id *of_id =
  1127. of_match_device(mxcnd_dt_ids, host->dev);
  1128. int buswidth;
  1129. if (!np)
  1130. return 1;
  1131. if (of_get_nand_ecc_mode(np) >= 0)
  1132. pdata->hw_ecc = 1;
  1133. pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
  1134. buswidth = of_get_nand_bus_width(np);
  1135. if (buswidth < 0)
  1136. return buswidth;
  1137. pdata->width = buswidth / 8;
  1138. host->devtype_data = of_id->data;
  1139. return 0;
  1140. }
  1141. #else
  1142. static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
  1143. {
  1144. return 1;
  1145. }
  1146. #endif
  1147. static int mxcnd_probe(struct platform_device *pdev)
  1148. {
  1149. struct nand_chip *this;
  1150. struct mtd_info *mtd;
  1151. struct mxc_nand_host *host;
  1152. struct resource *res;
  1153. int err = 0;
  1154. /* Allocate memory for MTD device structure and private data */
  1155. host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) +
  1156. NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL);
  1157. if (!host)
  1158. return -ENOMEM;
  1159. host->data_buf = (uint8_t *)(host + 1);
  1160. host->dev = &pdev->dev;
  1161. /* structures must be linked */
  1162. this = &host->nand;
  1163. mtd = &host->mtd;
  1164. mtd->priv = this;
  1165. mtd->owner = THIS_MODULE;
  1166. mtd->dev.parent = &pdev->dev;
  1167. mtd->name = DRIVER_NAME;
  1168. /* 50 us command delay time */
  1169. this->chip_delay = 5;
  1170. this->priv = host;
  1171. this->dev_ready = mxc_nand_dev_ready;
  1172. this->cmdfunc = mxc_nand_command;
  1173. this->read_byte = mxc_nand_read_byte;
  1174. this->read_word = mxc_nand_read_word;
  1175. this->write_buf = mxc_nand_write_buf;
  1176. this->read_buf = mxc_nand_read_buf;
  1177. host->clk = devm_clk_get(&pdev->dev, NULL);
  1178. if (IS_ERR(host->clk))
  1179. return PTR_ERR(host->clk);
  1180. err = mxcnd_probe_dt(host);
  1181. if (err > 0) {
  1182. struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
  1183. if (pdata) {
  1184. host->pdata = *pdata;
  1185. host->devtype_data = (struct mxc_nand_devtype_data *)
  1186. pdev->id_entry->driver_data;
  1187. } else {
  1188. err = -ENODEV;
  1189. }
  1190. }
  1191. if (err < 0)
  1192. return err;
  1193. if (host->devtype_data->needs_ip) {
  1194. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1195. if (!res)
  1196. return -ENODEV;
  1197. host->regs_ip = devm_request_and_ioremap(&pdev->dev, res);
  1198. if (!host->regs_ip)
  1199. return -ENOMEM;
  1200. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1201. } else {
  1202. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1203. }
  1204. if (!res)
  1205. return -ENODEV;
  1206. host->base = devm_request_and_ioremap(&pdev->dev, res);
  1207. if (!host->base)
  1208. return -ENOMEM;
  1209. host->main_area0 = host->base;
  1210. if (host->devtype_data->regs_offset)
  1211. host->regs = host->base + host->devtype_data->regs_offset;
  1212. host->spare0 = host->base + host->devtype_data->spare0_offset;
  1213. if (host->devtype_data->axi_offset)
  1214. host->regs_axi = host->base + host->devtype_data->axi_offset;
  1215. this->ecc.bytes = host->devtype_data->eccbytes;
  1216. host->eccsize = host->devtype_data->eccsize;
  1217. this->select_chip = host->devtype_data->select_chip;
  1218. this->ecc.size = 512;
  1219. this->ecc.layout = host->devtype_data->ecclayout_512;
  1220. if (host->pdata.hw_ecc) {
  1221. this->ecc.calculate = mxc_nand_calculate_ecc;
  1222. this->ecc.hwctl = mxc_nand_enable_hwecc;
  1223. this->ecc.correct = host->devtype_data->correct_data;
  1224. this->ecc.mode = NAND_ECC_HW;
  1225. } else {
  1226. this->ecc.mode = NAND_ECC_SOFT;
  1227. }
  1228. /* NAND bus width determines access functions used by upper layer */
  1229. if (host->pdata.width == 2)
  1230. this->options |= NAND_BUSWIDTH_16;
  1231. if (host->pdata.flash_bbt) {
  1232. this->bbt_td = &bbt_main_descr;
  1233. this->bbt_md = &bbt_mirror_descr;
  1234. /* update flash based bbt */
  1235. this->bbt_options |= NAND_BBT_USE_FLASH;
  1236. }
  1237. init_completion(&host->op_completion);
  1238. host->irq = platform_get_irq(pdev, 0);
  1239. /*
  1240. * Use host->devtype_data->irq_control() here instead of irq_control()
  1241. * because we must not disable_irq_nosync without having requested the
  1242. * irq.
  1243. */
  1244. host->devtype_data->irq_control(host, 0);
  1245. err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
  1246. IRQF_DISABLED, DRIVER_NAME, host);
  1247. if (err)
  1248. return err;
  1249. clk_prepare_enable(host->clk);
  1250. host->clk_act = 1;
  1251. /*
  1252. * Now that we "own" the interrupt make sure the interrupt mask bit is
  1253. * cleared on i.MX21. Otherwise we can't read the interrupt status bit
  1254. * on this machine.
  1255. */
  1256. if (host->devtype_data->irqpending_quirk) {
  1257. disable_irq_nosync(host->irq);
  1258. host->devtype_data->irq_control(host, 1);
  1259. }
  1260. /* first scan to find the device and get the page size */
  1261. if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
  1262. err = -ENXIO;
  1263. goto escan;
  1264. }
  1265. /* Call preset again, with correct writesize this time */
  1266. host->devtype_data->preset(mtd);
  1267. if (mtd->writesize == 2048)
  1268. this->ecc.layout = host->devtype_data->ecclayout_2k;
  1269. else if (mtd->writesize == 4096)
  1270. this->ecc.layout = host->devtype_data->ecclayout_4k;
  1271. if (this->ecc.mode == NAND_ECC_HW) {
  1272. if (is_imx21_nfc(host) || is_imx27_nfc(host))
  1273. this->ecc.strength = 1;
  1274. else
  1275. this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
  1276. }
  1277. /* second phase scan */
  1278. if (nand_scan_tail(mtd)) {
  1279. err = -ENXIO;
  1280. goto escan;
  1281. }
  1282. /* Register the partitions */
  1283. mtd_device_parse_register(mtd, part_probes,
  1284. &(struct mtd_part_parser_data){
  1285. .of_node = pdev->dev.of_node,
  1286. },
  1287. host->pdata.parts,
  1288. host->pdata.nr_parts);
  1289. platform_set_drvdata(pdev, host);
  1290. return 0;
  1291. escan:
  1292. if (host->clk_act)
  1293. clk_disable_unprepare(host->clk);
  1294. return err;
  1295. }
  1296. static int mxcnd_remove(struct platform_device *pdev)
  1297. {
  1298. struct mxc_nand_host *host = platform_get_drvdata(pdev);
  1299. platform_set_drvdata(pdev, NULL);
  1300. nand_release(&host->mtd);
  1301. return 0;
  1302. }
  1303. static struct platform_driver mxcnd_driver = {
  1304. .driver = {
  1305. .name = DRIVER_NAME,
  1306. .owner = THIS_MODULE,
  1307. .of_match_table = of_match_ptr(mxcnd_dt_ids),
  1308. },
  1309. .id_table = mxcnd_devtype,
  1310. .probe = mxcnd_probe,
  1311. .remove = mxcnd_remove,
  1312. };
  1313. module_platform_driver(mxcnd_driver);
  1314. MODULE_AUTHOR("Freescale Semiconductor, Inc.");
  1315. MODULE_DESCRIPTION("MXC NAND MTD driver");
  1316. MODULE_LICENSE("GPL");