vexpress-sysreg.c 12 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License version 2 as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * Copyright (C) 2012 ARM Limited
  12. */
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/io.h>
  16. #include <linux/leds.h>
  17. #include <linux/of_address.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regulator/driver.h>
  20. #include <linux/slab.h>
  21. #include <linux/stat.h>
  22. #include <linux/timer.h>
  23. #include <linux/vexpress.h>
  24. #define SYS_ID 0x000
  25. #define SYS_SW 0x004
  26. #define SYS_LED 0x008
  27. #define SYS_100HZ 0x024
  28. #define SYS_FLAGS 0x030
  29. #define SYS_FLAGSSET 0x030
  30. #define SYS_FLAGSCLR 0x034
  31. #define SYS_NVFLAGS 0x038
  32. #define SYS_NVFLAGSSET 0x038
  33. #define SYS_NVFLAGSCLR 0x03c
  34. #define SYS_MCI 0x048
  35. #define SYS_FLASH 0x04c
  36. #define SYS_CFGSW 0x058
  37. #define SYS_24MHZ 0x05c
  38. #define SYS_MISC 0x060
  39. #define SYS_DMA 0x064
  40. #define SYS_PROCID0 0x084
  41. #define SYS_PROCID1 0x088
  42. #define SYS_CFGDATA 0x0a0
  43. #define SYS_CFGCTRL 0x0a4
  44. #define SYS_CFGSTAT 0x0a8
  45. #define SYS_HBI_MASK 0xfff
  46. #define SYS_ID_HBI_SHIFT 16
  47. #define SYS_PROCIDx_HBI_SHIFT 0
  48. #define SYS_MCI_CARDIN (1 << 0)
  49. #define SYS_MCI_WPROT (1 << 1)
  50. #define SYS_FLASH_WPn (1 << 0)
  51. #define SYS_MISC_MASTERSITE (1 << 14)
  52. #define SYS_CFGCTRL_START (1 << 31)
  53. #define SYS_CFGCTRL_WRITE (1 << 30)
  54. #define SYS_CFGCTRL_DCC(n) (((n) & 0xf) << 26)
  55. #define SYS_CFGCTRL_FUNC(n) (((n) & 0x3f) << 20)
  56. #define SYS_CFGCTRL_SITE(n) (((n) & 0x3) << 16)
  57. #define SYS_CFGCTRL_POSITION(n) (((n) & 0xf) << 12)
  58. #define SYS_CFGCTRL_DEVICE(n) (((n) & 0xfff) << 0)
  59. #define SYS_CFGSTAT_ERR (1 << 1)
  60. #define SYS_CFGSTAT_COMPLETE (1 << 0)
  61. static void __iomem *vexpress_sysreg_base;
  62. static struct device *vexpress_sysreg_dev;
  63. static int vexpress_master_site;
  64. void vexpress_flags_set(u32 data)
  65. {
  66. writel(~0, vexpress_sysreg_base + SYS_FLAGSCLR);
  67. writel(data, vexpress_sysreg_base + SYS_FLAGSSET);
  68. }
  69. u32 vexpress_get_procid(int site)
  70. {
  71. if (site == VEXPRESS_SITE_MASTER)
  72. site = vexpress_master_site;
  73. return readl(vexpress_sysreg_base + (site == VEXPRESS_SITE_DB1 ?
  74. SYS_PROCID0 : SYS_PROCID1));
  75. }
  76. u32 vexpress_get_hbi(int site)
  77. {
  78. u32 id;
  79. switch (site) {
  80. case VEXPRESS_SITE_MB:
  81. id = readl(vexpress_sysreg_base + SYS_ID);
  82. return (id >> SYS_ID_HBI_SHIFT) & SYS_HBI_MASK;
  83. case VEXPRESS_SITE_MASTER:
  84. case VEXPRESS_SITE_DB1:
  85. case VEXPRESS_SITE_DB2:
  86. id = vexpress_get_procid(site);
  87. return (id >> SYS_PROCIDx_HBI_SHIFT) & SYS_HBI_MASK;
  88. }
  89. return ~0;
  90. }
  91. void __iomem *vexpress_get_24mhz_clock_base(void)
  92. {
  93. return vexpress_sysreg_base + SYS_24MHZ;
  94. }
  95. static void vexpress_sysreg_find_prop(struct device_node *node,
  96. const char *name, u32 *val)
  97. {
  98. of_node_get(node);
  99. while (node) {
  100. if (of_property_read_u32(node, name, val) == 0) {
  101. of_node_put(node);
  102. return;
  103. }
  104. node = of_get_next_parent(node);
  105. }
  106. }
  107. unsigned __vexpress_get_site(struct device *dev, struct device_node *node)
  108. {
  109. u32 site = 0;
  110. WARN_ON(dev && node && dev->of_node != node);
  111. if (dev && !node)
  112. node = dev->of_node;
  113. if (node) {
  114. vexpress_sysreg_find_prop(node, "arm,vexpress,site", &site);
  115. } else if (dev && dev->bus == &platform_bus_type) {
  116. struct platform_device *pdev = to_platform_device(dev);
  117. if (pdev->num_resources == 1 &&
  118. pdev->resource[0].flags == IORESOURCE_BUS)
  119. site = pdev->resource[0].start;
  120. } else if (dev && strncmp(dev_name(dev), "ct:", 3) == 0) {
  121. site = VEXPRESS_SITE_MASTER;
  122. }
  123. if (site == VEXPRESS_SITE_MASTER)
  124. site = vexpress_master_site;
  125. return site;
  126. }
  127. struct vexpress_sysreg_config_func {
  128. u32 template;
  129. u32 device;
  130. };
  131. static struct vexpress_config_bridge *vexpress_sysreg_config_bridge;
  132. static struct timer_list vexpress_sysreg_config_timer;
  133. static u32 *vexpress_sysreg_config_data;
  134. static int vexpress_sysreg_config_tries;
  135. static void *vexpress_sysreg_config_func_get(struct device *dev,
  136. struct device_node *node)
  137. {
  138. struct vexpress_sysreg_config_func *config_func;
  139. u32 site;
  140. u32 position = 0;
  141. u32 dcc = 0;
  142. u32 func_device[2];
  143. int err = -EFAULT;
  144. if (node) {
  145. of_node_get(node);
  146. vexpress_sysreg_find_prop(node, "arm,vexpress,site", &site);
  147. vexpress_sysreg_find_prop(node, "arm,vexpress,position",
  148. &position);
  149. vexpress_sysreg_find_prop(node, "arm,vexpress,dcc", &dcc);
  150. err = of_property_read_u32_array(node,
  151. "arm,vexpress-sysreg,func", func_device,
  152. ARRAY_SIZE(func_device));
  153. of_node_put(node);
  154. } else if (dev && dev->bus == &platform_bus_type) {
  155. struct platform_device *pdev = to_platform_device(dev);
  156. if (pdev->num_resources == 1 &&
  157. pdev->resource[0].flags == IORESOURCE_BUS) {
  158. site = pdev->resource[0].start;
  159. func_device[0] = pdev->resource[0].end;
  160. func_device[1] = pdev->id;
  161. err = 0;
  162. }
  163. }
  164. if (err)
  165. return NULL;
  166. config_func = kzalloc(sizeof(*config_func), GFP_KERNEL);
  167. if (!config_func)
  168. return NULL;
  169. config_func->template = SYS_CFGCTRL_DCC(dcc);
  170. config_func->template |= SYS_CFGCTRL_FUNC(func_device[0]);
  171. config_func->template |= SYS_CFGCTRL_SITE(site == VEXPRESS_SITE_MASTER ?
  172. vexpress_master_site : site);
  173. config_func->template |= SYS_CFGCTRL_POSITION(position);
  174. config_func->device |= func_device[1];
  175. dev_dbg(vexpress_sysreg_dev, "func 0x%p = 0x%x, %d\n", config_func,
  176. config_func->template, config_func->device);
  177. return config_func;
  178. }
  179. static void vexpress_sysreg_config_func_put(void *func)
  180. {
  181. kfree(func);
  182. }
  183. static int vexpress_sysreg_config_func_exec(void *func, int offset,
  184. bool write, u32 *data)
  185. {
  186. int status;
  187. struct vexpress_sysreg_config_func *config_func = func;
  188. u32 command;
  189. if (WARN_ON(!vexpress_sysreg_base))
  190. return -ENOENT;
  191. command = readl(vexpress_sysreg_base + SYS_CFGCTRL);
  192. if (WARN_ON(command & SYS_CFGCTRL_START))
  193. return -EBUSY;
  194. command = SYS_CFGCTRL_START;
  195. command |= write ? SYS_CFGCTRL_WRITE : 0;
  196. command |= config_func->template;
  197. command |= SYS_CFGCTRL_DEVICE(config_func->device + offset);
  198. /* Use a canary for reads */
  199. if (!write)
  200. *data = 0xdeadbeef;
  201. dev_dbg(vexpress_sysreg_dev, "command %x, data %x\n",
  202. command, *data);
  203. writel(*data, vexpress_sysreg_base + SYS_CFGDATA);
  204. writel(0, vexpress_sysreg_base + SYS_CFGSTAT);
  205. writel(command, vexpress_sysreg_base + SYS_CFGCTRL);
  206. mb();
  207. if (vexpress_sysreg_dev) {
  208. /* Schedule completion check */
  209. if (!write)
  210. vexpress_sysreg_config_data = data;
  211. vexpress_sysreg_config_tries = 100;
  212. mod_timer(&vexpress_sysreg_config_timer,
  213. jiffies + usecs_to_jiffies(100));
  214. status = VEXPRESS_CONFIG_STATUS_WAIT;
  215. } else {
  216. /* Early execution, no timer available, have to spin */
  217. u32 cfgstat;
  218. do {
  219. cpu_relax();
  220. cfgstat = readl(vexpress_sysreg_base + SYS_CFGSTAT);
  221. } while (!cfgstat);
  222. if (!write && (cfgstat & SYS_CFGSTAT_COMPLETE))
  223. *data = readl(vexpress_sysreg_base + SYS_CFGDATA);
  224. status = VEXPRESS_CONFIG_STATUS_DONE;
  225. if (cfgstat & SYS_CFGSTAT_ERR)
  226. status = -EINVAL;
  227. }
  228. return status;
  229. }
  230. struct vexpress_config_bridge_info vexpress_sysreg_config_bridge_info = {
  231. .name = "vexpress-sysreg",
  232. .func_get = vexpress_sysreg_config_func_get,
  233. .func_put = vexpress_sysreg_config_func_put,
  234. .func_exec = vexpress_sysreg_config_func_exec,
  235. };
  236. static void vexpress_sysreg_config_complete(unsigned long data)
  237. {
  238. int status = VEXPRESS_CONFIG_STATUS_DONE;
  239. u32 cfgstat = readl(vexpress_sysreg_base + SYS_CFGSTAT);
  240. if (cfgstat & SYS_CFGSTAT_ERR)
  241. status = -EINVAL;
  242. if (!vexpress_sysreg_config_tries--)
  243. status = -ETIMEDOUT;
  244. if (status < 0) {
  245. dev_err(vexpress_sysreg_dev, "error %d\n", status);
  246. } else if (!(cfgstat & SYS_CFGSTAT_COMPLETE)) {
  247. mod_timer(&vexpress_sysreg_config_timer,
  248. jiffies + usecs_to_jiffies(50));
  249. return;
  250. }
  251. if (vexpress_sysreg_config_data) {
  252. *vexpress_sysreg_config_data = readl(vexpress_sysreg_base +
  253. SYS_CFGDATA);
  254. dev_dbg(vexpress_sysreg_dev, "read data %x\n",
  255. *vexpress_sysreg_config_data);
  256. vexpress_sysreg_config_data = NULL;
  257. }
  258. vexpress_config_complete(vexpress_sysreg_config_bridge, status);
  259. }
  260. void __init vexpress_sysreg_early_init(void __iomem *base)
  261. {
  262. struct device_node *node = of_find_compatible_node(NULL, NULL,
  263. "arm,vexpress-sysreg");
  264. if (node)
  265. base = of_iomap(node, 0);
  266. if (WARN_ON(!base))
  267. return;
  268. vexpress_sysreg_base = base;
  269. if (readl(vexpress_sysreg_base + SYS_MISC) & SYS_MISC_MASTERSITE)
  270. vexpress_master_site = VEXPRESS_SITE_DB2;
  271. else
  272. vexpress_master_site = VEXPRESS_SITE_DB1;
  273. vexpress_sysreg_config_bridge = vexpress_config_bridge_register(
  274. node, &vexpress_sysreg_config_bridge_info);
  275. WARN_ON(!vexpress_sysreg_config_bridge);
  276. }
  277. void __init vexpress_sysreg_of_early_init(void)
  278. {
  279. vexpress_sysreg_early_init(NULL);
  280. }
  281. static struct vexpress_sysreg_gpio {
  282. unsigned long reg;
  283. u32 value;
  284. } vexpress_sysreg_gpios[] = {
  285. [VEXPRESS_GPIO_MMC_CARDIN] = {
  286. .reg = SYS_MCI,
  287. .value = SYS_MCI_CARDIN,
  288. },
  289. [VEXPRESS_GPIO_MMC_WPROT] = {
  290. .reg = SYS_MCI,
  291. .value = SYS_MCI_WPROT,
  292. },
  293. [VEXPRESS_GPIO_FLASH_WPn] = {
  294. .reg = SYS_FLASH,
  295. .value = SYS_FLASH_WPn,
  296. },
  297. };
  298. static int vexpress_sysreg_gpio_direction_input(struct gpio_chip *chip,
  299. unsigned offset)
  300. {
  301. return 0;
  302. }
  303. static int vexpress_sysreg_gpio_direction_output(struct gpio_chip *chip,
  304. unsigned offset, int value)
  305. {
  306. return 0;
  307. }
  308. static int vexpress_sysreg_gpio_get(struct gpio_chip *chip,
  309. unsigned offset)
  310. {
  311. struct vexpress_sysreg_gpio *gpio = &vexpress_sysreg_gpios[offset];
  312. u32 reg_value = readl(vexpress_sysreg_base + gpio->reg);
  313. return !!(reg_value & gpio->value);
  314. }
  315. static void vexpress_sysreg_gpio_set(struct gpio_chip *chip,
  316. unsigned offset, int value)
  317. {
  318. struct vexpress_sysreg_gpio *gpio = &vexpress_sysreg_gpios[offset];
  319. u32 reg_value = readl(vexpress_sysreg_base + gpio->reg);
  320. if (value)
  321. reg_value |= gpio->value;
  322. else
  323. reg_value &= ~gpio->value;
  324. writel(reg_value, vexpress_sysreg_base + gpio->reg);
  325. }
  326. static struct gpio_chip vexpress_sysreg_gpio_chip = {
  327. .label = "vexpress-sysreg",
  328. .direction_input = vexpress_sysreg_gpio_direction_input,
  329. .direction_output = vexpress_sysreg_gpio_direction_output,
  330. .get = vexpress_sysreg_gpio_get,
  331. .set = vexpress_sysreg_gpio_set,
  332. .ngpio = ARRAY_SIZE(vexpress_sysreg_gpios),
  333. .base = 0,
  334. };
  335. static ssize_t vexpress_sysreg_sys_id_show(struct device *dev,
  336. struct device_attribute *attr, char *buf)
  337. {
  338. return sprintf(buf, "0x%08x\n", readl(vexpress_sysreg_base + SYS_ID));
  339. }
  340. DEVICE_ATTR(sys_id, S_IRUGO, vexpress_sysreg_sys_id_show, NULL);
  341. static int vexpress_sysreg_probe(struct platform_device *pdev)
  342. {
  343. int err;
  344. struct resource *res = platform_get_resource(pdev,
  345. IORESOURCE_MEM, 0);
  346. if (!devm_request_mem_region(&pdev->dev, res->start,
  347. resource_size(res), pdev->name)) {
  348. dev_err(&pdev->dev, "Failed to request memory region!\n");
  349. return -EBUSY;
  350. }
  351. if (!vexpress_sysreg_base)
  352. vexpress_sysreg_base = devm_ioremap(&pdev->dev, res->start,
  353. resource_size(res));
  354. if (!vexpress_sysreg_base) {
  355. dev_err(&pdev->dev, "Failed to obtain base address!\n");
  356. return -EFAULT;
  357. }
  358. setup_timer(&vexpress_sysreg_config_timer,
  359. vexpress_sysreg_config_complete, 0);
  360. vexpress_sysreg_gpio_chip.dev = &pdev->dev;
  361. err = gpiochip_add(&vexpress_sysreg_gpio_chip);
  362. if (err) {
  363. vexpress_config_bridge_unregister(
  364. vexpress_sysreg_config_bridge);
  365. dev_err(&pdev->dev, "Failed to register GPIO chip! (%d)\n",
  366. err);
  367. return err;
  368. }
  369. vexpress_sysreg_dev = &pdev->dev;
  370. device_create_file(vexpress_sysreg_dev, &dev_attr_sys_id);
  371. return 0;
  372. }
  373. static const struct of_device_id vexpress_sysreg_match[] = {
  374. { .compatible = "arm,vexpress-sysreg", },
  375. {},
  376. };
  377. static struct platform_driver vexpress_sysreg_driver = {
  378. .driver = {
  379. .name = "vexpress-sysreg",
  380. .of_match_table = vexpress_sysreg_match,
  381. },
  382. .probe = vexpress_sysreg_probe,
  383. };
  384. static int __init vexpress_sysreg_init(void)
  385. {
  386. return platform_driver_register(&vexpress_sysreg_driver);
  387. }
  388. core_initcall(vexpress_sysreg_init);