ab8500-core.c 35 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com>
  7. * Author: Mattias Wallin <mattias.wallin@stericsson.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/irqdomain.h>
  14. #include <linux/delay.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/mfd/core.h>
  19. #include <linux/mfd/abx500.h>
  20. #include <linux/mfd/abx500/ab8500.h>
  21. #include <linux/mfd/dbx500-prcmu.h>
  22. #include <linux/regulator/ab8500.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. /*
  26. * Interrupt register offsets
  27. * Bank : 0x0E
  28. */
  29. #define AB8500_IT_SOURCE1_REG 0x00
  30. #define AB8500_IT_SOURCE2_REG 0x01
  31. #define AB8500_IT_SOURCE3_REG 0x02
  32. #define AB8500_IT_SOURCE4_REG 0x03
  33. #define AB8500_IT_SOURCE5_REG 0x04
  34. #define AB8500_IT_SOURCE6_REG 0x05
  35. #define AB8500_IT_SOURCE7_REG 0x06
  36. #define AB8500_IT_SOURCE8_REG 0x07
  37. #define AB9540_IT_SOURCE13_REG 0x0C
  38. #define AB8500_IT_SOURCE19_REG 0x12
  39. #define AB8500_IT_SOURCE20_REG 0x13
  40. #define AB8500_IT_SOURCE21_REG 0x14
  41. #define AB8500_IT_SOURCE22_REG 0x15
  42. #define AB8500_IT_SOURCE23_REG 0x16
  43. #define AB8500_IT_SOURCE24_REG 0x17
  44. /*
  45. * latch registers
  46. */
  47. #define AB8500_IT_LATCH1_REG 0x20
  48. #define AB8500_IT_LATCH2_REG 0x21
  49. #define AB8500_IT_LATCH3_REG 0x22
  50. #define AB8500_IT_LATCH4_REG 0x23
  51. #define AB8500_IT_LATCH5_REG 0x24
  52. #define AB8500_IT_LATCH6_REG 0x25
  53. #define AB8500_IT_LATCH7_REG 0x26
  54. #define AB8500_IT_LATCH8_REG 0x27
  55. #define AB8500_IT_LATCH9_REG 0x28
  56. #define AB8500_IT_LATCH10_REG 0x29
  57. #define AB8500_IT_LATCH12_REG 0x2B
  58. #define AB9540_IT_LATCH13_REG 0x2C
  59. #define AB8500_IT_LATCH19_REG 0x32
  60. #define AB8500_IT_LATCH20_REG 0x33
  61. #define AB8500_IT_LATCH21_REG 0x34
  62. #define AB8500_IT_LATCH22_REG 0x35
  63. #define AB8500_IT_LATCH23_REG 0x36
  64. #define AB8500_IT_LATCH24_REG 0x37
  65. /*
  66. * mask registers
  67. */
  68. #define AB8500_IT_MASK1_REG 0x40
  69. #define AB8500_IT_MASK2_REG 0x41
  70. #define AB8500_IT_MASK3_REG 0x42
  71. #define AB8500_IT_MASK4_REG 0x43
  72. #define AB8500_IT_MASK5_REG 0x44
  73. #define AB8500_IT_MASK6_REG 0x45
  74. #define AB8500_IT_MASK7_REG 0x46
  75. #define AB8500_IT_MASK8_REG 0x47
  76. #define AB8500_IT_MASK9_REG 0x48
  77. #define AB8500_IT_MASK10_REG 0x49
  78. #define AB8500_IT_MASK11_REG 0x4A
  79. #define AB8500_IT_MASK12_REG 0x4B
  80. #define AB8500_IT_MASK13_REG 0x4C
  81. #define AB8500_IT_MASK14_REG 0x4D
  82. #define AB8500_IT_MASK15_REG 0x4E
  83. #define AB8500_IT_MASK16_REG 0x4F
  84. #define AB8500_IT_MASK17_REG 0x50
  85. #define AB8500_IT_MASK18_REG 0x51
  86. #define AB8500_IT_MASK19_REG 0x52
  87. #define AB8500_IT_MASK20_REG 0x53
  88. #define AB8500_IT_MASK21_REG 0x54
  89. #define AB8500_IT_MASK22_REG 0x55
  90. #define AB8500_IT_MASK23_REG 0x56
  91. #define AB8500_IT_MASK24_REG 0x57
  92. /*
  93. * latch hierarchy registers
  94. */
  95. #define AB8500_IT_LATCHHIER1_REG 0x60
  96. #define AB8500_IT_LATCHHIER2_REG 0x61
  97. #define AB8500_IT_LATCHHIER3_REG 0x62
  98. #define AB8500_IT_LATCHHIER_NUM 3
  99. #define AB8500_REV_REG 0x80
  100. #define AB8500_IC_NAME_REG 0x82
  101. #define AB8500_SWITCH_OFF_STATUS 0x00
  102. #define AB8500_TURN_ON_STATUS 0x00
  103. static bool no_bm; /* No battery management */
  104. module_param(no_bm, bool, S_IRUGO);
  105. #define AB9540_MODEM_CTRL2_REG 0x23
  106. #define AB9540_MODEM_CTRL2_SWDBBRSTN_BIT BIT(2)
  107. /*
  108. * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  109. * numbers are indexed into this array with (num / 8). The interupts are
  110. * defined in linux/mfd/ab8500.h
  111. *
  112. * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
  113. * offset 0.
  114. */
  115. /* AB8500 support */
  116. static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
  117. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
  118. };
  119. /* AB9540 support */
  120. static const int ab9540_irq_regoffset[AB9540_NUM_IRQ_REGS] = {
  121. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21, 12, 13, 24,
  122. };
  123. static const char ab8500_version_str[][7] = {
  124. [AB8500_VERSION_AB8500] = "AB8500",
  125. [AB8500_VERSION_AB8505] = "AB8505",
  126. [AB8500_VERSION_AB9540] = "AB9540",
  127. [AB8500_VERSION_AB8540] = "AB8540",
  128. };
  129. static int ab8500_prcmu_write(struct ab8500 *ab8500, u16 addr, u8 data)
  130. {
  131. int ret;
  132. ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
  133. if (ret < 0)
  134. dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
  135. return ret;
  136. }
  137. static int ab8500_prcmu_write_masked(struct ab8500 *ab8500, u16 addr, u8 mask,
  138. u8 data)
  139. {
  140. int ret;
  141. ret = prcmu_abb_write_masked((u8)(addr >> 8), (u8)(addr & 0xFF), &data,
  142. &mask, 1);
  143. if (ret < 0)
  144. dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
  145. return ret;
  146. }
  147. static int ab8500_prcmu_read(struct ab8500 *ab8500, u16 addr)
  148. {
  149. int ret;
  150. u8 data;
  151. ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
  152. if (ret < 0) {
  153. dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
  154. return ret;
  155. }
  156. return (int)data;
  157. }
  158. static int ab8500_get_chip_id(struct device *dev)
  159. {
  160. struct ab8500 *ab8500;
  161. if (!dev)
  162. return -EINVAL;
  163. ab8500 = dev_get_drvdata(dev->parent);
  164. return ab8500 ? (int)ab8500->chip_id : -EINVAL;
  165. }
  166. static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  167. u8 reg, u8 data)
  168. {
  169. int ret;
  170. /*
  171. * Put the u8 bank and u8 register together into a an u16.
  172. * The bank on higher 8 bits and register in lower 8 bits.
  173. * */
  174. u16 addr = ((u16)bank) << 8 | reg;
  175. dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
  176. mutex_lock(&ab8500->lock);
  177. ret = ab8500->write(ab8500, addr, data);
  178. if (ret < 0)
  179. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  180. addr, ret);
  181. mutex_unlock(&ab8500->lock);
  182. return ret;
  183. }
  184. static int ab8500_set_register(struct device *dev, u8 bank,
  185. u8 reg, u8 value)
  186. {
  187. int ret;
  188. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  189. atomic_inc(&ab8500->transfer_ongoing);
  190. ret = set_register_interruptible(ab8500, bank, reg, value);
  191. atomic_dec(&ab8500->transfer_ongoing);
  192. return ret;
  193. }
  194. static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
  195. u8 reg, u8 *value)
  196. {
  197. int ret;
  198. /* put the u8 bank and u8 reg together into a an u16.
  199. * bank on higher 8 bits and reg in lower */
  200. u16 addr = ((u16)bank) << 8 | reg;
  201. mutex_lock(&ab8500->lock);
  202. ret = ab8500->read(ab8500, addr);
  203. if (ret < 0)
  204. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  205. addr, ret);
  206. else
  207. *value = ret;
  208. mutex_unlock(&ab8500->lock);
  209. dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
  210. return ret;
  211. }
  212. static int ab8500_get_register(struct device *dev, u8 bank,
  213. u8 reg, u8 *value)
  214. {
  215. int ret;
  216. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  217. atomic_inc(&ab8500->transfer_ongoing);
  218. ret = get_register_interruptible(ab8500, bank, reg, value);
  219. atomic_dec(&ab8500->transfer_ongoing);
  220. return ret;
  221. }
  222. static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  223. u8 reg, u8 bitmask, u8 bitvalues)
  224. {
  225. int ret;
  226. /* put the u8 bank and u8 reg together into a an u16.
  227. * bank on higher 8 bits and reg in lower */
  228. u16 addr = ((u16)bank) << 8 | reg;
  229. mutex_lock(&ab8500->lock);
  230. if (ab8500->write_masked == NULL) {
  231. u8 data;
  232. ret = ab8500->read(ab8500, addr);
  233. if (ret < 0) {
  234. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  235. addr, ret);
  236. goto out;
  237. }
  238. data = (u8)ret;
  239. data = (~bitmask & data) | (bitmask & bitvalues);
  240. ret = ab8500->write(ab8500, addr, data);
  241. if (ret < 0)
  242. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  243. addr, ret);
  244. dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr,
  245. data);
  246. goto out;
  247. }
  248. ret = ab8500->write_masked(ab8500, addr, bitmask, bitvalues);
  249. if (ret < 0)
  250. dev_err(ab8500->dev, "failed to modify reg %#x: %d\n", addr,
  251. ret);
  252. out:
  253. mutex_unlock(&ab8500->lock);
  254. return ret;
  255. }
  256. static int ab8500_mask_and_set_register(struct device *dev,
  257. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  258. {
  259. int ret;
  260. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  261. atomic_inc(&ab8500->transfer_ongoing);
  262. ret= mask_and_set_register_interruptible(ab8500, bank, reg,
  263. bitmask, bitvalues);
  264. atomic_dec(&ab8500->transfer_ongoing);
  265. return ret;
  266. }
  267. static struct abx500_ops ab8500_ops = {
  268. .get_chip_id = ab8500_get_chip_id,
  269. .get_register = ab8500_get_register,
  270. .set_register = ab8500_set_register,
  271. .get_register_page = NULL,
  272. .set_register_page = NULL,
  273. .mask_and_set_register = ab8500_mask_and_set_register,
  274. .event_registers_startup_state_get = NULL,
  275. .startup_irq_enabled = NULL,
  276. };
  277. static void ab8500_irq_lock(struct irq_data *data)
  278. {
  279. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  280. mutex_lock(&ab8500->irq_lock);
  281. atomic_inc(&ab8500->transfer_ongoing);
  282. }
  283. static void ab8500_irq_sync_unlock(struct irq_data *data)
  284. {
  285. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  286. int i;
  287. for (i = 0; i < ab8500->mask_size; i++) {
  288. u8 old = ab8500->oldmask[i];
  289. u8 new = ab8500->mask[i];
  290. int reg;
  291. if (new == old)
  292. continue;
  293. /*
  294. * Interrupt register 12 doesn't exist prior to AB8500 version
  295. * 2.0
  296. */
  297. if (ab8500->irq_reg_offset[i] == 11 &&
  298. is_ab8500_1p1_or_earlier(ab8500))
  299. continue;
  300. ab8500->oldmask[i] = new;
  301. reg = AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i];
  302. set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
  303. }
  304. atomic_dec(&ab8500->transfer_ongoing);
  305. mutex_unlock(&ab8500->irq_lock);
  306. }
  307. static void ab8500_irq_mask(struct irq_data *data)
  308. {
  309. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  310. int offset = data->hwirq;
  311. int index = offset / 8;
  312. int mask = 1 << (offset % 8);
  313. ab8500->mask[index] |= mask;
  314. }
  315. static void ab8500_irq_unmask(struct irq_data *data)
  316. {
  317. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  318. int offset = data->hwirq;
  319. int index = offset / 8;
  320. int mask = 1 << (offset % 8);
  321. ab8500->mask[index] &= ~mask;
  322. }
  323. static struct irq_chip ab8500_irq_chip = {
  324. .name = "ab8500",
  325. .irq_bus_lock = ab8500_irq_lock,
  326. .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
  327. .irq_mask = ab8500_irq_mask,
  328. .irq_disable = ab8500_irq_mask,
  329. .irq_unmask = ab8500_irq_unmask,
  330. };
  331. static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500,
  332. int latch_offset, u8 latch_val)
  333. {
  334. int int_bit = __ffs(latch_val);
  335. int line, i;
  336. do {
  337. int_bit = __ffs(latch_val);
  338. for (i = 0; i < ab8500->mask_size; i++)
  339. if (ab8500->irq_reg_offset[i] == latch_offset)
  340. break;
  341. if (i >= ab8500->mask_size) {
  342. dev_err(ab8500->dev, "Register offset 0x%2x not declared\n",
  343. latch_offset);
  344. return -ENXIO;
  345. }
  346. line = (i << 3) + int_bit;
  347. latch_val &= ~(1 << int_bit);
  348. handle_nested_irq(ab8500->irq_base + line);
  349. } while (latch_val);
  350. return 0;
  351. }
  352. static int ab8500_handle_hierarchical_latch(struct ab8500 *ab8500,
  353. int hier_offset, u8 hier_val)
  354. {
  355. int latch_bit, status;
  356. u8 latch_offset, latch_val;
  357. do {
  358. latch_bit = __ffs(hier_val);
  359. latch_offset = (hier_offset << 3) + latch_bit;
  360. /* Fix inconsistent ITFromLatch25 bit mapping... */
  361. if (unlikely(latch_offset == 17))
  362. latch_offset = 24;
  363. status = get_register_interruptible(ab8500,
  364. AB8500_INTERRUPT,
  365. AB8500_IT_LATCH1_REG + latch_offset,
  366. &latch_val);
  367. if (status < 0 || latch_val == 0)
  368. goto discard;
  369. status = ab8500_handle_hierarchical_line(ab8500,
  370. latch_offset, latch_val);
  371. if (status < 0)
  372. return status;
  373. discard:
  374. hier_val &= ~(1 << latch_bit);
  375. } while (hier_val);
  376. return 0;
  377. }
  378. static irqreturn_t ab8500_hierarchical_irq(int irq, void *dev)
  379. {
  380. struct ab8500 *ab8500 = dev;
  381. u8 i;
  382. dev_vdbg(ab8500->dev, "interrupt\n");
  383. /* Hierarchical interrupt version */
  384. for (i = 0; i < AB8500_IT_LATCHHIER_NUM; i++) {
  385. int status;
  386. u8 hier_val;
  387. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  388. AB8500_IT_LATCHHIER1_REG + i, &hier_val);
  389. if (status < 0 || hier_val == 0)
  390. continue;
  391. status = ab8500_handle_hierarchical_latch(ab8500, i, hier_val);
  392. if (status < 0)
  393. break;
  394. }
  395. return IRQ_HANDLED;
  396. }
  397. /**
  398. * ab8500_irq_get_virq(): Map an interrupt on a chip to a virtual IRQ
  399. *
  400. * @ab8500: ab8500_irq controller to operate on.
  401. * @irq: index of the interrupt requested in the chip IRQs
  402. *
  403. * Useful for drivers to request their own IRQs.
  404. */
  405. static int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq)
  406. {
  407. if (!ab8500)
  408. return -EINVAL;
  409. return irq_create_mapping(ab8500->domain, irq);
  410. }
  411. static irqreturn_t ab8500_irq(int irq, void *dev)
  412. {
  413. struct ab8500 *ab8500 = dev;
  414. int i;
  415. dev_vdbg(ab8500->dev, "interrupt\n");
  416. atomic_inc(&ab8500->transfer_ongoing);
  417. for (i = 0; i < ab8500->mask_size; i++) {
  418. int regoffset = ab8500->irq_reg_offset[i];
  419. int status;
  420. u8 value;
  421. /*
  422. * Interrupt register 12 doesn't exist prior to AB8500 version
  423. * 2.0
  424. */
  425. if (regoffset == 11 && is_ab8500_1p1_or_earlier(ab8500))
  426. continue;
  427. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  428. AB8500_IT_LATCH1_REG + regoffset, &value);
  429. if (status < 0 || value == 0)
  430. continue;
  431. do {
  432. int bit = __ffs(value);
  433. int line = i * 8 + bit;
  434. int virq = ab8500_irq_get_virq(ab8500, line);
  435. handle_nested_irq(virq);
  436. value &= ~(1 << bit);
  437. } while (value);
  438. }
  439. atomic_dec(&ab8500->transfer_ongoing);
  440. return IRQ_HANDLED;
  441. }
  442. static int ab8500_irq_map(struct irq_domain *d, unsigned int virq,
  443. irq_hw_number_t hwirq)
  444. {
  445. struct ab8500 *ab8500 = d->host_data;
  446. if (!ab8500)
  447. return -EINVAL;
  448. irq_set_chip_data(virq, ab8500);
  449. irq_set_chip_and_handler(virq, &ab8500_irq_chip,
  450. handle_simple_irq);
  451. irq_set_nested_thread(virq, 1);
  452. #ifdef CONFIG_ARM
  453. set_irq_flags(virq, IRQF_VALID);
  454. #else
  455. irq_set_noprobe(virq);
  456. #endif
  457. return 0;
  458. }
  459. static struct irq_domain_ops ab8500_irq_ops = {
  460. .map = ab8500_irq_map,
  461. .xlate = irq_domain_xlate_twocell,
  462. };
  463. static int ab8500_irq_init(struct ab8500 *ab8500, struct device_node *np)
  464. {
  465. int num_irqs;
  466. if (is_ab9540(ab8500))
  467. num_irqs = AB9540_NR_IRQS;
  468. else if (is_ab8505(ab8500))
  469. num_irqs = AB8505_NR_IRQS;
  470. else
  471. num_irqs = AB8500_NR_IRQS;
  472. /* If ->irq_base is zero this will give a linear mapping */
  473. ab8500->domain = irq_domain_add_simple(NULL,
  474. num_irqs, ab8500->irq_base,
  475. &ab8500_irq_ops, ab8500);
  476. if (!ab8500->domain) {
  477. dev_err(ab8500->dev, "Failed to create irqdomain\n");
  478. return -ENOSYS;
  479. }
  480. return 0;
  481. }
  482. int ab8500_suspend(struct ab8500 *ab8500)
  483. {
  484. if (atomic_read(&ab8500->transfer_ongoing))
  485. return -EINVAL;
  486. else
  487. return 0;
  488. }
  489. static struct resource ab8500_gpadc_resources[] = {
  490. {
  491. .name = "HW_CONV_END",
  492. .start = AB8500_INT_GP_HW_ADC_CONV_END,
  493. .end = AB8500_INT_GP_HW_ADC_CONV_END,
  494. .flags = IORESOURCE_IRQ,
  495. },
  496. {
  497. .name = "SW_CONV_END",
  498. .start = AB8500_INT_GP_SW_ADC_CONV_END,
  499. .end = AB8500_INT_GP_SW_ADC_CONV_END,
  500. .flags = IORESOURCE_IRQ,
  501. },
  502. };
  503. static struct resource ab8500_rtc_resources[] = {
  504. {
  505. .name = "60S",
  506. .start = AB8500_INT_RTC_60S,
  507. .end = AB8500_INT_RTC_60S,
  508. .flags = IORESOURCE_IRQ,
  509. },
  510. {
  511. .name = "ALARM",
  512. .start = AB8500_INT_RTC_ALARM,
  513. .end = AB8500_INT_RTC_ALARM,
  514. .flags = IORESOURCE_IRQ,
  515. },
  516. };
  517. static struct resource ab8500_poweronkey_db_resources[] = {
  518. {
  519. .name = "ONKEY_DBF",
  520. .start = AB8500_INT_PON_KEY1DB_F,
  521. .end = AB8500_INT_PON_KEY1DB_F,
  522. .flags = IORESOURCE_IRQ,
  523. },
  524. {
  525. .name = "ONKEY_DBR",
  526. .start = AB8500_INT_PON_KEY1DB_R,
  527. .end = AB8500_INT_PON_KEY1DB_R,
  528. .flags = IORESOURCE_IRQ,
  529. },
  530. };
  531. static struct resource ab8500_av_acc_detect_resources[] = {
  532. {
  533. .name = "ACC_DETECT_1DB_F",
  534. .start = AB8500_INT_ACC_DETECT_1DB_F,
  535. .end = AB8500_INT_ACC_DETECT_1DB_F,
  536. .flags = IORESOURCE_IRQ,
  537. },
  538. {
  539. .name = "ACC_DETECT_1DB_R",
  540. .start = AB8500_INT_ACC_DETECT_1DB_R,
  541. .end = AB8500_INT_ACC_DETECT_1DB_R,
  542. .flags = IORESOURCE_IRQ,
  543. },
  544. {
  545. .name = "ACC_DETECT_21DB_F",
  546. .start = AB8500_INT_ACC_DETECT_21DB_F,
  547. .end = AB8500_INT_ACC_DETECT_21DB_F,
  548. .flags = IORESOURCE_IRQ,
  549. },
  550. {
  551. .name = "ACC_DETECT_21DB_R",
  552. .start = AB8500_INT_ACC_DETECT_21DB_R,
  553. .end = AB8500_INT_ACC_DETECT_21DB_R,
  554. .flags = IORESOURCE_IRQ,
  555. },
  556. {
  557. .name = "ACC_DETECT_22DB_F",
  558. .start = AB8500_INT_ACC_DETECT_22DB_F,
  559. .end = AB8500_INT_ACC_DETECT_22DB_F,
  560. .flags = IORESOURCE_IRQ,
  561. },
  562. {
  563. .name = "ACC_DETECT_22DB_R",
  564. .start = AB8500_INT_ACC_DETECT_22DB_R,
  565. .end = AB8500_INT_ACC_DETECT_22DB_R,
  566. .flags = IORESOURCE_IRQ,
  567. },
  568. };
  569. static struct resource ab8500_charger_resources[] = {
  570. {
  571. .name = "MAIN_CH_UNPLUG_DET",
  572. .start = AB8500_INT_MAIN_CH_UNPLUG_DET,
  573. .end = AB8500_INT_MAIN_CH_UNPLUG_DET,
  574. .flags = IORESOURCE_IRQ,
  575. },
  576. {
  577. .name = "MAIN_CHARGE_PLUG_DET",
  578. .start = AB8500_INT_MAIN_CH_PLUG_DET,
  579. .end = AB8500_INT_MAIN_CH_PLUG_DET,
  580. .flags = IORESOURCE_IRQ,
  581. },
  582. {
  583. .name = "VBUS_DET_R",
  584. .start = AB8500_INT_VBUS_DET_R,
  585. .end = AB8500_INT_VBUS_DET_R,
  586. .flags = IORESOURCE_IRQ,
  587. },
  588. {
  589. .name = "VBUS_DET_F",
  590. .start = AB8500_INT_VBUS_DET_F,
  591. .end = AB8500_INT_VBUS_DET_F,
  592. .flags = IORESOURCE_IRQ,
  593. },
  594. {
  595. .name = "USB_LINK_STATUS",
  596. .start = AB8500_INT_USB_LINK_STATUS,
  597. .end = AB8500_INT_USB_LINK_STATUS,
  598. .flags = IORESOURCE_IRQ,
  599. },
  600. {
  601. .name = "VBUS_OVV",
  602. .start = AB8500_INT_VBUS_OVV,
  603. .end = AB8500_INT_VBUS_OVV,
  604. .flags = IORESOURCE_IRQ,
  605. },
  606. {
  607. .name = "USB_CH_TH_PROT_R",
  608. .start = AB8500_INT_USB_CH_TH_PROT_R,
  609. .end = AB8500_INT_USB_CH_TH_PROT_R,
  610. .flags = IORESOURCE_IRQ,
  611. },
  612. {
  613. .name = "USB_CH_TH_PROT_F",
  614. .start = AB8500_INT_USB_CH_TH_PROT_F,
  615. .end = AB8500_INT_USB_CH_TH_PROT_F,
  616. .flags = IORESOURCE_IRQ,
  617. },
  618. {
  619. .name = "MAIN_EXT_CH_NOT_OK",
  620. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  621. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  622. .flags = IORESOURCE_IRQ,
  623. },
  624. {
  625. .name = "MAIN_CH_TH_PROT_R",
  626. .start = AB8500_INT_MAIN_CH_TH_PROT_R,
  627. .end = AB8500_INT_MAIN_CH_TH_PROT_R,
  628. .flags = IORESOURCE_IRQ,
  629. },
  630. {
  631. .name = "MAIN_CH_TH_PROT_F",
  632. .start = AB8500_INT_MAIN_CH_TH_PROT_F,
  633. .end = AB8500_INT_MAIN_CH_TH_PROT_F,
  634. .flags = IORESOURCE_IRQ,
  635. },
  636. {
  637. .name = "USB_CHARGER_NOT_OKR",
  638. .start = AB8500_INT_USB_CHARGER_NOT_OKR,
  639. .end = AB8500_INT_USB_CHARGER_NOT_OKR,
  640. .flags = IORESOURCE_IRQ,
  641. },
  642. {
  643. .name = "CH_WD_EXP",
  644. .start = AB8500_INT_CH_WD_EXP,
  645. .end = AB8500_INT_CH_WD_EXP,
  646. .flags = IORESOURCE_IRQ,
  647. },
  648. };
  649. static struct resource ab8500_btemp_resources[] = {
  650. {
  651. .name = "BAT_CTRL_INDB",
  652. .start = AB8500_INT_BAT_CTRL_INDB,
  653. .end = AB8500_INT_BAT_CTRL_INDB,
  654. .flags = IORESOURCE_IRQ,
  655. },
  656. {
  657. .name = "BTEMP_LOW",
  658. .start = AB8500_INT_BTEMP_LOW,
  659. .end = AB8500_INT_BTEMP_LOW,
  660. .flags = IORESOURCE_IRQ,
  661. },
  662. {
  663. .name = "BTEMP_HIGH",
  664. .start = AB8500_INT_BTEMP_HIGH,
  665. .end = AB8500_INT_BTEMP_HIGH,
  666. .flags = IORESOURCE_IRQ,
  667. },
  668. {
  669. .name = "BTEMP_LOW_MEDIUM",
  670. .start = AB8500_INT_BTEMP_LOW_MEDIUM,
  671. .end = AB8500_INT_BTEMP_LOW_MEDIUM,
  672. .flags = IORESOURCE_IRQ,
  673. },
  674. {
  675. .name = "BTEMP_MEDIUM_HIGH",
  676. .start = AB8500_INT_BTEMP_MEDIUM_HIGH,
  677. .end = AB8500_INT_BTEMP_MEDIUM_HIGH,
  678. .flags = IORESOURCE_IRQ,
  679. },
  680. };
  681. static struct resource ab8500_fg_resources[] = {
  682. {
  683. .name = "NCONV_ACCU",
  684. .start = AB8500_INT_CCN_CONV_ACC,
  685. .end = AB8500_INT_CCN_CONV_ACC,
  686. .flags = IORESOURCE_IRQ,
  687. },
  688. {
  689. .name = "BATT_OVV",
  690. .start = AB8500_INT_BATT_OVV,
  691. .end = AB8500_INT_BATT_OVV,
  692. .flags = IORESOURCE_IRQ,
  693. },
  694. {
  695. .name = "LOW_BAT_F",
  696. .start = AB8500_INT_LOW_BAT_F,
  697. .end = AB8500_INT_LOW_BAT_F,
  698. .flags = IORESOURCE_IRQ,
  699. },
  700. {
  701. .name = "LOW_BAT_R",
  702. .start = AB8500_INT_LOW_BAT_R,
  703. .end = AB8500_INT_LOW_BAT_R,
  704. .flags = IORESOURCE_IRQ,
  705. },
  706. {
  707. .name = "CC_INT_CALIB",
  708. .start = AB8500_INT_CC_INT_CALIB,
  709. .end = AB8500_INT_CC_INT_CALIB,
  710. .flags = IORESOURCE_IRQ,
  711. },
  712. {
  713. .name = "CCEOC",
  714. .start = AB8500_INT_CCEOC,
  715. .end = AB8500_INT_CCEOC,
  716. .flags = IORESOURCE_IRQ,
  717. },
  718. };
  719. static struct resource ab8500_chargalg_resources[] = {};
  720. #ifdef CONFIG_DEBUG_FS
  721. static struct resource ab8500_debug_resources[] = {
  722. {
  723. .name = "IRQ_FIRST",
  724. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  725. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  726. .flags = IORESOURCE_IRQ,
  727. },
  728. {
  729. .name = "IRQ_LAST",
  730. .start = AB8500_INT_XTAL32K_KO,
  731. .end = AB8500_INT_XTAL32K_KO,
  732. .flags = IORESOURCE_IRQ,
  733. },
  734. };
  735. #endif
  736. static struct resource ab8500_usb_resources[] = {
  737. {
  738. .name = "ID_WAKEUP_R",
  739. .start = AB8500_INT_ID_WAKEUP_R,
  740. .end = AB8500_INT_ID_WAKEUP_R,
  741. .flags = IORESOURCE_IRQ,
  742. },
  743. {
  744. .name = "ID_WAKEUP_F",
  745. .start = AB8500_INT_ID_WAKEUP_F,
  746. .end = AB8500_INT_ID_WAKEUP_F,
  747. .flags = IORESOURCE_IRQ,
  748. },
  749. {
  750. .name = "VBUS_DET_F",
  751. .start = AB8500_INT_VBUS_DET_F,
  752. .end = AB8500_INT_VBUS_DET_F,
  753. .flags = IORESOURCE_IRQ,
  754. },
  755. {
  756. .name = "VBUS_DET_R",
  757. .start = AB8500_INT_VBUS_DET_R,
  758. .end = AB8500_INT_VBUS_DET_R,
  759. .flags = IORESOURCE_IRQ,
  760. },
  761. {
  762. .name = "USB_LINK_STATUS",
  763. .start = AB8500_INT_USB_LINK_STATUS,
  764. .end = AB8500_INT_USB_LINK_STATUS,
  765. .flags = IORESOURCE_IRQ,
  766. },
  767. {
  768. .name = "USB_ADP_PROBE_PLUG",
  769. .start = AB8500_INT_ADP_PROBE_PLUG,
  770. .end = AB8500_INT_ADP_PROBE_PLUG,
  771. .flags = IORESOURCE_IRQ,
  772. },
  773. {
  774. .name = "USB_ADP_PROBE_UNPLUG",
  775. .start = AB8500_INT_ADP_PROBE_UNPLUG,
  776. .end = AB8500_INT_ADP_PROBE_UNPLUG,
  777. .flags = IORESOURCE_IRQ,
  778. },
  779. };
  780. static struct resource ab8505_iddet_resources[] = {
  781. {
  782. .name = "KeyDeglitch",
  783. .start = AB8505_INT_KEYDEGLITCH,
  784. .end = AB8505_INT_KEYDEGLITCH,
  785. .flags = IORESOURCE_IRQ,
  786. },
  787. {
  788. .name = "KP",
  789. .start = AB8505_INT_KP,
  790. .end = AB8505_INT_KP,
  791. .flags = IORESOURCE_IRQ,
  792. },
  793. {
  794. .name = "IKP",
  795. .start = AB8505_INT_IKP,
  796. .end = AB8505_INT_IKP,
  797. .flags = IORESOURCE_IRQ,
  798. },
  799. {
  800. .name = "IKR",
  801. .start = AB8505_INT_IKR,
  802. .end = AB8505_INT_IKR,
  803. .flags = IORESOURCE_IRQ,
  804. },
  805. {
  806. .name = "KeyStuck",
  807. .start = AB8505_INT_KEYSTUCK,
  808. .end = AB8505_INT_KEYSTUCK,
  809. .flags = IORESOURCE_IRQ,
  810. },
  811. };
  812. static struct resource ab8500_temp_resources[] = {
  813. {
  814. .name = "AB8500_TEMP_WARM",
  815. .start = AB8500_INT_TEMP_WARM,
  816. .end = AB8500_INT_TEMP_WARM,
  817. .flags = IORESOURCE_IRQ,
  818. },
  819. };
  820. static struct mfd_cell abx500_common_devs[] = {
  821. #ifdef CONFIG_DEBUG_FS
  822. {
  823. .name = "ab8500-debug",
  824. .of_compatible = "stericsson,ab8500-debug",
  825. .num_resources = ARRAY_SIZE(ab8500_debug_resources),
  826. .resources = ab8500_debug_resources,
  827. },
  828. #endif
  829. {
  830. .name = "ab8500-sysctrl",
  831. .of_compatible = "stericsson,ab8500-sysctrl",
  832. },
  833. {
  834. .name = "ab8500-regulator",
  835. .of_compatible = "stericsson,ab8500-regulator",
  836. },
  837. {
  838. .name = "abx500-clk",
  839. .of_compatible = "stericsson,abx500-clk",
  840. },
  841. {
  842. .name = "ab8500-gpadc",
  843. .of_compatible = "stericsson,ab8500-gpadc",
  844. .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
  845. .resources = ab8500_gpadc_resources,
  846. },
  847. {
  848. .name = "ab8500-rtc",
  849. .of_compatible = "stericsson,ab8500-rtc",
  850. .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
  851. .resources = ab8500_rtc_resources,
  852. },
  853. {
  854. .name = "ab8500-acc-det",
  855. .of_compatible = "stericsson,ab8500-acc-det",
  856. .num_resources = ARRAY_SIZE(ab8500_av_acc_detect_resources),
  857. .resources = ab8500_av_acc_detect_resources,
  858. },
  859. {
  860. .name = "ab8500-poweron-key",
  861. .of_compatible = "stericsson,ab8500-poweron-key",
  862. .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
  863. .resources = ab8500_poweronkey_db_resources,
  864. },
  865. {
  866. .name = "ab8500-pwm",
  867. .of_compatible = "stericsson,ab8500-pwm",
  868. .id = 1,
  869. },
  870. {
  871. .name = "ab8500-pwm",
  872. .of_compatible = "stericsson,ab8500-pwm",
  873. .id = 2,
  874. },
  875. {
  876. .name = "ab8500-pwm",
  877. .of_compatible = "stericsson,ab8500-pwm",
  878. .id = 3,
  879. },
  880. {
  881. .name = "ab8500-leds",
  882. .of_compatible = "stericsson,ab8500-leds",
  883. },
  884. {
  885. .name = "ab8500-denc",
  886. .of_compatible = "stericsson,ab8500-denc",
  887. },
  888. {
  889. .name = "ab8500-temp",
  890. .of_compatible = "stericsson,ab8500-temp",
  891. .num_resources = ARRAY_SIZE(ab8500_temp_resources),
  892. .resources = ab8500_temp_resources,
  893. },
  894. };
  895. static struct mfd_cell ab8500_bm_devs[] = {
  896. {
  897. .name = "ab8500-charger",
  898. .of_compatible = "stericsson,ab8500-charger",
  899. .num_resources = ARRAY_SIZE(ab8500_charger_resources),
  900. .resources = ab8500_charger_resources,
  901. #ifndef CONFIG_OF
  902. .platform_data = &ab8500_bm_data,
  903. .pdata_size = sizeof(ab8500_bm_data),
  904. #endif
  905. },
  906. {
  907. .name = "ab8500-btemp",
  908. .of_compatible = "stericsson,ab8500-btemp",
  909. .num_resources = ARRAY_SIZE(ab8500_btemp_resources),
  910. .resources = ab8500_btemp_resources,
  911. #ifndef CONFIG_OF
  912. .platform_data = &ab8500_bm_data,
  913. .pdata_size = sizeof(ab8500_bm_data),
  914. #endif
  915. },
  916. {
  917. .name = "ab8500-fg",
  918. .of_compatible = "stericsson,ab8500-fg",
  919. .num_resources = ARRAY_SIZE(ab8500_fg_resources),
  920. .resources = ab8500_fg_resources,
  921. #ifndef CONFIG_OF
  922. .platform_data = &ab8500_bm_data,
  923. .pdata_size = sizeof(ab8500_bm_data),
  924. #endif
  925. },
  926. {
  927. .name = "ab8500-chargalg",
  928. .of_compatible = "stericsson,ab8500-chargalg",
  929. .num_resources = ARRAY_SIZE(ab8500_chargalg_resources),
  930. .resources = ab8500_chargalg_resources,
  931. #ifndef CONFIG_OF
  932. .platform_data = &ab8500_bm_data,
  933. .pdata_size = sizeof(ab8500_bm_data),
  934. #endif
  935. },
  936. };
  937. static struct mfd_cell ab8500_devs[] = {
  938. {
  939. .name = "ab8500-gpio",
  940. .of_compatible = "stericsson,ab8500-gpio",
  941. },
  942. {
  943. .name = "ab8500-usb",
  944. .of_compatible = "stericsson,ab8500-usb",
  945. .num_resources = ARRAY_SIZE(ab8500_usb_resources),
  946. .resources = ab8500_usb_resources,
  947. },
  948. {
  949. .name = "ab8500-codec",
  950. .of_compatible = "stericsson,ab8500-codec",
  951. },
  952. };
  953. static struct mfd_cell ab9540_devs[] = {
  954. {
  955. .name = "ab8500-gpio",
  956. },
  957. {
  958. .name = "ab9540-usb",
  959. .num_resources = ARRAY_SIZE(ab8500_usb_resources),
  960. .resources = ab8500_usb_resources,
  961. },
  962. {
  963. .name = "ab9540-codec",
  964. },
  965. };
  966. /* Device list common to ab9540 and ab8505 */
  967. static struct mfd_cell ab9540_ab8505_devs[] = {
  968. {
  969. .name = "ab-iddet",
  970. .num_resources = ARRAY_SIZE(ab8505_iddet_resources),
  971. .resources = ab8505_iddet_resources,
  972. },
  973. };
  974. static ssize_t show_chip_id(struct device *dev,
  975. struct device_attribute *attr, char *buf)
  976. {
  977. struct ab8500 *ab8500;
  978. ab8500 = dev_get_drvdata(dev);
  979. return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
  980. }
  981. /*
  982. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  983. * 0x01 Swoff bit programming
  984. * 0x02 Thermal protection activation
  985. * 0x04 Vbat lower then BattOk falling threshold
  986. * 0x08 Watchdog expired
  987. * 0x10 Non presence of 32kHz clock
  988. * 0x20 Battery level lower than power on reset threshold
  989. * 0x40 Power on key 1 pressed longer than 10 seconds
  990. * 0x80 DB8500 thermal shutdown
  991. */
  992. static ssize_t show_switch_off_status(struct device *dev,
  993. struct device_attribute *attr, char *buf)
  994. {
  995. int ret;
  996. u8 value;
  997. struct ab8500 *ab8500;
  998. ab8500 = dev_get_drvdata(dev);
  999. ret = get_register_interruptible(ab8500, AB8500_RTC,
  1000. AB8500_SWITCH_OFF_STATUS, &value);
  1001. if (ret < 0)
  1002. return ret;
  1003. return sprintf(buf, "%#x\n", value);
  1004. }
  1005. /*
  1006. * ab8500 has turned on due to (TURN_ON_STATUS):
  1007. * 0x01 PORnVbat
  1008. * 0x02 PonKey1dbF
  1009. * 0x04 PonKey2dbF
  1010. * 0x08 RTCAlarm
  1011. * 0x10 MainChDet
  1012. * 0x20 VbusDet
  1013. * 0x40 UsbIDDetect
  1014. * 0x80 Reserved
  1015. */
  1016. static ssize_t show_turn_on_status(struct device *dev,
  1017. struct device_attribute *attr, char *buf)
  1018. {
  1019. int ret;
  1020. u8 value;
  1021. struct ab8500 *ab8500;
  1022. ab8500 = dev_get_drvdata(dev);
  1023. ret = get_register_interruptible(ab8500, AB8500_SYS_CTRL1_BLOCK,
  1024. AB8500_TURN_ON_STATUS, &value);
  1025. if (ret < 0)
  1026. return ret;
  1027. return sprintf(buf, "%#x\n", value);
  1028. }
  1029. static ssize_t show_ab9540_dbbrstn(struct device *dev,
  1030. struct device_attribute *attr, char *buf)
  1031. {
  1032. struct ab8500 *ab8500;
  1033. int ret;
  1034. u8 value;
  1035. ab8500 = dev_get_drvdata(dev);
  1036. ret = get_register_interruptible(ab8500, AB8500_REGU_CTRL2,
  1037. AB9540_MODEM_CTRL2_REG, &value);
  1038. if (ret < 0)
  1039. return ret;
  1040. return sprintf(buf, "%d\n",
  1041. (value & AB9540_MODEM_CTRL2_SWDBBRSTN_BIT) ? 1 : 0);
  1042. }
  1043. static ssize_t store_ab9540_dbbrstn(struct device *dev,
  1044. struct device_attribute *attr, const char *buf, size_t count)
  1045. {
  1046. struct ab8500 *ab8500;
  1047. int ret = count;
  1048. int err;
  1049. u8 bitvalues;
  1050. ab8500 = dev_get_drvdata(dev);
  1051. if (count > 0) {
  1052. switch (buf[0]) {
  1053. case '0':
  1054. bitvalues = 0;
  1055. break;
  1056. case '1':
  1057. bitvalues = AB9540_MODEM_CTRL2_SWDBBRSTN_BIT;
  1058. break;
  1059. default:
  1060. goto exit;
  1061. }
  1062. err = mask_and_set_register_interruptible(ab8500,
  1063. AB8500_REGU_CTRL2, AB9540_MODEM_CTRL2_REG,
  1064. AB9540_MODEM_CTRL2_SWDBBRSTN_BIT, bitvalues);
  1065. if (err)
  1066. dev_info(ab8500->dev,
  1067. "Failed to set DBBRSTN %c, err %#x\n",
  1068. buf[0], err);
  1069. }
  1070. exit:
  1071. return ret;
  1072. }
  1073. static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
  1074. static DEVICE_ATTR(switch_off_status, S_IRUGO, show_switch_off_status, NULL);
  1075. static DEVICE_ATTR(turn_on_status, S_IRUGO, show_turn_on_status, NULL);
  1076. static DEVICE_ATTR(dbbrstn, S_IRUGO | S_IWUSR,
  1077. show_ab9540_dbbrstn, store_ab9540_dbbrstn);
  1078. static struct attribute *ab8500_sysfs_entries[] = {
  1079. &dev_attr_chip_id.attr,
  1080. &dev_attr_switch_off_status.attr,
  1081. &dev_attr_turn_on_status.attr,
  1082. NULL,
  1083. };
  1084. static struct attribute *ab9540_sysfs_entries[] = {
  1085. &dev_attr_chip_id.attr,
  1086. &dev_attr_switch_off_status.attr,
  1087. &dev_attr_turn_on_status.attr,
  1088. &dev_attr_dbbrstn.attr,
  1089. NULL,
  1090. };
  1091. static struct attribute_group ab8500_attr_group = {
  1092. .attrs = ab8500_sysfs_entries,
  1093. };
  1094. static struct attribute_group ab9540_attr_group = {
  1095. .attrs = ab9540_sysfs_entries,
  1096. };
  1097. static int ab8500_probe(struct platform_device *pdev)
  1098. {
  1099. static char *switch_off_status[] = {
  1100. "Swoff bit programming",
  1101. "Thermal protection activation",
  1102. "Vbat lower then BattOk falling threshold",
  1103. "Watchdog expired",
  1104. "Non presence of 32kHz clock",
  1105. "Battery level lower than power on reset threshold",
  1106. "Power on key 1 pressed longer than 10 seconds",
  1107. "DB8500 thermal shutdown"};
  1108. struct ab8500_platform_data *plat = dev_get_platdata(&pdev->dev);
  1109. const struct platform_device_id *platid = platform_get_device_id(pdev);
  1110. enum ab8500_version version = AB8500_VERSION_UNDEFINED;
  1111. struct device_node *np = pdev->dev.of_node;
  1112. struct ab8500 *ab8500;
  1113. struct resource *resource;
  1114. int ret;
  1115. int i;
  1116. u8 value;
  1117. ab8500 = devm_kzalloc(&pdev->dev, sizeof *ab8500, GFP_KERNEL);
  1118. if (!ab8500)
  1119. return -ENOMEM;
  1120. if (plat)
  1121. ab8500->irq_base = plat->irq_base;
  1122. ab8500->dev = &pdev->dev;
  1123. resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1124. if (!resource)
  1125. return -ENODEV;
  1126. ab8500->irq = resource->start;
  1127. ab8500->read = ab8500_prcmu_read;
  1128. ab8500->write = ab8500_prcmu_write;
  1129. ab8500->write_masked = ab8500_prcmu_write_masked;
  1130. mutex_init(&ab8500->lock);
  1131. mutex_init(&ab8500->irq_lock);
  1132. atomic_set(&ab8500->transfer_ongoing, 0);
  1133. platform_set_drvdata(pdev, ab8500);
  1134. if (platid)
  1135. version = platid->driver_data;
  1136. if (version != AB8500_VERSION_UNDEFINED)
  1137. ab8500->version = version;
  1138. else {
  1139. ret = get_register_interruptible(ab8500, AB8500_MISC,
  1140. AB8500_IC_NAME_REG, &value);
  1141. if (ret < 0)
  1142. return ret;
  1143. ab8500->version = value;
  1144. }
  1145. ret = get_register_interruptible(ab8500, AB8500_MISC,
  1146. AB8500_REV_REG, &value);
  1147. if (ret < 0)
  1148. return ret;
  1149. ab8500->chip_id = value;
  1150. dev_info(ab8500->dev, "detected chip, %s rev. %1x.%1x\n",
  1151. ab8500_version_str[ab8500->version],
  1152. ab8500->chip_id >> 4,
  1153. ab8500->chip_id & 0x0F);
  1154. /* Configure AB8500 or AB9540 IRQ */
  1155. if (is_ab9540(ab8500) || is_ab8505(ab8500)) {
  1156. ab8500->mask_size = AB9540_NUM_IRQ_REGS;
  1157. ab8500->irq_reg_offset = ab9540_irq_regoffset;
  1158. } else {
  1159. ab8500->mask_size = AB8500_NUM_IRQ_REGS;
  1160. ab8500->irq_reg_offset = ab8500_irq_regoffset;
  1161. }
  1162. ab8500->mask = devm_kzalloc(&pdev->dev, ab8500->mask_size, GFP_KERNEL);
  1163. if (!ab8500->mask)
  1164. return -ENOMEM;
  1165. ab8500->oldmask = devm_kzalloc(&pdev->dev, ab8500->mask_size, GFP_KERNEL);
  1166. if (!ab8500->oldmask)
  1167. return -ENOMEM;
  1168. /*
  1169. * ab8500 has switched off due to (SWITCH_OFF_STATUS):
  1170. * 0x01 Swoff bit programming
  1171. * 0x02 Thermal protection activation
  1172. * 0x04 Vbat lower then BattOk falling threshold
  1173. * 0x08 Watchdog expired
  1174. * 0x10 Non presence of 32kHz clock
  1175. * 0x20 Battery level lower than power on reset threshold
  1176. * 0x40 Power on key 1 pressed longer than 10 seconds
  1177. * 0x80 DB8500 thermal shutdown
  1178. */
  1179. ret = get_register_interruptible(ab8500, AB8500_RTC,
  1180. AB8500_SWITCH_OFF_STATUS, &value);
  1181. if (ret < 0)
  1182. return ret;
  1183. dev_info(ab8500->dev, "switch off cause(s) (%#x): ", value);
  1184. if (value) {
  1185. for (i = 0; i < ARRAY_SIZE(switch_off_status); i++) {
  1186. if (value & 1)
  1187. printk(KERN_CONT " \"%s\"",
  1188. switch_off_status[i]);
  1189. value = value >> 1;
  1190. }
  1191. printk(KERN_CONT "\n");
  1192. } else {
  1193. printk(KERN_CONT " None\n");
  1194. }
  1195. if (plat && plat->init)
  1196. plat->init(ab8500);
  1197. /* Clear and mask all interrupts */
  1198. for (i = 0; i < ab8500->mask_size; i++) {
  1199. /*
  1200. * Interrupt register 12 doesn't exist prior to AB8500 version
  1201. * 2.0
  1202. */
  1203. if (ab8500->irq_reg_offset[i] == 11 &&
  1204. is_ab8500_1p1_or_earlier(ab8500))
  1205. continue;
  1206. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  1207. AB8500_IT_LATCH1_REG + ab8500->irq_reg_offset[i],
  1208. &value);
  1209. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  1210. AB8500_IT_MASK1_REG + ab8500->irq_reg_offset[i], 0xff);
  1211. }
  1212. ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
  1213. if (ret)
  1214. return ret;
  1215. for (i = 0; i < ab8500->mask_size; i++)
  1216. ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
  1217. ret = ab8500_irq_init(ab8500, np);
  1218. if (ret)
  1219. return ret;
  1220. /* Activate this feature only in ab9540 */
  1221. /* till tests are done on ab8500 1p2 or later*/
  1222. if (is_ab9540(ab8500)) {
  1223. ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
  1224. ab8500_hierarchical_irq,
  1225. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  1226. "ab8500", ab8500);
  1227. }
  1228. else {
  1229. ret = devm_request_threaded_irq(&pdev->dev, ab8500->irq, NULL,
  1230. ab8500_irq,
  1231. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  1232. "ab8500", ab8500);
  1233. if (ret)
  1234. return ret;
  1235. }
  1236. ret = mfd_add_devices(ab8500->dev, 0, abx500_common_devs,
  1237. ARRAY_SIZE(abx500_common_devs), NULL,
  1238. ab8500->irq_base, ab8500->domain);
  1239. if (ret)
  1240. return ret;
  1241. if (is_ab9540(ab8500))
  1242. ret = mfd_add_devices(ab8500->dev, 0, ab9540_devs,
  1243. ARRAY_SIZE(ab9540_devs), NULL,
  1244. ab8500->irq_base, ab8500->domain);
  1245. else
  1246. ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
  1247. ARRAY_SIZE(ab8500_devs), NULL,
  1248. ab8500->irq_base, ab8500->domain);
  1249. if (ret)
  1250. return ret;
  1251. if (is_ab9540(ab8500) || is_ab8505(ab8500))
  1252. ret = mfd_add_devices(ab8500->dev, 0, ab9540_ab8505_devs,
  1253. ARRAY_SIZE(ab9540_ab8505_devs), NULL,
  1254. ab8500->irq_base, ab8500->domain);
  1255. if (ret)
  1256. return ret;
  1257. if (!no_bm) {
  1258. /* Add battery management devices */
  1259. ret = mfd_add_devices(ab8500->dev, 0, ab8500_bm_devs,
  1260. ARRAY_SIZE(ab8500_bm_devs), NULL,
  1261. ab8500->irq_base, ab8500->domain);
  1262. if (ret)
  1263. dev_err(ab8500->dev, "error adding bm devices\n");
  1264. }
  1265. if (is_ab9540(ab8500))
  1266. ret = sysfs_create_group(&ab8500->dev->kobj,
  1267. &ab9540_attr_group);
  1268. else
  1269. ret = sysfs_create_group(&ab8500->dev->kobj,
  1270. &ab8500_attr_group);
  1271. if (ret)
  1272. dev_err(ab8500->dev, "error creating sysfs entries\n");
  1273. return ret;
  1274. }
  1275. static int ab8500_remove(struct platform_device *pdev)
  1276. {
  1277. struct ab8500 *ab8500 = platform_get_drvdata(pdev);
  1278. if (is_ab9540(ab8500))
  1279. sysfs_remove_group(&ab8500->dev->kobj, &ab9540_attr_group);
  1280. else
  1281. sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
  1282. mfd_remove_devices(ab8500->dev);
  1283. return 0;
  1284. }
  1285. static const struct platform_device_id ab8500_id[] = {
  1286. { "ab8500-core", AB8500_VERSION_AB8500 },
  1287. { "ab8505-i2c", AB8500_VERSION_AB8505 },
  1288. { "ab9540-i2c", AB8500_VERSION_AB9540 },
  1289. { "ab8540-i2c", AB8500_VERSION_AB8540 },
  1290. { }
  1291. };
  1292. static struct platform_driver ab8500_core_driver = {
  1293. .driver = {
  1294. .name = "ab8500-core",
  1295. .owner = THIS_MODULE,
  1296. },
  1297. .probe = ab8500_probe,
  1298. .remove = ab8500_remove,
  1299. .id_table = ab8500_id,
  1300. };
  1301. static int __init ab8500_core_init(void)
  1302. {
  1303. return platform_driver_register(&ab8500_core_driver);
  1304. }
  1305. static void __exit ab8500_core_exit(void)
  1306. {
  1307. platform_driver_unregister(&ab8500_core_driver);
  1308. }
  1309. core_initcall(ab8500_core_init);
  1310. module_exit(ab8500_core_exit);
  1311. MODULE_AUTHOR("Mattias Wallin, Srinidhi Kasagar, Rabin Vincent");
  1312. MODULE_DESCRIPTION("AB8500 MFD core");
  1313. MODULE_LICENSE("GPL v2");