88pm800.c 14 KB

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  1. /*
  2. * Base driver for Marvell 88PM800
  3. *
  4. * Copyright (C) 2012 Marvell International Ltd.
  5. * Haojian Zhuang <haojian.zhuang@marvell.com>
  6. * Joseph(Yossi) Hanin <yhanin@marvell.com>
  7. * Qiao Zhou <zhouqiao@marvell.com>
  8. *
  9. * This file is subject to the terms and conditions of the GNU General
  10. * Public License. See the file "COPYING" in the main directory of this
  11. * archive for more details.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/i2c.h>
  25. #include <linux/mfd/core.h>
  26. #include <linux/mfd/88pm80x.h>
  27. #include <linux/slab.h>
  28. #define PM800_CHIP_ID (0x00)
  29. /* Interrupt Registers */
  30. #define PM800_INT_STATUS1 (0x05)
  31. #define PM800_ONKEY_INT_STS1 (1 << 0)
  32. #define PM800_EXTON_INT_STS1 (1 << 1)
  33. #define PM800_CHG_INT_STS1 (1 << 2)
  34. #define PM800_BAT_INT_STS1 (1 << 3)
  35. #define PM800_RTC_INT_STS1 (1 << 4)
  36. #define PM800_CLASSD_OC_INT_STS1 (1 << 5)
  37. #define PM800_INT_STATUS2 (0x06)
  38. #define PM800_VBAT_INT_STS2 (1 << 0)
  39. #define PM800_VSYS_INT_STS2 (1 << 1)
  40. #define PM800_VCHG_INT_STS2 (1 << 2)
  41. #define PM800_TINT_INT_STS2 (1 << 3)
  42. #define PM800_GPADC0_INT_STS2 (1 << 4)
  43. #define PM800_TBAT_INT_STS2 (1 << 5)
  44. #define PM800_GPADC2_INT_STS2 (1 << 6)
  45. #define PM800_GPADC3_INT_STS2 (1 << 7)
  46. #define PM800_INT_STATUS3 (0x07)
  47. #define PM800_INT_STATUS4 (0x08)
  48. #define PM800_GPIO0_INT_STS4 (1 << 0)
  49. #define PM800_GPIO1_INT_STS4 (1 << 1)
  50. #define PM800_GPIO2_INT_STS4 (1 << 2)
  51. #define PM800_GPIO3_INT_STS4 (1 << 3)
  52. #define PM800_GPIO4_INT_STS4 (1 << 4)
  53. #define PM800_INT_ENA_1 (0x09)
  54. #define PM800_ONKEY_INT_ENA1 (1 << 0)
  55. #define PM800_EXTON_INT_ENA1 (1 << 1)
  56. #define PM800_CHG_INT_ENA1 (1 << 2)
  57. #define PM800_BAT_INT_ENA1 (1 << 3)
  58. #define PM800_RTC_INT_ENA1 (1 << 4)
  59. #define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
  60. #define PM800_INT_ENA_2 (0x0A)
  61. #define PM800_VBAT_INT_ENA2 (1 << 0)
  62. #define PM800_VSYS_INT_ENA2 (1 << 1)
  63. #define PM800_VCHG_INT_ENA2 (1 << 2)
  64. #define PM800_TINT_INT_ENA2 (1 << 3)
  65. #define PM800_INT_ENA_3 (0x0B)
  66. #define PM800_GPADC0_INT_ENA3 (1 << 0)
  67. #define PM800_GPADC1_INT_ENA3 (1 << 1)
  68. #define PM800_GPADC2_INT_ENA3 (1 << 2)
  69. #define PM800_GPADC3_INT_ENA3 (1 << 3)
  70. #define PM800_GPADC4_INT_ENA3 (1 << 4)
  71. #define PM800_INT_ENA_4 (0x0C)
  72. #define PM800_GPIO0_INT_ENA4 (1 << 0)
  73. #define PM800_GPIO1_INT_ENA4 (1 << 1)
  74. #define PM800_GPIO2_INT_ENA4 (1 << 2)
  75. #define PM800_GPIO3_INT_ENA4 (1 << 3)
  76. #define PM800_GPIO4_INT_ENA4 (1 << 4)
  77. /* number of INT_ENA & INT_STATUS regs */
  78. #define PM800_INT_REG_NUM (4)
  79. /* Interrupt Number in 88PM800 */
  80. enum {
  81. PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
  82. PM800_IRQ_EXTON, /*EN1b1 */
  83. PM800_IRQ_CHG, /*EN1b2 */
  84. PM800_IRQ_BAT, /*EN1b3 */
  85. PM800_IRQ_RTC, /*EN1b4 */
  86. PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
  87. PM800_IRQ_VBAT, /*EN2b0 */
  88. PM800_IRQ_VSYS, /*EN2b1 */
  89. PM800_IRQ_VCHG, /*EN2b2 */
  90. PM800_IRQ_TINT, /*EN2b3 */
  91. PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
  92. PM800_IRQ_GPADC1, /*EN3b1 */
  93. PM800_IRQ_GPADC2, /*EN3b2 */
  94. PM800_IRQ_GPADC3, /*EN3b3 */
  95. PM800_IRQ_GPADC4, /*EN3b4 */
  96. PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
  97. PM800_IRQ_GPIO1, /*EN4b1 */
  98. PM800_IRQ_GPIO2, /*EN4b2 */
  99. PM800_IRQ_GPIO3, /*EN4b3 */
  100. PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
  101. PM800_MAX_IRQ,
  102. };
  103. enum {
  104. /* Procida */
  105. PM800_CHIP_A0 = 0x60,
  106. PM800_CHIP_A1 = 0x61,
  107. PM800_CHIP_B0 = 0x62,
  108. PM800_CHIP_C0 = 0x63,
  109. PM800_CHIP_END = PM800_CHIP_C0,
  110. /* Make sure to update this to the last stepping */
  111. PM8XXX_CHIP_END = PM800_CHIP_END
  112. };
  113. static const struct i2c_device_id pm80x_id_table[] = {
  114. {"88PM800", CHIP_PM800},
  115. {} /* NULL terminated */
  116. };
  117. MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
  118. static struct resource rtc_resources[] = {
  119. {
  120. .name = "88pm80x-rtc",
  121. .start = PM800_IRQ_RTC,
  122. .end = PM800_IRQ_RTC,
  123. .flags = IORESOURCE_IRQ,
  124. },
  125. };
  126. static struct mfd_cell rtc_devs[] = {
  127. {
  128. .name = "88pm80x-rtc",
  129. .num_resources = ARRAY_SIZE(rtc_resources),
  130. .resources = &rtc_resources[0],
  131. .id = -1,
  132. },
  133. };
  134. static struct resource onkey_resources[] = {
  135. {
  136. .name = "88pm80x-onkey",
  137. .start = PM800_IRQ_ONKEY,
  138. .end = PM800_IRQ_ONKEY,
  139. .flags = IORESOURCE_IRQ,
  140. },
  141. };
  142. static struct mfd_cell onkey_devs[] = {
  143. {
  144. .name = "88pm80x-onkey",
  145. .num_resources = 1,
  146. .resources = &onkey_resources[0],
  147. .id = -1,
  148. },
  149. };
  150. static const struct regmap_irq pm800_irqs[] = {
  151. /* INT0 */
  152. [PM800_IRQ_ONKEY] = {
  153. .mask = PM800_ONKEY_INT_ENA1,
  154. },
  155. [PM800_IRQ_EXTON] = {
  156. .mask = PM800_EXTON_INT_ENA1,
  157. },
  158. [PM800_IRQ_CHG] = {
  159. .mask = PM800_CHG_INT_ENA1,
  160. },
  161. [PM800_IRQ_BAT] = {
  162. .mask = PM800_BAT_INT_ENA1,
  163. },
  164. [PM800_IRQ_RTC] = {
  165. .mask = PM800_RTC_INT_ENA1,
  166. },
  167. [PM800_IRQ_CLASSD] = {
  168. .mask = PM800_CLASSD_OC_INT_ENA1,
  169. },
  170. /* INT1 */
  171. [PM800_IRQ_VBAT] = {
  172. .reg_offset = 1,
  173. .mask = PM800_VBAT_INT_ENA2,
  174. },
  175. [PM800_IRQ_VSYS] = {
  176. .reg_offset = 1,
  177. .mask = PM800_VSYS_INT_ENA2,
  178. },
  179. [PM800_IRQ_VCHG] = {
  180. .reg_offset = 1,
  181. .mask = PM800_VCHG_INT_ENA2,
  182. },
  183. [PM800_IRQ_TINT] = {
  184. .reg_offset = 1,
  185. .mask = PM800_TINT_INT_ENA2,
  186. },
  187. /* INT2 */
  188. [PM800_IRQ_GPADC0] = {
  189. .reg_offset = 2,
  190. .mask = PM800_GPADC0_INT_ENA3,
  191. },
  192. [PM800_IRQ_GPADC1] = {
  193. .reg_offset = 2,
  194. .mask = PM800_GPADC1_INT_ENA3,
  195. },
  196. [PM800_IRQ_GPADC2] = {
  197. .reg_offset = 2,
  198. .mask = PM800_GPADC2_INT_ENA3,
  199. },
  200. [PM800_IRQ_GPADC3] = {
  201. .reg_offset = 2,
  202. .mask = PM800_GPADC3_INT_ENA3,
  203. },
  204. [PM800_IRQ_GPADC4] = {
  205. .reg_offset = 2,
  206. .mask = PM800_GPADC4_INT_ENA3,
  207. },
  208. /* INT3 */
  209. [PM800_IRQ_GPIO0] = {
  210. .reg_offset = 3,
  211. .mask = PM800_GPIO0_INT_ENA4,
  212. },
  213. [PM800_IRQ_GPIO1] = {
  214. .reg_offset = 3,
  215. .mask = PM800_GPIO1_INT_ENA4,
  216. },
  217. [PM800_IRQ_GPIO2] = {
  218. .reg_offset = 3,
  219. .mask = PM800_GPIO2_INT_ENA4,
  220. },
  221. [PM800_IRQ_GPIO3] = {
  222. .reg_offset = 3,
  223. .mask = PM800_GPIO3_INT_ENA4,
  224. },
  225. [PM800_IRQ_GPIO4] = {
  226. .reg_offset = 3,
  227. .mask = PM800_GPIO4_INT_ENA4,
  228. },
  229. };
  230. static int device_gpadc_init(struct pm80x_chip *chip,
  231. struct pm80x_platform_data *pdata)
  232. {
  233. struct pm80x_subchip *subchip = chip->subchip;
  234. struct regmap *map = subchip->regmap_gpadc;
  235. int data = 0, mask = 0, ret = 0;
  236. if (!map) {
  237. dev_warn(chip->dev,
  238. "Warning: gpadc regmap is not available!\n");
  239. return -EINVAL;
  240. }
  241. /*
  242. * initialize GPADC without activating it turn on GPADC
  243. * measurments
  244. */
  245. ret = regmap_update_bits(map,
  246. PM800_GPADC_MISC_CONFIG2,
  247. PM800_GPADC_MISC_GPFSM_EN,
  248. PM800_GPADC_MISC_GPFSM_EN);
  249. if (ret < 0)
  250. goto out;
  251. /*
  252. * This function configures the ADC as requires for
  253. * CP implementation.CP does not "own" the ADC configuration
  254. * registers and relies on AP.
  255. * Reason: enable automatic ADC measurements needed
  256. * for CP to get VBAT and RF temperature readings.
  257. */
  258. ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
  259. PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
  260. if (ret < 0)
  261. goto out;
  262. ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
  263. (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
  264. (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
  265. if (ret < 0)
  266. goto out;
  267. /*
  268. * the defult of PM800 is GPADC operates at 100Ks/s rate
  269. * and Number of GPADC slots with active current bias prior
  270. * to GPADC sampling = 1 slot for all GPADCs set for
  271. * Temprature mesurmants
  272. */
  273. mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
  274. PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
  275. if (pdata && (pdata->batt_det == 0))
  276. data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
  277. PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
  278. else
  279. data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
  280. PM800_GPADC_GP_BIAS_EN3);
  281. ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
  282. if (ret < 0)
  283. goto out;
  284. dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
  285. return 0;
  286. out:
  287. dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
  288. return ret;
  289. }
  290. static int device_irq_init_800(struct pm80x_chip *chip)
  291. {
  292. struct regmap *map = chip->regmap;
  293. unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
  294. int data, mask, ret = -EINVAL;
  295. if (!map || !chip->irq) {
  296. dev_err(chip->dev, "incorrect parameters\n");
  297. return -EINVAL;
  298. }
  299. /*
  300. * irq_mode defines the way of clearing interrupt. it's read-clear by
  301. * default.
  302. */
  303. mask =
  304. PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
  305. PM800_WAKEUP2_INT_MASK;
  306. data = PM800_WAKEUP2_INT_CLEAR;
  307. ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
  308. if (ret < 0)
  309. goto out;
  310. ret =
  311. regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
  312. chip->regmap_irq_chip, &chip->irq_data);
  313. out:
  314. return ret;
  315. }
  316. static void device_irq_exit_800(struct pm80x_chip *chip)
  317. {
  318. regmap_del_irq_chip(chip->irq, chip->irq_data);
  319. }
  320. static struct regmap_irq_chip pm800_irq_chip = {
  321. .name = "88pm800",
  322. .irqs = pm800_irqs,
  323. .num_irqs = ARRAY_SIZE(pm800_irqs),
  324. .num_regs = 4,
  325. .status_base = PM800_INT_STATUS1,
  326. .mask_base = PM800_INT_ENA_1,
  327. .ack_base = PM800_INT_STATUS1,
  328. };
  329. static int pm800_pages_init(struct pm80x_chip *chip)
  330. {
  331. struct pm80x_subchip *subchip;
  332. struct i2c_client *client = chip->client;
  333. subchip = chip->subchip;
  334. /* PM800 block power: i2c addr 0x31 */
  335. if (subchip->power_page_addr) {
  336. subchip->power_page =
  337. i2c_new_dummy(client->adapter, subchip->power_page_addr);
  338. subchip->regmap_power =
  339. devm_regmap_init_i2c(subchip->power_page,
  340. &pm80x_regmap_config);
  341. i2c_set_clientdata(subchip->power_page, chip);
  342. } else
  343. dev_info(chip->dev,
  344. "PM800 block power 0x31: No power_page_addr\n");
  345. /* PM800 block GPADC: i2c addr 0x32 */
  346. if (subchip->gpadc_page_addr) {
  347. subchip->gpadc_page = i2c_new_dummy(client->adapter,
  348. subchip->gpadc_page_addr);
  349. subchip->regmap_gpadc =
  350. devm_regmap_init_i2c(subchip->gpadc_page,
  351. &pm80x_regmap_config);
  352. i2c_set_clientdata(subchip->gpadc_page, chip);
  353. } else
  354. dev_info(chip->dev,
  355. "PM800 block GPADC 0x32: No gpadc_page_addr\n");
  356. return 0;
  357. }
  358. static void pm800_pages_exit(struct pm80x_chip *chip)
  359. {
  360. struct pm80x_subchip *subchip;
  361. regmap_exit(chip->regmap);
  362. i2c_unregister_device(chip->client);
  363. subchip = chip->subchip;
  364. if (subchip->power_page) {
  365. regmap_exit(subchip->regmap_power);
  366. i2c_unregister_device(subchip->power_page);
  367. }
  368. if (subchip->gpadc_page) {
  369. regmap_exit(subchip->regmap_gpadc);
  370. i2c_unregister_device(subchip->gpadc_page);
  371. }
  372. }
  373. static int device_800_init(struct pm80x_chip *chip,
  374. struct pm80x_platform_data *pdata)
  375. {
  376. int ret, pmic_id;
  377. unsigned int val;
  378. ret = regmap_read(chip->regmap, PM800_CHIP_ID, &val);
  379. if (ret < 0) {
  380. dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
  381. goto out;
  382. }
  383. pmic_id = val & PM80X_VERSION_MASK;
  384. if ((pmic_id >= PM800_CHIP_A0) && (pmic_id <= PM800_CHIP_END)) {
  385. chip->version = val;
  386. dev_info(chip->dev,
  387. "88PM80x:Marvell 88PM800 (ID:0x%x) detected\n", val);
  388. } else {
  389. dev_err(chip->dev,
  390. "Failed to detect Marvell 88PM800:ChipID[0x%x]\n", val);
  391. ret = -EINVAL;
  392. goto out;
  393. }
  394. /*
  395. * alarm wake up bit will be clear in device_irq_init(),
  396. * read before that
  397. */
  398. ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
  399. if (ret < 0) {
  400. dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
  401. goto out;
  402. }
  403. if (val & PM800_ALARM_WAKEUP) {
  404. if (pdata && pdata->rtc)
  405. pdata->rtc->rtc_wakeup = 1;
  406. }
  407. ret = device_gpadc_init(chip, pdata);
  408. if (ret < 0) {
  409. dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
  410. goto out;
  411. }
  412. chip->regmap_irq_chip = &pm800_irq_chip;
  413. ret = device_irq_init_800(chip);
  414. if (ret < 0) {
  415. dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
  416. goto out;
  417. }
  418. ret =
  419. mfd_add_devices(chip->dev, 0, &onkey_devs[0],
  420. ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
  421. NULL);
  422. if (ret < 0) {
  423. dev_err(chip->dev, "Failed to add onkey subdev\n");
  424. goto out_dev;
  425. } else
  426. dev_info(chip->dev, "[%s]:Added mfd onkey_devs\n", __func__);
  427. if (pdata && pdata->rtc) {
  428. rtc_devs[0].platform_data = pdata->rtc;
  429. rtc_devs[0].pdata_size = sizeof(struct pm80x_rtc_pdata);
  430. ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
  431. ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
  432. if (ret < 0) {
  433. dev_err(chip->dev, "Failed to add rtc subdev\n");
  434. goto out_dev;
  435. } else
  436. dev_info(chip->dev,
  437. "[%s]:Added mfd rtc_devs\n", __func__);
  438. }
  439. return 0;
  440. out_dev:
  441. mfd_remove_devices(chip->dev);
  442. device_irq_exit_800(chip);
  443. out:
  444. return ret;
  445. }
  446. static int pm800_probe(struct i2c_client *client,
  447. const struct i2c_device_id *id)
  448. {
  449. int ret = 0;
  450. struct pm80x_chip *chip;
  451. struct pm80x_platform_data *pdata = client->dev.platform_data;
  452. struct pm80x_subchip *subchip;
  453. ret = pm80x_init(client, id);
  454. if (ret) {
  455. dev_err(&client->dev, "pm800_init fail\n");
  456. goto out_init;
  457. }
  458. chip = i2c_get_clientdata(client);
  459. /* init subchip for PM800 */
  460. subchip =
  461. devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
  462. GFP_KERNEL);
  463. if (!subchip) {
  464. ret = -ENOMEM;
  465. goto err_subchip_alloc;
  466. }
  467. subchip->power_page_addr = pdata->power_page_addr;
  468. subchip->gpadc_page_addr = pdata->gpadc_page_addr;
  469. chip->subchip = subchip;
  470. ret = device_800_init(chip, pdata);
  471. if (ret) {
  472. dev_err(chip->dev, "%s id 0x%x failed!\n", __func__, chip->id);
  473. goto err_800_init;
  474. }
  475. ret = pm800_pages_init(chip);
  476. if (ret) {
  477. dev_err(&client->dev, "pm800_pages_init failed!\n");
  478. goto err_page_init;
  479. }
  480. if (pdata->plat_config)
  481. pdata->plat_config(chip, pdata);
  482. err_page_init:
  483. mfd_remove_devices(chip->dev);
  484. device_irq_exit_800(chip);
  485. err_800_init:
  486. devm_kfree(&client->dev, subchip);
  487. err_subchip_alloc:
  488. pm80x_deinit(client);
  489. out_init:
  490. return ret;
  491. }
  492. static int pm800_remove(struct i2c_client *client)
  493. {
  494. struct pm80x_chip *chip = i2c_get_clientdata(client);
  495. mfd_remove_devices(chip->dev);
  496. device_irq_exit_800(chip);
  497. pm800_pages_exit(chip);
  498. devm_kfree(&client->dev, chip->subchip);
  499. pm80x_deinit(client);
  500. return 0;
  501. }
  502. static struct i2c_driver pm800_driver = {
  503. .driver = {
  504. .name = "88PM80X",
  505. .owner = THIS_MODULE,
  506. .pm = &pm80x_pm_ops,
  507. },
  508. .probe = pm800_probe,
  509. .remove = pm800_remove,
  510. .id_table = pm80x_id_table,
  511. };
  512. static int __init pm800_i2c_init(void)
  513. {
  514. return i2c_add_driver(&pm800_driver);
  515. }
  516. subsys_initcall(pm800_i2c_init);
  517. static void __exit pm800_i2c_exit(void)
  518. {
  519. i2c_del_driver(&pm800_driver);
  520. }
  521. module_exit(pm800_i2c_exit);
  522. MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
  523. MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
  524. MODULE_LICENSE("GPL");