s5c73m3-core.c 40 KB

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  1. /*
  2. * Samsung LSI S5C73M3 8M pixel camera driver
  3. *
  4. * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. * Andrzej Hajda <a.hajda@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/sizes.h>
  18. #include <linux/delay.h>
  19. #include <linux/firmware.h>
  20. #include <linux/gpio.h>
  21. #include <linux/i2c.h>
  22. #include <linux/init.h>
  23. #include <linux/media.h>
  24. #include <linux/module.h>
  25. #include <linux/regulator/consumer.h>
  26. #include <linux/slab.h>
  27. #include <linux/spi/spi.h>
  28. #include <linux/videodev2.h>
  29. #include <media/media-entity.h>
  30. #include <media/v4l2-ctrls.h>
  31. #include <media/v4l2-device.h>
  32. #include <media/v4l2-subdev.h>
  33. #include <media/v4l2-mediabus.h>
  34. #include <media/s5c73m3.h>
  35. #include "s5c73m3.h"
  36. int s5c73m3_dbg;
  37. module_param_named(debug, s5c73m3_dbg, int, 0644);
  38. static int boot_from_rom = 1;
  39. module_param(boot_from_rom, int, 0644);
  40. static int update_fw;
  41. module_param(update_fw, int, 0644);
  42. #define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K
  43. static const char * const s5c73m3_supply_names[S5C73M3_MAX_SUPPLIES] = {
  44. "vdd-int", /* Digital Core supply (1.2V), CAM_ISP_CORE_1.2V */
  45. "vdda", /* Analog Core supply (1.2V), CAM_SENSOR_CORE_1.2V */
  46. "vdd-reg", /* Regulator input supply (2.8V), CAM_SENSOR_A2.8V */
  47. "vddio-host", /* Digital Host I/O power supply (1.8V...2.8V),
  48. CAM_ISP_SENSOR_1.8V */
  49. "vddio-cis", /* Digital CIS I/O power (1.2V...1.8V),
  50. CAM_ISP_MIPI_1.2V */
  51. "vdd-af", /* Lens, CAM_AF_2.8V */
  52. };
  53. static const struct s5c73m3_frame_size s5c73m3_isp_resolutions[] = {
  54. { 320, 240, COMM_CHG_MODE_YUV_320_240 },
  55. { 352, 288, COMM_CHG_MODE_YUV_352_288 },
  56. { 640, 480, COMM_CHG_MODE_YUV_640_480 },
  57. { 880, 720, COMM_CHG_MODE_YUV_880_720 },
  58. { 960, 720, COMM_CHG_MODE_YUV_960_720 },
  59. { 1008, 672, COMM_CHG_MODE_YUV_1008_672 },
  60. { 1184, 666, COMM_CHG_MODE_YUV_1184_666 },
  61. { 1280, 720, COMM_CHG_MODE_YUV_1280_720 },
  62. { 1536, 864, COMM_CHG_MODE_YUV_1536_864 },
  63. { 1600, 1200, COMM_CHG_MODE_YUV_1600_1200 },
  64. { 1632, 1224, COMM_CHG_MODE_YUV_1632_1224 },
  65. { 1920, 1080, COMM_CHG_MODE_YUV_1920_1080 },
  66. { 1920, 1440, COMM_CHG_MODE_YUV_1920_1440 },
  67. { 2304, 1296, COMM_CHG_MODE_YUV_2304_1296 },
  68. { 3264, 2448, COMM_CHG_MODE_YUV_3264_2448 },
  69. };
  70. static const struct s5c73m3_frame_size s5c73m3_jpeg_resolutions[] = {
  71. { 640, 480, COMM_CHG_MODE_JPEG_640_480 },
  72. { 800, 450, COMM_CHG_MODE_JPEG_800_450 },
  73. { 800, 600, COMM_CHG_MODE_JPEG_800_600 },
  74. { 1024, 768, COMM_CHG_MODE_JPEG_1024_768 },
  75. { 1280, 720, COMM_CHG_MODE_JPEG_1280_720 },
  76. { 1280, 960, COMM_CHG_MODE_JPEG_1280_960 },
  77. { 1600, 900, COMM_CHG_MODE_JPEG_1600_900 },
  78. { 1600, 1200, COMM_CHG_MODE_JPEG_1600_1200 },
  79. { 2048, 1152, COMM_CHG_MODE_JPEG_2048_1152 },
  80. { 2048, 1536, COMM_CHG_MODE_JPEG_2048_1536 },
  81. { 2560, 1440, COMM_CHG_MODE_JPEG_2560_1440 },
  82. { 2560, 1920, COMM_CHG_MODE_JPEG_2560_1920 },
  83. { 3264, 1836, COMM_CHG_MODE_JPEG_3264_1836 },
  84. { 3264, 2176, COMM_CHG_MODE_JPEG_3264_2176 },
  85. { 3264, 2448, COMM_CHG_MODE_JPEG_3264_2448 },
  86. };
  87. static const struct s5c73m3_frame_size * const s5c73m3_resolutions[] = {
  88. [RES_ISP] = s5c73m3_isp_resolutions,
  89. [RES_JPEG] = s5c73m3_jpeg_resolutions
  90. };
  91. static const int s5c73m3_resolutions_len[] = {
  92. [RES_ISP] = ARRAY_SIZE(s5c73m3_isp_resolutions),
  93. [RES_JPEG] = ARRAY_SIZE(s5c73m3_jpeg_resolutions)
  94. };
  95. static const struct s5c73m3_interval s5c73m3_intervals[] = {
  96. { COMM_FRAME_RATE_FIXED_7FPS, {142857, 1000000}, {3264, 2448} },
  97. { COMM_FRAME_RATE_FIXED_15FPS, {66667, 1000000}, {3264, 2448} },
  98. { COMM_FRAME_RATE_FIXED_20FPS, {50000, 1000000}, {2304, 1296} },
  99. { COMM_FRAME_RATE_FIXED_30FPS, {33333, 1000000}, {2304, 1296} },
  100. };
  101. #define S5C73M3_DEFAULT_FRAME_INTERVAL 3 /* 30 fps */
  102. static void s5c73m3_fill_mbus_fmt(struct v4l2_mbus_framefmt *mf,
  103. const struct s5c73m3_frame_size *fs,
  104. u32 code)
  105. {
  106. mf->width = fs->width;
  107. mf->height = fs->height;
  108. mf->code = code;
  109. mf->colorspace = V4L2_COLORSPACE_JPEG;
  110. mf->field = V4L2_FIELD_NONE;
  111. }
  112. static int s5c73m3_i2c_write(struct i2c_client *client, u16 addr, u16 data)
  113. {
  114. u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff };
  115. int ret = i2c_master_send(client, buf, sizeof(buf));
  116. v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n",
  117. __func__, addr, data);
  118. if (ret == 4)
  119. return 0;
  120. return ret < 0 ? ret : -EREMOTEIO;
  121. }
  122. static int s5c73m3_i2c_read(struct i2c_client *client, u16 addr, u16 *data)
  123. {
  124. int ret;
  125. u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff };
  126. struct i2c_msg msg[2] = {
  127. {
  128. .addr = client->addr,
  129. .flags = 0,
  130. .len = sizeof(wbuf),
  131. .buf = wbuf
  132. }, {
  133. .addr = client->addr,
  134. .flags = I2C_M_RD,
  135. .len = sizeof(rbuf),
  136. .buf = rbuf
  137. }
  138. };
  139. /*
  140. * Issue repeated START after writing 2 address bytes and
  141. * just one STOP only after reading the data bytes.
  142. */
  143. ret = i2c_transfer(client->adapter, msg, 2);
  144. if (ret == 2) {
  145. *data = be16_to_cpup((u16 *)rbuf);
  146. v4l2_dbg(4, s5c73m3_dbg, client,
  147. "%s: addr: 0x%04x, data: 0x%04x\n",
  148. __func__, addr, *data);
  149. return 0;
  150. }
  151. v4l2_err(client, "I2C read failed: addr: %04x, (%d)\n", addr, ret);
  152. return ret >= 0 ? -EREMOTEIO : ret;
  153. }
  154. int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data)
  155. {
  156. struct i2c_client *client = state->i2c_client;
  157. int ret;
  158. if ((addr ^ state->i2c_write_address) & 0xffff0000) {
  159. ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRH, addr >> 16);
  160. if (ret < 0) {
  161. state->i2c_write_address = 0;
  162. return ret;
  163. }
  164. }
  165. if ((addr ^ state->i2c_write_address) & 0xffff) {
  166. ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRL, addr & 0xffff);
  167. if (ret < 0) {
  168. state->i2c_write_address = 0;
  169. return ret;
  170. }
  171. }
  172. state->i2c_write_address = addr;
  173. ret = s5c73m3_i2c_write(client, REG_CMDBUF_ADDR, data);
  174. if (ret < 0)
  175. return ret;
  176. state->i2c_write_address += 2;
  177. return ret;
  178. }
  179. int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data)
  180. {
  181. struct i2c_client *client = state->i2c_client;
  182. int ret;
  183. if ((addr ^ state->i2c_read_address) & 0xffff0000) {
  184. ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRH, addr >> 16);
  185. if (ret < 0) {
  186. state->i2c_read_address = 0;
  187. return ret;
  188. }
  189. }
  190. if ((addr ^ state->i2c_read_address) & 0xffff) {
  191. ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRL, addr & 0xffff);
  192. if (ret < 0) {
  193. state->i2c_read_address = 0;
  194. return ret;
  195. }
  196. }
  197. state->i2c_read_address = addr;
  198. ret = s5c73m3_i2c_read(client, REG_CMDBUF_ADDR, data);
  199. if (ret < 0)
  200. return ret;
  201. state->i2c_read_address += 2;
  202. return ret;
  203. }
  204. static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value)
  205. {
  206. unsigned long start = jiffies;
  207. unsigned long end = start + msecs_to_jiffies(2000);
  208. int ret = 0;
  209. u16 status;
  210. int count = 0;
  211. while (time_is_after_jiffies(end)) {
  212. ret = s5c73m3_read(state, REG_STATUS, &status);
  213. if (ret < 0 || status == value)
  214. break;
  215. usleep_range(500, 1000);
  216. ++count;
  217. }
  218. if (count > 0)
  219. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  220. "status check took %dms\n",
  221. jiffies_to_msecs(jiffies - start));
  222. if (ret == 0 && status != value) {
  223. u16 i2c_status = 0;
  224. u16 i2c_seq_status = 0;
  225. s5c73m3_read(state, REG_I2C_STATUS, &i2c_status);
  226. s5c73m3_read(state, REG_I2C_SEQ_STATUS, &i2c_seq_status);
  227. v4l2_err(&state->sensor_sd,
  228. "wrong status %#x, expected: %#x, i2c_status: %#x/%#x\n",
  229. status, value, i2c_status, i2c_seq_status);
  230. return -ETIMEDOUT;
  231. }
  232. return ret;
  233. }
  234. int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data)
  235. {
  236. int ret;
  237. ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
  238. if (ret < 0)
  239. return ret;
  240. ret = s5c73m3_write(state, 0x00095000, command);
  241. if (ret < 0)
  242. return ret;
  243. ret = s5c73m3_write(state, 0x00095002, data);
  244. if (ret < 0)
  245. return ret;
  246. return s5c73m3_write(state, REG_STATUS, 0x0001);
  247. }
  248. static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command,
  249. u16 *data)
  250. {
  251. return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data);
  252. }
  253. static int s5c73m3_set_af_softlanding(struct s5c73m3 *state)
  254. {
  255. unsigned long start = jiffies;
  256. u16 af_softlanding;
  257. int count = 0;
  258. int ret;
  259. const char *msg;
  260. ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING,
  261. COMM_AF_SOFTLANDING_ON);
  262. if (ret < 0) {
  263. v4l2_info(&state->sensor_sd, "AF soft-landing failed\n");
  264. return ret;
  265. }
  266. for (;;) {
  267. ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING,
  268. &af_softlanding);
  269. if (ret < 0) {
  270. msg = "failed";
  271. break;
  272. }
  273. if (af_softlanding == COMM_AF_SOFTLANDING_RES_COMPLETE) {
  274. msg = "succeeded";
  275. break;
  276. }
  277. if (++count > 100) {
  278. ret = -ETIME;
  279. msg = "timed out";
  280. break;
  281. }
  282. msleep(25);
  283. }
  284. v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n",
  285. msg, jiffies_to_msecs(jiffies - start));
  286. return ret;
  287. }
  288. static int s5c73m3_load_fw(struct v4l2_subdev *sd)
  289. {
  290. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  291. struct i2c_client *client = state->i2c_client;
  292. const struct firmware *fw;
  293. int ret;
  294. char fw_name[20];
  295. snprintf(fw_name, sizeof(fw_name), "SlimISP_%.2s.bin",
  296. state->fw_file_version);
  297. ret = request_firmware(&fw, fw_name, &client->dev);
  298. if (ret < 0) {
  299. v4l2_err(sd, "Firmware request failed (%s)\n", fw_name);
  300. return -EINVAL;
  301. }
  302. v4l2_info(sd, "Loading firmware (%s, %d B)\n", fw_name, fw->size);
  303. ret = s5c73m3_spi_write(state, fw->data, fw->size, 64);
  304. if (ret >= 0)
  305. state->isp_ready = 1;
  306. else
  307. v4l2_err(sd, "SPI write failed\n");
  308. release_firmware(fw);
  309. return ret;
  310. }
  311. static int s5c73m3_set_frame_size(struct s5c73m3 *state)
  312. {
  313. const struct s5c73m3_frame_size *prev_size =
  314. state->sensor_pix_size[RES_ISP];
  315. const struct s5c73m3_frame_size *cap_size =
  316. state->sensor_pix_size[RES_JPEG];
  317. unsigned int chg_mode;
  318. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  319. "Preview size: %dx%d, reg_val: 0x%x\n",
  320. prev_size->width, prev_size->height, prev_size->reg_val);
  321. chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW;
  322. if (state->mbus_code == S5C73M3_JPEG_FMT) {
  323. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  324. "Capture size: %dx%d, reg_val: 0x%x\n",
  325. cap_size->width, cap_size->height, cap_size->reg_val);
  326. chg_mode |= cap_size->reg_val;
  327. }
  328. return s5c73m3_isp_command(state, COMM_CHG_MODE, chg_mode);
  329. }
  330. static int s5c73m3_set_frame_rate(struct s5c73m3 *state)
  331. {
  332. int ret;
  333. if (state->ctrls.stabilization->val)
  334. return 0;
  335. if (WARN_ON(state->fiv == NULL))
  336. return -EINVAL;
  337. ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, state->fiv->fps_reg);
  338. if (!ret)
  339. state->apply_fiv = 0;
  340. return ret;
  341. }
  342. static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd,
  343. int on)
  344. {
  345. u16 mode;
  346. int ret;
  347. if (on && state->apply_fmt) {
  348. if (state->mbus_code == S5C73M3_JPEG_FMT)
  349. mode = COMM_IMG_OUTPUT_INTERLEAVED;
  350. else
  351. mode = COMM_IMG_OUTPUT_YUV;
  352. ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, mode);
  353. if (!ret)
  354. ret = s5c73m3_set_frame_size(state);
  355. if (ret)
  356. return ret;
  357. state->apply_fmt = 0;
  358. }
  359. ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, !!on);
  360. if (ret)
  361. return ret;
  362. state->streaming = !!on;
  363. if (!on)
  364. return ret;
  365. if (state->apply_fiv) {
  366. ret = s5c73m3_set_frame_rate(state);
  367. if (ret < 0)
  368. v4l2_err(sd, "Error setting frame rate(%d)\n", ret);
  369. }
  370. return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
  371. }
  372. static int s5c73m3_oif_s_stream(struct v4l2_subdev *sd, int on)
  373. {
  374. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  375. int ret;
  376. mutex_lock(&state->lock);
  377. ret = __s5c73m3_s_stream(state, sd, on);
  378. mutex_unlock(&state->lock);
  379. return ret;
  380. }
  381. static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value,
  382. unsigned int delay, unsigned int steps)
  383. {
  384. u16 reg = 0;
  385. while (steps-- > 0) {
  386. int ret = s5c73m3_read(state, 0x30100010, &reg);
  387. if (ret < 0)
  388. return ret;
  389. if (reg == value)
  390. return 0;
  391. usleep_range(delay, delay + 25);
  392. }
  393. return -ETIMEDOUT;
  394. }
  395. static int s5c73m3_read_fw_version(struct s5c73m3 *state)
  396. {
  397. struct v4l2_subdev *sd = &state->sensor_sd;
  398. int i, ret;
  399. u16 data[2];
  400. int offset;
  401. offset = state->isp_ready ? 0x60 : 0;
  402. for (i = 0; i < S5C73M3_SENSOR_FW_LEN / 2; i++) {
  403. ret = s5c73m3_read(state, offset + i * 2, data);
  404. if (ret < 0)
  405. return ret;
  406. state->sensor_fw[i * 2] = (char)(*data & 0xff);
  407. state->sensor_fw[i * 2 + 1] = (char)(*data >> 8);
  408. }
  409. state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0';
  410. for (i = 0; i < S5C73M3_SENSOR_TYPE_LEN / 2; i++) {
  411. ret = s5c73m3_read(state, offset + 6 + i * 2, data);
  412. if (ret < 0)
  413. return ret;
  414. state->sensor_type[i * 2] = (char)(*data & 0xff);
  415. state->sensor_type[i * 2 + 1] = (char)(*data >> 8);
  416. }
  417. state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0';
  418. ret = s5c73m3_read(state, offset + 0x14, data);
  419. if (ret >= 0) {
  420. ret = s5c73m3_read(state, offset + 0x16, data + 1);
  421. if (ret >= 0)
  422. state->fw_size = data[0] + (data[1] << 16);
  423. }
  424. v4l2_info(sd, "Sensor type: %s, FW version: %s\n",
  425. state->sensor_type, state->sensor_fw);
  426. return ret;
  427. }
  428. static int s5c73m3_fw_update_from(struct s5c73m3 *state)
  429. {
  430. struct v4l2_subdev *sd = &state->sensor_sd;
  431. u16 status = COMM_FW_UPDATE_NOT_READY;
  432. int ret;
  433. int count = 0;
  434. v4l2_warn(sd, "Updating F-ROM firmware.\n");
  435. do {
  436. if (status == COMM_FW_UPDATE_NOT_READY) {
  437. ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, 0);
  438. if (ret < 0)
  439. return ret;
  440. }
  441. ret = s5c73m3_read(state, 0x00095906, &status);
  442. if (ret < 0)
  443. return ret;
  444. switch (status) {
  445. case COMM_FW_UPDATE_FAIL:
  446. v4l2_warn(sd, "Updating F-ROM firmware failed.\n");
  447. return -EIO;
  448. case COMM_FW_UPDATE_SUCCESS:
  449. v4l2_warn(sd, "Updating F-ROM firmware finished.\n");
  450. return 0;
  451. }
  452. ++count;
  453. msleep(20);
  454. } while (count < 500);
  455. v4l2_warn(sd, "Updating F-ROM firmware timed-out.\n");
  456. return -ETIMEDOUT;
  457. }
  458. static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw)
  459. {
  460. struct v4l2_subdev *sd = &state->sensor_sd;
  461. int ret;
  462. /* Run ARM MCU */
  463. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  464. if (ret < 0)
  465. return ret;
  466. usleep_range(400, 500);
  467. /* Check booting status */
  468. ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
  469. if (ret < 0) {
  470. v4l2_err(sd, "booting failed: %d\n", ret);
  471. return ret;
  472. }
  473. /* P,M,S and Boot Mode */
  474. ret = s5c73m3_write(state, 0x30100014, 0x2146);
  475. if (ret < 0)
  476. return ret;
  477. ret = s5c73m3_write(state, 0x30100010, 0x210c);
  478. if (ret < 0)
  479. return ret;
  480. usleep_range(200, 250);
  481. /* Check SPI status */
  482. ret = s5c73m3_system_status_wait(state, 0x210d, 100, 300);
  483. if (ret < 0)
  484. v4l2_err(sd, "SPI not ready: %d\n", ret);
  485. /* Firmware download over SPI */
  486. if (load_fw)
  487. s5c73m3_load_fw(sd);
  488. /* MCU reset */
  489. ret = s5c73m3_write(state, 0x30000004, 0xfffd);
  490. if (ret < 0)
  491. return ret;
  492. /* Remap */
  493. ret = s5c73m3_write(state, 0x301000a4, 0x0183);
  494. if (ret < 0)
  495. return ret;
  496. /* MCU restart */
  497. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  498. if (ret < 0 || !load_fw)
  499. return ret;
  500. ret = s5c73m3_read_fw_version(state);
  501. if (ret < 0)
  502. return ret;
  503. if (load_fw && update_fw) {
  504. ret = s5c73m3_fw_update_from(state);
  505. update_fw = 0;
  506. }
  507. return ret;
  508. }
  509. static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state)
  510. {
  511. static const u32 regs[][2] = {
  512. { 0x30100018, 0x0618 },
  513. { 0x3010001c, 0x10c1 },
  514. { 0x30100020, 0x249e }
  515. };
  516. int ret;
  517. int i;
  518. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  519. ret = s5c73m3_write(state, regs[i][0], regs[i][1]);
  520. if (ret < 0)
  521. return ret;
  522. }
  523. return 0;
  524. }
  525. static void s5c73m3_set_fw_file_version(struct s5c73m3 *state)
  526. {
  527. switch (state->sensor_fw[0]) {
  528. case 'G':
  529. case 'O':
  530. state->fw_file_version[0] = 'G';
  531. break;
  532. case 'S':
  533. case 'Z':
  534. state->fw_file_version[0] = 'Z';
  535. break;
  536. }
  537. switch (state->sensor_fw[1]) {
  538. case 'C'...'F':
  539. state->fw_file_version[1] = state->sensor_fw[1];
  540. break;
  541. }
  542. }
  543. static int s5c73m3_get_fw_version(struct s5c73m3 *state)
  544. {
  545. struct v4l2_subdev *sd = &state->sensor_sd;
  546. int ret;
  547. /* Run ARM MCU */
  548. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  549. if (ret < 0)
  550. return ret;
  551. usleep_range(400, 500);
  552. /* Check booting status */
  553. ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
  554. if (ret < 0) {
  555. v4l2_err(sd, "%s: booting failed: %d\n", __func__, ret);
  556. return ret;
  557. }
  558. /* Change I/O Driver Current in order to read from F-ROM */
  559. ret = s5c73m3_write(state, 0x30100120, 0x0820);
  560. ret = s5c73m3_write(state, 0x30100124, 0x0820);
  561. /* Offset Setting */
  562. ret = s5c73m3_write(state, 0x00010418, 0x0008);
  563. /* P,M,S and Boot Mode */
  564. ret = s5c73m3_write(state, 0x30100014, 0x2146);
  565. if (ret < 0)
  566. return ret;
  567. ret = s5c73m3_write(state, 0x30100010, 0x230c);
  568. if (ret < 0)
  569. return ret;
  570. usleep_range(200, 250);
  571. /* Check SPI status */
  572. ret = s5c73m3_system_status_wait(state, 0x230e, 100, 300);
  573. if (ret < 0)
  574. v4l2_err(sd, "SPI not ready: %d\n", ret);
  575. /* ARM reset */
  576. ret = s5c73m3_write(state, 0x30000004, 0xfffd);
  577. if (ret < 0)
  578. return ret;
  579. /* Remap */
  580. ret = s5c73m3_write(state, 0x301000a4, 0x0183);
  581. if (ret < 0)
  582. return ret;
  583. s5c73m3_set_timing_register_for_vdd(state);
  584. ret = s5c73m3_read_fw_version(state);
  585. s5c73m3_set_fw_file_version(state);
  586. return ret;
  587. }
  588. static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw)
  589. {
  590. static const u32 boot_regs[][2] = {
  591. { 0x3100010c, 0x0044 },
  592. { 0x31000108, 0x000d },
  593. { 0x31000304, 0x0001 },
  594. { 0x00010000, 0x5800 },
  595. { 0x00010002, 0x0002 },
  596. { 0x31000000, 0x0001 },
  597. { 0x30100014, 0x1b85 },
  598. { 0x30100010, 0x230c }
  599. };
  600. struct v4l2_subdev *sd = &state->sensor_sd;
  601. int i, ret;
  602. /* Run ARM MCU */
  603. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  604. if (ret < 0)
  605. return ret;
  606. usleep_range(400, 450);
  607. /* Check booting status */
  608. ret = s5c73m3_system_status_wait(state, 0x0c, 100, 4);
  609. if (ret < 0) {
  610. v4l2_err(sd, "Booting failed: %d\n", ret);
  611. return ret;
  612. }
  613. for (i = 0; i < ARRAY_SIZE(boot_regs); i++) {
  614. ret = s5c73m3_write(state, boot_regs[i][0], boot_regs[i][1]);
  615. if (ret < 0)
  616. return ret;
  617. }
  618. msleep(200);
  619. /* Check the binary read status */
  620. ret = s5c73m3_system_status_wait(state, 0x230e, 1000, 150);
  621. if (ret < 0) {
  622. v4l2_err(sd, "Binary read failed: %d\n", ret);
  623. return ret;
  624. }
  625. /* ARM reset */
  626. ret = s5c73m3_write(state, 0x30000004, 0xfffd);
  627. if (ret < 0)
  628. return ret;
  629. /* Remap */
  630. ret = s5c73m3_write(state, 0x301000a4, 0x0183);
  631. if (ret < 0)
  632. return ret;
  633. /* MCU re-start */
  634. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  635. if (ret < 0)
  636. return ret;
  637. state->isp_ready = 1;
  638. return s5c73m3_read_fw_version(state);
  639. }
  640. static int s5c73m3_isp_init(struct s5c73m3 *state)
  641. {
  642. int ret;
  643. state->i2c_read_address = 0;
  644. state->i2c_write_address = 0;
  645. ret = s5c73m3_i2c_write(state->i2c_client, AHB_MSB_ADDR_PTR, 0x3310);
  646. if (ret < 0)
  647. return ret;
  648. if (boot_from_rom)
  649. return s5c73m3_rom_boot(state, true);
  650. else
  651. return s5c73m3_spi_boot(state, true);
  652. }
  653. static const struct s5c73m3_frame_size *s5c73m3_find_frame_size(
  654. struct v4l2_mbus_framefmt *fmt,
  655. enum s5c73m3_resolution_types idx)
  656. {
  657. const struct s5c73m3_frame_size *fs;
  658. const struct s5c73m3_frame_size *best_fs;
  659. int best_dist = INT_MAX;
  660. int i;
  661. fs = s5c73m3_resolutions[idx];
  662. best_fs = NULL;
  663. for (i = 0; i < s5c73m3_resolutions_len[idx]; ++i) {
  664. int dist = abs(fs->width - fmt->width) +
  665. abs(fs->height - fmt->height);
  666. if (dist < best_dist) {
  667. best_dist = dist;
  668. best_fs = fs;
  669. }
  670. ++fs;
  671. }
  672. return best_fs;
  673. }
  674. static void s5c73m3_oif_try_format(struct s5c73m3 *state,
  675. struct v4l2_subdev_fh *fh,
  676. struct v4l2_subdev_format *fmt,
  677. const struct s5c73m3_frame_size **fs)
  678. {
  679. u32 code;
  680. switch (fmt->pad) {
  681. case OIF_ISP_PAD:
  682. *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
  683. code = S5C73M3_ISP_FMT;
  684. break;
  685. case OIF_JPEG_PAD:
  686. *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
  687. code = S5C73M3_JPEG_FMT;
  688. break;
  689. case OIF_SOURCE_PAD:
  690. default:
  691. if (fmt->format.code == S5C73M3_JPEG_FMT)
  692. code = S5C73M3_JPEG_FMT;
  693. else
  694. code = S5C73M3_ISP_FMT;
  695. if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  696. *fs = state->oif_pix_size[RES_ISP];
  697. else
  698. *fs = s5c73m3_find_frame_size(
  699. v4l2_subdev_get_try_format(fh,
  700. OIF_ISP_PAD),
  701. RES_ISP);
  702. break;
  703. }
  704. s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
  705. }
  706. static void s5c73m3_try_format(struct s5c73m3 *state,
  707. struct v4l2_subdev_fh *fh,
  708. struct v4l2_subdev_format *fmt,
  709. const struct s5c73m3_frame_size **fs)
  710. {
  711. u32 code;
  712. if (fmt->pad == S5C73M3_ISP_PAD) {
  713. *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
  714. code = S5C73M3_ISP_FMT;
  715. } else {
  716. *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
  717. code = S5C73M3_JPEG_FMT;
  718. }
  719. s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
  720. }
  721. static int s5c73m3_oif_g_frame_interval(struct v4l2_subdev *sd,
  722. struct v4l2_subdev_frame_interval *fi)
  723. {
  724. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  725. if (fi->pad != OIF_SOURCE_PAD)
  726. return -EINVAL;
  727. mutex_lock(&state->lock);
  728. fi->interval = state->fiv->interval;
  729. mutex_unlock(&state->lock);
  730. return 0;
  731. }
  732. static int __s5c73m3_set_frame_interval(struct s5c73m3 *state,
  733. struct v4l2_subdev_frame_interval *fi)
  734. {
  735. const struct s5c73m3_frame_size *prev_size =
  736. state->sensor_pix_size[RES_ISP];
  737. const struct s5c73m3_interval *fiv = &s5c73m3_intervals[0];
  738. unsigned int ret, min_err = UINT_MAX;
  739. unsigned int i, fr_time;
  740. if (fi->interval.denominator == 0)
  741. return -EINVAL;
  742. fr_time = fi->interval.numerator * 1000 / fi->interval.denominator;
  743. for (i = 0; i < ARRAY_SIZE(s5c73m3_intervals); i++) {
  744. const struct s5c73m3_interval *iv = &s5c73m3_intervals[i];
  745. if (prev_size->width > iv->size.width ||
  746. prev_size->height > iv->size.height)
  747. continue;
  748. ret = abs(iv->interval.numerator / 1000 - fr_time);
  749. if (ret < min_err) {
  750. fiv = iv;
  751. min_err = ret;
  752. }
  753. }
  754. state->fiv = fiv;
  755. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  756. "Changed frame interval to %u us\n", fiv->interval.numerator);
  757. return 0;
  758. }
  759. static int s5c73m3_oif_s_frame_interval(struct v4l2_subdev *sd,
  760. struct v4l2_subdev_frame_interval *fi)
  761. {
  762. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  763. int ret;
  764. if (fi->pad != OIF_SOURCE_PAD)
  765. return -EINVAL;
  766. v4l2_dbg(1, s5c73m3_dbg, sd, "Setting %d/%d frame interval\n",
  767. fi->interval.numerator, fi->interval.denominator);
  768. mutex_lock(&state->lock);
  769. ret = __s5c73m3_set_frame_interval(state, fi);
  770. if (!ret) {
  771. if (state->streaming)
  772. ret = s5c73m3_set_frame_rate(state);
  773. else
  774. state->apply_fiv = 1;
  775. }
  776. mutex_unlock(&state->lock);
  777. return ret;
  778. }
  779. static int s5c73m3_oif_enum_frame_interval(struct v4l2_subdev *sd,
  780. struct v4l2_subdev_fh *fh,
  781. struct v4l2_subdev_frame_interval_enum *fie)
  782. {
  783. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  784. const struct s5c73m3_interval *fi;
  785. int ret = 0;
  786. if (fie->pad != OIF_SOURCE_PAD)
  787. return -EINVAL;
  788. if (fie->index > ARRAY_SIZE(s5c73m3_intervals))
  789. return -EINVAL;
  790. mutex_lock(&state->lock);
  791. fi = &s5c73m3_intervals[fie->index];
  792. if (fie->width > fi->size.width || fie->height > fi->size.height)
  793. ret = -EINVAL;
  794. else
  795. fie->interval = fi->interval;
  796. mutex_unlock(&state->lock);
  797. return ret;
  798. }
  799. static int s5c73m3_oif_get_pad_code(int pad, int index)
  800. {
  801. if (pad == OIF_SOURCE_PAD) {
  802. if (index > 1)
  803. return -EINVAL;
  804. return (index == 0) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
  805. }
  806. if (index > 0)
  807. return -EINVAL;
  808. return (pad == OIF_ISP_PAD) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
  809. }
  810. static int s5c73m3_get_fmt(struct v4l2_subdev *sd,
  811. struct v4l2_subdev_fh *fh,
  812. struct v4l2_subdev_format *fmt)
  813. {
  814. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  815. const struct s5c73m3_frame_size *fs;
  816. u32 code;
  817. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  818. fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
  819. return 0;
  820. }
  821. mutex_lock(&state->lock);
  822. switch (fmt->pad) {
  823. case S5C73M3_ISP_PAD:
  824. code = S5C73M3_ISP_FMT;
  825. fs = state->sensor_pix_size[RES_ISP];
  826. break;
  827. case S5C73M3_JPEG_PAD:
  828. code = S5C73M3_JPEG_FMT;
  829. fs = state->sensor_pix_size[RES_JPEG];
  830. break;
  831. default:
  832. mutex_unlock(&state->lock);
  833. return -EINVAL;
  834. }
  835. s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
  836. mutex_unlock(&state->lock);
  837. return 0;
  838. }
  839. static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd,
  840. struct v4l2_subdev_fh *fh,
  841. struct v4l2_subdev_format *fmt)
  842. {
  843. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  844. const struct s5c73m3_frame_size *fs;
  845. u32 code;
  846. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  847. fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
  848. return 0;
  849. }
  850. mutex_lock(&state->lock);
  851. switch (fmt->pad) {
  852. case OIF_ISP_PAD:
  853. code = S5C73M3_ISP_FMT;
  854. fs = state->oif_pix_size[RES_ISP];
  855. break;
  856. case OIF_JPEG_PAD:
  857. code = S5C73M3_JPEG_FMT;
  858. fs = state->oif_pix_size[RES_JPEG];
  859. break;
  860. case OIF_SOURCE_PAD:
  861. code = state->mbus_code;
  862. fs = state->oif_pix_size[RES_ISP];
  863. break;
  864. default:
  865. mutex_unlock(&state->lock);
  866. return -EINVAL;
  867. }
  868. s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
  869. mutex_unlock(&state->lock);
  870. return 0;
  871. }
  872. static int s5c73m3_set_fmt(struct v4l2_subdev *sd,
  873. struct v4l2_subdev_fh *fh,
  874. struct v4l2_subdev_format *fmt)
  875. {
  876. const struct s5c73m3_frame_size *frame_size = NULL;
  877. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  878. struct v4l2_mbus_framefmt *mf;
  879. int ret = 0;
  880. mutex_lock(&state->lock);
  881. s5c73m3_try_format(state, fh, fmt, &frame_size);
  882. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  883. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  884. *mf = fmt->format;
  885. } else {
  886. switch (fmt->pad) {
  887. case S5C73M3_ISP_PAD:
  888. state->sensor_pix_size[RES_ISP] = frame_size;
  889. break;
  890. case S5C73M3_JPEG_PAD:
  891. state->sensor_pix_size[RES_JPEG] = frame_size;
  892. break;
  893. default:
  894. ret = -EBUSY;
  895. }
  896. if (state->streaming)
  897. ret = -EBUSY;
  898. else
  899. state->apply_fmt = 1;
  900. }
  901. mutex_unlock(&state->lock);
  902. return ret;
  903. }
  904. static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd,
  905. struct v4l2_subdev_fh *fh,
  906. struct v4l2_subdev_format *fmt)
  907. {
  908. const struct s5c73m3_frame_size *frame_size = NULL;
  909. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  910. struct v4l2_mbus_framefmt *mf;
  911. int ret = 0;
  912. mutex_lock(&state->lock);
  913. s5c73m3_oif_try_format(state, fh, fmt, &frame_size);
  914. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  915. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  916. *mf = fmt->format;
  917. } else {
  918. switch (fmt->pad) {
  919. case OIF_ISP_PAD:
  920. state->oif_pix_size[RES_ISP] = frame_size;
  921. break;
  922. case OIF_JPEG_PAD:
  923. state->oif_pix_size[RES_JPEG] = frame_size;
  924. break;
  925. case OIF_SOURCE_PAD:
  926. state->mbus_code = fmt->format.code;
  927. break;
  928. default:
  929. ret = -EBUSY;
  930. }
  931. if (state->streaming)
  932. ret = -EBUSY;
  933. else
  934. state->apply_fmt = 1;
  935. }
  936. mutex_unlock(&state->lock);
  937. return ret;
  938. }
  939. static int s5c73m3_oif_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
  940. struct v4l2_mbus_frame_desc *fd)
  941. {
  942. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  943. int i;
  944. if (pad != OIF_SOURCE_PAD || fd == NULL)
  945. return -EINVAL;
  946. mutex_lock(&state->lock);
  947. fd->num_entries = 2;
  948. for (i = 0; i < fd->num_entries; i++)
  949. fd->entry[i] = state->frame_desc.entry[i];
  950. mutex_unlock(&state->lock);
  951. return 0;
  952. }
  953. static int s5c73m3_oif_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
  954. struct v4l2_mbus_frame_desc *fd)
  955. {
  956. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  957. struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc;
  958. int i;
  959. if (pad != OIF_SOURCE_PAD || fd == NULL)
  960. return -EINVAL;
  961. fd->entry[0].length = 10 * SZ_1M;
  962. fd->entry[1].length = max_t(u32, fd->entry[1].length,
  963. S5C73M3_EMBEDDED_DATA_MAXLEN);
  964. fd->num_entries = 2;
  965. mutex_lock(&state->lock);
  966. for (i = 0; i < fd->num_entries; i++)
  967. frame_desc->entry[i] = fd->entry[i];
  968. mutex_unlock(&state->lock);
  969. return 0;
  970. }
  971. static int s5c73m3_enum_mbus_code(struct v4l2_subdev *sd,
  972. struct v4l2_subdev_fh *fh,
  973. struct v4l2_subdev_mbus_code_enum *code)
  974. {
  975. static const int codes[] = {
  976. [S5C73M3_ISP_PAD] = S5C73M3_ISP_FMT,
  977. [S5C73M3_JPEG_PAD] = S5C73M3_JPEG_FMT};
  978. if (code->index > 0 || code->pad >= S5C73M3_NUM_PADS)
  979. return -EINVAL;
  980. code->code = codes[code->pad];
  981. return 0;
  982. }
  983. static int s5c73m3_oif_enum_mbus_code(struct v4l2_subdev *sd,
  984. struct v4l2_subdev_fh *fh,
  985. struct v4l2_subdev_mbus_code_enum *code)
  986. {
  987. int ret;
  988. ret = s5c73m3_oif_get_pad_code(code->pad, code->index);
  989. if (ret < 0)
  990. return ret;
  991. code->code = ret;
  992. return 0;
  993. }
  994. static int s5c73m3_enum_frame_size(struct v4l2_subdev *sd,
  995. struct v4l2_subdev_fh *fh,
  996. struct v4l2_subdev_frame_size_enum *fse)
  997. {
  998. int idx;
  999. if (fse->pad == S5C73M3_ISP_PAD) {
  1000. if (fse->code != S5C73M3_ISP_FMT)
  1001. return -EINVAL;
  1002. idx = RES_ISP;
  1003. } else{
  1004. if (fse->code != S5C73M3_JPEG_FMT)
  1005. return -EINVAL;
  1006. idx = RES_JPEG;
  1007. }
  1008. if (fse->index >= s5c73m3_resolutions_len[idx])
  1009. return -EINVAL;
  1010. fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
  1011. fse->max_width = fse->min_width;
  1012. fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
  1013. fse->min_height = fse->max_height;
  1014. return 0;
  1015. }
  1016. static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd,
  1017. struct v4l2_subdev_fh *fh,
  1018. struct v4l2_subdev_frame_size_enum *fse)
  1019. {
  1020. int idx;
  1021. if (fse->pad == OIF_SOURCE_PAD) {
  1022. if (fse->index > 0)
  1023. return -EINVAL;
  1024. switch (fse->code) {
  1025. case S5C73M3_JPEG_FMT:
  1026. case S5C73M3_ISP_FMT: {
  1027. struct v4l2_mbus_framefmt *mf =
  1028. v4l2_subdev_get_try_format(fh, OIF_ISP_PAD);
  1029. fse->max_width = fse->min_width = mf->width;
  1030. fse->max_height = fse->min_height = mf->height;
  1031. return 0;
  1032. }
  1033. default:
  1034. return -EINVAL;
  1035. }
  1036. }
  1037. if (fse->code != s5c73m3_oif_get_pad_code(fse->pad, 0))
  1038. return -EINVAL;
  1039. if (fse->pad == OIF_JPEG_PAD)
  1040. idx = RES_JPEG;
  1041. else
  1042. idx = RES_ISP;
  1043. if (fse->index >= s5c73m3_resolutions_len[idx])
  1044. return -EINVAL;
  1045. fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
  1046. fse->max_width = fse->min_width;
  1047. fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
  1048. fse->min_height = fse->max_height;
  1049. return 0;
  1050. }
  1051. static int s5c73m3_oif_log_status(struct v4l2_subdev *sd)
  1052. {
  1053. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1054. v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
  1055. v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power,
  1056. state->apply_fmt);
  1057. return 0;
  1058. }
  1059. static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1060. {
  1061. struct v4l2_mbus_framefmt *mf;
  1062. mf = v4l2_subdev_get_try_format(fh, S5C73M3_ISP_PAD);
  1063. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
  1064. S5C73M3_ISP_FMT);
  1065. mf = v4l2_subdev_get_try_format(fh, S5C73M3_JPEG_PAD);
  1066. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
  1067. S5C73M3_JPEG_FMT);
  1068. return 0;
  1069. }
  1070. static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1071. {
  1072. struct v4l2_mbus_framefmt *mf;
  1073. mf = v4l2_subdev_get_try_format(fh, OIF_ISP_PAD);
  1074. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
  1075. S5C73M3_ISP_FMT);
  1076. mf = v4l2_subdev_get_try_format(fh, OIF_JPEG_PAD);
  1077. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
  1078. S5C73M3_JPEG_FMT);
  1079. mf = v4l2_subdev_get_try_format(fh, OIF_SOURCE_PAD);
  1080. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
  1081. S5C73M3_ISP_FMT);
  1082. return 0;
  1083. }
  1084. static int s5c73m3_gpio_set_value(struct s5c73m3 *priv, int id, u32 val)
  1085. {
  1086. if (!gpio_is_valid(priv->gpio[id].gpio))
  1087. return 0;
  1088. gpio_set_value(priv->gpio[id].gpio, !!val);
  1089. return 1;
  1090. }
  1091. static int s5c73m3_gpio_assert(struct s5c73m3 *priv, int id)
  1092. {
  1093. return s5c73m3_gpio_set_value(priv, id, priv->gpio[id].level);
  1094. }
  1095. static int s5c73m3_gpio_deassert(struct s5c73m3 *priv, int id)
  1096. {
  1097. return s5c73m3_gpio_set_value(priv, id, !priv->gpio[id].level);
  1098. }
  1099. static int __s5c73m3_power_on(struct s5c73m3 *state)
  1100. {
  1101. int i, ret;
  1102. for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) {
  1103. ret = regulator_enable(state->supplies[i].consumer);
  1104. if (ret)
  1105. goto err;
  1106. }
  1107. s5c73m3_gpio_deassert(state, STBY);
  1108. usleep_range(100, 200);
  1109. s5c73m3_gpio_deassert(state, RST);
  1110. usleep_range(50, 100);
  1111. return 0;
  1112. err:
  1113. for (--i; i >= 0; i--)
  1114. regulator_disable(state->supplies[i].consumer);
  1115. return ret;
  1116. }
  1117. static int __s5c73m3_power_off(struct s5c73m3 *state)
  1118. {
  1119. int i, ret;
  1120. if (s5c73m3_gpio_assert(state, RST))
  1121. usleep_range(10, 50);
  1122. if (s5c73m3_gpio_assert(state, STBY))
  1123. usleep_range(100, 200);
  1124. state->streaming = 0;
  1125. state->isp_ready = 0;
  1126. for (i = S5C73M3_MAX_SUPPLIES - 1; i >= 0; i--) {
  1127. ret = regulator_disable(state->supplies[i].consumer);
  1128. if (ret)
  1129. goto err;
  1130. }
  1131. return 0;
  1132. err:
  1133. for (++i; i < S5C73M3_MAX_SUPPLIES; i++)
  1134. regulator_enable(state->supplies[i].consumer);
  1135. return ret;
  1136. }
  1137. static int s5c73m3_oif_set_power(struct v4l2_subdev *sd, int on)
  1138. {
  1139. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1140. int ret = 0;
  1141. mutex_lock(&state->lock);
  1142. if (on && !state->power) {
  1143. ret = __s5c73m3_power_on(state);
  1144. if (!ret)
  1145. ret = s5c73m3_isp_init(state);
  1146. if (!ret) {
  1147. state->apply_fiv = 1;
  1148. state->apply_fmt = 1;
  1149. }
  1150. } else if (!on == state->power) {
  1151. ret = s5c73m3_set_af_softlanding(state);
  1152. if (!ret)
  1153. ret = __s5c73m3_power_off(state);
  1154. else
  1155. v4l2_err(sd, "Soft landing lens failed\n");
  1156. }
  1157. if (!ret)
  1158. state->power += on ? 1 : -1;
  1159. v4l2_dbg(1, s5c73m3_dbg, sd, "%s: power: %d\n",
  1160. __func__, state->power);
  1161. mutex_unlock(&state->lock);
  1162. return ret;
  1163. }
  1164. static int s5c73m3_oif_registered(struct v4l2_subdev *sd)
  1165. {
  1166. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1167. int ret;
  1168. ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->sensor_sd);
  1169. if (ret) {
  1170. v4l2_err(sd->v4l2_dev, "Failed to register %s\n",
  1171. state->oif_sd.name);
  1172. return ret;
  1173. }
  1174. ret = media_entity_create_link(&state->sensor_sd.entity,
  1175. S5C73M3_ISP_PAD, &state->oif_sd.entity, OIF_ISP_PAD,
  1176. MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
  1177. ret = media_entity_create_link(&state->sensor_sd.entity,
  1178. S5C73M3_JPEG_PAD, &state->oif_sd.entity, OIF_JPEG_PAD,
  1179. MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
  1180. mutex_lock(&state->lock);
  1181. ret = __s5c73m3_power_on(state);
  1182. if (ret == 0)
  1183. s5c73m3_get_fw_version(state);
  1184. __s5c73m3_power_off(state);
  1185. mutex_unlock(&state->lock);
  1186. v4l2_dbg(1, s5c73m3_dbg, sd, "%s: Booting %s (%d)\n",
  1187. __func__, ret ? "failed" : "succeded", ret);
  1188. return ret;
  1189. }
  1190. static const struct v4l2_subdev_internal_ops s5c73m3_internal_ops = {
  1191. .open = s5c73m3_open,
  1192. };
  1193. static const struct v4l2_subdev_pad_ops s5c73m3_pad_ops = {
  1194. .enum_mbus_code = s5c73m3_enum_mbus_code,
  1195. .enum_frame_size = s5c73m3_enum_frame_size,
  1196. .get_fmt = s5c73m3_get_fmt,
  1197. .set_fmt = s5c73m3_set_fmt,
  1198. };
  1199. static const struct v4l2_subdev_ops s5c73m3_subdev_ops = {
  1200. .pad = &s5c73m3_pad_ops,
  1201. };
  1202. static const struct v4l2_subdev_internal_ops oif_internal_ops = {
  1203. .registered = s5c73m3_oif_registered,
  1204. .open = s5c73m3_oif_open,
  1205. };
  1206. static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = {
  1207. .enum_mbus_code = s5c73m3_oif_enum_mbus_code,
  1208. .enum_frame_size = s5c73m3_oif_enum_frame_size,
  1209. .enum_frame_interval = s5c73m3_oif_enum_frame_interval,
  1210. .get_fmt = s5c73m3_oif_get_fmt,
  1211. .set_fmt = s5c73m3_oif_set_fmt,
  1212. .get_frame_desc = s5c73m3_oif_get_frame_desc,
  1213. .set_frame_desc = s5c73m3_oif_set_frame_desc,
  1214. };
  1215. static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = {
  1216. .s_power = s5c73m3_oif_set_power,
  1217. .log_status = s5c73m3_oif_log_status,
  1218. };
  1219. static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = {
  1220. .s_stream = s5c73m3_oif_s_stream,
  1221. .g_frame_interval = s5c73m3_oif_g_frame_interval,
  1222. .s_frame_interval = s5c73m3_oif_s_frame_interval,
  1223. };
  1224. static const struct v4l2_subdev_ops oif_subdev_ops = {
  1225. .core = &s5c73m3_oif_core_ops,
  1226. .pad = &s5c73m3_oif_pad_ops,
  1227. .video = &s5c73m3_oif_video_ops,
  1228. };
  1229. static int s5c73m3_configure_gpio(int nr, int val, const char *name)
  1230. {
  1231. unsigned long flags = val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
  1232. int ret;
  1233. if (!gpio_is_valid(nr))
  1234. return 0;
  1235. ret = gpio_request_one(nr, flags, name);
  1236. if (!ret)
  1237. gpio_export(nr, 0);
  1238. return ret;
  1239. }
  1240. static int s5c73m3_free_gpios(struct s5c73m3 *state)
  1241. {
  1242. int i;
  1243. for (i = 0; i < ARRAY_SIZE(state->gpio); i++) {
  1244. if (!gpio_is_valid(state->gpio[i].gpio))
  1245. continue;
  1246. gpio_free(state->gpio[i].gpio);
  1247. state->gpio[i].gpio = -EINVAL;
  1248. }
  1249. return 0;
  1250. }
  1251. static int s5c73m3_configure_gpios(struct s5c73m3 *state,
  1252. const struct s5c73m3_platform_data *pdata)
  1253. {
  1254. const struct s5c73m3_gpio *gpio = &pdata->gpio_stby;
  1255. int ret;
  1256. state->gpio[STBY].gpio = -EINVAL;
  1257. state->gpio[RST].gpio = -EINVAL;
  1258. ret = s5c73m3_configure_gpio(gpio->gpio, gpio->level, "S5C73M3_STBY");
  1259. if (ret) {
  1260. s5c73m3_free_gpios(state);
  1261. return ret;
  1262. }
  1263. state->gpio[STBY] = *gpio;
  1264. if (gpio_is_valid(gpio->gpio))
  1265. gpio_set_value(gpio->gpio, 0);
  1266. gpio = &pdata->gpio_reset;
  1267. ret = s5c73m3_configure_gpio(gpio->gpio, gpio->level, "S5C73M3_RST");
  1268. if (ret) {
  1269. s5c73m3_free_gpios(state);
  1270. return ret;
  1271. }
  1272. state->gpio[RST] = *gpio;
  1273. if (gpio_is_valid(gpio->gpio))
  1274. gpio_set_value(gpio->gpio, 0);
  1275. return 0;
  1276. }
  1277. static int s5c73m3_probe(struct i2c_client *client,
  1278. const struct i2c_device_id *id)
  1279. {
  1280. struct device *dev = &client->dev;
  1281. const struct s5c73m3_platform_data *pdata = client->dev.platform_data;
  1282. struct v4l2_subdev *sd;
  1283. struct v4l2_subdev *oif_sd;
  1284. struct s5c73m3 *state;
  1285. int ret, i;
  1286. if (pdata == NULL) {
  1287. dev_err(&client->dev, "Platform data not specified\n");
  1288. return -EINVAL;
  1289. }
  1290. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  1291. if (!state)
  1292. return -ENOMEM;
  1293. mutex_init(&state->lock);
  1294. sd = &state->sensor_sd;
  1295. oif_sd = &state->oif_sd;
  1296. v4l2_subdev_init(sd, &s5c73m3_subdev_ops);
  1297. sd->owner = client->driver->driver.owner;
  1298. v4l2_set_subdevdata(sd, state);
  1299. strlcpy(sd->name, "S5C73M3", sizeof(sd->name));
  1300. sd->internal_ops = &s5c73m3_internal_ops;
  1301. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1302. state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE;
  1303. state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE;
  1304. sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
  1305. ret = media_entity_init(&sd->entity, S5C73M3_NUM_PADS,
  1306. state->sensor_pads, 0);
  1307. if (ret < 0)
  1308. return ret;
  1309. v4l2_i2c_subdev_init(oif_sd, client, &oif_subdev_ops);
  1310. strcpy(oif_sd->name, "S5C73M3-OIF");
  1311. oif_sd->internal_ops = &oif_internal_ops;
  1312. oif_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1313. state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK;
  1314. state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK;
  1315. state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE;
  1316. oif_sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
  1317. ret = media_entity_init(&oif_sd->entity, OIF_NUM_PADS,
  1318. state->oif_pads, 0);
  1319. if (ret < 0)
  1320. return ret;
  1321. state->mclk_frequency = pdata->mclk_frequency;
  1322. state->bus_type = pdata->bus_type;
  1323. ret = s5c73m3_configure_gpios(state, pdata);
  1324. if (ret)
  1325. goto out_err1;
  1326. for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++)
  1327. state->supplies[i].supply = s5c73m3_supply_names[i];
  1328. ret = devm_regulator_bulk_get(dev, S5C73M3_MAX_SUPPLIES,
  1329. state->supplies);
  1330. if (ret) {
  1331. dev_err(dev, "failed to get regulators\n");
  1332. goto out_err2;
  1333. }
  1334. ret = s5c73m3_init_controls(state);
  1335. if (ret)
  1336. goto out_err2;
  1337. state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1];
  1338. state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1];
  1339. state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP];
  1340. state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG];
  1341. state->mbus_code = S5C73M3_ISP_FMT;
  1342. state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL];
  1343. state->fw_file_version[0] = 'G';
  1344. state->fw_file_version[1] = 'C';
  1345. ret = s5c73m3_register_spi_driver(state);
  1346. if (ret < 0)
  1347. goto out_err2;
  1348. state->i2c_client = client;
  1349. v4l2_info(sd, "%s: completed succesfully\n", __func__);
  1350. return 0;
  1351. out_err2:
  1352. s5c73m3_free_gpios(state);
  1353. out_err1:
  1354. media_entity_cleanup(&sd->entity);
  1355. return ret;
  1356. }
  1357. static int s5c73m3_remove(struct i2c_client *client)
  1358. {
  1359. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1360. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  1361. v4l2_device_unregister_subdev(sd);
  1362. v4l2_ctrl_handler_free(sd->ctrl_handler);
  1363. media_entity_cleanup(&sd->entity);
  1364. s5c73m3_unregister_spi_driver(state);
  1365. s5c73m3_free_gpios(state);
  1366. return 0;
  1367. }
  1368. static const struct i2c_device_id s5c73m3_id[] = {
  1369. { DRIVER_NAME, 0 },
  1370. { }
  1371. };
  1372. MODULE_DEVICE_TABLE(i2c, s5c73m3_id);
  1373. static struct i2c_driver s5c73m3_i2c_driver = {
  1374. .driver = {
  1375. .name = DRIVER_NAME,
  1376. },
  1377. .probe = s5c73m3_probe,
  1378. .remove = s5c73m3_remove,
  1379. .id_table = s5c73m3_id,
  1380. };
  1381. module_i2c_driver(s5c73m3_i2c_driver);
  1382. MODULE_DESCRIPTION("Samsung S5C73M3 camera driver");
  1383. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  1384. MODULE_LICENSE("GPL");