nv10_fence.c 5.0 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs <bskeggs@redhat.com>
  23. */
  24. #include <core/object.h>
  25. #include <core/class.h>
  26. #include "nouveau_drm.h"
  27. #include "nouveau_dma.h"
  28. #include "nouveau_fence.h"
  29. struct nv10_fence_chan {
  30. struct nouveau_fence_chan base;
  31. };
  32. struct nv10_fence_priv {
  33. struct nouveau_fence_priv base;
  34. struct nouveau_bo *bo;
  35. spinlock_t lock;
  36. u32 sequence;
  37. };
  38. int
  39. nv10_fence_emit(struct nouveau_fence *fence)
  40. {
  41. struct nouveau_channel *chan = fence->channel;
  42. int ret = RING_SPACE(chan, 2);
  43. if (ret == 0) {
  44. BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1);
  45. OUT_RING (chan, fence->sequence);
  46. FIRE_RING (chan);
  47. }
  48. return ret;
  49. }
  50. static int
  51. nv10_fence_sync(struct nouveau_fence *fence,
  52. struct nouveau_channel *prev, struct nouveau_channel *chan)
  53. {
  54. return -ENODEV;
  55. }
  56. int
  57. nv17_fence_sync(struct nouveau_fence *fence,
  58. struct nouveau_channel *prev, struct nouveau_channel *chan)
  59. {
  60. struct nv10_fence_priv *priv = chan->drm->fence;
  61. u32 value;
  62. int ret;
  63. if (!mutex_trylock(&prev->cli->mutex))
  64. return -EBUSY;
  65. spin_lock(&priv->lock);
  66. value = priv->sequence;
  67. priv->sequence += 2;
  68. spin_unlock(&priv->lock);
  69. ret = RING_SPACE(prev, 5);
  70. if (!ret) {
  71. BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
  72. OUT_RING (prev, NvSema);
  73. OUT_RING (prev, 0);
  74. OUT_RING (prev, value + 0);
  75. OUT_RING (prev, value + 1);
  76. FIRE_RING (prev);
  77. }
  78. if (!ret && !(ret = RING_SPACE(chan, 5))) {
  79. BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
  80. OUT_RING (chan, NvSema);
  81. OUT_RING (chan, 0);
  82. OUT_RING (chan, value + 1);
  83. OUT_RING (chan, value + 2);
  84. FIRE_RING (chan);
  85. }
  86. mutex_unlock(&prev->cli->mutex);
  87. return 0;
  88. }
  89. u32
  90. nv10_fence_read(struct nouveau_channel *chan)
  91. {
  92. return nv_ro32(chan->object, 0x0048);
  93. }
  94. void
  95. nv10_fence_context_del(struct nouveau_channel *chan)
  96. {
  97. struct nv10_fence_chan *fctx = chan->fence;
  98. nouveau_fence_context_del(&fctx->base);
  99. chan->fence = NULL;
  100. kfree(fctx);
  101. }
  102. static int
  103. nv10_fence_context_new(struct nouveau_channel *chan)
  104. {
  105. struct nv10_fence_priv *priv = chan->drm->fence;
  106. struct nv10_fence_chan *fctx;
  107. int ret = 0;
  108. fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
  109. if (!fctx)
  110. return -ENOMEM;
  111. nouveau_fence_context_new(&fctx->base);
  112. if (priv->bo) {
  113. struct ttm_mem_reg *mem = &priv->bo->bo.mem;
  114. struct nouveau_object *object;
  115. u32 start = mem->start * PAGE_SIZE;
  116. u32 limit = mem->start + mem->size - 1;
  117. ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
  118. NvSema, 0x0002,
  119. &(struct nv_dma_class) {
  120. .flags = NV_DMA_TARGET_VRAM |
  121. NV_DMA_ACCESS_RDWR,
  122. .start = start,
  123. .limit = limit,
  124. }, sizeof(struct nv_dma_class),
  125. &object);
  126. }
  127. if (ret)
  128. nv10_fence_context_del(chan);
  129. return ret;
  130. }
  131. void
  132. nv10_fence_destroy(struct nouveau_drm *drm)
  133. {
  134. struct nv10_fence_priv *priv = drm->fence;
  135. nouveau_bo_unmap(priv->bo);
  136. if (priv->bo)
  137. nouveau_bo_unpin(priv->bo);
  138. nouveau_bo_ref(NULL, &priv->bo);
  139. drm->fence = NULL;
  140. kfree(priv);
  141. }
  142. int
  143. nv10_fence_create(struct nouveau_drm *drm)
  144. {
  145. struct nv10_fence_priv *priv;
  146. int ret = 0;
  147. priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
  148. if (!priv)
  149. return -ENOMEM;
  150. priv->base.dtor = nv10_fence_destroy;
  151. priv->base.context_new = nv10_fence_context_new;
  152. priv->base.context_del = nv10_fence_context_del;
  153. priv->base.emit = nv10_fence_emit;
  154. priv->base.read = nv10_fence_read;
  155. priv->base.sync = nv10_fence_sync;
  156. spin_lock_init(&priv->lock);
  157. if (nv_device(drm->device)->chipset >= 0x17) {
  158. ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
  159. 0, 0x0000, NULL, &priv->bo);
  160. if (!ret) {
  161. ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
  162. if (!ret) {
  163. ret = nouveau_bo_map(priv->bo);
  164. if (ret)
  165. nouveau_bo_unpin(priv->bo);
  166. }
  167. if (ret)
  168. nouveau_bo_ref(NULL, &priv->bo);
  169. }
  170. if (ret == 0) {
  171. nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
  172. priv->base.sync = nv17_fence_sync;
  173. }
  174. }
  175. if (ret)
  176. nv10_fence_destroy(drm);
  177. return ret;
  178. }