Kconfig 10 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. config EDAC_SUPPORT
  7. bool
  8. menuconfig EDAC
  9. bool "EDAC (Error Detection And Correction) reporting"
  10. depends on HAS_IOMEM
  11. depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
  12. help
  13. EDAC is designed to report errors in the core system.
  14. These are low-level errors that are reported in the CPU or
  15. supporting chipset or other subsystems:
  16. memory errors, cache errors, PCI errors, thermal throttling, etc..
  17. If unsure, select 'Y'.
  18. If this code is reporting problems on your system, please
  19. see the EDAC project web pages for more information at:
  20. <http://bluesmoke.sourceforge.net/>
  21. and:
  22. <http://buttersideup.com/edacwiki>
  23. There is also a mailing list for the EDAC project, which can
  24. be found via the sourceforge page.
  25. if EDAC
  26. config EDAC_LEGACY_SYSFS
  27. bool "EDAC legacy sysfs"
  28. default y
  29. help
  30. Enable the compatibility sysfs nodes.
  31. Use 'Y' if your edac utilities aren't ported to work with the newer
  32. structures.
  33. config EDAC_DEBUG
  34. bool "Debugging"
  35. help
  36. This turns on debugging information for the entire EDAC subsystem.
  37. You do so by inserting edac_module with "edac_debug_level=x." Valid
  38. levels are 0-4 (from low to high) and by default it is set to 2.
  39. Usually you should select 'N' here.
  40. config EDAC_DECODE_MCE
  41. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  42. depends on CPU_SUP_AMD && X86_MCE_AMD
  43. default y
  44. ---help---
  45. Enable this option if you want to decode Machine Check Exceptions
  46. occurring on your machine in human-readable form.
  47. You should definitely say Y here in case you want to decode MCEs
  48. which occur really early upon boot, before the module infrastructure
  49. has been initialized.
  50. config EDAC_MCE_INJ
  51. tristate "Simple MCE injection interface over /sysfs"
  52. depends on EDAC_DECODE_MCE
  53. default n
  54. help
  55. This is a simple interface to inject MCEs over /sysfs and test
  56. the MCE decoding code in EDAC.
  57. This is currently AMD-only.
  58. config EDAC_MM_EDAC
  59. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  60. help
  61. Some systems are able to detect and correct errors in main
  62. memory. EDAC can report statistics on memory error
  63. detection and correction (EDAC - or commonly referred to ECC
  64. errors). EDAC will also try to decode where these errors
  65. occurred so that a particular failing memory module can be
  66. replaced. If unsure, select 'Y'.
  67. config EDAC_AMD64
  68. tristate "AMD64 (Opteron, Athlon64) K8, F10h"
  69. depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
  70. help
  71. Support for error detection and correction of DRAM ECC errors on
  72. the AMD64 families of memory controllers (K8 and F10h)
  73. config EDAC_AMD64_ERROR_INJECTION
  74. bool "Sysfs HW Error injection facilities"
  75. depends on EDAC_AMD64
  76. help
  77. Recent Opterons (Family 10h and later) provide for Memory Error
  78. Injection into the ECC detection circuits. The amd64_edac module
  79. allows the operator/user to inject Uncorrectable and Correctable
  80. errors into DRAM.
  81. When enabled, in each of the respective memory controller directories
  82. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  83. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  84. - inject_word (0..8, 16-bit word of 16-byte section),
  85. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  86. In addition, there are two control files, inject_read and inject_write,
  87. which trigger the DRAM ECC Read and Write respectively.
  88. config EDAC_AMD76X
  89. tristate "AMD 76x (760, 762, 768)"
  90. depends on EDAC_MM_EDAC && PCI && X86_32
  91. help
  92. Support for error detection and correction on the AMD 76x
  93. series of chipsets used with the Athlon processor.
  94. config EDAC_E7XXX
  95. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  96. depends on EDAC_MM_EDAC && PCI && X86_32
  97. help
  98. Support for error detection and correction on the Intel
  99. E7205, E7500, E7501 and E7505 server chipsets.
  100. config EDAC_E752X
  101. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  102. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  103. help
  104. Support for error detection and correction on the Intel
  105. E7520, E7525, E7320 server chipsets.
  106. config EDAC_I82443BXGX
  107. tristate "Intel 82443BX/GX (440BX/GX)"
  108. depends on EDAC_MM_EDAC && PCI && X86_32
  109. depends on BROKEN
  110. help
  111. Support for error detection and correction on the Intel
  112. 82443BX/GX memory controllers (440BX/GX chipsets).
  113. config EDAC_I82875P
  114. tristate "Intel 82875p (D82875P, E7210)"
  115. depends on EDAC_MM_EDAC && PCI && X86_32
  116. help
  117. Support for error detection and correction on the Intel
  118. DP82785P and E7210 server chipsets.
  119. config EDAC_I82975X
  120. tristate "Intel 82975x (D82975x)"
  121. depends on EDAC_MM_EDAC && PCI && X86
  122. help
  123. Support for error detection and correction on the Intel
  124. DP82975x server chipsets.
  125. config EDAC_I3000
  126. tristate "Intel 3000/3010"
  127. depends on EDAC_MM_EDAC && PCI && X86
  128. help
  129. Support for error detection and correction on the Intel
  130. 3000 and 3010 server chipsets.
  131. config EDAC_I3200
  132. tristate "Intel 3200"
  133. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  134. help
  135. Support for error detection and correction on the Intel
  136. 3200 and 3210 server chipsets.
  137. config EDAC_X38
  138. tristate "Intel X38"
  139. depends on EDAC_MM_EDAC && PCI && X86
  140. help
  141. Support for error detection and correction on the Intel
  142. X38 server chipsets.
  143. config EDAC_I5400
  144. tristate "Intel 5400 (Seaburg) chipsets"
  145. depends on EDAC_MM_EDAC && PCI && X86
  146. help
  147. Support for error detection and correction the Intel
  148. i5400 MCH chipset (Seaburg).
  149. config EDAC_I7CORE
  150. tristate "Intel i7 Core (Nehalem) processors"
  151. depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
  152. help
  153. Support for error detection and correction the Intel
  154. i7 Core (Nehalem) Integrated Memory Controller that exists on
  155. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  156. and Xeon 55xx processors.
  157. config EDAC_I82860
  158. tristate "Intel 82860"
  159. depends on EDAC_MM_EDAC && PCI && X86_32
  160. help
  161. Support for error detection and correction on the Intel
  162. 82860 chipset.
  163. config EDAC_R82600
  164. tristate "Radisys 82600 embedded chipset"
  165. depends on EDAC_MM_EDAC && PCI && X86_32
  166. help
  167. Support for error detection and correction on the Radisys
  168. 82600 embedded chipset.
  169. config EDAC_I5000
  170. tristate "Intel Greencreek/Blackford chipset"
  171. depends on EDAC_MM_EDAC && X86 && PCI
  172. help
  173. Support for error detection and correction the Intel
  174. Greekcreek/Blackford chipsets.
  175. config EDAC_I5100
  176. tristate "Intel San Clemente MCH"
  177. depends on EDAC_MM_EDAC && X86 && PCI
  178. help
  179. Support for error detection and correction the Intel
  180. San Clemente MCH.
  181. config EDAC_I7300
  182. tristate "Intel Clarksboro MCH"
  183. depends on EDAC_MM_EDAC && X86 && PCI
  184. help
  185. Support for error detection and correction the Intel
  186. Clarksboro MCH (Intel 7300 chipset).
  187. config EDAC_SBRIDGE
  188. tristate "Intel Sandy-Bridge Integrated MC"
  189. depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
  190. depends on PCI_MMCONFIG && EXPERIMENTAL
  191. help
  192. Support for error detection and correction the Intel
  193. Sandy Bridge Integrated Memory Controller.
  194. config EDAC_MPC85XX
  195. tristate "Freescale MPC83xx / MPC85xx"
  196. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
  197. help
  198. Support for error detection and correction on the Freescale
  199. MPC8349, MPC8560, MPC8540, MPC8548
  200. config EDAC_MV64X60
  201. tristate "Marvell MV64x60"
  202. depends on EDAC_MM_EDAC && MV64X60
  203. help
  204. Support for error detection and correction on the Marvell
  205. MV64360 and MV64460 chipsets.
  206. config EDAC_PASEMI
  207. tristate "PA Semi PWRficient"
  208. depends on EDAC_MM_EDAC && PCI
  209. depends on PPC_PASEMI
  210. help
  211. Support for error detection and correction on PA Semi
  212. PWRficient.
  213. config EDAC_CELL
  214. tristate "Cell Broadband Engine memory controller"
  215. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  216. help
  217. Support for error detection and correction on the
  218. Cell Broadband Engine internal memory controller
  219. on platform without a hypervisor
  220. config EDAC_PPC4XX
  221. tristate "PPC4xx IBM DDR2 Memory Controller"
  222. depends on EDAC_MM_EDAC && 4xx
  223. help
  224. This enables support for EDAC on the ECC memory used
  225. with the IBM DDR2 memory controller found in various
  226. PowerPC 4xx embedded processors such as the 405EX[r],
  227. 440SP, 440SPe, 460EX, 460GT and 460SX.
  228. config EDAC_AMD8131
  229. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  230. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  231. help
  232. Support for error detection and correction on the
  233. AMD8131 HyperTransport PCI-X Tunnel chip.
  234. Note, add more Kconfig dependency if it's adopted
  235. on some machine other than Maple.
  236. config EDAC_AMD8111
  237. tristate "AMD8111 HyperTransport I/O Hub"
  238. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  239. help
  240. Support for error detection and correction on the
  241. AMD8111 HyperTransport I/O Hub chip.
  242. Note, add more Kconfig dependency if it's adopted
  243. on some machine other than Maple.
  244. config EDAC_CPC925
  245. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  246. depends on EDAC_MM_EDAC && PPC64
  247. help
  248. Support for error detection and correction on the
  249. IBM CPC925 Bridge and Memory Controller, which is
  250. a companion chip to the PowerPC 970 family of
  251. processors.
  252. config EDAC_TILE
  253. tristate "Tilera Memory Controller"
  254. depends on EDAC_MM_EDAC && TILE
  255. default y
  256. help
  257. Support for error detection and correction on the
  258. Tilera memory controller.
  259. config EDAC_HIGHBANK_MC
  260. tristate "Highbank Memory Controller"
  261. depends on EDAC_MM_EDAC && ARCH_HIGHBANK
  262. help
  263. Support for error detection and correction on the
  264. Calxeda Highbank memory controller.
  265. config EDAC_HIGHBANK_L2
  266. tristate "Highbank L2 Cache"
  267. depends on EDAC_MM_EDAC && ARCH_HIGHBANK
  268. help
  269. Support for error detection and correction on the
  270. Calxeda Highbank memory controller.
  271. config EDAC_OCTEON_PC
  272. tristate "Cavium Octeon Primary Caches"
  273. depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
  274. help
  275. Support for error detection and correction on the primary caches of
  276. the cnMIPS cores of Cavium Octeon family SOCs.
  277. config EDAC_OCTEON_L2C
  278. tristate "Cavium Octeon Secondary Caches (L2C)"
  279. depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
  280. help
  281. Support for error detection and correction on the
  282. Cavium Octeon family of SOCs.
  283. config EDAC_OCTEON_LMC
  284. tristate "Cavium Octeon DRAM Memory Controller (LMC)"
  285. depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
  286. help
  287. Support for error detection and correction on the
  288. Cavium Octeon family of SOCs.
  289. config EDAC_OCTEON_PCI
  290. tristate "Cavium Octeon PCI Controller"
  291. depends on EDAC_MM_EDAC && PCI && CPU_CAVIUM_OCTEON
  292. help
  293. Support for error detection and correction on the
  294. Cavium Octeon family of SOCs.
  295. endif # EDAC