dmatest.c 18 KB

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  1. /*
  2. * DMA Engine test module
  3. *
  4. * Copyright (C) 2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/dmaengine.h>
  13. #include <linux/freezer.h>
  14. #include <linux/init.h>
  15. #include <linux/kthread.h>
  16. #include <linux/module.h>
  17. #include <linux/moduleparam.h>
  18. #include <linux/random.h>
  19. #include <linux/slab.h>
  20. #include <linux/wait.h>
  21. static unsigned int test_buf_size = 16384;
  22. module_param(test_buf_size, uint, S_IRUGO);
  23. MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
  24. static char test_channel[20];
  25. module_param_string(channel, test_channel, sizeof(test_channel), S_IRUGO);
  26. MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
  27. static char test_device[20];
  28. module_param_string(device, test_device, sizeof(test_device), S_IRUGO);
  29. MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
  30. static unsigned int threads_per_chan = 1;
  31. module_param(threads_per_chan, uint, S_IRUGO);
  32. MODULE_PARM_DESC(threads_per_chan,
  33. "Number of threads to start per channel (default: 1)");
  34. static unsigned int max_channels;
  35. module_param(max_channels, uint, S_IRUGO);
  36. MODULE_PARM_DESC(max_channels,
  37. "Maximum number of channels to use (default: all)");
  38. static unsigned int iterations;
  39. module_param(iterations, uint, S_IRUGO);
  40. MODULE_PARM_DESC(iterations,
  41. "Iterations before stopping test (default: infinite)");
  42. static unsigned int xor_sources = 3;
  43. module_param(xor_sources, uint, S_IRUGO);
  44. MODULE_PARM_DESC(xor_sources,
  45. "Number of xor source buffers (default: 3)");
  46. static unsigned int pq_sources = 3;
  47. module_param(pq_sources, uint, S_IRUGO);
  48. MODULE_PARM_DESC(pq_sources,
  49. "Number of p+q source buffers (default: 3)");
  50. static int timeout = 3000;
  51. module_param(timeout, uint, S_IRUGO);
  52. MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
  53. "Pass -1 for infinite timeout");
  54. /*
  55. * Initialization patterns. All bytes in the source buffer has bit 7
  56. * set, all bytes in the destination buffer has bit 7 cleared.
  57. *
  58. * Bit 6 is set for all bytes which are to be copied by the DMA
  59. * engine. Bit 5 is set for all bytes which are to be overwritten by
  60. * the DMA engine.
  61. *
  62. * The remaining bits are the inverse of a counter which increments by
  63. * one for each byte address.
  64. */
  65. #define PATTERN_SRC 0x80
  66. #define PATTERN_DST 0x00
  67. #define PATTERN_COPY 0x40
  68. #define PATTERN_OVERWRITE 0x20
  69. #define PATTERN_COUNT_MASK 0x1f
  70. struct dmatest_thread {
  71. struct list_head node;
  72. struct task_struct *task;
  73. struct dma_chan *chan;
  74. u8 **srcs;
  75. u8 **dsts;
  76. enum dma_transaction_type type;
  77. };
  78. struct dmatest_chan {
  79. struct list_head node;
  80. struct dma_chan *chan;
  81. struct list_head threads;
  82. };
  83. /*
  84. * These are protected by dma_list_mutex since they're only used by
  85. * the DMA filter function callback
  86. */
  87. static LIST_HEAD(dmatest_channels);
  88. static unsigned int nr_channels;
  89. static bool dmatest_match_channel(struct dma_chan *chan)
  90. {
  91. if (test_channel[0] == '\0')
  92. return true;
  93. return strcmp(dma_chan_name(chan), test_channel) == 0;
  94. }
  95. static bool dmatest_match_device(struct dma_device *device)
  96. {
  97. if (test_device[0] == '\0')
  98. return true;
  99. return strcmp(dev_name(device->dev), test_device) == 0;
  100. }
  101. static unsigned long dmatest_random(void)
  102. {
  103. unsigned long buf;
  104. get_random_bytes(&buf, sizeof(buf));
  105. return buf;
  106. }
  107. static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len)
  108. {
  109. unsigned int i;
  110. u8 *buf;
  111. for (; (buf = *bufs); bufs++) {
  112. for (i = 0; i < start; i++)
  113. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  114. for ( ; i < start + len; i++)
  115. buf[i] = PATTERN_SRC | PATTERN_COPY
  116. | (~i & PATTERN_COUNT_MASK);
  117. for ( ; i < test_buf_size; i++)
  118. buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK);
  119. buf++;
  120. }
  121. }
  122. static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len)
  123. {
  124. unsigned int i;
  125. u8 *buf;
  126. for (; (buf = *bufs); bufs++) {
  127. for (i = 0; i < start; i++)
  128. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  129. for ( ; i < start + len; i++)
  130. buf[i] = PATTERN_DST | PATTERN_OVERWRITE
  131. | (~i & PATTERN_COUNT_MASK);
  132. for ( ; i < test_buf_size; i++)
  133. buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK);
  134. }
  135. }
  136. static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
  137. unsigned int counter, bool is_srcbuf)
  138. {
  139. u8 diff = actual ^ pattern;
  140. u8 expected = pattern | (~counter & PATTERN_COUNT_MASK);
  141. const char *thread_name = current->comm;
  142. if (is_srcbuf)
  143. pr_warning("%s: srcbuf[0x%x] overwritten!"
  144. " Expected %02x, got %02x\n",
  145. thread_name, index, expected, actual);
  146. else if ((pattern & PATTERN_COPY)
  147. && (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
  148. pr_warning("%s: dstbuf[0x%x] not copied!"
  149. " Expected %02x, got %02x\n",
  150. thread_name, index, expected, actual);
  151. else if (diff & PATTERN_SRC)
  152. pr_warning("%s: dstbuf[0x%x] was copied!"
  153. " Expected %02x, got %02x\n",
  154. thread_name, index, expected, actual);
  155. else
  156. pr_warning("%s: dstbuf[0x%x] mismatch!"
  157. " Expected %02x, got %02x\n",
  158. thread_name, index, expected, actual);
  159. }
  160. static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
  161. unsigned int end, unsigned int counter, u8 pattern,
  162. bool is_srcbuf)
  163. {
  164. unsigned int i;
  165. unsigned int error_count = 0;
  166. u8 actual;
  167. u8 expected;
  168. u8 *buf;
  169. unsigned int counter_orig = counter;
  170. for (; (buf = *bufs); bufs++) {
  171. counter = counter_orig;
  172. for (i = start; i < end; i++) {
  173. actual = buf[i];
  174. expected = pattern | (~counter & PATTERN_COUNT_MASK);
  175. if (actual != expected) {
  176. if (error_count < 32)
  177. dmatest_mismatch(actual, pattern, i,
  178. counter, is_srcbuf);
  179. error_count++;
  180. }
  181. counter++;
  182. }
  183. }
  184. if (error_count > 32)
  185. pr_warning("%s: %u errors suppressed\n",
  186. current->comm, error_count - 32);
  187. return error_count;
  188. }
  189. /* poor man's completion - we want to use wait_event_freezable() on it */
  190. struct dmatest_done {
  191. bool done;
  192. wait_queue_head_t *wait;
  193. };
  194. static void dmatest_callback(void *arg)
  195. {
  196. struct dmatest_done *done = arg;
  197. done->done = true;
  198. wake_up_all(done->wait);
  199. }
  200. static inline void unmap_src(struct device *dev, dma_addr_t *addr, size_t len,
  201. unsigned int count)
  202. {
  203. while (count--)
  204. dma_unmap_single(dev, addr[count], len, DMA_TO_DEVICE);
  205. }
  206. static inline void unmap_dst(struct device *dev, dma_addr_t *addr, size_t len,
  207. unsigned int count)
  208. {
  209. while (count--)
  210. dma_unmap_single(dev, addr[count], len, DMA_BIDIRECTIONAL);
  211. }
  212. /*
  213. * This function repeatedly tests DMA transfers of various lengths and
  214. * offsets for a given operation type until it is told to exit by
  215. * kthread_stop(). There may be multiple threads running this function
  216. * in parallel for a single channel, and there may be multiple channels
  217. * being tested in parallel.
  218. *
  219. * Before each test, the source and destination buffer is initialized
  220. * with a known pattern. This pattern is different depending on
  221. * whether it's in an area which is supposed to be copied or
  222. * overwritten, and different in the source and destination buffers.
  223. * So if the DMA engine doesn't copy exactly what we tell it to copy,
  224. * we'll notice.
  225. */
  226. static int dmatest_func(void *data)
  227. {
  228. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait);
  229. struct dmatest_thread *thread = data;
  230. struct dmatest_done done = { .wait = &done_wait };
  231. struct dma_chan *chan;
  232. const char *thread_name;
  233. unsigned int src_off, dst_off, len;
  234. unsigned int error_count;
  235. unsigned int failed_tests = 0;
  236. unsigned int total_tests = 0;
  237. dma_cookie_t cookie;
  238. enum dma_status status;
  239. enum dma_ctrl_flags flags;
  240. u8 pq_coefs[pq_sources + 1];
  241. int ret;
  242. int src_cnt;
  243. int dst_cnt;
  244. int i;
  245. thread_name = current->comm;
  246. set_freezable();
  247. ret = -ENOMEM;
  248. smp_rmb();
  249. chan = thread->chan;
  250. if (thread->type == DMA_MEMCPY)
  251. src_cnt = dst_cnt = 1;
  252. else if (thread->type == DMA_XOR) {
  253. src_cnt = xor_sources | 1; /* force odd to ensure dst = src */
  254. dst_cnt = 1;
  255. } else if (thread->type == DMA_PQ) {
  256. src_cnt = pq_sources | 1; /* force odd to ensure dst = src */
  257. dst_cnt = 2;
  258. for (i = 0; i < src_cnt; i++)
  259. pq_coefs[i] = 1;
  260. } else
  261. goto err_srcs;
  262. thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL);
  263. if (!thread->srcs)
  264. goto err_srcs;
  265. for (i = 0; i < src_cnt; i++) {
  266. thread->srcs[i] = kmalloc(test_buf_size, GFP_KERNEL);
  267. if (!thread->srcs[i])
  268. goto err_srcbuf;
  269. }
  270. thread->srcs[i] = NULL;
  271. thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL);
  272. if (!thread->dsts)
  273. goto err_dsts;
  274. for (i = 0; i < dst_cnt; i++) {
  275. thread->dsts[i] = kmalloc(test_buf_size, GFP_KERNEL);
  276. if (!thread->dsts[i])
  277. goto err_dstbuf;
  278. }
  279. thread->dsts[i] = NULL;
  280. set_user_nice(current, 10);
  281. /*
  282. * src buffers are freed by the DMAEngine code with dma_unmap_single()
  283. * dst buffers are freed by ourselves below
  284. */
  285. flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT
  286. | DMA_COMPL_SKIP_DEST_UNMAP | DMA_COMPL_SRC_UNMAP_SINGLE;
  287. while (!kthread_should_stop()
  288. && !(iterations && total_tests >= iterations)) {
  289. struct dma_device *dev = chan->device;
  290. struct dma_async_tx_descriptor *tx = NULL;
  291. dma_addr_t dma_srcs[src_cnt];
  292. dma_addr_t dma_dsts[dst_cnt];
  293. u8 align = 0;
  294. total_tests++;
  295. /* honor alignment restrictions */
  296. if (thread->type == DMA_MEMCPY)
  297. align = dev->copy_align;
  298. else if (thread->type == DMA_XOR)
  299. align = dev->xor_align;
  300. else if (thread->type == DMA_PQ)
  301. align = dev->pq_align;
  302. if (1 << align > test_buf_size) {
  303. pr_err("%u-byte buffer too small for %d-byte alignment\n",
  304. test_buf_size, 1 << align);
  305. break;
  306. }
  307. len = dmatest_random() % test_buf_size + 1;
  308. len = (len >> align) << align;
  309. if (!len)
  310. len = 1 << align;
  311. src_off = dmatest_random() % (test_buf_size - len + 1);
  312. dst_off = dmatest_random() % (test_buf_size - len + 1);
  313. src_off = (src_off >> align) << align;
  314. dst_off = (dst_off >> align) << align;
  315. dmatest_init_srcs(thread->srcs, src_off, len);
  316. dmatest_init_dsts(thread->dsts, dst_off, len);
  317. for (i = 0; i < src_cnt; i++) {
  318. u8 *buf = thread->srcs[i] + src_off;
  319. dma_srcs[i] = dma_map_single(dev->dev, buf, len,
  320. DMA_TO_DEVICE);
  321. ret = dma_mapping_error(dev->dev, dma_srcs[i]);
  322. if (ret) {
  323. unmap_src(dev->dev, dma_srcs, len, i);
  324. pr_warn("%s: #%u: mapping error %d with "
  325. "src_off=0x%x len=0x%x\n",
  326. thread_name, total_tests - 1, ret,
  327. src_off, len);
  328. failed_tests++;
  329. continue;
  330. }
  331. }
  332. /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
  333. for (i = 0; i < dst_cnt; i++) {
  334. dma_dsts[i] = dma_map_single(dev->dev, thread->dsts[i],
  335. test_buf_size,
  336. DMA_BIDIRECTIONAL);
  337. ret = dma_mapping_error(dev->dev, dma_dsts[i]);
  338. if (ret) {
  339. unmap_src(dev->dev, dma_srcs, len, src_cnt);
  340. unmap_dst(dev->dev, dma_dsts, test_buf_size, i);
  341. pr_warn("%s: #%u: mapping error %d with "
  342. "dst_off=0x%x len=0x%x\n",
  343. thread_name, total_tests - 1, ret,
  344. dst_off, test_buf_size);
  345. failed_tests++;
  346. continue;
  347. }
  348. }
  349. if (thread->type == DMA_MEMCPY)
  350. tx = dev->device_prep_dma_memcpy(chan,
  351. dma_dsts[0] + dst_off,
  352. dma_srcs[0], len,
  353. flags);
  354. else if (thread->type == DMA_XOR)
  355. tx = dev->device_prep_dma_xor(chan,
  356. dma_dsts[0] + dst_off,
  357. dma_srcs, src_cnt,
  358. len, flags);
  359. else if (thread->type == DMA_PQ) {
  360. dma_addr_t dma_pq[dst_cnt];
  361. for (i = 0; i < dst_cnt; i++)
  362. dma_pq[i] = dma_dsts[i] + dst_off;
  363. tx = dev->device_prep_dma_pq(chan, dma_pq, dma_srcs,
  364. src_cnt, pq_coefs,
  365. len, flags);
  366. }
  367. if (!tx) {
  368. unmap_src(dev->dev, dma_srcs, len, src_cnt);
  369. unmap_dst(dev->dev, dma_dsts, test_buf_size, dst_cnt);
  370. pr_warning("%s: #%u: prep error with src_off=0x%x "
  371. "dst_off=0x%x len=0x%x\n",
  372. thread_name, total_tests - 1,
  373. src_off, dst_off, len);
  374. msleep(100);
  375. failed_tests++;
  376. continue;
  377. }
  378. done.done = false;
  379. tx->callback = dmatest_callback;
  380. tx->callback_param = &done;
  381. cookie = tx->tx_submit(tx);
  382. if (dma_submit_error(cookie)) {
  383. pr_warning("%s: #%u: submit error %d with src_off=0x%x "
  384. "dst_off=0x%x len=0x%x\n",
  385. thread_name, total_tests - 1, cookie,
  386. src_off, dst_off, len);
  387. msleep(100);
  388. failed_tests++;
  389. continue;
  390. }
  391. dma_async_issue_pending(chan);
  392. wait_event_freezable_timeout(done_wait, done.done,
  393. msecs_to_jiffies(timeout));
  394. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  395. if (!done.done) {
  396. /*
  397. * We're leaving the timed out dma operation with
  398. * dangling pointer to done_wait. To make this
  399. * correct, we'll need to allocate wait_done for
  400. * each test iteration and perform "who's gonna
  401. * free it this time?" dancing. For now, just
  402. * leave it dangling.
  403. */
  404. pr_warning("%s: #%u: test timed out\n",
  405. thread_name, total_tests - 1);
  406. failed_tests++;
  407. continue;
  408. } else if (status != DMA_SUCCESS) {
  409. pr_warning("%s: #%u: got completion callback,"
  410. " but status is \'%s\'\n",
  411. thread_name, total_tests - 1,
  412. status == DMA_ERROR ? "error" : "in progress");
  413. failed_tests++;
  414. continue;
  415. }
  416. /* Unmap by myself (see DMA_COMPL_SKIP_DEST_UNMAP above) */
  417. unmap_dst(dev->dev, dma_dsts, test_buf_size, dst_cnt);
  418. error_count = 0;
  419. pr_debug("%s: verifying source buffer...\n", thread_name);
  420. error_count += dmatest_verify(thread->srcs, 0, src_off,
  421. 0, PATTERN_SRC, true);
  422. error_count += dmatest_verify(thread->srcs, src_off,
  423. src_off + len, src_off,
  424. PATTERN_SRC | PATTERN_COPY, true);
  425. error_count += dmatest_verify(thread->srcs, src_off + len,
  426. test_buf_size, src_off + len,
  427. PATTERN_SRC, true);
  428. pr_debug("%s: verifying dest buffer...\n",
  429. thread->task->comm);
  430. error_count += dmatest_verify(thread->dsts, 0, dst_off,
  431. 0, PATTERN_DST, false);
  432. error_count += dmatest_verify(thread->dsts, dst_off,
  433. dst_off + len, src_off,
  434. PATTERN_SRC | PATTERN_COPY, false);
  435. error_count += dmatest_verify(thread->dsts, dst_off + len,
  436. test_buf_size, dst_off + len,
  437. PATTERN_DST, false);
  438. if (error_count) {
  439. pr_warning("%s: #%u: %u errors with "
  440. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  441. thread_name, total_tests - 1, error_count,
  442. src_off, dst_off, len);
  443. failed_tests++;
  444. } else {
  445. pr_debug("%s: #%u: No errors with "
  446. "src_off=0x%x dst_off=0x%x len=0x%x\n",
  447. thread_name, total_tests - 1,
  448. src_off, dst_off, len);
  449. }
  450. }
  451. ret = 0;
  452. for (i = 0; thread->dsts[i]; i++)
  453. kfree(thread->dsts[i]);
  454. err_dstbuf:
  455. kfree(thread->dsts);
  456. err_dsts:
  457. for (i = 0; thread->srcs[i]; i++)
  458. kfree(thread->srcs[i]);
  459. err_srcbuf:
  460. kfree(thread->srcs);
  461. err_srcs:
  462. pr_notice("%s: terminating after %u tests, %u failures (status %d)\n",
  463. thread_name, total_tests, failed_tests, ret);
  464. /* terminate all transfers on specified channels */
  465. chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
  466. if (iterations > 0)
  467. while (!kthread_should_stop()) {
  468. DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit);
  469. interruptible_sleep_on(&wait_dmatest_exit);
  470. }
  471. return ret;
  472. }
  473. static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
  474. {
  475. struct dmatest_thread *thread;
  476. struct dmatest_thread *_thread;
  477. int ret;
  478. list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
  479. ret = kthread_stop(thread->task);
  480. pr_debug("dmatest: thread %s exited with status %d\n",
  481. thread->task->comm, ret);
  482. list_del(&thread->node);
  483. kfree(thread);
  484. }
  485. /* terminate all transfers on specified channels */
  486. dtc->chan->device->device_control(dtc->chan, DMA_TERMINATE_ALL, 0);
  487. kfree(dtc);
  488. }
  489. static int dmatest_add_threads(struct dmatest_chan *dtc, enum dma_transaction_type type)
  490. {
  491. struct dmatest_thread *thread;
  492. struct dma_chan *chan = dtc->chan;
  493. char *op;
  494. unsigned int i;
  495. if (type == DMA_MEMCPY)
  496. op = "copy";
  497. else if (type == DMA_XOR)
  498. op = "xor";
  499. else if (type == DMA_PQ)
  500. op = "pq";
  501. else
  502. return -EINVAL;
  503. for (i = 0; i < threads_per_chan; i++) {
  504. thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
  505. if (!thread) {
  506. pr_warning("dmatest: No memory for %s-%s%u\n",
  507. dma_chan_name(chan), op, i);
  508. break;
  509. }
  510. thread->chan = dtc->chan;
  511. thread->type = type;
  512. smp_wmb();
  513. thread->task = kthread_run(dmatest_func, thread, "%s-%s%u",
  514. dma_chan_name(chan), op, i);
  515. if (IS_ERR(thread->task)) {
  516. pr_warning("dmatest: Failed to run thread %s-%s%u\n",
  517. dma_chan_name(chan), op, i);
  518. kfree(thread);
  519. break;
  520. }
  521. /* srcbuf and dstbuf are allocated by the thread itself */
  522. list_add_tail(&thread->node, &dtc->threads);
  523. }
  524. return i;
  525. }
  526. static int dmatest_add_channel(struct dma_chan *chan)
  527. {
  528. struct dmatest_chan *dtc;
  529. struct dma_device *dma_dev = chan->device;
  530. unsigned int thread_count = 0;
  531. int cnt;
  532. dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
  533. if (!dtc) {
  534. pr_warning("dmatest: No memory for %s\n", dma_chan_name(chan));
  535. return -ENOMEM;
  536. }
  537. dtc->chan = chan;
  538. INIT_LIST_HEAD(&dtc->threads);
  539. if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
  540. cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
  541. thread_count += cnt > 0 ? cnt : 0;
  542. }
  543. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  544. cnt = dmatest_add_threads(dtc, DMA_XOR);
  545. thread_count += cnt > 0 ? cnt : 0;
  546. }
  547. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  548. cnt = dmatest_add_threads(dtc, DMA_PQ);
  549. thread_count += cnt > 0 ? cnt : 0;
  550. }
  551. pr_info("dmatest: Started %u threads using %s\n",
  552. thread_count, dma_chan_name(chan));
  553. list_add_tail(&dtc->node, &dmatest_channels);
  554. nr_channels++;
  555. return 0;
  556. }
  557. static bool filter(struct dma_chan *chan, void *param)
  558. {
  559. if (!dmatest_match_channel(chan) || !dmatest_match_device(chan->device))
  560. return false;
  561. else
  562. return true;
  563. }
  564. static int __init dmatest_init(void)
  565. {
  566. dma_cap_mask_t mask;
  567. struct dma_chan *chan;
  568. int err = 0;
  569. dma_cap_zero(mask);
  570. dma_cap_set(DMA_MEMCPY, mask);
  571. for (;;) {
  572. chan = dma_request_channel(mask, filter, NULL);
  573. if (chan) {
  574. err = dmatest_add_channel(chan);
  575. if (err) {
  576. dma_release_channel(chan);
  577. break; /* add_channel failed, punt */
  578. }
  579. } else
  580. break; /* no more channels available */
  581. if (max_channels && nr_channels >= max_channels)
  582. break; /* we have all we need */
  583. }
  584. return err;
  585. }
  586. /* when compiled-in wait for drivers to load first */
  587. late_initcall(dmatest_init);
  588. static void __exit dmatest_exit(void)
  589. {
  590. struct dmatest_chan *dtc, *_dtc;
  591. struct dma_chan *chan;
  592. list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) {
  593. list_del(&dtc->node);
  594. chan = dtc->chan;
  595. dmatest_cleanup_channel(dtc);
  596. pr_debug("dmatest: dropped channel %s\n",
  597. dma_chan_name(chan));
  598. dma_release_channel(chan);
  599. }
  600. }
  601. module_exit(dmatest_exit);
  602. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  603. MODULE_LICENSE("GPL v2");