dmaengine.c 29 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. static DEFINE_MUTEX(dma_list_mutex);
  63. static DEFINE_IDR(dma_idr);
  64. static LIST_HEAD(dma_device_list);
  65. static long dmaengine_ref_count;
  66. /* --- sysfs implementation --- */
  67. /**
  68. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  69. * @dev - device node
  70. *
  71. * Must be called under dma_list_mutex
  72. */
  73. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  74. {
  75. struct dma_chan_dev *chan_dev;
  76. chan_dev = container_of(dev, typeof(*chan_dev), device);
  77. return chan_dev->chan;
  78. }
  79. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  80. {
  81. struct dma_chan *chan;
  82. unsigned long count = 0;
  83. int i;
  84. int err;
  85. mutex_lock(&dma_list_mutex);
  86. chan = dev_to_dma_chan(dev);
  87. if (chan) {
  88. for_each_possible_cpu(i)
  89. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  90. err = sprintf(buf, "%lu\n", count);
  91. } else
  92. err = -ENODEV;
  93. mutex_unlock(&dma_list_mutex);
  94. return err;
  95. }
  96. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  97. char *buf)
  98. {
  99. struct dma_chan *chan;
  100. unsigned long count = 0;
  101. int i;
  102. int err;
  103. mutex_lock(&dma_list_mutex);
  104. chan = dev_to_dma_chan(dev);
  105. if (chan) {
  106. for_each_possible_cpu(i)
  107. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  108. err = sprintf(buf, "%lu\n", count);
  109. } else
  110. err = -ENODEV;
  111. mutex_unlock(&dma_list_mutex);
  112. return err;
  113. }
  114. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  115. {
  116. struct dma_chan *chan;
  117. int err;
  118. mutex_lock(&dma_list_mutex);
  119. chan = dev_to_dma_chan(dev);
  120. if (chan)
  121. err = sprintf(buf, "%d\n", chan->client_count);
  122. else
  123. err = -ENODEV;
  124. mutex_unlock(&dma_list_mutex);
  125. return err;
  126. }
  127. static struct device_attribute dma_attrs[] = {
  128. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  129. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  130. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  131. __ATTR_NULL
  132. };
  133. static void chan_dev_release(struct device *dev)
  134. {
  135. struct dma_chan_dev *chan_dev;
  136. chan_dev = container_of(dev, typeof(*chan_dev), device);
  137. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  138. mutex_lock(&dma_list_mutex);
  139. idr_remove(&dma_idr, chan_dev->dev_id);
  140. mutex_unlock(&dma_list_mutex);
  141. kfree(chan_dev->idr_ref);
  142. }
  143. kfree(chan_dev);
  144. }
  145. static struct class dma_devclass = {
  146. .name = "dma",
  147. .dev_attrs = dma_attrs,
  148. .dev_release = chan_dev_release,
  149. };
  150. /* --- client and device registration --- */
  151. #define dma_device_satisfies_mask(device, mask) \
  152. __dma_device_satisfies_mask((device), &(mask))
  153. static int
  154. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  155. {
  156. dma_cap_mask_t has;
  157. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  158. DMA_TX_TYPE_END);
  159. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  160. }
  161. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  162. {
  163. return chan->device->dev->driver->owner;
  164. }
  165. /**
  166. * balance_ref_count - catch up the channel reference count
  167. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  168. *
  169. * balance_ref_count must be called under dma_list_mutex
  170. */
  171. static void balance_ref_count(struct dma_chan *chan)
  172. {
  173. struct module *owner = dma_chan_to_owner(chan);
  174. while (chan->client_count < dmaengine_ref_count) {
  175. __module_get(owner);
  176. chan->client_count++;
  177. }
  178. }
  179. /**
  180. * dma_chan_get - try to grab a dma channel's parent driver module
  181. * @chan - channel to grab
  182. *
  183. * Must be called under dma_list_mutex
  184. */
  185. static int dma_chan_get(struct dma_chan *chan)
  186. {
  187. int err = -ENODEV;
  188. struct module *owner = dma_chan_to_owner(chan);
  189. if (chan->client_count) {
  190. __module_get(owner);
  191. err = 0;
  192. } else if (try_module_get(owner))
  193. err = 0;
  194. if (err == 0)
  195. chan->client_count++;
  196. /* allocate upon first client reference */
  197. if (chan->client_count == 1 && err == 0) {
  198. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  199. if (desc_cnt < 0) {
  200. err = desc_cnt;
  201. chan->client_count = 0;
  202. module_put(owner);
  203. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  204. balance_ref_count(chan);
  205. }
  206. return err;
  207. }
  208. /**
  209. * dma_chan_put - drop a reference to a dma channel's parent driver module
  210. * @chan - channel to release
  211. *
  212. * Must be called under dma_list_mutex
  213. */
  214. static void dma_chan_put(struct dma_chan *chan)
  215. {
  216. if (!chan->client_count)
  217. return; /* this channel failed alloc_chan_resources */
  218. chan->client_count--;
  219. module_put(dma_chan_to_owner(chan));
  220. if (chan->client_count == 0)
  221. chan->device->device_free_chan_resources(chan);
  222. }
  223. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  224. {
  225. enum dma_status status;
  226. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  227. dma_async_issue_pending(chan);
  228. do {
  229. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  230. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  231. pr_err("%s: timeout!\n", __func__);
  232. return DMA_ERROR;
  233. }
  234. } while (status == DMA_IN_PROGRESS);
  235. return status;
  236. }
  237. EXPORT_SYMBOL(dma_sync_wait);
  238. /**
  239. * dma_cap_mask_all - enable iteration over all operation types
  240. */
  241. static dma_cap_mask_t dma_cap_mask_all;
  242. /**
  243. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  244. * @chan - associated channel for this entry
  245. */
  246. struct dma_chan_tbl_ent {
  247. struct dma_chan *chan;
  248. };
  249. /**
  250. * channel_table - percpu lookup table for memory-to-memory offload providers
  251. */
  252. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  253. static int __init dma_channel_table_init(void)
  254. {
  255. enum dma_transaction_type cap;
  256. int err = 0;
  257. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  258. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  259. * but are not associated with an operation so they do not need
  260. * an entry in the channel_table
  261. */
  262. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  263. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  264. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  265. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  266. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  267. if (!channel_table[cap]) {
  268. err = -ENOMEM;
  269. break;
  270. }
  271. }
  272. if (err) {
  273. pr_err("initialization failure\n");
  274. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  275. if (channel_table[cap])
  276. free_percpu(channel_table[cap]);
  277. }
  278. return err;
  279. }
  280. arch_initcall(dma_channel_table_init);
  281. /**
  282. * dma_find_channel - find a channel to carry out the operation
  283. * @tx_type: transaction type
  284. */
  285. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  286. {
  287. return this_cpu_read(channel_table[tx_type]->chan);
  288. }
  289. EXPORT_SYMBOL(dma_find_channel);
  290. /*
  291. * net_dma_find_channel - find a channel for net_dma
  292. * net_dma has alignment requirements
  293. */
  294. struct dma_chan *net_dma_find_channel(void)
  295. {
  296. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  297. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  298. return NULL;
  299. return chan;
  300. }
  301. EXPORT_SYMBOL(net_dma_find_channel);
  302. /**
  303. * dma_issue_pending_all - flush all pending operations across all channels
  304. */
  305. void dma_issue_pending_all(void)
  306. {
  307. struct dma_device *device;
  308. struct dma_chan *chan;
  309. rcu_read_lock();
  310. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  311. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  312. continue;
  313. list_for_each_entry(chan, &device->channels, device_node)
  314. if (chan->client_count)
  315. device->device_issue_pending(chan);
  316. }
  317. rcu_read_unlock();
  318. }
  319. EXPORT_SYMBOL(dma_issue_pending_all);
  320. /**
  321. * nth_chan - returns the nth channel of the given capability
  322. * @cap: capability to match
  323. * @n: nth channel desired
  324. *
  325. * Defaults to returning the channel with the desired capability and the
  326. * lowest reference count when 'n' cannot be satisfied. Must be called
  327. * under dma_list_mutex.
  328. */
  329. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  330. {
  331. struct dma_device *device;
  332. struct dma_chan *chan;
  333. struct dma_chan *ret = NULL;
  334. struct dma_chan *min = NULL;
  335. list_for_each_entry(device, &dma_device_list, global_node) {
  336. if (!dma_has_cap(cap, device->cap_mask) ||
  337. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  338. continue;
  339. list_for_each_entry(chan, &device->channels, device_node) {
  340. if (!chan->client_count)
  341. continue;
  342. if (!min)
  343. min = chan;
  344. else if (chan->table_count < min->table_count)
  345. min = chan;
  346. if (n-- == 0) {
  347. ret = chan;
  348. break; /* done */
  349. }
  350. }
  351. if (ret)
  352. break; /* done */
  353. }
  354. if (!ret)
  355. ret = min;
  356. if (ret)
  357. ret->table_count++;
  358. return ret;
  359. }
  360. /**
  361. * dma_channel_rebalance - redistribute the available channels
  362. *
  363. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  364. * operation type) in the SMP case, and operation isolation (avoid
  365. * multi-tasking channels) in the non-SMP case. Must be called under
  366. * dma_list_mutex.
  367. */
  368. static void dma_channel_rebalance(void)
  369. {
  370. struct dma_chan *chan;
  371. struct dma_device *device;
  372. int cpu;
  373. int cap;
  374. int n;
  375. /* undo the last distribution */
  376. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  377. for_each_possible_cpu(cpu)
  378. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  379. list_for_each_entry(device, &dma_device_list, global_node) {
  380. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  381. continue;
  382. list_for_each_entry(chan, &device->channels, device_node)
  383. chan->table_count = 0;
  384. }
  385. /* don't populate the channel_table if no clients are available */
  386. if (!dmaengine_ref_count)
  387. return;
  388. /* redistribute available channels */
  389. n = 0;
  390. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  391. for_each_online_cpu(cpu) {
  392. if (num_possible_cpus() > 1)
  393. chan = nth_chan(cap, n++);
  394. else
  395. chan = nth_chan(cap, -1);
  396. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  397. }
  398. }
  399. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  400. dma_filter_fn fn, void *fn_param)
  401. {
  402. struct dma_chan *chan;
  403. if (!__dma_device_satisfies_mask(dev, mask)) {
  404. pr_debug("%s: wrong capabilities\n", __func__);
  405. return NULL;
  406. }
  407. /* devices with multiple channels need special handling as we need to
  408. * ensure that all channels are either private or public.
  409. */
  410. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  411. list_for_each_entry(chan, &dev->channels, device_node) {
  412. /* some channels are already publicly allocated */
  413. if (chan->client_count)
  414. return NULL;
  415. }
  416. list_for_each_entry(chan, &dev->channels, device_node) {
  417. if (chan->client_count) {
  418. pr_debug("%s: %s busy\n",
  419. __func__, dma_chan_name(chan));
  420. continue;
  421. }
  422. if (fn && !fn(chan, fn_param)) {
  423. pr_debug("%s: %s filter said false\n",
  424. __func__, dma_chan_name(chan));
  425. continue;
  426. }
  427. return chan;
  428. }
  429. return NULL;
  430. }
  431. /**
  432. * dma_request_channel - try to allocate an exclusive channel
  433. * @mask: capabilities that the channel must satisfy
  434. * @fn: optional callback to disposition available channels
  435. * @fn_param: opaque parameter to pass to dma_filter_fn
  436. */
  437. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  438. {
  439. struct dma_device *device, *_d;
  440. struct dma_chan *chan = NULL;
  441. int err;
  442. /* Find a channel */
  443. mutex_lock(&dma_list_mutex);
  444. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  445. chan = private_candidate(mask, device, fn, fn_param);
  446. if (chan) {
  447. /* Found a suitable channel, try to grab, prep, and
  448. * return it. We first set DMA_PRIVATE to disable
  449. * balance_ref_count as this channel will not be
  450. * published in the general-purpose allocator
  451. */
  452. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  453. device->privatecnt++;
  454. err = dma_chan_get(chan);
  455. if (err == -ENODEV) {
  456. pr_debug("%s: %s module removed\n",
  457. __func__, dma_chan_name(chan));
  458. list_del_rcu(&device->global_node);
  459. } else if (err)
  460. pr_debug("%s: failed to get %s: (%d)\n",
  461. __func__, dma_chan_name(chan), err);
  462. else
  463. break;
  464. if (--device->privatecnt == 0)
  465. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  466. chan = NULL;
  467. }
  468. }
  469. mutex_unlock(&dma_list_mutex);
  470. pr_debug("%s: %s (%s)\n",
  471. __func__,
  472. chan ? "success" : "fail",
  473. chan ? dma_chan_name(chan) : NULL);
  474. return chan;
  475. }
  476. EXPORT_SYMBOL_GPL(__dma_request_channel);
  477. void dma_release_channel(struct dma_chan *chan)
  478. {
  479. mutex_lock(&dma_list_mutex);
  480. WARN_ONCE(chan->client_count != 1,
  481. "chan reference count %d != 1\n", chan->client_count);
  482. dma_chan_put(chan);
  483. /* drop PRIVATE cap enabled by __dma_request_channel() */
  484. if (--chan->device->privatecnt == 0)
  485. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  486. mutex_unlock(&dma_list_mutex);
  487. }
  488. EXPORT_SYMBOL_GPL(dma_release_channel);
  489. /**
  490. * dmaengine_get - register interest in dma_channels
  491. */
  492. void dmaengine_get(void)
  493. {
  494. struct dma_device *device, *_d;
  495. struct dma_chan *chan;
  496. int err;
  497. mutex_lock(&dma_list_mutex);
  498. dmaengine_ref_count++;
  499. /* try to grab channels */
  500. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  501. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  502. continue;
  503. list_for_each_entry(chan, &device->channels, device_node) {
  504. err = dma_chan_get(chan);
  505. if (err == -ENODEV) {
  506. /* module removed before we could use it */
  507. list_del_rcu(&device->global_node);
  508. break;
  509. } else if (err)
  510. pr_debug("%s: failed to get %s: (%d)\n",
  511. __func__, dma_chan_name(chan), err);
  512. }
  513. }
  514. /* if this is the first reference and there were channels
  515. * waiting we need to rebalance to get those channels
  516. * incorporated into the channel table
  517. */
  518. if (dmaengine_ref_count == 1)
  519. dma_channel_rebalance();
  520. mutex_unlock(&dma_list_mutex);
  521. }
  522. EXPORT_SYMBOL(dmaengine_get);
  523. /**
  524. * dmaengine_put - let dma drivers be removed when ref_count == 0
  525. */
  526. void dmaengine_put(void)
  527. {
  528. struct dma_device *device;
  529. struct dma_chan *chan;
  530. mutex_lock(&dma_list_mutex);
  531. dmaengine_ref_count--;
  532. BUG_ON(dmaengine_ref_count < 0);
  533. /* drop channel references */
  534. list_for_each_entry(device, &dma_device_list, global_node) {
  535. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  536. continue;
  537. list_for_each_entry(chan, &device->channels, device_node)
  538. dma_chan_put(chan);
  539. }
  540. mutex_unlock(&dma_list_mutex);
  541. }
  542. EXPORT_SYMBOL(dmaengine_put);
  543. static bool device_has_all_tx_types(struct dma_device *device)
  544. {
  545. /* A device that satisfies this test has channels that will never cause
  546. * an async_tx channel switch event as all possible operation types can
  547. * be handled.
  548. */
  549. #ifdef CONFIG_ASYNC_TX_DMA
  550. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  551. return false;
  552. #endif
  553. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  554. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  555. return false;
  556. #endif
  557. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  558. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  559. return false;
  560. #endif
  561. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  562. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  563. return false;
  564. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  565. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  566. return false;
  567. #endif
  568. #endif
  569. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  570. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  571. return false;
  572. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  573. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  574. return false;
  575. #endif
  576. #endif
  577. return true;
  578. }
  579. static int get_dma_id(struct dma_device *device)
  580. {
  581. int rc;
  582. idr_retry:
  583. if (!idr_pre_get(&dma_idr, GFP_KERNEL))
  584. return -ENOMEM;
  585. mutex_lock(&dma_list_mutex);
  586. rc = idr_get_new(&dma_idr, NULL, &device->dev_id);
  587. mutex_unlock(&dma_list_mutex);
  588. if (rc == -EAGAIN)
  589. goto idr_retry;
  590. else if (rc != 0)
  591. return rc;
  592. return 0;
  593. }
  594. /**
  595. * dma_async_device_register - registers DMA devices found
  596. * @device: &dma_device
  597. */
  598. int dma_async_device_register(struct dma_device *device)
  599. {
  600. int chancnt = 0, rc;
  601. struct dma_chan* chan;
  602. atomic_t *idr_ref;
  603. if (!device)
  604. return -ENODEV;
  605. /* validate device routines */
  606. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  607. !device->device_prep_dma_memcpy);
  608. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  609. !device->device_prep_dma_xor);
  610. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  611. !device->device_prep_dma_xor_val);
  612. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  613. !device->device_prep_dma_pq);
  614. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  615. !device->device_prep_dma_pq_val);
  616. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  617. !device->device_prep_dma_memset);
  618. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  619. !device->device_prep_dma_interrupt);
  620. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  621. !device->device_prep_dma_sg);
  622. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  623. !device->device_prep_dma_cyclic);
  624. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  625. !device->device_control);
  626. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  627. !device->device_prep_interleaved_dma);
  628. BUG_ON(!device->device_alloc_chan_resources);
  629. BUG_ON(!device->device_free_chan_resources);
  630. BUG_ON(!device->device_tx_status);
  631. BUG_ON(!device->device_issue_pending);
  632. BUG_ON(!device->dev);
  633. /* note: this only matters in the
  634. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  635. */
  636. if (device_has_all_tx_types(device))
  637. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  638. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  639. if (!idr_ref)
  640. return -ENOMEM;
  641. rc = get_dma_id(device);
  642. if (rc != 0) {
  643. kfree(idr_ref);
  644. return rc;
  645. }
  646. atomic_set(idr_ref, 0);
  647. /* represent channels in sysfs. Probably want devs too */
  648. list_for_each_entry(chan, &device->channels, device_node) {
  649. rc = -ENOMEM;
  650. chan->local = alloc_percpu(typeof(*chan->local));
  651. if (chan->local == NULL)
  652. goto err_out;
  653. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  654. if (chan->dev == NULL) {
  655. free_percpu(chan->local);
  656. chan->local = NULL;
  657. goto err_out;
  658. }
  659. chan->chan_id = chancnt++;
  660. chan->dev->device.class = &dma_devclass;
  661. chan->dev->device.parent = device->dev;
  662. chan->dev->chan = chan;
  663. chan->dev->idr_ref = idr_ref;
  664. chan->dev->dev_id = device->dev_id;
  665. atomic_inc(idr_ref);
  666. dev_set_name(&chan->dev->device, "dma%dchan%d",
  667. device->dev_id, chan->chan_id);
  668. rc = device_register(&chan->dev->device);
  669. if (rc) {
  670. free_percpu(chan->local);
  671. chan->local = NULL;
  672. kfree(chan->dev);
  673. atomic_dec(idr_ref);
  674. goto err_out;
  675. }
  676. chan->client_count = 0;
  677. }
  678. device->chancnt = chancnt;
  679. mutex_lock(&dma_list_mutex);
  680. /* take references on public channels */
  681. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  682. list_for_each_entry(chan, &device->channels, device_node) {
  683. /* if clients are already waiting for channels we need
  684. * to take references on their behalf
  685. */
  686. if (dma_chan_get(chan) == -ENODEV) {
  687. /* note we can only get here for the first
  688. * channel as the remaining channels are
  689. * guaranteed to get a reference
  690. */
  691. rc = -ENODEV;
  692. mutex_unlock(&dma_list_mutex);
  693. goto err_out;
  694. }
  695. }
  696. list_add_tail_rcu(&device->global_node, &dma_device_list);
  697. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  698. device->privatecnt++; /* Always private */
  699. dma_channel_rebalance();
  700. mutex_unlock(&dma_list_mutex);
  701. return 0;
  702. err_out:
  703. /* if we never registered a channel just release the idr */
  704. if (atomic_read(idr_ref) == 0) {
  705. mutex_lock(&dma_list_mutex);
  706. idr_remove(&dma_idr, device->dev_id);
  707. mutex_unlock(&dma_list_mutex);
  708. kfree(idr_ref);
  709. return rc;
  710. }
  711. list_for_each_entry(chan, &device->channels, device_node) {
  712. if (chan->local == NULL)
  713. continue;
  714. mutex_lock(&dma_list_mutex);
  715. chan->dev->chan = NULL;
  716. mutex_unlock(&dma_list_mutex);
  717. device_unregister(&chan->dev->device);
  718. free_percpu(chan->local);
  719. }
  720. return rc;
  721. }
  722. EXPORT_SYMBOL(dma_async_device_register);
  723. /**
  724. * dma_async_device_unregister - unregister a DMA device
  725. * @device: &dma_device
  726. *
  727. * This routine is called by dma driver exit routines, dmaengine holds module
  728. * references to prevent it being called while channels are in use.
  729. */
  730. void dma_async_device_unregister(struct dma_device *device)
  731. {
  732. struct dma_chan *chan;
  733. mutex_lock(&dma_list_mutex);
  734. list_del_rcu(&device->global_node);
  735. dma_channel_rebalance();
  736. mutex_unlock(&dma_list_mutex);
  737. list_for_each_entry(chan, &device->channels, device_node) {
  738. WARN_ONCE(chan->client_count,
  739. "%s called while %d clients hold a reference\n",
  740. __func__, chan->client_count);
  741. mutex_lock(&dma_list_mutex);
  742. chan->dev->chan = NULL;
  743. mutex_unlock(&dma_list_mutex);
  744. device_unregister(&chan->dev->device);
  745. free_percpu(chan->local);
  746. }
  747. }
  748. EXPORT_SYMBOL(dma_async_device_unregister);
  749. /**
  750. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  751. * @chan: DMA channel to offload copy to
  752. * @dest: destination address (virtual)
  753. * @src: source address (virtual)
  754. * @len: length
  755. *
  756. * Both @dest and @src must be mappable to a bus address according to the
  757. * DMA mapping API rules for streaming mappings.
  758. * Both @dest and @src must stay memory resident (kernel memory or locked
  759. * user space pages).
  760. */
  761. dma_cookie_t
  762. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  763. void *src, size_t len)
  764. {
  765. struct dma_device *dev = chan->device;
  766. struct dma_async_tx_descriptor *tx;
  767. dma_addr_t dma_dest, dma_src;
  768. dma_cookie_t cookie;
  769. unsigned long flags;
  770. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  771. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  772. flags = DMA_CTRL_ACK |
  773. DMA_COMPL_SRC_UNMAP_SINGLE |
  774. DMA_COMPL_DEST_UNMAP_SINGLE;
  775. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  776. if (!tx) {
  777. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  778. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  779. return -ENOMEM;
  780. }
  781. tx->callback = NULL;
  782. cookie = tx->tx_submit(tx);
  783. preempt_disable();
  784. __this_cpu_add(chan->local->bytes_transferred, len);
  785. __this_cpu_inc(chan->local->memcpy_count);
  786. preempt_enable();
  787. return cookie;
  788. }
  789. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  790. /**
  791. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  792. * @chan: DMA channel to offload copy to
  793. * @page: destination page
  794. * @offset: offset in page to copy to
  795. * @kdata: source address (virtual)
  796. * @len: length
  797. *
  798. * Both @page/@offset and @kdata must be mappable to a bus address according
  799. * to the DMA mapping API rules for streaming mappings.
  800. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  801. * locked user space pages)
  802. */
  803. dma_cookie_t
  804. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  805. unsigned int offset, void *kdata, size_t len)
  806. {
  807. struct dma_device *dev = chan->device;
  808. struct dma_async_tx_descriptor *tx;
  809. dma_addr_t dma_dest, dma_src;
  810. dma_cookie_t cookie;
  811. unsigned long flags;
  812. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  813. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  814. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  815. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  816. if (!tx) {
  817. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  818. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  819. return -ENOMEM;
  820. }
  821. tx->callback = NULL;
  822. cookie = tx->tx_submit(tx);
  823. preempt_disable();
  824. __this_cpu_add(chan->local->bytes_transferred, len);
  825. __this_cpu_inc(chan->local->memcpy_count);
  826. preempt_enable();
  827. return cookie;
  828. }
  829. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  830. /**
  831. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  832. * @chan: DMA channel to offload copy to
  833. * @dest_pg: destination page
  834. * @dest_off: offset in page to copy to
  835. * @src_pg: source page
  836. * @src_off: offset in page to copy from
  837. * @len: length
  838. *
  839. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  840. * address according to the DMA mapping API rules for streaming mappings.
  841. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  842. * (kernel memory or locked user space pages).
  843. */
  844. dma_cookie_t
  845. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  846. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  847. size_t len)
  848. {
  849. struct dma_device *dev = chan->device;
  850. struct dma_async_tx_descriptor *tx;
  851. dma_addr_t dma_dest, dma_src;
  852. dma_cookie_t cookie;
  853. unsigned long flags;
  854. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  855. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  856. DMA_FROM_DEVICE);
  857. flags = DMA_CTRL_ACK;
  858. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  859. if (!tx) {
  860. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  861. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  862. return -ENOMEM;
  863. }
  864. tx->callback = NULL;
  865. cookie = tx->tx_submit(tx);
  866. preempt_disable();
  867. __this_cpu_add(chan->local->bytes_transferred, len);
  868. __this_cpu_inc(chan->local->memcpy_count);
  869. preempt_enable();
  870. return cookie;
  871. }
  872. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  873. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  874. struct dma_chan *chan)
  875. {
  876. tx->chan = chan;
  877. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  878. spin_lock_init(&tx->lock);
  879. #endif
  880. }
  881. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  882. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  883. * @tx: in-flight transaction to wait on
  884. */
  885. enum dma_status
  886. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  887. {
  888. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  889. if (!tx)
  890. return DMA_SUCCESS;
  891. while (tx->cookie == -EBUSY) {
  892. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  893. pr_err("%s timeout waiting for descriptor submission\n",
  894. __func__);
  895. return DMA_ERROR;
  896. }
  897. cpu_relax();
  898. }
  899. return dma_sync_wait(tx->chan, tx->cookie);
  900. }
  901. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  902. /* dma_run_dependencies - helper routine for dma drivers to process
  903. * (start) dependent operations on their target channel
  904. * @tx: transaction with dependencies
  905. */
  906. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  907. {
  908. struct dma_async_tx_descriptor *dep = txd_next(tx);
  909. struct dma_async_tx_descriptor *dep_next;
  910. struct dma_chan *chan;
  911. if (!dep)
  912. return;
  913. /* we'll submit tx->next now, so clear the link */
  914. txd_clear_next(tx);
  915. chan = dep->chan;
  916. /* keep submitting up until a channel switch is detected
  917. * in that case we will be called again as a result of
  918. * processing the interrupt from async_tx_channel_switch
  919. */
  920. for (; dep; dep = dep_next) {
  921. txd_lock(dep);
  922. txd_clear_parent(dep);
  923. dep_next = txd_next(dep);
  924. if (dep_next && dep_next->chan == chan)
  925. txd_clear_next(dep); /* ->next will be submitted */
  926. else
  927. dep_next = NULL; /* submit current dep and terminate */
  928. txd_unlock(dep);
  929. dep->tx_submit(dep);
  930. }
  931. chan->device->device_issue_pending(chan);
  932. }
  933. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  934. static int __init dma_bus_init(void)
  935. {
  936. return class_register(&dma_devclass);
  937. }
  938. arch_initcall(dma_bus_init);