exynos-cpufreq.c 7.9 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * EXYNOS - CPU frequency scaling support for EXYNOS series
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/err.h>
  13. #include <linux/clk.h>
  14. #include <linux/io.h>
  15. #include <linux/slab.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/cpufreq.h>
  18. #include <linux/suspend.h>
  19. #include <mach/cpufreq.h>
  20. #include <plat/cpu.h>
  21. static struct exynos_dvfs_info *exynos_info;
  22. static struct regulator *arm_regulator;
  23. static struct cpufreq_freqs freqs;
  24. static unsigned int locking_frequency;
  25. static bool frequency_locked;
  26. static DEFINE_MUTEX(cpufreq_lock);
  27. static int exynos_verify_speed(struct cpufreq_policy *policy)
  28. {
  29. return cpufreq_frequency_table_verify(policy,
  30. exynos_info->freq_table);
  31. }
  32. static unsigned int exynos_getspeed(unsigned int cpu)
  33. {
  34. return clk_get_rate(exynos_info->cpu_clk) / 1000;
  35. }
  36. static int exynos_target(struct cpufreq_policy *policy,
  37. unsigned int target_freq,
  38. unsigned int relation)
  39. {
  40. unsigned int index, old_index;
  41. unsigned int arm_volt, safe_arm_volt = 0;
  42. int ret = 0;
  43. struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
  44. unsigned int *volt_table = exynos_info->volt_table;
  45. unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
  46. mutex_lock(&cpufreq_lock);
  47. freqs.old = policy->cur;
  48. if (frequency_locked && target_freq != locking_frequency) {
  49. ret = -EAGAIN;
  50. goto out;
  51. }
  52. /*
  53. * The policy max have been changed so that we cannot get proper
  54. * old_index with cpufreq_frequency_table_target(). Thus, ignore
  55. * policy and get the index from the raw freqeuncy table.
  56. */
  57. for (old_index = 0;
  58. freq_table[old_index].frequency != CPUFREQ_TABLE_END;
  59. old_index++)
  60. if (freq_table[old_index].frequency == freqs.old)
  61. break;
  62. if (freq_table[old_index].frequency == CPUFREQ_TABLE_END) {
  63. ret = -EINVAL;
  64. goto out;
  65. }
  66. if (cpufreq_frequency_table_target(policy, freq_table,
  67. target_freq, relation, &index)) {
  68. ret = -EINVAL;
  69. goto out;
  70. }
  71. freqs.new = freq_table[index].frequency;
  72. freqs.cpu = policy->cpu;
  73. /*
  74. * ARM clock source will be changed APLL to MPLL temporary
  75. * To support this level, need to control regulator for
  76. * required voltage level
  77. */
  78. if (exynos_info->need_apll_change != NULL) {
  79. if (exynos_info->need_apll_change(old_index, index) &&
  80. (freq_table[index].frequency < mpll_freq_khz) &&
  81. (freq_table[old_index].frequency < mpll_freq_khz))
  82. safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
  83. }
  84. arm_volt = volt_table[index];
  85. for_each_cpu(freqs.cpu, policy->cpus)
  86. cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  87. /* When the new frequency is higher than current frequency */
  88. if ((freqs.new > freqs.old) && !safe_arm_volt) {
  89. /* Firstly, voltage up to increase frequency */
  90. regulator_set_voltage(arm_regulator, arm_volt,
  91. arm_volt);
  92. }
  93. if (safe_arm_volt)
  94. regulator_set_voltage(arm_regulator, safe_arm_volt,
  95. safe_arm_volt);
  96. if (freqs.new != freqs.old)
  97. exynos_info->set_freq(old_index, index);
  98. for_each_cpu(freqs.cpu, policy->cpus)
  99. cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  100. /* When the new frequency is lower than current frequency */
  101. if ((freqs.new < freqs.old) ||
  102. ((freqs.new > freqs.old) && safe_arm_volt)) {
  103. /* down the voltage after frequency change */
  104. regulator_set_voltage(arm_regulator, arm_volt,
  105. arm_volt);
  106. }
  107. out:
  108. mutex_unlock(&cpufreq_lock);
  109. return ret;
  110. }
  111. #ifdef CONFIG_PM
  112. static int exynos_cpufreq_suspend(struct cpufreq_policy *policy)
  113. {
  114. return 0;
  115. }
  116. static int exynos_cpufreq_resume(struct cpufreq_policy *policy)
  117. {
  118. return 0;
  119. }
  120. #endif
  121. /**
  122. * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
  123. * context
  124. * @notifier
  125. * @pm_event
  126. * @v
  127. *
  128. * While frequency_locked == true, target() ignores every frequency but
  129. * locking_frequency. The locking_frequency value is the initial frequency,
  130. * which is set by the bootloader. In order to eliminate possible
  131. * inconsistency in clock values, we save and restore frequencies during
  132. * suspend and resume and block CPUFREQ activities. Note that the standard
  133. * suspend/resume cannot be used as they are too deep (syscore_ops) for
  134. * regulator actions.
  135. */
  136. static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier,
  137. unsigned long pm_event, void *v)
  138. {
  139. struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
  140. static unsigned int saved_frequency;
  141. unsigned int temp;
  142. mutex_lock(&cpufreq_lock);
  143. switch (pm_event) {
  144. case PM_SUSPEND_PREPARE:
  145. if (frequency_locked)
  146. goto out;
  147. frequency_locked = true;
  148. if (locking_frequency) {
  149. saved_frequency = exynos_getspeed(0);
  150. mutex_unlock(&cpufreq_lock);
  151. exynos_target(policy, locking_frequency,
  152. CPUFREQ_RELATION_H);
  153. mutex_lock(&cpufreq_lock);
  154. }
  155. break;
  156. case PM_POST_SUSPEND:
  157. if (saved_frequency) {
  158. /*
  159. * While frequency_locked, only locking_frequency
  160. * is valid for target(). In order to use
  161. * saved_frequency while keeping frequency_locked,
  162. * we temporarly overwrite locking_frequency.
  163. */
  164. temp = locking_frequency;
  165. locking_frequency = saved_frequency;
  166. mutex_unlock(&cpufreq_lock);
  167. exynos_target(policy, locking_frequency,
  168. CPUFREQ_RELATION_H);
  169. mutex_lock(&cpufreq_lock);
  170. locking_frequency = temp;
  171. }
  172. frequency_locked = false;
  173. break;
  174. }
  175. out:
  176. mutex_unlock(&cpufreq_lock);
  177. return NOTIFY_OK;
  178. }
  179. static struct notifier_block exynos_cpufreq_nb = {
  180. .notifier_call = exynos_cpufreq_pm_notifier,
  181. };
  182. static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
  183. {
  184. policy->cur = policy->min = policy->max = exynos_getspeed(policy->cpu);
  185. cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu);
  186. locking_frequency = exynos_getspeed(0);
  187. /* set the transition latency value */
  188. policy->cpuinfo.transition_latency = 100000;
  189. /*
  190. * EXYNOS4 multi-core processors has 2 cores
  191. * that the frequency cannot be set independently.
  192. * Each cpu is bound to the same speed.
  193. * So the affected cpu is all of the cpus.
  194. */
  195. if (num_online_cpus() == 1) {
  196. cpumask_copy(policy->related_cpus, cpu_possible_mask);
  197. cpumask_copy(policy->cpus, cpu_online_mask);
  198. } else {
  199. policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
  200. cpumask_setall(policy->cpus);
  201. }
  202. return cpufreq_frequency_table_cpuinfo(policy, exynos_info->freq_table);
  203. }
  204. static struct cpufreq_driver exynos_driver = {
  205. .flags = CPUFREQ_STICKY,
  206. .verify = exynos_verify_speed,
  207. .target = exynos_target,
  208. .get = exynos_getspeed,
  209. .init = exynos_cpufreq_cpu_init,
  210. .name = "exynos_cpufreq",
  211. #ifdef CONFIG_PM
  212. .suspend = exynos_cpufreq_suspend,
  213. .resume = exynos_cpufreq_resume,
  214. #endif
  215. };
  216. static int __init exynos_cpufreq_init(void)
  217. {
  218. int ret = -EINVAL;
  219. exynos_info = kzalloc(sizeof(struct exynos_dvfs_info), GFP_KERNEL);
  220. if (!exynos_info)
  221. return -ENOMEM;
  222. if (soc_is_exynos4210())
  223. ret = exynos4210_cpufreq_init(exynos_info);
  224. else if (soc_is_exynos4212() || soc_is_exynos4412())
  225. ret = exynos4x12_cpufreq_init(exynos_info);
  226. else if (soc_is_exynos5250())
  227. ret = exynos5250_cpufreq_init(exynos_info);
  228. else
  229. pr_err("%s: CPU type not found\n", __func__);
  230. if (ret)
  231. goto err_vdd_arm;
  232. if (exynos_info->set_freq == NULL) {
  233. pr_err("%s: No set_freq function (ERR)\n", __func__);
  234. goto err_vdd_arm;
  235. }
  236. arm_regulator = regulator_get(NULL, "vdd_arm");
  237. if (IS_ERR(arm_regulator)) {
  238. pr_err("%s: failed to get resource vdd_arm\n", __func__);
  239. goto err_vdd_arm;
  240. }
  241. register_pm_notifier(&exynos_cpufreq_nb);
  242. if (cpufreq_register_driver(&exynos_driver)) {
  243. pr_err("%s: failed to register cpufreq driver\n", __func__);
  244. goto err_cpufreq;
  245. }
  246. return 0;
  247. err_cpufreq:
  248. unregister_pm_notifier(&exynos_cpufreq_nb);
  249. if (!IS_ERR(arm_regulator))
  250. regulator_put(arm_regulator);
  251. err_vdd_arm:
  252. kfree(exynos_info);
  253. pr_debug("%s: failed initialization\n", __func__);
  254. return -EINVAL;
  255. }
  256. late_initcall(exynos_cpufreq_init);