driver_pci_host.c 17 KB

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  1. /*
  2. * Broadcom specific AMBA
  3. * PCI Core in hostmode
  4. *
  5. * Copyright 2005 - 2011, Broadcom Corporation
  6. * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
  7. * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
  8. *
  9. * Licensed under the GNU/GPL. See COPYING for details.
  10. */
  11. #include "bcma_private.h"
  12. #include <linux/pci.h>
  13. #include <linux/export.h>
  14. #include <linux/bcma/bcma.h>
  15. #include <asm/paccess.h>
  16. /* Probe a 32bit value on the bus and catch bus exceptions.
  17. * Returns nonzero on a bus exception.
  18. * This is MIPS specific */
  19. #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
  20. /* Assume one-hot slot wiring */
  21. #define BCMA_PCI_SLOT_MAX 16
  22. #define PCI_CONFIG_SPACE_SIZE 256
  23. bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
  24. {
  25. struct bcma_bus *bus = pc->core->bus;
  26. u16 chipid_top;
  27. u32 tmp;
  28. chipid_top = (bus->chipinfo.id & 0xFF00);
  29. if (chipid_top != 0x4700 &&
  30. chipid_top != 0x5300)
  31. return false;
  32. bcma_core_enable(pc->core, 0);
  33. return !mips_busprobe32(tmp, pc->core->io_addr);
  34. }
  35. static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
  36. {
  37. pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
  38. pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
  39. return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
  40. }
  41. static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
  42. u32 data)
  43. {
  44. pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
  45. pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
  46. pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
  47. }
  48. static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
  49. unsigned int func, unsigned int off)
  50. {
  51. u32 addr = 0;
  52. /* Issue config commands only when the data link is up (atleast
  53. * one external pcie device is present).
  54. */
  55. if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
  56. & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
  57. goto out;
  58. /* Type 0 transaction */
  59. /* Slide the PCI window to the appropriate slot */
  60. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
  61. /* Calculate the address */
  62. addr = pc->host_controller->host_cfg_addr;
  63. addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
  64. addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
  65. addr |= (off & ~3);
  66. out:
  67. return addr;
  68. }
  69. static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
  70. unsigned int func, unsigned int off,
  71. void *buf, int len)
  72. {
  73. int err = -EINVAL;
  74. u32 addr, val;
  75. void __iomem *mmio = 0;
  76. WARN_ON(!pc->hostmode);
  77. if (unlikely(len != 1 && len != 2 && len != 4))
  78. goto out;
  79. if (dev == 0) {
  80. /* we support only two functions on device 0 */
  81. if (func > 1)
  82. return -EINVAL;
  83. /* accesses to config registers with offsets >= 256
  84. * requires indirect access.
  85. */
  86. if (off >= PCI_CONFIG_SPACE_SIZE) {
  87. addr = (func << 12);
  88. addr |= (off & 0x0FFF);
  89. val = bcma_pcie_read_config(pc, addr);
  90. } else {
  91. addr = BCMA_CORE_PCI_PCICFG0;
  92. addr |= (func << 8);
  93. addr |= (off & 0xfc);
  94. val = pcicore_read32(pc, addr);
  95. }
  96. } else {
  97. addr = bcma_get_cfgspace_addr(pc, dev, func, off);
  98. if (unlikely(!addr))
  99. goto out;
  100. err = -ENOMEM;
  101. mmio = ioremap_nocache(addr, sizeof(val));
  102. if (!mmio)
  103. goto out;
  104. if (mips_busprobe32(val, mmio)) {
  105. val = 0xffffffff;
  106. goto unmap;
  107. }
  108. val = readl(mmio);
  109. }
  110. val >>= (8 * (off & 3));
  111. switch (len) {
  112. case 1:
  113. *((u8 *)buf) = (u8)val;
  114. break;
  115. case 2:
  116. *((u16 *)buf) = (u16)val;
  117. break;
  118. case 4:
  119. *((u32 *)buf) = (u32)val;
  120. break;
  121. }
  122. err = 0;
  123. unmap:
  124. if (mmio)
  125. iounmap(mmio);
  126. out:
  127. return err;
  128. }
  129. static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
  130. unsigned int func, unsigned int off,
  131. const void *buf, int len)
  132. {
  133. int err = -EINVAL;
  134. u32 addr = 0, val = 0;
  135. void __iomem *mmio = 0;
  136. u16 chipid = pc->core->bus->chipinfo.id;
  137. WARN_ON(!pc->hostmode);
  138. if (unlikely(len != 1 && len != 2 && len != 4))
  139. goto out;
  140. if (dev == 0) {
  141. /* accesses to config registers with offsets >= 256
  142. * requires indirect access.
  143. */
  144. if (off < PCI_CONFIG_SPACE_SIZE) {
  145. addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
  146. addr |= (func << 8);
  147. addr |= (off & 0xfc);
  148. mmio = ioremap_nocache(addr, sizeof(val));
  149. if (!mmio)
  150. goto out;
  151. }
  152. } else {
  153. addr = bcma_get_cfgspace_addr(pc, dev, func, off);
  154. if (unlikely(!addr))
  155. goto out;
  156. err = -ENOMEM;
  157. mmio = ioremap_nocache(addr, sizeof(val));
  158. if (!mmio)
  159. goto out;
  160. if (mips_busprobe32(val, mmio)) {
  161. val = 0xffffffff;
  162. goto unmap;
  163. }
  164. }
  165. switch (len) {
  166. case 1:
  167. val = readl(mmio);
  168. val &= ~(0xFF << (8 * (off & 3)));
  169. val |= *((const u8 *)buf) << (8 * (off & 3));
  170. break;
  171. case 2:
  172. val = readl(mmio);
  173. val &= ~(0xFFFF << (8 * (off & 3)));
  174. val |= *((const u16 *)buf) << (8 * (off & 3));
  175. break;
  176. case 4:
  177. val = *((const u32 *)buf);
  178. break;
  179. }
  180. if (dev == 0 && !addr) {
  181. /* accesses to config registers with offsets >= 256
  182. * requires indirect access.
  183. */
  184. addr = (func << 12);
  185. addr |= (off & 0x0FFF);
  186. bcma_pcie_write_config(pc, addr, val);
  187. } else {
  188. writel(val, mmio);
  189. if (chipid == BCMA_CHIP_ID_BCM4716 ||
  190. chipid == BCMA_CHIP_ID_BCM4748)
  191. readl(mmio);
  192. }
  193. err = 0;
  194. unmap:
  195. if (mmio)
  196. iounmap(mmio);
  197. out:
  198. return err;
  199. }
  200. static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
  201. unsigned int devfn,
  202. int reg, int size, u32 *val)
  203. {
  204. unsigned long flags;
  205. int err;
  206. struct bcma_drv_pci *pc;
  207. struct bcma_drv_pci_host *pc_host;
  208. pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
  209. pc = pc_host->pdev;
  210. spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
  211. err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
  212. PCI_FUNC(devfn), reg, val, size);
  213. spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
  214. return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  215. }
  216. static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
  217. unsigned int devfn,
  218. int reg, int size, u32 val)
  219. {
  220. unsigned long flags;
  221. int err;
  222. struct bcma_drv_pci *pc;
  223. struct bcma_drv_pci_host *pc_host;
  224. pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
  225. pc = pc_host->pdev;
  226. spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
  227. err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
  228. PCI_FUNC(devfn), reg, &val, size);
  229. spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
  230. return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
  231. }
  232. /* return cap_offset if requested capability exists in the PCI config space */
  233. static u8 bcma_find_pci_capability(struct bcma_drv_pci *pc, unsigned int dev,
  234. unsigned int func, u8 req_cap_id,
  235. unsigned char *buf, u32 *buflen)
  236. {
  237. u8 cap_id;
  238. u8 cap_ptr = 0;
  239. u32 bufsize;
  240. u8 byte_val;
  241. /* check for Header type 0 */
  242. bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
  243. sizeof(u8));
  244. if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
  245. return cap_ptr;
  246. /* check if the capability pointer field exists */
  247. bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
  248. sizeof(u8));
  249. if (!(byte_val & PCI_STATUS_CAP_LIST))
  250. return cap_ptr;
  251. /* check if the capability pointer is 0x00 */
  252. bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
  253. sizeof(u8));
  254. if (cap_ptr == 0x00)
  255. return cap_ptr;
  256. /* loop thr'u the capability list and see if the requested capabilty
  257. * exists */
  258. bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
  259. while (cap_id != req_cap_id) {
  260. bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
  261. sizeof(u8));
  262. if (cap_ptr == 0x00)
  263. return cap_ptr;
  264. bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
  265. sizeof(u8));
  266. }
  267. /* found the caller requested capability */
  268. if ((buf != NULL) && (buflen != NULL)) {
  269. u8 cap_data;
  270. bufsize = *buflen;
  271. if (!bufsize)
  272. return cap_ptr;
  273. *buflen = 0;
  274. /* copy the cpability data excluding cap ID and next ptr */
  275. cap_data = cap_ptr + 2;
  276. if ((bufsize + cap_data) > PCI_CONFIG_SPACE_SIZE)
  277. bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
  278. *buflen = bufsize;
  279. while (bufsize--) {
  280. bcma_extpci_read_config(pc, dev, func, cap_data, buf,
  281. sizeof(u8));
  282. cap_data++;
  283. buf++;
  284. }
  285. }
  286. return cap_ptr;
  287. }
  288. /* If the root port is capable of returning Config Request
  289. * Retry Status (CRS) Completion Status to software then
  290. * enable the feature.
  291. */
  292. static void bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
  293. {
  294. struct bcma_bus *bus = pc->core->bus;
  295. u8 cap_ptr, root_ctrl, root_cap, dev;
  296. u16 val16;
  297. int i;
  298. cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
  299. NULL);
  300. root_cap = cap_ptr + PCI_EXP_RTCAP;
  301. bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
  302. if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
  303. /* Enable CRS software visibility */
  304. root_ctrl = cap_ptr + PCI_EXP_RTCTL;
  305. val16 = PCI_EXP_RTCTL_CRSSVE;
  306. bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
  307. sizeof(u16));
  308. /* Initiate a configuration request to read the vendor id
  309. * field of the device function's config space header after
  310. * 100 ms wait time from the end of Reset. If the device is
  311. * not done with its internal initialization, it must at
  312. * least return a completion TLP, with a completion status
  313. * of "Configuration Request Retry Status (CRS)". The root
  314. * complex must complete the request to the host by returning
  315. * a read-data value of 0001h for the Vendor ID field and
  316. * all 1s for any additional bytes included in the request.
  317. * Poll using the config reads for max wait time of 1 sec or
  318. * until we receive the successful completion status. Repeat
  319. * the procedure for all the devices.
  320. */
  321. for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
  322. for (i = 0; i < 100000; i++) {
  323. bcma_extpci_read_config(pc, dev, 0,
  324. PCI_VENDOR_ID, &val16,
  325. sizeof(val16));
  326. if (val16 != 0x1)
  327. break;
  328. udelay(10);
  329. }
  330. if (val16 == 0x1)
  331. bcma_err(bus, "PCI: Broken device in slot %d\n",
  332. dev);
  333. }
  334. }
  335. }
  336. void bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
  337. {
  338. struct bcma_bus *bus = pc->core->bus;
  339. struct bcma_drv_pci_host *pc_host;
  340. u32 tmp;
  341. u32 pci_membase_1G;
  342. unsigned long io_map_base;
  343. bcma_info(bus, "PCIEcore in host mode found\n");
  344. if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
  345. bcma_info(bus, "This PCIE core is disabled and not working\n");
  346. return;
  347. }
  348. pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
  349. if (!pc_host) {
  350. bcma_err(bus, "can not allocate memory");
  351. return;
  352. }
  353. pc->host_controller = pc_host;
  354. pc_host->pci_controller.io_resource = &pc_host->io_resource;
  355. pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
  356. pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
  357. pc_host->pdev = pc;
  358. pci_membase_1G = BCMA_SOC_PCI_DMA;
  359. pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
  360. pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
  361. pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
  362. pc_host->mem_resource.name = "BCMA PCIcore external memory",
  363. pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
  364. pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
  365. pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
  366. pc_host->io_resource.name = "BCMA PCIcore external I/O",
  367. pc_host->io_resource.start = 0x100;
  368. pc_host->io_resource.end = 0x7FF;
  369. pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
  370. /* Reset RC */
  371. usleep_range(3000, 5000);
  372. pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
  373. usleep_range(1000, 2000);
  374. pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
  375. BCMA_CORE_PCI_CTL_RST_OE);
  376. /* 64 MB I/O access window. On 4716, use
  377. * sbtopcie0 to access the device registers. We
  378. * can't use address match 2 (1 GB window) region
  379. * as mips can't generate 64-bit address on the
  380. * backplane.
  381. */
  382. if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 ||
  383. bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) {
  384. pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
  385. pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
  386. BCMA_SOC_PCI_MEM_SZ - 1;
  387. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
  388. BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
  389. } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
  390. tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
  391. tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
  392. tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
  393. if (pc->core->core_unit == 0) {
  394. pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
  395. pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
  396. BCMA_SOC_PCI_MEM_SZ - 1;
  397. pc_host->io_resource.start = 0x100;
  398. pc_host->io_resource.end = 0x47F;
  399. pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
  400. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
  401. tmp | BCMA_SOC_PCI_MEM);
  402. } else if (pc->core->core_unit == 1) {
  403. pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
  404. pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
  405. BCMA_SOC_PCI_MEM_SZ - 1;
  406. pc_host->io_resource.start = 0x480;
  407. pc_host->io_resource.end = 0x7FF;
  408. pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
  409. pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
  410. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
  411. tmp | BCMA_SOC_PCI1_MEM);
  412. }
  413. } else
  414. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
  415. BCMA_CORE_PCI_SBTOPCI_IO);
  416. /* 64 MB configuration access window */
  417. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
  418. /* 1 GB memory access window */
  419. pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
  420. BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
  421. /* As per PCI Express Base Spec 1.1 we need to wait for
  422. * at least 100 ms from the end of a reset (cold/warm/hot)
  423. * before issuing configuration requests to PCI Express
  424. * devices.
  425. */
  426. msleep(100);
  427. bcma_core_pci_enable_crs(pc);
  428. /* Enable PCI bridge BAR0 memory & master access */
  429. tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  430. bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
  431. /* Enable PCI interrupts */
  432. pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
  433. /* Ok, ready to run, register it to the system.
  434. * The following needs change, if we want to port hostmode
  435. * to non-MIPS platform. */
  436. io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start,
  437. resource_size(&pc_host->mem_resource));
  438. pc_host->pci_controller.io_map_base = io_map_base;
  439. set_io_port_base(pc_host->pci_controller.io_map_base);
  440. /* Give some time to the PCI controller to configure itself with the new
  441. * values. Not waiting at this point causes crashes of the machine. */
  442. usleep_range(10000, 15000);
  443. register_pci_controller(&pc_host->pci_controller);
  444. return;
  445. }
  446. /* Early PCI fixup for a device on the PCI-core bridge. */
  447. static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
  448. {
  449. if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
  450. /* This is not a device on the PCI-core bridge. */
  451. return;
  452. }
  453. if (PCI_SLOT(dev->devfn) != 0)
  454. return;
  455. pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
  456. /* Enable PCI bridge bus mastering and memory space */
  457. pci_set_master(dev);
  458. if (pcibios_enable_device(dev, ~0) < 0) {
  459. pr_err("PCI: BCMA bridge enable failed\n");
  460. return;
  461. }
  462. /* Enable PCI bridge BAR1 prefetch and burst */
  463. pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
  464. }
  465. DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
  466. /* Early PCI fixup for all PCI-cores to set the correct memory address. */
  467. static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
  468. {
  469. struct resource *res;
  470. int pos, err;
  471. if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
  472. /* This is not a device on the PCI-core bridge. */
  473. return;
  474. }
  475. if (PCI_SLOT(dev->devfn) == 0)
  476. return;
  477. pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
  478. for (pos = 0; pos < 6; pos++) {
  479. res = &dev->resource[pos];
  480. if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) {
  481. err = pci_assign_resource(dev, pos);
  482. if (err)
  483. pr_err("PCI: Problem fixing up the addresses on %s\n",
  484. pci_name(dev));
  485. }
  486. }
  487. }
  488. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
  489. /* This function is called when doing a pci_enable_device().
  490. * We must first check if the device is a device on the PCI-core bridge. */
  491. int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
  492. {
  493. struct bcma_drv_pci_host *pc_host;
  494. if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
  495. /* This is not a device on the PCI-core bridge. */
  496. return -ENODEV;
  497. }
  498. pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
  499. pci_ops);
  500. pr_info("PCI: Fixing up device %s\n", pci_name(dev));
  501. /* Fix up interrupt lines */
  502. dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
  503. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  504. return 0;
  505. }
  506. EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
  507. /* PCI device IRQ mapping. */
  508. int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
  509. {
  510. struct bcma_drv_pci_host *pc_host;
  511. if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
  512. /* This is not a device on the PCI-core bridge. */
  513. return -ENODEV;
  514. }
  515. pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
  516. pci_ops);
  517. return bcma_core_mips_irq(pc_host->pdev->core) + 2;
  518. }
  519. EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);